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* Support kJitTableAddress in x86/arm/arm64.Nicolas Geoffray2016-11-091-5/+10
| | | | | test: test-art-host test-art-target, angler boots and runs. Change-Id: I3654ae2809d4d759db76ee1ada1c17f3a9c3b392
* Merge "Remove default argument values in GenerateGcRootFieldLoad."Roland Levillain2016-10-281-2/+2
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| * Remove default argument values in GenerateGcRootFieldLoad.Roland Levillain2016-10-271-2/+2
| | | | | | | | | | | | | | | | | | These values were never or rarely used. Test: mmma art (with and without `ART_USE_READ_BARRIER=true`) Bug: 12687968 Bug: 29516974 Change-Id: I5d15140ce501bf50d7a87871b1e492cee54913db
* | Add support for Baker read barriers in UnsafeCASObject intrinsics.Roland Levillain2016-10-261-1/+15
|/ | | | | | | | | | | | | Prior to doing the compare-and-swap operation, ensure the expected reference stored in the holding object's field is in the to-space by loading it, emitting a read barrier and updating that field with a strong compare-and-set operation with relaxed memory synchronization ordering (if needed). Test: ART host and target tests and Nexus 5X boot test with Baker read barriers. Bug: 29516905 Bug: 12687968 Change-Id: I480f6a9b59547f11d0a04777406b9bfeb905bfd2
* Delete unused blocked_register_pairs_ in code generatorsMathieu Chartier2016-10-181-3/+0
| | | | | | | Legacy code for compatibility with quick? Test: test-art-host CC Change-Id: I9de261daea67dfd9bd3df89826ba9d10f135e29e
* Revert "Revert "Store resolved Strings for AOT code in .bss.""Vladimir Marko2016-10-041-2/+6
| | | | | | | | | | | | | | | | Fixed oat_test to keep dex files alive. Fixed mips build. Rewritten the .bss GC root visiting and added write barrier to the artResolveStringFromCode(). Test: build aosp_mips-eng Test: m ART_DEFAULT_GC_TYPE=SS test-art-target-host-gtest-oat_test Test: Run ART test suite on host and Nexus 9. Bug: 20323084 Bug: 30627598 This reverts commit 5f926055cb88089d8ca27243f35a9dfd89d981f0. Change-Id: I07fa2278d82b8eb64964c9a4b66cb93726ccda6b
* Revert "Store resolved Strings for AOT code in .bss."Vladimir Marko2016-09-301-6/+2
| | | | | | | | | | | | | | There are some issues with oat_test64 on host and aosp_mips-eng. Also reverts "compiler_driver: Fix build." Bug: 20323084 Bug: 30627598 This reverts commit 63dccbbefef3014c99c22748d18befcc7bcb3b41. This reverts commit 04a44135ace10123f059373691594ae0f270a8a4. Change-Id: I568ba3e58cf103987fdd63c8a21521010a9f27c4
* Store resolved Strings for AOT code in .bss.Vladimir Marko2016-09-291-2/+6
| | | | | | | | | | | And do some related refactorings. Bug: 20323084 Bug: 30627598 Test: Run ART test suite including gcstress on host and Nexus 9. Test: Run ART test suite including gcstress with baker CC on host and Nexus 9. Test: Build aosp_mips64-eng. Change-Id: I1b12c1570fee8e5da490b47f231050142afcbd1e
* Clean-up sharpening and compiler driver.Nicolas Geoffray2016-09-231-1/+1
| | | | | | | | | | | | | Remove dependency on compiler driver for sharpening and dex2dex (the methods called on the compiler driver were doing unnecessary work), and remove the now unused methods in compiler driver. Also remove test that is now invalid, as sharpening always succeeds. test: m test-art-host m test-art-target Change-Id: I54e91c6839bd5b0b86182f2f43ba5d2c112ef908
* ARM: Use stm/ldm for live registers save/restore in SlowPathCode.Artem Serov2016-09-191-1/+13
| | | | | | | | | In case when there is more than 4 register to save/restore in the SlowPathCode stm/ldm can save some code size. Test: m test-art-target; m test-art-host Change-Id: I2d5b44bab58b67207105302cd7d8ee3300b9040a
* Add missing OVERRIDE qualifiers in code generators.Roland Levillain2016-09-141-3/+3
| | | | | Test: mmma art Change-Id: I91d0a2dc23dc8d63a9bb3607eb1c1517eabaeb1f
* Avoid read barrier for image HLoadClassMathieu Chartier2016-09-071-2/+3
| | | | | | | | | | | | | | | | | | | | Concurrent copying baker: X86_64 core-optimizing-pic.oat: 28583112 -> 27906824 (2.4% smaller) Around 0.4% of 2.4% is from re-enabling kBootImageLinkTimeAddress, kBootImageLinkTimePcRelative, and kBootImageAddress. N6P boot.oat 32: 73042140 -> 71891956 (1.57% smaller) N6P boot.oat 64: 83831608 -> 82531456 (1.55% smaller) EAAC: 1252 -> 1245 (32 samples) Bug: 29516974 Test: test-art-host CC baker, N6P booting Change-Id: I9a196cf0157058836981c43c93872e9f0c4919aa
* Remove workarounds for [D]CHECK()s in constexpr functions.Vladimir Marko2016-08-311-3/+3
| | | | | | | | | | We're now using C++14, so we can use [D]CHECK()s directly in constexpr functions. Remove the C++11 workaround macros ([D]CHECK_CONSTEXPR) and C++ version checks. Also remove the 'static' qualifier from inline functions in affected files. Test: m test-art-host Change-Id: I0f962ad75e4efe9b65325d022cd272b229574222
* ARM: Make runtime invokes use InvokeRuntime().Serban Constantinescu2016-08-261-6/+3
| | | | | | | | This patch refactors all of the ARM Optimizing compiler runtime invokes to use InvokeRuntime(). It also fixes some misuses of RecordPcInfo(). Change-Id: I722bc2ba95e42ff69ca12c3edc09326e0de2881f
* ARM: Embed constants in add/sub-long.Vladimir Marko2016-08-051-1/+2
| | | | | | Test: 538-checker-embed-constants Test: Run ART test suite on Nexus 5. Change-Id: Ib9639748c74d5c56dc354a6830987b613b922654
* Merge "ARM: Embed 0.0 in VCMP."Vladimir Marko2016-08-021-0/+2
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| * ARM: Embed 0.0 in VCMP.Vladimir Marko2016-08-021-0/+2
| | | | | | | | | | Test: Run ART test suite on Nexus 5. Change-Id: I5cbbd98c4d64a4d9213e27adcae929ead5099a39
* | ART: Convert pointer size to enumAndreas Gampe2016-08-011-1/+2
|/ | | | | | | | | Move away from size_t to dedicated enum (class). Bug: 30373134 Bug: 30419309 Test: m test-art-host Change-Id: Id453c330f1065012e7d4f9fc24ac477cc9bb9269
* ART: Delete old compiler_enums.hAndreas Gampe2016-07-271-1/+0
| | | | | | | | Holdover from the Quick days. Move the two enums that are still used closer to the actual users (and prune no longer used cases). Test: m test-art-host Change-Id: I88aa49961a54635788cafac570ddc3125aa38262
* Do not emit stack maps for runtime calls to ReadBarrierMarkRegX.Roland Levillain2016-07-221-0/+6
| | | | | | | | | | | | | | * Boot image code size variation on Nexus 5X (aosp_bullhead-userdebug build): - total ARM64 framework Oat files size change: 115584120 bytes -> 109124728 bytes (-5.59%) - total ARM framework Oat files size change: 97387728 bytes -> 92517584 (-5.00%) Test: ART host and target (ARM, ARM64) tests. Bug: 29506760 Bug: 12687968 Change-Id: I979d9fb2b4e09f4c0c7bf33af2cd91750a67f989
* ARM: Change mem address mode for array accesses.Artem Serov2016-07-201-0/+18
| | | | | | | | | | | | | | | Switch from: add IP, r[Array], r[Index], LSL #2 ldr r0, [IP, #12] To: add IP. r[Array], #12 ldr r0, [IP, r[Index], LSL #2] These is a base for the future TryExtractArrayAccessAddress optimization port to arm. Test: aosp_shamu-userdebug boots and passes "m test-art-target". Change-Id: I6ab01ba3271a8f79599ddd91a6b63cd1b37d2d67
* Revert "Revert "Dump more dex file data in oatdump""Mathieu Chartier2016-07-141-1/+1
| | | | | | | | | | Delete runtime to fix leak before callin exit. Bug: 29462018 This reverts commit 9c05578dd2306231437bd290c0f70abc2bb3b6d8. Change-Id: Ica23ba0f2d07496d0e4a3288329945f612ac3b20
* Revert "Dump more dex file data in oatdump"Nicolas Geoffray2016-07-141-1/+1
| | | | | | | | | | Breaks valgrind. Bug: 29462018 This reverts commit 8e2c56252aa9527bd9a82bdd147fdc46cf5deb9c. Change-Id: If58cedcee75dd0eda8571e90d63e080a4709d773
* Dump more dex file data in oatdumpMathieu Chartier2016-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Dump some statistics for each dex file along side with strings loaded from code and dex code bytes. Sample output: Cumulative dex file data Num string ids: 202809 Num method ids: 320464 Num field ids: 162822 Num type ids: 68151 Num class defs: 48061 Unique strings loaded from dex code: 51049 Total strings loaded from dex code: 106651 Number of unique dex code items: 247929 Total number of dex code bytes: 11090574 Added content testing to oat dump test. No significant slowdown. TEST: test-art-host Bug: 29462018 Change-Id: I60effd3087d8c427eda4ee26431d5d77165b3939
* Merge changes I4d8da7ce,I4da5be01,Idfbead82Roland Levillain2016-06-241-10/+10
|\ | | | | | | | | | | | | * changes: Re-enable most intrinsics with read barriers. Fix ARM & ARM64 UnsafeGetObject intrinsics with read barriers. Fix x86 & x86-64 UnsafeGetObject intrinsics with read barriers.
| * Fix ARM & ARM64 UnsafeGetObject intrinsics with read barriers.Roland Levillain2016-06-231-10/+10
| | | | | | | | | | | | | | | | | | | | | | The implementation was incorrectly interpreting the 'offset' input as an index in a (4-byte) object reference array, whereas it is a (1-byte) offset to an object reference field within the 'base' (object) input. Bug: 29516905 Change-Id: I4da5be0193217965f25e5d141c242592dea6ffe8 Test: Covered by test/004-UnsafeTest.
* | Improve HLoadClass code generation.Vladimir Marko2016-06-211-5/+20
|/ | | | | | | | | | | | | | | | | | | | | | | For classes in the boot image, use either direct pointers or PC-relative addresses. For other classes, use PC-relative access to the dex cache arrays for AOT and direct address of the type's dex cache slot for JIT. For aosp_flounder-userdebug: - 32-bit boot.oat: -252KiB (-0.3%) - 64-bit boot.oat: -412KiB (-0.4%) - 32-bit dalvik cache total: -392KiB (-0.4%) - 64-bit dalvik-cache total: -2312KiB (-1.0%) (contains more files than the 32-bit dalvik cache) For aosp_flounder-userdebug forced to compile PIC: - 32-bit boot.oat: -124KiB (-0.2%) - 64-bit boot.oat: -420KiB (-0.5%) - 32-bit dalvik cache total: -136KiB (-0.1%) - 64-bit dalvik-cache total: -1136KiB (-0.5%) (contains more files than the 32-bit dalvik cache) Bug: 27950288 Change-Id: I4da991a4b7e53c63c92558b97923d18092acf139
* Fix: correctly destruct VIXL labels.Alexandre Rames2016-04-151-1/+1
| | | | Bug: 27505766 Change-Id: I077465e3d308f4331e7a861902e05865f9d99835
* Revert "Revert "Refactor HGraphBuilder and SsaBuilder to remove HLocals""David Brazdil2016-04-071-2/+0
| | | | | | | | | | | | | | | | | | | | This patch merges the instruction-building phases from HGraphBuilder and SsaBuilder into a single HInstructionBuilder class. As a result, it is not necessary to generate HLocal, HLoadLocal and HStoreLocal instructions any more, as the builder produces SSA form directly. Saves 5-15% of arena-allocated memory (see bug for more data): GMS 20.46MB => 19.26MB (-5.86%) Maps 24.12MB => 21.47MB (-10.98%) YouTube 28.60MB => 26.01MB (-9.05%) This CL fixed an issue with parsing quickened instructions. Bug: 27894376 Bug: 27998571 Bug: 27995065 Change-Id: I20dbe1bf2d0fe296377478db98cb86cba695e694
* Revert "Refactor HGraphBuilder and SsaBuilder to remove HLocals"David Brazdil2016-04-041-0/+2
| | | | | | | Bug: 27995065 This reverts commit e3ff7b293be2a6791fe9d135d660c0cffe4bd73f. Change-Id: I5363c7ce18f47fd422c15eed5423a345a57249d8
* Refactor HGraphBuilder and SsaBuilder to remove HLocalsDavid Brazdil2016-04-041-2/+0
| | | | | | | | | | | | | | | This patch merges the instruction-building phases from HGraphBuilder and SsaBuilder into a single HInstructionBuilder class. As a result, it is not necessary to generate HLocal, HLoadLocal and HStoreLocal instructions any more, as the builder produces SSA form directly. Saves 5-15% of arena-allocated memory (see bug for more data): GMS 20.46MB => 19.26MB (-5.86%) Maps 24.12MB => 21.47MB (-10.98%) YouTube 28.60MB => 26.01MB (-9.05%) Bug: 27894376 Change-Id: Iefe28d40600c169c5d306fd2c77034ae19476d90
* Optimizing: Improve const-string code generation.Vladimir Marko2016-03-291-21/+42
| | | | | | | | | | | | | | | | | | | | | | | For strings in the boot image, use either direct pointers or pc-relative addresses. For other strings, use PC-relative access to the dex cache arrays for AOT and direct address of the string's dex cache slot for JIT. For aosp_flounder-userdebug: - 32-bit boot.oat: -692KiB (-0.9%) - 64-bit boot.oat: -948KiB (-1.1%) - 32-bit dalvik cache total: -900KiB (-0.9%) - 64-bit dalvik cache total: -3672KiB (-1.5%) (contains more files than the 32-bit dalvik cache) For aosp_flounder-userdebug forced to compile PIC: - 32-bit boot.oat: -380KiB (-0.5%) - 64-bit boot.oat: -928KiB (-1.0%) - 32-bit dalvik cache total: -468KiB (-0.4%) - 64-bit dalvik cache total: -1928KiB (-0.8%) (contains more files than the 32-bit dalvik cache) Bug: 26884697 Change-Id: Iec7266ce67e6fedc107be78fab2e742a8dab2696
* Ensure art::HRor support boolean, byte, short and char inputs.Roland Levillain2016-03-181-2/+0
| | | | | | | | | | Also extend tests covering the IntegerRotateLeft, LongRotateLeft, IntegerRotateRight and LongRotateRight intrinsics and their translation into an art::HRor instruction. Bug: 27682579 Change-Id: I89f6ea6a7315659a172482bf09875cfb7e7422a1
* Clean up NullCheck generation and record stats about it.Calin Juravle2016-03-161-3/+3
| | | | | | | This removes redundant code from the generators and allows for easier stat recording. Change-Id: Iccd4368f9e9d87a6fecb863dee4e2145c97851c4
* Revert "Revert "ARM/ARM64: Extend support of instruction combining.""Artem Udovichenko2016-02-251-0/+2
| | | | | | This reverts commit 6b5afdd144d2bb3bf994240797834b5666b2cf98. Change-Id: Ic27a10f02e21109503edd64e6d73d1bb0c6a8ac6
* Remove HNativeDebugInfo from start of basic blocks.David Srbecky2016-02-241-0/+2
| | | | | | | We do not require full environment at the start of basic block. The dex pc contained in basic block is sufficient for line mapping. Change-Id: I5ba9e5f5acbc4a783ad544769f9a73bb33e2bafa
* ART: Remove HTemporaryDavid Brazdil2016-02-121-1/+0
| | | | Change-Id: I21b984224370a9ce7a4a13a9652503cfb03c5f03
* Improve documentation and assertions of read barrier instrumentation.Roland Levillain2016-01-221-4/+10
| | | | | | | | | For ARM, x86, x86-64 back ends. The case of the ARM64 back end is already handled in https://android-review.googlesource.com/#/c/197870/. Bug: 12687968 Change-Id: I6df1128cc100cbdb89020876e1a54de719508be3
* Revert "ARM/ARM64: Extend support of instruction combining."Nicolas Geoffray2016-01-221-2/+0
| | | | | | | | The test fails its checker parts. This reverts commit debeb98aaa8950caf1a19df490f2ac9bf563075b. Change-Id: I49929e15950c7814da6c411ecd2b640d12de80df
* ARM/ARM64: Extend support of instruction combining.Ilmir Usmanov2016-01-211-0/+2
| | | | | | | | | | | Combine multiply instructions in the following way: ARM64: MUL/NEG -> MNEG ARM32 (32-bit integers only): MUL/ADD -> MLA MUL/SUB -> MLS Change-Id: If20f2d8fb060145ab6fbceeb5a8f1a3d02e0ecdb
* Some read barrier clean-up in Optimizing.Roland Levillain2016-01-191-2/+2
| | | | | | | | | These changes make the read barrier compiler instrumentation code more uniform among the ARM, ARM64, x86 and x86-64 back ends. Bug: 12687968 Change-Id: I6b1c0cf2bc22ed6cd6b14754136bef4a2a036ea5
* ART: Remove Baseline compilerDavid Brazdil2016-01-181-3/+1
| | | | | | | We don't need Baseline any more and it hasn't been maintained for a while anyway. Let's remove it. Change-Id: I442ed26855527be2df3c79935403a25b1ee55df6
* Reduce code size by sharing slow paths.Aart Bik2016-01-121-1/+1
| | | | | | | | | | | | | | | Rationale: Sharing identical slow path code reduces code size. Background: Currently, slow paths with the same dex-pc, same physical register spilling code, and identical stack maps are shared (making this only useful for deopt slow paths). The newly introduced mechanism is sufficiently general to allow future improvements by e.g. allowing different dex-pc (by passing this to runtime) or even the kind of slow paths (by passing runtime addresses to the slowpath). Change-Id: I819615c47b4fd98440a241f681f93e4fc22d12e0
* Merge "Optimizing/ARM: Fix CmpConstant()."Vladimir Marko2016-01-121-1/+0
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| * Optimizing/ARM: Fix CmpConstant().Vladimir Marko2015-12-221-1/+0
| | | | | | | | | | | | | | | | | | | | | | CMN updates flags based on addition of its operands. Do not confuse the "N" suffix with bitwise inversion performed by MVN. Also add more special cases analogous to AddConstant() and use CmpConstant() more in code generator. Change-Id: I0d4571770a3f0fdf162e97d4bde56814098e7246
* | ARM Baker's read barrier fast path implementation.Roland Levillain2016-01-081-20/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce an ARM fast path implementation in Optimizing for Baker's read barriers (for both heap reference loads and GC root loads). The marking phase of the read barrier is performed by a slow path, invoking the runtime entry point artReadBarrierMark. Other read barrier algorithms continue to use the original slow path based implementation, which has been renamed as GenerateReadBarrierSlow/GenerateReadBarrierForRootSlow. Bug: 12687968 Change-Id: Ie7ee85b1b4c0564148270cebdd3cbd4c3da51b3a
* | Rewrite HInstruction::Is/As<type>().Vladimir Marko2015-12-231-0/+2
|/ | | | | | | | | | | | | | | | | | | | | | | Make Is<type>() and As<type>() non-virtual for concrete instruction types, relying on GetKind(), and mark GetKind() as PURE to improve optimization opportunities. This reduces the number of relocations in libart-compiler.so's .rel.dyn section by ~4K, or ~44%, and in .data.rel.ro by ~18K, or ~65%. The file is 96KiB smaller for Nexus 5, including 8KiB reduction of the .text section. Unfortunately, the g++/clang++ __attribute__((pure)) is not strong enough to avoid duplicated virtual calls and we would need the C++ [[pure]] attribute proposed in n3744 instead. To work around this deficiency, we introduce an extra non-virtual indirection for GetKind(), so that the compiler can optimize common expressions such as instruction->IsAdd() || instruction->IsSub() or instruction->IsAdd() && instruction->AsAdd()->... which contain two virtual calls to GetKind() after inlining. Change-Id: I83787de0671a5cb9f5b0a5f4a536cef239d5b401
* Replace rotate patterns and invokes with HRor IR.Scott Wakeling2015-12-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Replace constant and register version bitfield rotate patterns, and rotateRight/Left intrinsic invokes, with new HRor IR. Where k is constant and r is a register, with the UShr and Shl on either side of a |, +, or ^, the following patterns are replaced: x >>> #k OP x << #(reg_size - k) x >>> #k OP x << #-k x >>> r OP x << (#reg_size - r) x >>> (#reg_size - r) OP x << r x >>> r OP x << -r x >>> -r OP x << r Implemented for ARM/ARM64 & X86/X86_64. Tests changed to not be inlined to prevent optimization from folding them out. Additional tests added for constant rotate amounts. Change-Id: I5847d104c0a0348e5792be6c5072ce5090ca2c34
* Optimizing/ARM: Implement kDexCachePcRelative dispatch.Vladimir Marko2015-12-011-0/+32
| | | | Change-Id: I0fe2da50a30a3f62bec8ea01688dd1fec84b1831
* ARM read barrier support for concurrent GC in Optimizing.Roland Levillain2015-11-171-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | This first implementation uses slow paths to instrument heap reference loads and GC root loads for the concurrent copying collector, respectively calling the artReadBarrierSlow and artReadBarrierForRootSlow runtime entry points. Notes: - This implementation does not instrument HInvokeVirtual nor HInvokeInterface instructions (for class reference loads), as the corresponding read barriers are not stricly required with the current concurrent copying collector. - Intrinsics which may eventually call (on slow path) are disabled when read barriers are enabled, as the current slow path infrastructure does not support this case. - When read barriers are enabled, the code generated for a HArraySet instruction always go into the array set slow path for object arrays (delegating the operation to the runtime), as we are lacking a mechanism to keep a temporary register live accross a runtime call (needed for the instrumentation of type checking code, which requires two successive read barriers). Bug: 12687968 Change-Id: I92e8db414d029f952c07f3d3a98069e46dfdbc2a
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