summaryrefslogtreecommitdiff
path: root/compiler/optimizing/code_generator_utils.cc
Commit message (Collapse)AuthorAgeFilesLines
* ART: Implement support for instruction inliningDavid Brazdil2016-01-281-1/+1
| | | | | | | | | | | | | | Optimizing HIR contains 'non-materialized' instructions which are emitted at their use sites rather than their defining sites. This was not properly handled by the liveness analysis which did not adjust the use positions of the inputs of such instructions. Despite the analysis being incorrect, the current use cases never produce incorrect code. This patch generalizes the concept of inlined instructions and updates liveness analysis to set the compute use positions correctly. Change-Id: Id703c154b20ab861241ae5c715a150385d3ff621
* ART: Refactor GenerateTestAndBranchDavid Brazdil2015-11-171-13/+2
| | | | | | | | | | | Each code generator implements a method for generating condition evaluation and branching to arbitrary labels. This patch refactors it for better clarity but also to generate fewer jumps when the true branch is the fallthrough successor. This is preliminary work for implementing HSelect. Change-Id: Iaa545a5ecbacb761c5aa241fa69140cf6eb5952f
* Fix conditional jump over jmp (X86/X86-64/ARM32)Mark Mendell2015-11-051-0/+16
| | | | | | | | | | | | Optimize the code generation for 'if' statements to jump to the 'false' block if the next block to be generated is the 'true' block. Add an X86-64 test for this case. Note that ARM64 & MIPS64 have not been updated. Change-Id: Iebb1352feb9d3bd0142d8b0621a2e3069a708ea7 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Follow up of "div/rem on x86 and x86_64", to tidy up the code a little.Guillaume Sanchez2015-04-101-7/+11
| | | | Change-Id: Ibf39cbc8ac1d773599d70be2cb1e941674b60f1d
* Speedup div/rem by constants on x86 and x86_64Guillaume Sanchez2015-04-091-0/+93
This is done using the algorithms in Hacker's Delight chapter 10. Change-Id: I7bacefe10067569769ed31a1f7834f796fb41119