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Diffstat (limited to 'vm/compiler/codegen/arm/CodegenDriver.c')
-rw-r--r--vm/compiler/codegen/arm/CodegenDriver.c66
1 files changed, 32 insertions, 34 deletions
diff --git a/vm/compiler/codegen/arm/CodegenDriver.c b/vm/compiler/codegen/arm/CodegenDriver.c
index 657533bf0..f0745aed2 100644
--- a/vm/compiler/codegen/arm/CodegenDriver.c
+++ b/vm/compiler/codegen/arm/CodegenDriver.c
@@ -31,8 +31,7 @@ static void markCard(CompilationUnit *cUnit, int valReg, int tgtAddrReg)
{
int regCardBase = dvmCompilerAllocTemp(cUnit);
int regCardNo = dvmCompilerAllocTemp(cUnit);
- opRegImm(cUnit, kOpCmp, valReg, 0); /* storing null? */
- ArmLIR *branchOver = opCondBranch(cUnit, kArmCondEq);
+ ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondEq, valReg, 0);
loadWordDisp(cUnit, rGLUE, offsetof(InterpState, cardTable),
regCardBase);
opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, GC_CARD_SHIFT);
@@ -318,7 +317,7 @@ static void genIGet(CompilationUnit *cUnit, MIR *mir, OpSize size,
size, rlObj.sRegLow);
HEAP_ACCESS_SHADOW(false);
if (isVolatile) {
- dvmCompilerGenMemBarrier(cUnit);
+ dvmCompilerGenMemBarrier(cUnit, kSY);
}
storeValue(cUnit, rlDest, rlResult);
@@ -340,7 +339,7 @@ static void genIPut(CompilationUnit *cUnit, MIR *mir, OpSize size,
NULL);/* null object? */
if (isVolatile) {
- dvmCompilerGenMemBarrier(cUnit);
+ dvmCompilerGenMemBarrier(cUnit, kSY);
}
HEAP_ACCESS_SHADOW(true);
storeBaseDisp(cUnit, rlObj.lowReg, fieldOffset, rlSrc.lowReg, size);
@@ -541,8 +540,7 @@ static void genArrayObjectPut(CompilationUnit *cUnit, MIR *mir,
LOAD_FUNC_ADDR(cUnit, r2, (int)dvmCanPutArrayElement);
/* Are we storing null? If so, avoid check */
- opRegImm(cUnit, kOpCmp, r0, 0);
- ArmLIR *branchOver = opCondBranch(cUnit, kArmCondEq);
+ ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondEq, r0, 0);
/* Make sure the types are compatible */
loadWordDisp(cUnit, regArray, offsetof(Object, clazz), r1);
@@ -1064,16 +1062,21 @@ static void genInvokeSingletonCommon(CompilationUnit *cUnit, MIR *mir,
ArmLIR *retChainingCell = &labelList[bb->fallThrough->id];
/* r1 = &retChainingCell */
- dvmCompilerLockTemp(cUnit, r1);
ArmLIR *addrRetChain = opRegRegImm(cUnit, kOpAdd, r1, rpc, 0);
+
/* r4PC = dalvikCallsite */
loadConstant(cUnit, r4PC,
(int) (cUnit->method->insns + mir->offset));
addrRetChain->generic.target = (LIR *) retChainingCell;
+
+ /* r7 = calleeMethod->registersSize */
+ loadConstant(cUnit, r7, calleeMethod->registersSize);
/*
* r0 = calleeMethod (loaded upon calling genInvokeSingletonCommon)
* r1 = &ChainingCell
+ * r2 = calleeMethod->outsSize (to be loaded later for Java callees)
* r4PC = callsiteDPC
+ * r7 = calleeMethod->registersSize
*/
if (dvmIsNativeMethod(calleeMethod)) {
genDispatchToHandler(cUnit, TEMPLATE_INVOKE_METHOD_NATIVE);
@@ -1081,6 +1084,8 @@ static void genInvokeSingletonCommon(CompilationUnit *cUnit, MIR *mir,
gDvmJit.invokeNative++;
#endif
} else {
+ /* For Java callees, set up r2 to be calleeMethod->outsSize */
+ loadConstant(cUnit, r2, calleeMethod->outsSize);
genDispatchToHandler(cUnit, TEMPLATE_INVOKE_METHOD_CHAIN);
#if defined(WITH_JIT_TUNING)
gDvmJit.invokeMonomorphic++;
@@ -1175,9 +1180,7 @@ static void genInvokeVirtualCommon(CompilationUnit *cUnit, MIR *mir,
loadWordDisp(cUnit, r7, methodIndex * 4, r0);
/* Check if rechain limit is reached */
- opRegImm(cUnit, kOpCmp, r1, 0);
-
- ArmLIR *bypassRechaining = opCondBranch(cUnit, kArmCondGt);
+ ArmLIR *bypassRechaining = genCmpImmBranch(cUnit, kArmCondGt, r1, 0);
loadWordDisp(cUnit, rGLUE, offsetof(InterpState,
jitToInterpEntries.dvmJitToPatchPredictedChain), r7);
@@ -1219,7 +1222,6 @@ static void genPuntToInterp(CompilationUnit *cUnit, unsigned int offset)
/* r0 = dalvik pc */
dvmCompilerFlushAllRegs(cUnit);
loadConstant(cUnit, r0, (int) (cUnit->method->insns + offset));
- loadWordDisp(cUnit, r0, offsetof(Object, clazz), r3);
loadWordDisp(cUnit, rGLUE, offsetof(InterpState,
jitToInterpEntries.dvmJitToInterpPunt), r1);
opReg(cUnit, kOpBlx, r1);
@@ -1291,8 +1293,8 @@ static void genMonitorPortable(CompilationUnit *cUnit, MIR *mir)
LOAD_FUNC_ADDR(cUnit, r2, (int)dvmUnlockObject);
/* Do the call */
opReg(cUnit, kOpBlx, r2);
- opRegImm(cUnit, kOpCmp, r0, 0); /* Did we throw? */
- ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe);
+ /* Did we throw? */
+ ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
loadConstant(cUnit, r0,
(int) (cUnit->method->insns + mir->offset +
dexGetInstrWidthAbs(gDvm.instrWidth, OP_MONITOR_EXIT)));
@@ -1327,13 +1329,15 @@ static bool handleFmt10x(CompilationUnit *cUnit, MIR *mir)
return true;
}
switch (dalvikOpCode) {
+ case OP_RETURN_VOID_BARRIER:
+ dvmCompilerGenMemBarrier(cUnit, kST);
+ // Intentional fallthrough
case OP_RETURN_VOID:
genReturnCommon(cUnit,mir);
break;
case OP_UNUSED_73:
case OP_UNUSED_79:
case OP_UNUSED_7A:
- case OP_UNUSED_F1:
case OP_UNUSED_FF:
LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpCode);
return true;
@@ -1484,7 +1488,7 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir)
loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
if (isVolatile) {
- dvmCompilerGenMemBarrier(cUnit);
+ dvmCompilerGenMemBarrier(cUnit, kSY);
}
HEAP_ACCESS_SHADOW(true);
loadWordDisp(cUnit, tReg, 0, rlResult.lowReg);
@@ -1559,7 +1563,7 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir)
dvmCompilerFreeTemp(cUnit, tReg);
HEAP_ACCESS_SHADOW(false);
if (isVolatile) {
- dvmCompilerGenMemBarrier(cUnit);
+ dvmCompilerGenMemBarrier(cUnit, kSY);
}
if (isSputObject) {
/* NOTE: marking card based sfield->clazz */
@@ -1617,8 +1621,7 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir)
opReg(cUnit, kOpBlx, r2);
dvmCompilerClobberCallRegs(cUnit);
/* generate a branch over if allocation is successful */
- opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */
- ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe);
+ ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
/*
* OOM exception needs to be thrown here and cannot re-execute
*/
@@ -1659,8 +1662,9 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir)
loadConstant(cUnit, r1, (int) classPtr );
rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- opRegImm(cUnit, kOpCmp, rlSrc.lowReg, 0); /* Null? */
- ArmLIR *branch1 = opCondBranch(cUnit, kArmCondEq);
+ /* Null? */
+ ArmLIR *branch1 = genCmpImmBranch(cUnit, kArmCondEq,
+ rlSrc.lowReg, 0);
/*
* rlSrc.lowReg now contains object->clazz. Note that
* it could have been allocated r0, but we're okay so long
@@ -2264,8 +2268,7 @@ static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir)
opReg(cUnit, kOpBlx, r3);
dvmCompilerClobberCallRegs(cUnit);
/* generate a branch over if allocation is successful */
- opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */
- ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe);
+ ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
/*
* OOM exception needs to be thrown here and cannot re-execute
*/
@@ -2304,10 +2307,8 @@ static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir)
dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
loadValueDirectFixed(cUnit, rlSrc, r0); /* Ref */
loadConstant(cUnit, r2, (int) classPtr );
-//TUNING: compare to 0 primative to allow use of CB[N]Z
- opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */
/* When taken r0 has NULL which can be used for store directly */
- ArmLIR *branch1 = opCondBranch(cUnit, kArmCondEq);
+ ArmLIR *branch1 = genCmpImmBranch(cUnit, kArmCondEq, r0, 0);
/* r1 now contains object->clazz */
loadWordDisp(cUnit, r0, offsetof(Object, clazz), r1);
/* r1 now contains object->clazz */
@@ -2705,8 +2706,7 @@ static bool handleFmt31t(CompilationUnit *cUnit, MIR *mir)
opReg(cUnit, kOpBlx, r2);
dvmCompilerClobberCallRegs(cUnit);
/* generate a branch over if successful */
- opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */
- ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe);
+ ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
loadConstant(cUnit, r0,
(int) (cUnit->method->insns + mir->offset));
genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
@@ -3052,8 +3052,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
dvmCompilerClobberCallRegs(cUnit);
/* generate a branch over if the interface method is resolved */
- opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */
- ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe);
+ ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
/*
* calleeMethod == NULL -> throw
*/
@@ -3069,9 +3068,8 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
genRegCopy(cUnit, r1, r8);
/* Check if rechain limit is reached */
- opRegImm(cUnit, kOpCmp, r1, 0);
-
- ArmLIR *bypassRechaining = opCondBranch(cUnit, kArmCondGt);
+ ArmLIR *bypassRechaining = genCmpImmBranch(cUnit, kArmCondGt,
+ r1, 0);
loadWordDisp(cUnit, rGLUE, offsetof(InterpState,
jitToInterpEntries.dvmJitToPatchPredictedChain), r7);
@@ -3445,8 +3443,8 @@ static bool handleExecuteInline(CompilationUnit *cUnit, MIR *mir)
}
opReg(cUnit, kOpBlx, r4PC);
opRegImm(cUnit, kOpAdd, r13, 8);
- opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */
- ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe);
+ /* NULL? */
+ ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
loadConstant(cUnit, r0,
(int) (cUnit->method->insns + mir->offset));
genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-06 20:05:01 +0000