diff options
Diffstat (limited to 'vm/compiler/codegen/arm/CodegenDriver.c')
| -rw-r--r-- | vm/compiler/codegen/arm/CodegenDriver.c | 328 |
1 files changed, 162 insertions, 166 deletions
diff --git a/vm/compiler/codegen/arm/CodegenDriver.c b/vm/compiler/codegen/arm/CodegenDriver.c index 011679b60..02c39f6d0 100644 --- a/vm/compiler/codegen/arm/CodegenDriver.c +++ b/vm/compiler/codegen/arm/CodegenDriver.c @@ -31,8 +31,7 @@ static void markCard(CompilationUnit *cUnit, int valReg, int tgtAddrReg) { int regCardBase = dvmCompilerAllocTemp(cUnit); int regCardNo = dvmCompilerAllocTemp(cUnit); - opRegImm(cUnit, kOpCmp, valReg, 0); /* storing null? */ - ArmLIR *branchOver = opCondBranch(cUnit, kArmCondEq); + ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondEq, valReg, 0); loadWordDisp(cUnit, rGLUE, offsetof(InterpState, cardTable), regCardBase); opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, GC_CARD_SHIFT); @@ -86,7 +85,7 @@ static bool genArithOpFloatPortable(CompilationUnit *cUnit, MIR *mir, RegLocation rlResult; void* funct; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_ADD_FLOAT_2ADDR: case OP_ADD_FLOAT: funct = (void*) __aeabi_fadd; @@ -132,7 +131,7 @@ static bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir, RegLocation rlResult; void* funct; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_ADD_DOUBLE_2ADDR: case OP_ADD_DOUBLE: funct = (void*) __aeabi_dadd; @@ -173,9 +172,9 @@ static bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir, static bool genConversionPortable(CompilationUnit *cUnit, MIR *mir) { - OpCode opCode = mir->dalvikInsn.opCode; + Opcode opcode = mir->dalvikInsn.opcode; - switch (opCode) { + switch (opcode) { case OP_INT_TO_FLOAT: return genConversionCall(cUnit, mir, (void*)__aeabi_i2f, 1, 1); case OP_FLOAT_TO_INT: @@ -203,11 +202,11 @@ static bool genConversionPortable(CompilationUnit *cUnit, MIR *mir) } #if defined(WITH_SELF_VERIFICATION) -static void selfVerificationBranchInsert(LIR *currentLIR, ArmOpCode opCode, +static void selfVerificationBranchInsert(LIR *currentLIR, ArmOpcode opcode, int dest, int src1) { ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true); - insn->opCode = opCode; + insn->opcode = opcode; insn->operands[0] = dest; insn->operands[1] = src1; setupResourceMasks(insn); @@ -217,7 +216,7 @@ static void selfVerificationBranchInsert(LIR *currentLIR, ArmOpCode opCode, static void selfVerificationBranchInsertPass(CompilationUnit *cUnit) { ArmLIR *thisLIR; - TemplateOpCode opCode = TEMPLATE_MEM_OP_DECODE; + TemplateOpcode opcode = TEMPLATE_MEM_OP_DECODE; for (thisLIR = (ArmLIR *) cUnit->firstLIRInsn; thisLIR != (ArmLIR *) cUnit->lastLIRInsn; @@ -225,11 +224,11 @@ static void selfVerificationBranchInsertPass(CompilationUnit *cUnit) if (thisLIR->branchInsertSV) { /* Branch to mem op decode template */ selfVerificationBranchInsert((LIR *) thisLIR, kThumbBlx1, - (int) gDvmJit.codeCache + templateEntryOffsets[opCode], - (int) gDvmJit.codeCache + templateEntryOffsets[opCode]); + (int) gDvmJit.codeCache + templateEntryOffsets[opcode], + (int) gDvmJit.codeCache + templateEntryOffsets[opcode]); selfVerificationBranchInsert((LIR *) thisLIR, kThumbBlx2, - (int) gDvmJit.codeCache + templateEntryOffsets[opCode], - (int) gDvmJit.codeCache + templateEntryOffsets[opCode]); + (int) gDvmJit.codeCache + templateEntryOffsets[opcode], + (int) gDvmJit.codeCache + templateEntryOffsets[opcode]); } } } @@ -318,7 +317,7 @@ static void genIGet(CompilationUnit *cUnit, MIR *mir, OpSize size, size, rlObj.sRegLow); HEAP_ACCESS_SHADOW(false); if (isVolatile) { - dvmCompilerGenMemBarrier(cUnit); + dvmCompilerGenMemBarrier(cUnit, kSY); } storeValue(cUnit, rlDest, rlResult); @@ -340,7 +339,7 @@ static void genIPut(CompilationUnit *cUnit, MIR *mir, OpSize size, NULL);/* null object? */ if (isVolatile) { - dvmCompilerGenMemBarrier(cUnit); + dvmCompilerGenMemBarrier(cUnit, kSY); } HEAP_ACCESS_SHADOW(true); storeBaseDisp(cUnit, rlObj.lowReg, fieldOffset, rlSrc.lowReg, size); @@ -541,8 +540,7 @@ static void genArrayObjectPut(CompilationUnit *cUnit, MIR *mir, LOAD_FUNC_ADDR(cUnit, r2, (int)dvmCanPutArrayElement); /* Are we storing null? If so, avoid check */ - opRegImm(cUnit, kOpCmp, r0, 0); - ArmLIR *branchOver = opCondBranch(cUnit, kArmCondEq); + ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondEq, r0, 0); /* Make sure the types are compatible */ loadWordDisp(cUnit, regArray, offsetof(Object, clazz), r1); @@ -595,7 +593,7 @@ static bool genShiftOpLong(CompilationUnit *cUnit, MIR *mir, loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1); loadValueDirect(cUnit, rlShift, r2); - switch( mir->dalvikInsn.opCode) { + switch( mir->dalvikInsn.opcode) { case OP_SHL_LONG: case OP_SHL_LONG_2ADDR: genDispatchToHandler(cUnit, TEMPLATE_SHL_LONG); @@ -627,7 +625,7 @@ static bool genArithOpLong(CompilationUnit *cUnit, MIR *mir, void *callTgt; int retReg = r0; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_NOT_LONG: rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg); rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true); @@ -727,7 +725,7 @@ static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir, RegLocation rlResult; bool shiftOp = false; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_NEG_INT: op = kOpNeg; unary = true; @@ -792,7 +790,7 @@ static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir, break; default: LOGE("Invalid word arith op: 0x%x(%d)", - mir->dalvikInsn.opCode, mir->dalvikInsn.opCode); + mir->dalvikInsn.opcode, mir->dalvikInsn.opcode); dvmCompilerAbort(cUnit); } if (!callOut) { @@ -839,7 +837,7 @@ static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir, static bool genArithOp(CompilationUnit *cUnit, MIR *mir) { - OpCode opCode = mir->dalvikInsn.opCode; + Opcode opcode = mir->dalvikInsn.opcode; RegLocation rlDest; RegLocation rlSrc1; RegLocation rlSrc2; @@ -862,34 +860,34 @@ static bool genArithOp(CompilationUnit *cUnit, MIR *mir) rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1); } - if ((opCode >= OP_ADD_LONG_2ADDR) && (opCode <= OP_XOR_LONG_2ADDR)) { + if ((opcode >= OP_ADD_LONG_2ADDR) && (opcode <= OP_XOR_LONG_2ADDR)) { return genArithOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_LONG) && (opCode <= OP_XOR_LONG)) { + if ((opcode >= OP_ADD_LONG) && (opcode <= OP_XOR_LONG)) { return genArithOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_SHL_LONG_2ADDR) && (opCode <= OP_USHR_LONG_2ADDR)) { + if ((opcode >= OP_SHL_LONG_2ADDR) && (opcode <= OP_USHR_LONG_2ADDR)) { return genShiftOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_SHL_LONG) && (opCode <= OP_USHR_LONG)) { + if ((opcode >= OP_SHL_LONG) && (opcode <= OP_USHR_LONG)) { return genShiftOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_INT_2ADDR) && (opCode <= OP_USHR_INT_2ADDR)) { + if ((opcode >= OP_ADD_INT_2ADDR) && (opcode <= OP_USHR_INT_2ADDR)) { return genArithOpInt(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_INT) && (opCode <= OP_USHR_INT)) { + if ((opcode >= OP_ADD_INT) && (opcode <= OP_USHR_INT)) { return genArithOpInt(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_FLOAT_2ADDR) && (opCode <= OP_REM_FLOAT_2ADDR)) { + if ((opcode >= OP_ADD_FLOAT_2ADDR) && (opcode <= OP_REM_FLOAT_2ADDR)) { return genArithOpFloat(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_FLOAT) && (opCode <= OP_REM_FLOAT)) { + if ((opcode >= OP_ADD_FLOAT) && (opcode <= OP_REM_FLOAT)) { return genArithOpFloat(cUnit, mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_DOUBLE_2ADDR) && (opCode <= OP_REM_DOUBLE_2ADDR)) { + if ((opcode >= OP_ADD_DOUBLE_2ADDR) && (opcode <= OP_REM_DOUBLE_2ADDR)) { return genArithOpDouble(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_DOUBLE) && (opCode <= OP_REM_DOUBLE)) { + if ((opcode >= OP_ADD_DOUBLE) && (opcode <= OP_REM_DOUBLE)) { return genArithOpDouble(cUnit,mir, rlDest, rlSrc1, rlSrc2); } return true; @@ -915,7 +913,7 @@ static void genReturnCommon(CompilationUnit *cUnit, MIR *mir) ArmLIR *branch = genUnconditionalBranch(cUnit, NULL); /* Set up the place holder to reconstruct this Dalvik PC */ ArmLIR *pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true); - pcrLabel->opCode = kArmPseudoPCReconstructionCell; + pcrLabel->opcode = kArmPseudoPCReconstructionCell; pcrLabel->operands[0] = dPC; pcrLabel->operands[1] = mir->offset; /* Insert the place holder to the growable list */ @@ -1064,16 +1062,21 @@ static void genInvokeSingletonCommon(CompilationUnit *cUnit, MIR *mir, ArmLIR *retChainingCell = &labelList[bb->fallThrough->id]; /* r1 = &retChainingCell */ - dvmCompilerLockTemp(cUnit, r1); ArmLIR *addrRetChain = opRegRegImm(cUnit, kOpAdd, r1, rpc, 0); + /* r4PC = dalvikCallsite */ loadConstant(cUnit, r4PC, (int) (cUnit->method->insns + mir->offset)); addrRetChain->generic.target = (LIR *) retChainingCell; + + /* r7 = calleeMethod->registersSize */ + loadConstant(cUnit, r7, calleeMethod->registersSize); /* * r0 = calleeMethod (loaded upon calling genInvokeSingletonCommon) * r1 = &ChainingCell + * r2 = calleeMethod->outsSize (to be loaded later for Java callees) * r4PC = callsiteDPC + * r7 = calleeMethod->registersSize */ if (dvmIsNativeMethod(calleeMethod)) { genDispatchToHandler(cUnit, TEMPLATE_INVOKE_METHOD_NATIVE); @@ -1081,6 +1084,8 @@ static void genInvokeSingletonCommon(CompilationUnit *cUnit, MIR *mir, gDvmJit.invokeNative++; #endif } else { + /* For Java callees, set up r2 to be calleeMethod->outsSize */ + loadConstant(cUnit, r2, calleeMethod->outsSize); genDispatchToHandler(cUnit, TEMPLATE_INVOKE_METHOD_CHAIN); #if defined(WITH_JIT_TUNING) gDvmJit.invokeMonomorphic++; @@ -1106,7 +1111,7 @@ static void genInvokeSingletonCommon(CompilationUnit *cUnit, MIR *mir, * 0x426a99b8 : ldr r0, [r7, #44] --> r0 <- this->class->vtable[methodIdx] * 0x426a99ba : cmp r1, #0 --> compare r1 (rechain count) against 0 * 0x426a99bc : bgt 0x426a99c2 --> >=0? don't rechain - * 0x426a99be : ldr r7, [r6, #96] --+ dvmJitToPatchPredictedChain + * 0x426a99be : ldr r7, [pc, #off]--+ dvmJitToPatchPredictedChain * 0x426a99c0 : blx r7 --+ * 0x426a99c2 : add r1, pc, #12 --> r1 <- &retChainingCell * 0x426a99c4 : blx_1 0x426a9098 --+ TEMPLATE_INVOKE_METHOD_NO_OPT @@ -1152,7 +1157,7 @@ static void genInvokeVirtualCommon(CompilationUnit *cUnit, MIR *mir, if (pcrLabel == NULL) { int dPC = (int) (cUnit->method->insns + mir->offset); pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true); - pcrLabel->opCode = kArmPseudoPCReconstructionCell; + pcrLabel->opcode = kArmPseudoPCReconstructionCell; pcrLabel->operands[0] = dPC; pcrLabel->operands[1] = mir->offset; /* Insert the place holder to the growable list */ @@ -1175,12 +1180,9 @@ static void genInvokeVirtualCommon(CompilationUnit *cUnit, MIR *mir, loadWordDisp(cUnit, r7, methodIndex * 4, r0); /* Check if rechain limit is reached */ - opRegImm(cUnit, kOpCmp, r1, 0); + ArmLIR *bypassRechaining = genCmpImmBranch(cUnit, kArmCondGt, r1, 0); - ArmLIR *bypassRechaining = opCondBranch(cUnit, kArmCondGt); - - loadWordDisp(cUnit, rGLUE, offsetof(InterpState, - jitToInterpEntries.dvmJitToPatchPredictedChain), r7); + LOAD_FUNC_ADDR(cUnit, r7, (int) dvmJitToPatchPredictedChain); genRegCopy(cUnit, r1, rGLUE); @@ -1230,12 +1232,12 @@ static void genPuntToInterp(CompilationUnit *cUnit, unsigned int offset) */ static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir) { - int flags = dexGetInstrFlags(gDvm.instrFlags, mir->dalvikInsn.opCode); + int flags = dexGetFlagsFromOpcode(mir->dalvikInsn.opcode); int flagsToCheck = kInstrCanBranch | kInstrCanSwitch | kInstrCanReturn | kInstrCanThrow; //If already optimized out, just ignore - if (mir->dalvikInsn.opCode == OP_NOP) + if (mir->dalvikInsn.opcode == OP_NOP) return; //Ugly, but necessary. Flush all Dalvik regs so Interp can find them @@ -1270,7 +1272,7 @@ static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir) */ static void genMonitorPortable(CompilationUnit *cUnit, MIR *mir) { - bool isEnter = (mir->dalvikInsn.opCode == OP_MONITOR_ENTER); + bool isEnter = (mir->dalvikInsn.opcode == OP_MONITOR_ENTER); genExportPC(cUnit, mir); dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0); @@ -1280,7 +1282,7 @@ static void genMonitorPortable(CompilationUnit *cUnit, MIR *mir) if (isEnter) { /* Get dPC of next insn */ loadConstant(cUnit, r4PC, (int)(cUnit->method->insns + mir->offset + - dexGetInstrWidthAbs(gDvm.instrWidth, OP_MONITOR_ENTER))); + dexGetWidthFromOpcode(OP_MONITOR_ENTER))); #if defined(WITH_DEADLOCK_PREDICTION) genDispatchToHandler(cUnit, TEMPLATE_MONITOR_ENTER_DEBUG); #else @@ -1290,11 +1292,11 @@ static void genMonitorPortable(CompilationUnit *cUnit, MIR *mir) LOAD_FUNC_ADDR(cUnit, r2, (int)dvmUnlockObject); /* Do the call */ opReg(cUnit, kOpBlx, r2); - opRegImm(cUnit, kOpCmp, r0, 0); /* Did we throw? */ - ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe); + /* Did we throw? */ + ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0); loadConstant(cUnit, r0, (int) (cUnit->method->insns + mir->offset + - dexGetInstrWidthAbs(gDvm.instrWidth, OP_MONITOR_EXIT))); + dexGetWidthFromOpcode(OP_MONITOR_EXIT))); genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON); ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel); target->defMask = ENCODE_ALL; @@ -1320,21 +1322,23 @@ static bool handleFmt10t_Fmt20t_Fmt30t(CompilationUnit *cUnit, MIR *mir, static bool handleFmt10x(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; - if ((dalvikOpCode >= OP_UNUSED_3E) && (dalvikOpCode <= OP_UNUSED_43)) { - LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpCode); + Opcode dalvikOpcode = mir->dalvikInsn.opcode; + if ((dalvikOpcode >= OP_UNUSED_3E) && (dalvikOpcode <= OP_UNUSED_43)) { + LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpcode); return true; } - switch (dalvikOpCode) { + switch (dalvikOpcode) { + case OP_RETURN_VOID_BARRIER: + dvmCompilerGenMemBarrier(cUnit, kST); + // Intentional fallthrough case OP_RETURN_VOID: genReturnCommon(cUnit,mir); break; case OP_UNUSED_73: case OP_UNUSED_79: case OP_UNUSED_7A: - case OP_UNUSED_F1: - case OP_UNUSED_FF: - LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpCode); + case OP_DISPATCH_FF: + LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpcode); return true; case OP_NOP: break; @@ -1354,7 +1358,7 @@ static bool handleFmt11n_Fmt31i(CompilationUnit *cUnit, MIR *mir) rlDest = dvmCompilerGetDest(cUnit, mir, 0); } - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_CONST: case OP_CONST_4: { rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true); @@ -1389,7 +1393,7 @@ static bool handleFmt21h(CompilationUnit *cUnit, MIR *mir) } rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true); - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_CONST_HIGH16: { loadConstantNoClobber(cUnit, rlResult.lowReg, mir->dalvikInsn.vB << 16); @@ -1421,7 +1425,7 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir) RegLocation rlDest; RegLocation rlSrc; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_CONST_STRING_JUMBO: case OP_CONST_STRING: { void *strPtr = (void*) @@ -1474,8 +1478,8 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir) dvmAbort(); } - isVolatile = (mir->dalvikInsn.opCode == OP_SGET_VOLATILE) || - (mir->dalvikInsn.opCode == OP_SGET_OBJECT_VOLATILE) || + isVolatile = (mir->dalvikInsn.opcode == OP_SGET_VOLATILE) || + (mir->dalvikInsn.opcode == OP_SGET_OBJECT_VOLATILE) || dvmIsVolatileField(fieldPtr); rlDest = dvmCompilerGetDest(cUnit, mir, 0); @@ -1483,7 +1487,7 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir) loadConstant(cUnit, tReg, (int) fieldPtr + valOffset); if (isVolatile) { - dvmCompilerGenMemBarrier(cUnit); + dvmCompilerGenMemBarrier(cUnit, kSY); } HEAP_ACCESS_SHADOW(true); loadWordDisp(cUnit, tReg, 0, rlResult.lowReg); @@ -1534,12 +1538,12 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir) void *fieldPtr = (void*) (method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]); - isVolatile = (mir->dalvikInsn.opCode == OP_SPUT_VOLATILE) || - (mir->dalvikInsn.opCode == OP_SPUT_OBJECT_VOLATILE) || + isVolatile = (mir->dalvikInsn.opcode == OP_SPUT_VOLATILE) || + (mir->dalvikInsn.opcode == OP_SPUT_OBJECT_VOLATILE) || dvmIsVolatileField(fieldPtr); - isSputObject = (mir->dalvikInsn.opCode == OP_SPUT_OBJECT) || - (mir->dalvikInsn.opCode == OP_SPUT_OBJECT_VOLATILE); + isSputObject = (mir->dalvikInsn.opcode == OP_SPUT_OBJECT) || + (mir->dalvikInsn.opcode == OP_SPUT_OBJECT_VOLATILE); if (fieldPtr == NULL) { LOGE("Unexpected null static field"); @@ -1558,7 +1562,7 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir) dvmCompilerFreeTemp(cUnit, tReg); HEAP_ACCESS_SHADOW(false); if (isVolatile) { - dvmCompilerGenMemBarrier(cUnit); + dvmCompilerGenMemBarrier(cUnit, kSY); } if (isSputObject) { /* NOTE: marking card based sfield->clazz */ @@ -1616,8 +1620,7 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir) opReg(cUnit, kOpBlx, r2); dvmCompilerClobberCallRegs(cUnit); /* generate a branch over if allocation is successful */ - opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */ - ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe); + ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0); /* * OOM exception needs to be thrown here and cannot re-execute */ @@ -1658,8 +1661,9 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir) loadConstant(cUnit, r1, (int) classPtr ); rlSrc = dvmCompilerGetSrc(cUnit, mir, 0); rlSrc = loadValue(cUnit, rlSrc, kCoreReg); - opRegImm(cUnit, kOpCmp, rlSrc.lowReg, 0); /* Null? */ - ArmLIR *branch1 = opCondBranch(cUnit, kArmCondEq); + /* Null? */ + ArmLIR *branch1 = genCmpImmBranch(cUnit, kArmCondEq, + rlSrc.lowReg, 0); /* * rlSrc.lowReg now contains object->clazz. Note that * it could have been allocated r0, but we're okay so long @@ -1713,9 +1717,9 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir) */ static bool handleFmt11x(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; RegLocation rlResult; - switch (dalvikOpCode) { + switch (dalvikOpcode) { case OP_MOVE_EXCEPTION: { int offset = offsetof(InterpState, self); int exOffset = offsetof(Thread, exception); @@ -1788,12 +1792,12 @@ static bool handleFmt11x(CompilationUnit *cUnit, MIR *mir) static bool handleFmt12x(CompilationUnit *cUnit, MIR *mir) { - OpCode opCode = mir->dalvikInsn.opCode; + Opcode opcode = mir->dalvikInsn.opcode; RegLocation rlDest; RegLocation rlSrc; RegLocation rlResult; - if ( (opCode >= OP_ADD_INT_2ADDR) && (opCode <= OP_REM_DOUBLE_2ADDR)) { + if ( (opcode >= OP_ADD_INT_2ADDR) && (opcode <= OP_REM_DOUBLE_2ADDR)) { return genArithOp( cUnit, mir ); } @@ -1806,7 +1810,7 @@ static bool handleFmt12x(CompilationUnit *cUnit, MIR *mir) else rlDest = dvmCompilerGetDest(cUnit, mir, 0); - switch (opCode) { + switch (opcode) { case OP_DOUBLE_TO_INT: case OP_INT_TO_FLOAT: case OP_FLOAT_TO_INT: @@ -1889,18 +1893,18 @@ static bool handleFmt12x(CompilationUnit *cUnit, MIR *mir) static bool handleFmt21s(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; RegLocation rlDest; RegLocation rlResult; int BBBB = mir->dalvikInsn.vB; - if (dalvikOpCode == OP_CONST_WIDE_16) { + if (dalvikOpcode == OP_CONST_WIDE_16) { rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1); rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true); loadConstantNoClobber(cUnit, rlResult.lowReg, BBBB); //TUNING: do high separately to avoid load dependency opRegRegImm(cUnit, kOpAsr, rlResult.highReg, rlResult.lowReg, 31); storeValueWide(cUnit, rlDest, rlResult); - } else if (dalvikOpCode == OP_CONST_16) { + } else if (dalvikOpcode == OP_CONST_16) { rlDest = dvmCompilerGetDest(cUnit, mir, 0); rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true); loadConstantNoClobber(cUnit, rlResult.lowReg, BBBB); @@ -1914,14 +1918,14 @@ static bool handleFmt21s(CompilationUnit *cUnit, MIR *mir) static bool handleFmt21t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, ArmLIR *labelList) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; ArmConditionCode cond; RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0); rlSrc = loadValue(cUnit, rlSrc, kCoreReg); opRegImm(cUnit, kOpCmp, rlSrc.lowReg, 0); //TUNING: break this out to allow use of Thumb2 CB[N]Z - switch (dalvikOpCode) { + switch (dalvikOpcode) { case OP_IF_EQZ: cond = kArmCondEq; break; @@ -1942,7 +1946,7 @@ static bool handleFmt21t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, break; default: cond = 0; - LOGE("Unexpected opcode (%d) for Fmt21t\n", dalvikOpCode); + LOGE("Unexpected opcode (%d) for Fmt21t\n", dalvikOpcode); dvmCompilerAbort(cUnit); } genConditionalBranch(cUnit, cond, &labelList[bb->taken->id]); @@ -1979,7 +1983,7 @@ static int lowestSetBit(unsigned int x) { // Returns true if it added instructions to 'cUnit' to divide 'rlSrc' by 'lit' // and store the result in 'rlDest'. -static bool handleEasyDivide(CompilationUnit *cUnit, OpCode dalvikOpCode, +static bool handleEasyDivide(CompilationUnit *cUnit, Opcode dalvikOpcode, RegLocation rlSrc, RegLocation rlDest, int lit) { if (lit < 2 || !isPowerOfTwo(lit)) { @@ -1990,7 +1994,7 @@ static bool handleEasyDivide(CompilationUnit *cUnit, OpCode dalvikOpCode, // Avoid special cases. return false; } - bool div = (dalvikOpCode == OP_DIV_INT_LIT8 || dalvikOpCode == OP_DIV_INT_LIT16); + bool div = (dalvikOpcode == OP_DIV_INT_LIT8 || dalvikOpcode == OP_DIV_INT_LIT16); rlSrc = loadValue(cUnit, rlSrc, kCoreReg); RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true); if (div) { @@ -2075,7 +2079,7 @@ static bool handleEasyMultiply(CompilationUnit *cUnit, static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0); RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0); RegLocation rlResult; @@ -2084,7 +2088,7 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir) int shiftOp = false; bool isDiv = false; - switch (dalvikOpCode) { + switch (dalvikOpcode) { case OP_RSUB_INT_LIT8: case OP_RSUB_INT: { int tReg; @@ -2149,14 +2153,14 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir) genInterpSingleStep(cUnit, mir); return false; } - if (handleEasyDivide(cUnit, dalvikOpCode, rlSrc, rlDest, lit)) { + if (handleEasyDivide(cUnit, dalvikOpcode, rlSrc, rlDest, lit)) { return false; } dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */ loadValueDirectFixed(cUnit, rlSrc, r0); dvmCompilerClobber(cUnit, r0); - if ((dalvikOpCode == OP_DIV_INT_LIT8) || - (dalvikOpCode == OP_DIV_INT_LIT16)) { + if ((dalvikOpcode == OP_DIV_INT_LIT8) || + (dalvikOpcode == OP_DIV_INT_LIT16)) { LOAD_FUNC_ADDR(cUnit, r2, (int)__aeabi_idiv); isDiv = true; } else { @@ -2190,10 +2194,10 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir) static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; int fieldOffset = -1; bool isVolatile = false; - switch (dalvikOpCode) { + switch (dalvikOpcode) { /* * Wide volatiles currently handled via single step. * Add them here if generating in-line code. @@ -2235,7 +2239,7 @@ static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir) break; } - switch (dalvikOpCode) { + switch (dalvikOpcode) { case OP_NEW_ARRAY: { // Generates a call - use explicit registers RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0); @@ -2263,8 +2267,7 @@ static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir) opReg(cUnit, kOpBlx, r3); dvmCompilerClobberCallRegs(cUnit); /* generate a branch over if allocation is successful */ - opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */ - ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe); + ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0); /* * OOM exception needs to be thrown here and cannot re-execute */ @@ -2303,10 +2306,8 @@ static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir) dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */ loadValueDirectFixed(cUnit, rlSrc, r0); /* Ref */ loadConstant(cUnit, r2, (int) classPtr ); -//TUNING: compare to 0 primative to allow use of CB[N]Z - opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */ /* When taken r0 has NULL which can be used for store directly */ - ArmLIR *branch1 = opCondBranch(cUnit, kArmCondEq); + ArmLIR *branch1 = genCmpImmBranch(cUnit, kArmCondEq, r0, 0); /* r1 now contains object->clazz */ loadWordDisp(cUnit, r0, offsetof(Object, clazz), r1); /* r1 now contains object->clazz */ @@ -2371,9 +2372,9 @@ static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir) static bool handleFmt22cs(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; int fieldOffset = mir->dalvikInsn.vC; - switch (dalvikOpCode) { + switch (dalvikOpcode) { case OP_IGET_QUICK: case OP_IGET_OBJECT_QUICK: genIGet(cUnit, mir, kWord, fieldOffset, false); @@ -2401,7 +2402,7 @@ static bool handleFmt22cs(CompilationUnit *cUnit, MIR *mir) static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, ArmLIR *labelList) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; ArmConditionCode cond; RegLocation rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0); RegLocation rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1); @@ -2410,7 +2411,7 @@ static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg); opRegReg(cUnit, kOpCmp, rlSrc1.lowReg, rlSrc2.lowReg); - switch (dalvikOpCode) { + switch (dalvikOpcode) { case OP_IF_EQ: cond = kArmCondEq; break; @@ -2431,7 +2432,7 @@ static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, break; default: cond = 0; - LOGE("Unexpected opcode (%d) for Fmt22t\n", dalvikOpCode); + LOGE("Unexpected opcode (%d) for Fmt22t\n", dalvikOpcode); dvmCompilerAbort(cUnit); } genConditionalBranch(cUnit, cond, &labelList[bb->taken->id]); @@ -2442,9 +2443,9 @@ static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, static bool handleFmt22x_Fmt32x(CompilationUnit *cUnit, MIR *mir) { - OpCode opCode = mir->dalvikInsn.opCode; + Opcode opcode = mir->dalvikInsn.opcode; - switch (opCode) { + switch (opcode) { case OP_MOVE_16: case OP_MOVE_OBJECT_16: case OP_MOVE_FROM16: @@ -2467,12 +2468,12 @@ static bool handleFmt22x_Fmt32x(CompilationUnit *cUnit, MIR *mir) static bool handleFmt23x(CompilationUnit *cUnit, MIR *mir) { - OpCode opCode = mir->dalvikInsn.opCode; + Opcode opcode = mir->dalvikInsn.opcode; RegLocation rlSrc1; RegLocation rlSrc2; RegLocation rlDest; - if ( (opCode >= OP_ADD_INT) && (opCode <= OP_REM_DOUBLE)) { + if ( (opcode >= OP_ADD_INT) && (opcode <= OP_REM_DOUBLE)) { return genArithOp( cUnit, mir ); } @@ -2507,7 +2508,7 @@ static bool handleFmt23x(CompilationUnit *cUnit, MIR *mir) } - switch (opCode) { + switch (opcode) { case OP_CMPL_FLOAT: case OP_CMPG_FLOAT: case OP_CMPL_DOUBLE: @@ -2690,8 +2691,8 @@ static s8 findSparseSwitchIndex(const u2* switchData, int testVal, int pc) static bool handleFmt31t(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; - switch (dalvikOpCode) { + Opcode dalvikOpcode = mir->dalvikInsn.opcode; + switch (dalvikOpcode) { case OP_FILL_ARRAY_DATA: { RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0); // Making a call - use explicit registers @@ -2704,8 +2705,7 @@ static bool handleFmt31t(CompilationUnit *cUnit, MIR *mir) opReg(cUnit, kOpBlx, r2); dvmCompilerClobberCallRegs(cUnit); /* generate a branch over if successful */ - opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */ - ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe); + ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0); loadConstant(cUnit, r0, (int) (cUnit->method->insns + mir->offset)); genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON); @@ -2725,7 +2725,7 @@ static bool handleFmt31t(CompilationUnit *cUnit, MIR *mir) dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */ loadValueDirectFixed(cUnit, rlSrc, r1); dvmCompilerLockAllTemps(cUnit); - if (dalvikOpCode == OP_PACKED_SWITCH) { + if (dalvikOpcode == OP_PACKED_SWITCH) { LOAD_FUNC_ADDR(cUnit, r4PC, (int)findPackedSwitchIndex); } else { LOAD_FUNC_ADDR(cUnit, r4PC, (int)findSparseSwitchIndex); @@ -2792,7 +2792,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, retChainingCell = &labelList[bb->fallThrough->id]; DecodedInstruction *dInsn = &mir->dalvikInsn; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { /* * calleeMethod = this->clazz->vtable[ * method->clazz->pDvmDex->pResMethods[BBBB]->methodIndex @@ -2814,7 +2814,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList); } - if (mir->dalvikInsn.opCode == OP_INVOKE_VIRTUAL) + if (mir->dalvikInsn.opcode == OP_INVOKE_VIRTUAL) genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel); else genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel); @@ -2837,7 +2837,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, cUnit->method->clazz->pDvmDex-> pResMethods[dInsn->vB]->methodIndex]); - if (mir->dalvikInsn.opCode == OP_INVOKE_SUPER) + if (mir->dalvikInsn.opcode == OP_INVOKE_SUPER) genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel); else genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel); @@ -2857,7 +2857,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, assert(calleeMethod == cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]); - if (mir->dalvikInsn.opCode == OP_INVOKE_DIRECT) + if (mir->dalvikInsn.opcode == OP_INVOKE_DIRECT) genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel); else genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel); @@ -2877,7 +2877,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, assert(calleeMethod == cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]); - if (mir->dalvikInsn.opCode == OP_INVOKE_STATIC) + if (mir->dalvikInsn.opcode == OP_INVOKE_STATIC) genProcessArgsNoRange(cUnit, mir, dInsn, NULL /* no null check */); else @@ -2928,7 +2928,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, * 0x47357e6e : mov r1, r8 --> r1 <- &retChainingCell * 0x47357e70 : cmp r1, #0 --> compare against 0 * 0x47357e72 : bgt 0x47357e7c --> >=0? don't rechain - * 0x47357e74 : ldr r7, [r6, #108] --+ + * 0x47357e74 : ldr r7, [pc, #off] --+ * 0x47357e76 : mov r2, r9 | dvmJitToPatchPredictedChain * 0x47357e78 : mov r3, r10 | * 0x47357e7a : blx r7 --+ @@ -2975,7 +2975,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList); } - if (mir->dalvikInsn.opCode == OP_INVOKE_INTERFACE) + if (mir->dalvikInsn.opcode == OP_INVOKE_INTERFACE) genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel); else genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel); @@ -3008,7 +3008,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, if (pcrLabel == NULL) { int dPC = (int) (cUnit->method->insns + mir->offset); pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true); - pcrLabel->opCode = kArmPseudoPCReconstructionCell; + pcrLabel->opcode = kArmPseudoPCReconstructionCell; pcrLabel->operands[0] = dPC; pcrLabel->operands[1] = mir->offset; /* Insert the place holder to the growable list */ @@ -3051,8 +3051,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, dvmCompilerClobberCallRegs(cUnit); /* generate a branch over if the interface method is resolved */ - opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */ - ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe); + ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0); /* * calleeMethod == NULL -> throw */ @@ -3068,12 +3067,10 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, genRegCopy(cUnit, r1, r8); /* Check if rechain limit is reached */ - opRegImm(cUnit, kOpCmp, r1, 0); - - ArmLIR *bypassRechaining = opCondBranch(cUnit, kArmCondGt); + ArmLIR *bypassRechaining = genCmpImmBranch(cUnit, kArmCondGt, + r1, 0); - loadWordDisp(cUnit, rGLUE, offsetof(InterpState, - jitToInterpEntries.dvmJitToPatchPredictedChain), r7); + LOAD_FUNC_ADDR(cUnit, r7, (int) dvmJitToPatchPredictedChain); genRegCopy(cUnit, r1, rGLUE); genRegCopy(cUnit, r2, r9); @@ -3128,8 +3125,6 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, static bool handleFmt35ms_3rms(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, ArmLIR *labelList) { - ArmLIR *retChainingCell = &labelList[bb->fallThrough->id]; - ArmLIR *predChainingCell = &labelList[bb->taken->id]; ArmLIR *pcrLabel = NULL; /* An invoke with the MIR_INLINED is effectively a no-op */ @@ -3137,11 +3132,13 @@ static bool handleFmt35ms_3rms(CompilationUnit *cUnit, MIR *mir, return false; DecodedInstruction *dInsn = &mir->dalvikInsn; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { /* calleeMethod = this->clazz->vtable[BBBB] */ case OP_INVOKE_VIRTUAL_QUICK_RANGE: case OP_INVOKE_VIRTUAL_QUICK: { int methodIndex = dInsn->vB; + ArmLIR *retChainingCell = &labelList[bb->fallThrough->id]; + ArmLIR *predChainingCell = &labelList[bb->taken->id]; /* * If the invoke has non-null misPredBranchOver, we need to generate @@ -3152,7 +3149,7 @@ static bool handleFmt35ms_3rms(CompilationUnit *cUnit, MIR *mir, genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList); } - if (mir->dalvikInsn.opCode == OP_INVOKE_VIRTUAL_QUICK) + if (mir->dalvikInsn.opcode == OP_INVOKE_VIRTUAL_QUICK) genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel); else genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel); @@ -3171,7 +3168,7 @@ static bool handleFmt35ms_3rms(CompilationUnit *cUnit, MIR *mir, assert(calleeMethod == cUnit->method->clazz->super->vtable[dInsn->vB]); - if (mir->dalvikInsn.opCode == OP_INVOKE_SUPER_QUICK) + if (mir->dalvikInsn.opcode == OP_INVOKE_SUPER_QUICK) genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel); else genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel); @@ -3367,7 +3364,7 @@ static bool genInlinedLongDoubleConversion(CompilationUnit *cUnit, MIR *mir) static bool handleExecuteInline(CompilationUnit *cUnit, MIR *mir) { DecodedInstruction *dInsn = &mir->dalvikInsn; - switch( mir->dalvikInsn.opCode) { + switch( mir->dalvikInsn.opcode) { case OP_EXECUTE_INLINE_RANGE: case OP_EXECUTE_INLINE: { unsigned int i; @@ -3444,8 +3441,8 @@ static bool handleExecuteInline(CompilationUnit *cUnit, MIR *mir) } opReg(cUnit, kOpBlx, r4PC); opRegImm(cUnit, kOpAdd, r13, 8); - opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */ - ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe); + /* NULL? */ + ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0); loadConstant(cUnit, r0, (int) (cUnit->method->insns + mir->offset)); genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON); @@ -3832,13 +3829,13 @@ static void genValidationForPredictedInline(CompilationUnit *cUnit, MIR *mir) /* Extended MIR instructions like PHI */ static void handleExtendedMIR(CompilationUnit *cUnit, MIR *mir) { - int opOffset = mir->dalvikInsn.opCode - kMirOpFirst; + int opOffset = mir->dalvikInsn.opcode - kMirOpFirst; char *msg = dvmCompilerNew(strlen(extendedMIROpNames[opOffset]) + 1, false); strcpy(msg, extendedMIROpNames[opOffset]); newLIR1(cUnit, kArmPseudoExtended, (int) msg); - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case kMirOpPhi: { char *ssaString = dvmCompilerGetSSAString(cUnit, mir->ssaRep); newLIR1(cUnit, kArmPseudoSSARep, (int) ssaString); @@ -3882,7 +3879,7 @@ static void setupLoopEntryBlock(CompilationUnit *cUnit, BasicBlock *entry, { /* Set up the place holder to reconstruct this Dalvik PC */ ArmLIR *pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true); - pcrLabel->opCode = kArmPseudoPCReconstructionCell; + pcrLabel->opcode = kArmPseudoPCReconstructionCell; pcrLabel->operands[0] = (int) (cUnit->method->insns + entry->startOffset); pcrLabel->operands[1] = entry->startOffset; @@ -3894,13 +3891,13 @@ static void setupLoopEntryBlock(CompilationUnit *cUnit, BasicBlock *entry, * other branch to the PCR cell to punt. */ ArmLIR *branchToBody = dvmCompilerNew(sizeof(ArmLIR), true); - branchToBody->opCode = kThumbBUncond; + branchToBody->opcode = kThumbBUncond; branchToBody->generic.target = (LIR *) bodyLabel; setupResourceMasks(branchToBody); cUnit->loopAnalysis->branchToBody = (LIR *) branchToBody; ArmLIR *branchToPCR = dvmCompilerNew(sizeof(ArmLIR), true); - branchToPCR->opCode = kThumbBUncond; + branchToPCR->opcode = kThumbBUncond; branchToPCR->generic.target = (LIR *) pcrLabel; setupResourceMasks(branchToPCR); cUnit->loopAnalysis->branchToPCR = (LIR *) branchToPCR; @@ -3910,7 +3907,7 @@ static void setupLoopEntryBlock(CompilationUnit *cUnit, BasicBlock *entry, static bool selfVerificationPuntOps(MIR *mir) { DecodedInstruction *decInsn = &mir->dalvikInsn; - OpCode op = decInsn->opCode; + Opcode op = decInsn->opcode; /* * All opcodes that can throw exceptions and use the @@ -3996,7 +3993,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) } if (blockList[i]->blockType == kTraceEntryBlock) { - labelList[i].opCode = kArmPseudoEntryBlock; + labelList[i].opcode = kArmPseudoEntryBlock; if (blockList[i]->firstMIRInsn == NULL) { continue; } else { @@ -4004,10 +4001,10 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) &labelList[blockList[i]->fallThrough->id]); } } else if (blockList[i]->blockType == kTraceExitBlock) { - labelList[i].opCode = kArmPseudoExitBlock; + labelList[i].opcode = kArmPseudoExitBlock; goto gen_fallthrough; } else if (blockList[i]->blockType == kDalvikByteCode) { - labelList[i].opCode = kArmPseudoNormalBlockLabel; + labelList[i].opcode = kArmPseudoNormalBlockLabel; /* Reset the register state */ dvmCompilerResetRegPool(cUnit); dvmCompilerClobberAllRegs(cUnit); @@ -4015,13 +4012,13 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) } else { switch (blockList[i]->blockType) { case kChainingCellNormal: - labelList[i].opCode = kArmPseudoChainingCellNormal; + labelList[i].opcode = kArmPseudoChainingCellNormal; /* handle the codegen later */ dvmInsertGrowableList( &chainingListByType[kChainingCellNormal], (void *) i); break; case kChainingCellInvokeSingleton: - labelList[i].opCode = + labelList[i].opcode = kArmPseudoChainingCellInvokeSingleton; labelList[i].operands[0] = (int) blockList[i]->containingMethod; @@ -4031,7 +4028,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) (void *) i); break; case kChainingCellInvokePredicted: - labelList[i].opCode = + labelList[i].opcode = kArmPseudoChainingCellInvokePredicted; /* handle the codegen later */ dvmInsertGrowableList( @@ -4039,7 +4036,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) (void *) i); break; case kChainingCellHot: - labelList[i].opCode = + labelList[i].opcode = kArmPseudoChainingCellHot; /* handle the codegen later */ dvmInsertGrowableList( @@ -4048,13 +4045,13 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) break; case kPCReconstruction: /* Make sure exception handling block is next */ - labelList[i].opCode = + labelList[i].opcode = kArmPseudoPCReconstructionBlockLabel; assert (i == cUnit->numBlocks - 2); handlePCReconstruction(cUnit, &labelList[i+1]); break; case kExceptionHandling: - labelList[i].opCode = kArmPseudoEHBlockLabel; + labelList[i].opcode = kArmPseudoEHBlockLabel; if (cUnit->pcReconstructionList.numUsed) { loadWordDisp(cUnit, rGLUE, offsetof(InterpState, jitToInterpEntries.dvmJitToInterpPunt), @@ -4064,7 +4061,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) break; #if defined(WITH_SELF_VERIFICATION) || defined(WITH_JIT_TUNING) case kChainingCellBackwardBranch: - labelList[i].opCode = + labelList[i].opcode = kArmPseudoChainingCellBackwardBranch; /* handle the codegen later */ dvmInsertGrowableList( @@ -4091,15 +4088,14 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) dvmCompilerResetDefTracking(cUnit); } - if (mir->dalvikInsn.opCode >= kMirOpFirst) { + if (mir->dalvikInsn.opcode >= kMirOpFirst) { handleExtendedMIR(cUnit, mir); continue; } - OpCode dalvikOpCode = mir->dalvikInsn.opCode; - InstructionFormat dalvikFormat = - dexGetInstrFormat(gDvm.instrFormat, dalvikOpCode); + Opcode dalvikOpcode = mir->dalvikInsn.opcode; + InstructionFormat dalvikFormat = dexGetFormatFromOpcode(dalvikOpcode); char *note; if (mir->OptimizationFlags & MIR_INLINED) { note = " (I)"; @@ -4133,7 +4129,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) * Debugging: screen the opcode first to see if it is in the * do[-not]-compile list */ - bool singleStepMe = SINGLE_STEP_OP(dalvikOpCode); + bool singleStepMe = SINGLE_STEP_OP(dalvikOpcode); #if defined(WITH_SELF_VERIFICATION) if (singleStepMe == false) { singleStepMe = selfVerificationPuntOps(mir); @@ -4143,7 +4139,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) notHandled = false; genInterpSingleStep(cUnit, mir); } else { - opcodeCoverage[dalvikOpCode]++; + opcodeCoverage[dalvikOpcode]++; switch (dalvikFormat) { case kFmt10t: case kFmt20t: @@ -4215,8 +4211,8 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) notHandled = handleFmt35ms_3rms(cUnit, mir,blockList[i], labelList); break; - case kFmt3inline: - case kFmt3rinline: + case kFmt35mi: + case kFmt3rmi: notHandled = handleExecuteInline(cUnit, mir); break; case kFmt51l: @@ -4230,7 +4226,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) if (notHandled) { LOGE("%#06x: Opcode 0x%x (%s) / Fmt %d not handled\n", mir->offset, - dalvikOpCode, dexGetOpcodeName(dalvikOpCode), + dalvikOpcode, dexGetOpcodeName(dalvikOpcode), dalvikFormat); dvmCompilerAbort(cUnit); break; @@ -4385,13 +4381,13 @@ void dvmCompilerArchDump(void) streak = i = 0; buf[0] = 0; - while (opcodeCoverage[i] == 0 && i < 256) { + while (opcodeCoverage[i] == 0 && i < kNumPackedOpcodes) { i++; } - if (i == 256) { + if (i == kNumPackedOpcodes) { return; } - for (start = i++, streak = 1; i < 256; i++) { + for (start = i++, streak = 1; i < kNumPackedOpcodes; i++) { if (opcodeCoverage[i]) { streak++; } else { @@ -4401,10 +4397,10 @@ void dvmCompilerArchDump(void) sprintf(buf+strlen(buf), "%x-%x,", start, start + streak - 1); } streak = 0; - while (opcodeCoverage[i] == 0 && i < 256) { + while (opcodeCoverage[i] == 0 && i < kNumPackedOpcodes) { i++; } - if (i < 256) { + if (i < kNumPackedOpcodes) { streak = 1; start = i; } @@ -4428,9 +4424,9 @@ bool dvmCompilerArchInit() int i; for (i = 0; i < kArmLast; i++) { - if (EncodingMap[i].opCode != i) { + if (EncodingMap[i].opcode != i) { LOGE("Encoding order for %s is wrong: expecting %d, seeing %d", - EncodingMap[i].name, i, EncodingMap[i].opCode); + EncodingMap[i].name, i, EncodingMap[i].opcode); dvmAbort(); // OK to dvmAbort - build error } } |