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* GC Card marking fix for SPUT_OBJECT - use correct object headbuzbee2010-09-301-4/+4
| | | | Change-Id: I8b84a4f1e1690f5b62de7404ea6ede00317848bb
* Change GC card making to use object head, bug fix for volatile sput objbuzbee2010-09-281-5/+14
| | | | | | | | | This CL changes the way we mark GC card to consistently use the object head (previously, we marked somewhere in the object - often the head, but not always). Also, previously a coding error caused us to skip the card mark for OP_APUT_OBJECT_VOLATILES. Fixed here. Change-Id: I133ef6395c51a0466c9708209b08e79c3083aff2
* JIT: Fix inconsistent handling of sub-word instance git/putbuzbee2010-09-091-19/+5
| | | | | | | | | | | | The portable interpreter and fast interpreter use 32-bit accesses for all sub-word scalars. The JIT generated code to tailor the access to the data size. It doesn't matter which approach is taken, but all interpreters & JIT must be consistent. Changing the JIT to use 32-bit accesses for all sub-word instance scalars. Fix for Issue 2973137 Change-Id: I8b1e9e6be075012c7c174728b77c7a76884975b7
* Correct Volatile SGET/SPUT format tag, add missing cases for JITbuzbee2010-09-031-0/+2
| | | | | | | | | | | | Fix for http://b/issue?id=2971877, which was identified via debug tracing on http://b/issue?id=2971569. There were a couple of problems: first, the volatile sget/sput byte codes had the wrong format tag (22c instead of 21c). Second, the JIT was missing a couple of case statments to handle these. As far as the JIT goes, this would not have caused correctness problems, but would have been slower than necessary. Change-Id: I57a41c4e063642b0c19acba5bb0855dd8ce2d4ba
* Intrinsics for float/int and double/long conversions.Elliott Hughes2010-09-011-1/+27
| | | | | | | [cherry-picked e22bd84c8c8a57ddd86c21a1f65137d549b07935 from dalvik-dev to gingerbread] Bug: 2935622 Change-Id: Ib4de19033dc4a08f41bf0eb0f7a21dcde216aae3
* JIT: Add memory barriers on monitor enter/exit [issue 2951403]buzbee2010-08-271-0/+2
| | | | | | Possibly the cause of [2950977 error in onDraw() method for stingray] Change-Id: I3237c95a34daa75cd680b73d426dde11f3611a0e
* Make JIT inliner work under single-stepping mode.Ben Cheng2010-08-261-5/+1
| | | | | | | | Bug: 2936661 (cherry-picked from dalvik-dev) Change-Id: I35a012bd4dba2a2f9541b96a2e787687bbc7cd19
* JIT: Fix for armv5te-VFP bug [Issue 2916682]buzbee2010-08-131-20/+20
| | | | | | | Temp register was clobbered after explicit use rather than before. Affects only armv5te-vfp builds. Change-Id: I0a1c3f69a299f31bd50f3ec95ae83681b89ae6f1
* JIT: Correct conversion of cb[n]z to cmp/cond_br pairbuzbee2010-08-101-1/+1
| | | | | | | | | This fixes the regression introduced in the fast assembly retry that was causing excessive bailouts. The good news is that with this fix, we're seeing a ~5% boost in Linpack because of the cb[n]z usage. Change-Id: Ib4a48dcba809af4343456eae49a90b4a1e3aee9d
* Print callee information in the JIT profile outoutBen Cheng2010-08-061-0/+19
| | | | | | | | | | | For example: TRACEPROFILE 0x48bbb2d4 11057 0.55% [0x45d(+1), 14011] ... -> Ljava/util/HashMap$HashIterator;hasNext;()Z It means the trace ends with a call to hasNext(), and inlining probably won't help the overall performance more than 0.55%. Change-Id: I9bf2a79c48d6cb569a9fe2e329022edf968664bb
* JIT: Fix for lightweight assembler retry mechanism.buzbee2010-08-061-6/+1
| | | | | | | | | | Removed a special path in the assembler that took in sideband info on some instructions and used it to modify pc-relative load addresses. This mechanism (used in some older chaining cells) is no longer needed, and was causing a problem for the new lightweight assembler retry mechanism. Change-Id: I1cca5b719bcdea0810831d889ebe2f935c61966f
* JIT: Fix for 2898397 assert in JIT (chain cell offset)buzbee2010-08-061-0/+2
| | | | | | | | My previous change to allow for lightweight assembler retries neglected to restore a sanity check cookie when re-assembling without fully rebuilding the trace. Change-Id: Ief7eb76263e272b9cd79345f8344bd35926f5b10
* More SMP fixes.Andy McFadden2010-08-061-2/+2
| | | | | | | | | | | Convert some ANDROID_MEMBAR_FULL uses into equivalent atomic ops. A couple of "bool" had to convert to "int" since we don't have atomic ops for bools. Replaced a local implementation of atomic inc with a call to the atomic inc function. Change-Id: I948b8080d743552bde014d3a6e716ed2c30ebef8
* JIT: Support for shift field in disassembler [issue 2465170]buzbee2010-08-052-8/+23
| | | | | | | | Many Thumb2 instructions allow for an optional shift to be applied to operand 2. This cl enhances the disassembler to show a non-zero shift in the dump output. Change-Id: I6cbfec46cd45e3f2acc9553f880e80764a1eb65d
* JIT: Reworked the assembler to be smarter about short instruction formsbuzbee2010-08-044-42/+70
| | | | | | | | | | | | | | | Previously, the JIT wasn't generating short-form compare and branch on zero/not zero instructions for Thumb2. The reason was that these only allow a 1-byte displacement, and when they didn't reach the assembler would abort the trace, split it in half and try again. This change re-enables cbz, cbnz generation and introduces a relatively lightweight retry mechanism. Also includes changes for Thumb2 to always generate large displacement literal loads and conditional branches to minimize the number of retry attempts. Change-Id: Icf066836fad203f5c0fcbbb2ae8e1aa73d1cf816
* Bug fixes for JIT loop detection and formationBen Cheng2010-08-041-2/+2
| | | | | | | | | | | Specifically: - Don't apply loop optimization if the basic induction variable is manipulated (ie excluding cases like "i+=0") - Fix a case where variables reloaded with constants in the body are not considered as loop invariants Bug: 2804188 Change-Id: Ia5ebb29bc6814b1be069e23794585f8313900b7d
* am baf196a7: Fix for 2892472 jit spew: No free temp registersbuzbee2010-08-041-0/+6
|\ | | | | | | | | | | | | Merge commit 'baf196a7b259704137cccf4058b78da15d4c3998' into dalvik-dev * commit 'baf196a7b259704137cccf4058b78da15d4c3998': Fix for 2892472 jit spew: No free temp registers
| * Fix for 2892472 jit spew: No free temp registersbuzbee2010-08-041-0/+6
| | | | | | | | | | | | | | Neglected some register allocation hygene, which caused a problem on armv5te builds. Change-Id: I666b39b88822c4d3d3d7f0e84386aca2920bb9f1
* | Implement method inlining for getters/settersBen Cheng2010-08-024-42/+257
|/ | | | | | | | | | | | | | | | | | Changes include: 1) Force the trace that ends with an invoke instruction to include the next instruction if it is a move-result (because both need to be turned into no-ops if callee is inlined). 2) Interpreter entry point/trace builder changes so that return target won't automatically be considered as trace starting points (to avoid duplicate traces that include the move result instructions). 3) Codegen changes to handle getters/setters invoked from both monomorphic and polymorphic callsites. 4) Extend/fix self-verification to form identical trace regions and handle traces with inlined callees. 5) Apply touchups to the method based parsing - still not in use. Change-Id: I116b934df01bf9ada6d5a25187510e352bccd13c
* JIT: Fix for Issue 2881687 - fix volatiles and re-enable JITbuzbee2010-07-301-15/+43
| | | | Change-Id: I2ccb4b46d92b729d5504ea9c1b771a5147096858
* JIT: Support for Dalvik volatiles (issue 2781881)buzbee2010-07-219-20/+129
| | | | | | Also, on SMP systems generate memory barriers. Change-Id: If64f7c98a8de426930b8f36ac77913e53b7b2d7a
* Interpreter & JIT support for write barriersbuzbee2010-07-131-6/+42
| | | | | | | | | In this iteration, cards are marked on either the store address or the object head (whichever leads to faster code). In all cases, though, card marks are deferred until after the associated store has completed. Change-Id: I633d6e8c3bebdb80bde92efb4fa6fc7cc84f60fc
* JIT: Fix for 2813841, use core regs for sub-word dataBill Buzbee2010-07-074-15/+38
| | | | | | | | | | | In an attempt to avoid unnecessary register copies, the JIT allows data items to live in either floating point or core registers until an instruction is used which requires one or the other. The bug here was that sub-word data was allowed to live in floating point registers at the point of a load or store. This cl forces the use of core registers in those cases. Change-Id: I60c2a0d1df9a299f6c5130371f44f2be9c348ded
* Add missing ']'s in ARM disassembler output.Elliott Hughes2010-06-291-20/+20
| | | | | | Also insert missing spaces after commas in some loads and stores. Change-Id: I1dad10eb86ef8dc0d0ab4b3b98c94d3a7663861e
* Jit: Fix for 2793725 SIGSEGV in JIT code cacheBill Buzbee2010-06-231-0/+2
| | | | | | | r8 was missing from the handler clobber set, and is stepped on by the handlers for inline string compareto and indexof. Change-Id: I6e5d6f46b595d638863b27edcc8718157a3e411f
* Relocate OpCodeNames.[ch].Andy McFadden2010-06-227-7/+7
| | | | | | | The JIT was pulling it out of the dexdump directory, which is Just Plain Wrong[tm]. Now it's part of libdex, for all to enjoy. Change-Id: Ic1e4c981eb2d70ccc3c841ceb5a54f4f77af2008
* Add opcodes for volatile field accessesAndy McFadden2010-06-181-2/+3
| | | | | | | | | | | | | | | | | | | | This adds instructions for {i,s}{get,put}{,-object}-volatile, for a total of eight new instructions. On SMP systems, these instructions will be substituted in for existing field access instructions, either by dexopt or during just-in-time verification. Unlike the wide-volatile instructions, these will not be used at all when the VM is not built for SMP. (Ideally we'd omit the volatile instruction implementations entirely on non-SMP builds, but that requires a little work in gen-mterp.py.) The change defines and implements the opcodes and support methods, but does not cause them to be used. Also, changed dvmQuasiAtomicRead64's argument to be const. Change-Id: I9e44fe881e87f27aa41f6c6e898ec4402cb5493e
* Atomic op cleanup.Andy McFadden2010-06-161-1/+1
| | | | | | | | | | | | | | | Replaced VM-local macros for barrier and CAS calls with the actual versions provided by cutils. ATOMIC_CMP_SWAP(addr,old,new) --> android_atomic_release_cas(old,new,addr) MEM_BARRIER --> ANDROID_MEMBAR_FULL Renamed android_quasiatomic* to dvmQuasiAtomic*. Didn't change how anything works, just the names. Change-Id: I8c68f28e1f7c9cb832183e0918d097dfe6a2cac8
* Remove repeated newlines at the end of files.Carl Shapiro2010-06-081-1/+0
| | | | Change-Id: I1e3d103a7b932ef21acedb6438c0f26b315df28f
* Include move-result into the same trace as the invoke.Ben Cheng2010-06-021-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for method inlining implementation. Example trace: D/dalvikvm( 708): Compiler: Building trace for fibonacci, offset 0x10 D/dalvikvm( 708): 0x426b6fa8: 0x0016 const-wide/16 v0, (#2), (#0) D/dalvikvm( 708): 0x426b6fac: 0x009c sub-long v0, v7, v0 D/dalvikvm( 708): 0x426b6fb0: 0x0070 invoke-direct v6, v0, v1 D/dalvikvm( 708): 0x426b6fb6: 0x000b move-result-wide v0, (#0), (#0) D/dalvikvm( 708): TRACEINFO (3): 0x426b6f88 Lcom/android/unit_tests/PerformanceTests$FibonacciSlow;fibonacci 0x10 8 of 32, 7 blocks D/dalvikvm( 708): 7 blocks in total D/dalvikvm( 708): Block 0 (insn 0010 - 0010 empty) D/dalvikvm( 708): Fallthrough : block 1 (0010) D/dalvikvm( 708): Block 1 (insn 0010 - 0014) D/dalvikvm( 708): Taken branch: block 3 (0000) D/dalvikvm( 708): Fallthrough : block 2 (0017) D/dalvikvm( 708): Block 2 (insn 0017 - 0017) D/dalvikvm( 708): Fallthrough : block 4 (0018) D/dalvikvm( 708): Block 3 (insn 0000 - 0000 empty) D/dalvikvm( 708): Block 4 (insn 0018 - 0018 empty) D/dalvikvm( 708): Block 5 (insn 0000 - 0000 empty) D/dalvikvm( 708): Block 6 (insn 0000 - 0000 empty) Once implemented the inliner will consume the invoke-direct and move-result-wide instructions altogether. Change-Id: I4e0e6283989a468d9edf01cf26f644d2d8d7ec64
* Clean up warnings detected by gcc.Ben Cheng2010-05-2811-7/+29
| | | | | | Also re-enabled the JIT for the ARMv5te target. Change-Id: I89fd229205e30e6ee92a4933290a7d8dca001232
* Remove the write permission for the JIT code cache when not neededBen Cheng2010-05-273-129/+98
| | | | | | | | To support the feature, redesigned the predicted chaining mechanism so that the profile count is shared globally in InterpState. Bug: 2690371 Change-Id: Ifed427e8b1fa4f6c670f19e0761e45e2d4afdbb6
* Jit: Fix for 2717275 First JIT bug reported by external developersbuzbee2010-05-261-3/+9
| | | | | | | | | | | The JIT was incorrectly keeping a short value in a floating point register rather than copying it to a core register before storing. There was an assert to catch this case, but asserts don't fire in production builds. The fix is safe and simple - just exclude this case from the "optimization". Change-Id: I33767c8a202b6fa36a19d918ac5b914a5e4e4de3
* Remove unused labels, variables, and functions. Enable warnings.Carl Shapiro2010-05-219-63/+5
| | | | Change-Id: Icbe24eaf1ad499f28b68b6a5f05368271a0a7e86
* JIT: Fix for [Issue 2675245] FRF40 monkey crash in jit-cacheBill Buzbee2010-05-173-47/+66
| | | | | | | | | | | | | | | | | | | | | | | The JIT's chaining mechanism suffered from a narrow window that could result in i-cache inconsistency. One of the forms of chaining cell consisted of a two 16-bit thumb instruction sequence. If a thread were interrupted between the execution of those two instructions *and* another thread picked that moment to convert that cell's chained/unchained state, then bad things happen. This CL alters the chain/unchain model somewhat to avoid this case. Chainable chaining cells grow by 4 bytes each, and instead of rewriting a 32-bit cell to chain/unchain, we switch between chained and unchained state by [re]writing the first 16-bits of the cell as either a 16-bit Thumb unconditional branch (unchained mode) or the first half of a 32-bit Thumb branch. The 2nd 16-bits of the cell will never change once the cell moves from its inital state - thus avoiding the possibility of it becoming inconsistent. This adds a trivial execution penalty on the slow path, but will add about a kByte of memory usage to a typical process. Change-Id: Id8b99802e11386cfbab23da6abae10e2d9fc4065
* Add counters to track JIT inline cache hit rate and code cache patch counts.Ben Cheng2010-05-132-6/+20
| | | | | | Also did some WITH_JIT_TUNING cleanup. Change-Id: I8bb2d681a06b0f2af1f976a007326825a88cea38
* Abandon a JIT trace if it contains static fields that are not fully initializedBen Cheng2010-05-101-10/+51
| | | | | | | | Also turn some asserts into aborts to capture future contract changes between the VM and the JIT. Bug: 2655384 Change-Id: I8bb0226c7ae26fedf6b4ad25a1cd1aa7013b60d4
* am d1bf0ff1: am 632320c9: am 948c39d2: am ff1965e6: am 743fe2ce: Merge ↵Ben Cheng2010-05-021-58/+80
|\ | | | | | | | | | | | | | | | | "Throw an exception in JIT\'ed code if dvmFindInterfaceMethodInCache returns NULL" into froyo Merge commit 'd1bf0ff180ba3a6fbd9c668301be68de5c97f443' into dalvik-dev * commit 'd1bf0ff180ba3a6fbd9c668301be68de5c97f443': Throw an exception in JIT'ed code if dvmFindInterfaceMethodInCache returns NULL
| * Merge "Throw an exception in JIT'ed code if dvmFindInterfaceMethodInCache ↵Ben Cheng2010-05-021-58/+80
| |\ | | | | | | | | | returns NULL" into froyo
| | * Throw an exception in JIT'ed code if dvmFindInterfaceMethodInCache returns NULLBen Cheng2010-05-021-58/+80
| | | | | | | | | | | | | | | Bug: 2642019 Change-Id: Iec2be8f61388d99b1500bb144e56b86febe76c0b
* | | am 02a1acfa: am e7295d6c: am 560b3568: am 8dbde000: am 73e00c82: Merge "Fix ↵Ben Cheng2010-05-021-6/+29
|\| | | | | | | | | | | | | | | | | | | | | | | | | | a memory ordering bug when updating the inline cache for predicted chaining." into froyo Merge commit '02a1acfa7dd85f4a3db87fbd278ffd4c63a15b4a' into dalvik-dev * commit '02a1acfa7dd85f4a3db87fbd278ffd4c63a15b4a': Fix a memory ordering bug when updating the inline cache for predicted chaining.
| * | Fix a memory ordering bug when updating the inline cache for predicted chaining.Ben Cheng2010-04-301-6/+29
| |/ | | | | | | | | | | | | | | | | | | | | Also collect the statistics about fast/queued/dropped IC update. Example output: D/dalvikvm( 86): JIT: ICPatch: 603 fast, 6 queued; 0 dropped Bug: 2642019 Change-Id: I8cffdc9e422189bfd94bf845bcb2cff516f37077
* | Optimize rem-int/lit too.Elliott Hughes2010-04-281-13/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bryan hitting the bug in my div-int/lit optimization (that caused it to try to rewrite rem-int/lit too) shows that I was wrong in assuming % wasn't worth doing because it wouldn't be hot enough. Before: benchmark ns logarithmic runtime RemainderIntByConstant2 44 XXXXXXXXXXXXXXXXXXXXXXXXXXXXX RemainderIntByConstant2048 34 XXXXXXXXXXXXXXXXXXXXXX||||| RemainderIntByConstant8 44 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX RemainderIntByVariable2 40 XXXXXXXXXXXXXXXXXXXXXXXXXXX|| After: benchmark ns logarithmic runtime RemainderIntByConstant2 13 XXXXXXXXX||||||||||| RemainderIntByConstant2048 16 XXXXXXXXXXXX|||||||||| RemainderIntByConstant8 16 XXXXXXXXXXXX|||||||||| RemainderIntByVariable2 40 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Bug: 2614702 Change-Id: I719fc8765feececd5b73c3cb2e44dd3cf20c45ce
* | Don't accidentally convert % into /...Elliott Hughes2010-04-281-2/+5
| | | | | | | | | | | | | | Fix a JIT bug I introduced the other day by not paying attention to the exact dalvik opcode being optimized. Change-Id: Ic0518645a5436e2903c2a34ef46d0205f23d571b
* | Optimize idiv-int/lit for powers of 2.Elliott Hughes2010-04-261-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | before: DivideIntByConstant10 32 XXXXXXXXXXXXXXXXXXXXXXXXXXXX| DivideIntByConstant100 32 XXXXXXXXXXXXXXXXXXXXXXXXXXXX| DivideIntByConstant100_HandOptimized 34 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX DivideIntByConstant2 32 XXXXXXXXXXXXXXXXXXXXXXXXXXXX| DivideIntByConstant2048 22 XXXXXXXXXXXXXXXXXXX||||||| DivideIntByConstant8 20 XXXXXXXXXXXXXXXXX|||||||| DivideIntByVariable10 21 XXXXXXXXXXXXXXXXXX||||||| DivideIntByVariable2 21 XXXXXXXXXXXXXXXXXX||||||| after: benchmark ns logarithmic runtime DivideIntByConstant10 32 XXXXXXXXXXXXXXXXXXXXXXXXXXXXX DivideIntByConstant100 32 XXXXXXXXXXXXXXXXXXXXXXXXXXXXX DivideIntByConstant100_HandOptimized 33 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX DivideIntByConstant2 11 XXXXXXXXX||||||||||| DivideIntByConstant2048 13 XXXXXXXXXXX||||||||||| DivideIntByConstant8 13 XXXXXXXXXXX||||||||||| DivideIntByVariable10 21 XXXXXXXXXXXXXXXXXXX||||||| DivideIntByVariable2 22 XXXXXXXXXXXXXXXXXXXX|||||| Bug: 2614702 Change-Id: I9dde73d80580446a362cdcc9b82959a4b6bfb384
* | Fix supplementary character support.Elliott Hughes2010-04-121-14/+5
| | | | | | | | | | | | | | | | | | | | Fixes all known bugs in our handling of supplementary characters. This change introduces a performance regression on the assumption that it won't be released without a corresponding JIT change to enable the code to be inlined back to pretty much what it used to be. Bug: 2587122 Change-Id: I3449c9718bbe32ebe53b6c10454ae1dc82105b59
* | An InlineNative for String.isEmpty, so it's not slower than length() == 0.Elliott Hughes2010-04-082-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: benchmark ns logarithmic runtime IsEmpty 115 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX LengthEqualsZero 21 XXXXX|||||||||||||| With C intrinsic: IsEmpty 30 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX LengthEqualsZero 20 XXXXXXXXXXXXXXXXXXXX|||||| With assembler intrinsic: IsEmpty 15 XXXXXXXXXXXXXXXXXXXX|||||| LengthEqualsZero 21 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX (All times on passion.) Change-Id: Ifcc37fe7b8efdd377675a448e0085e490d6767bc
* | am 67050d11: am bd1326d0: Clean up the codegen for invoking helper callout ↵Ben Cheng2010-04-028-82/+187
|\| | | | | | | | | | | | | | | | | functions. Merge commit '67050d11e5afa7c2396bb0fc4f8d455ea2616f95' into dalvik-dev * commit '67050d11e5afa7c2396bb0fc4f8d455ea2616f95': Clean up the codegen for invoking helper callout functions.
| * Clean up the codegen for invoking helper callout functions.Ben Cheng2010-04-028-82/+187
| | | | | | | | | | | | | | All invoked functions are documented in compiler/codegen/arm/CalloutHelper.h Bug: 2567981 Change-Id: Ia7cd4107272df1b0b5588fbcc0aafcc6d0723d60
* | am 1071056d: am a497359a: Fix a race condition in JIT state refresh under ↵Ben Cheng2010-04-024-34/+34
|\| | | | | | | | | | | | | | | | | debugging / misc code cleanup. Merge commit '1071056dace973442293b718bf12e328935126f1' into dalvik-dev * commit '1071056dace973442293b718bf12e328935126f1': Fix a race condition in JIT state refresh under debugging / misc code cleanup.
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