diff options
| author | dianlujitao <dianlujitao@lineageos.org> | 2022-08-16 14:59:33 +0800 |
|---|---|---|
| committer | dianlujitao <dianlujitao@lineageos.org> | 2022-09-03 14:41:03 +0800 |
| commit | 29fc04b372427907ddae6740f35eb6e6140733e2 (patch) | |
| tree | c7410507834b711a7fa1b8c0e798e88edc245c74 | |
| parent | d0a2ae45628700e5e47e9366ff9bd8497107186d (diff) | |
nio: Decommonize NFC specifics
Change-Id: I57134c350a7a8f790732ef0558b643db72bea271
| -rw-r--r-- | device.mk | 8 | ||||
| -rw-r--r-- | nfc/libnfc-nci.conf | 111 | ||||
| -rw-r--r-- | nfc/libnfc-nxp.conf | 666 |
3 files changed, 785 insertions, 0 deletions
@@ -25,5 +25,13 @@ PRODUCT_COPY_FILES += \ PRODUCT_PACKAGES += \ init.device.rc +# NFC +PRODUCT_PACKAGES += \ + android.hardware.nfc@1.2-service + +PRODUCT_COPY_FILES += \ + $(LOCAL_PATH)/nfc/libnfc-nci.conf:$(TARGET_COPY_OUT_VENDOR)/etc/libnfc-nci.conf \ + $(LOCAL_PATH)/nfc/libnfc-nxp.conf:$(TARGET_COPY_OUT_VENDOR)/etc/libnfc-nxp.conf + # Get non-open-source specific aspects $(call inherit-product-if-exists, vendor/motorola/nio/nio-vendor.mk) diff --git a/nfc/libnfc-nci.conf b/nfc/libnfc-nci.conf new file mode 100644 index 00000000..2b6649a2 --- /dev/null +++ b/nfc/libnfc-nci.conf @@ -0,0 +1,111 @@ +############################################################################### +## Modified by Motorola Mobility LLC +## Version : common.1 (2020/06/08) +############################################################################### + +########################## Start of libnfc-nci_NCI2_0.conf ########################### +############################################################################### +# Application options +APPL_TRACE_LEVEL=0xFF +PROTOCOL_TRACE_LEVEL=0xFFFFFFFF + +NFC_DEBUG_ENABLED=0x01 + +############################################################################### +# File used for NFA storage +NFA_STORAGE="/data/nfc" + +############################################################################### +# Configure the default Destination Gate used by HCI (the default is 4, which +# is the ETSI loopback gate. +NFA_HCI_DEFAULT_DEST_GATE=0xF0 + +############################################################################### +# Force UICC to only listen to the following technology(s). +# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h. +# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B | NFA_TECHNOLOGY_MASK_F +UICC_LISTEN_TECH_MASK=0x07 + +############################################################################### +# Forcing HOST to listen for a selected protocol +# 0x00 : Disable Host Listen +# 0x01 : Enable Host to Listen (A) for ISO-DEP tech A +# 0x02 : Enable Host to Listen (B) for ISO-DEP tech B +# 0x04 : Enable Host to Listen (F) for T3T Tag Type Protocol tech F +# 0x07 : Enable Host to Listen (ABF)for ISO-DEP tech AB & T3T Tag Type Protocol tech F +HOST_LISTEN_TECH_MASK=0x07 + +############################################################################### +# Enabling/Disabling Forward functionality +# Disable 0x00 +# Enable 0x01 +NXP_FWD_FUNCTIONALITY_ENABLE=0x00 + +############################################################################### +# AID for Empty Select command +# If specified, this AID will be substituted when an Empty SELECT command is +# detected. The first byte is the length of the AID. Maximum length is 16. +AID_FOR_EMPTY_SELECT={08:A0:00:00:01:51:00:00:00} + +############################################################################### +# When screen is turned off, specify the desired power state of the controller. +# 0: power-off-sleep state; DEFAULT +# 1: full-power state +# 2: screen-off card-emulation (CE4/CE3/CE1 modes are used) +SCREEN_OFF_POWER_STATE=1 + +############################################################################### +# Default poll duration (in ms) +# The defualt is 500ms if not set (see nfc_target.h) +#NFA_DM_DISC_DURATION_POLL=333 + +############################################################################### +# Force tag polling for the following technology(s). +# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h. +# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B | +# NFA_TECHNOLOGY_MASK_F | NFA_TECHNOLOGY_MASK_ISO15693 | +# NFA_TECHNOLOGY_MASK_B_PRIME | NFA_TECHNOLOGY_MASK_KOVIO | +#NFA_TECHNOLOGY_MASK_ACTIVE +# +# Notable bits: +# NFA_TECHNOLOGY_MASK_A 0x01 /* NFC Technology A */ +# NFA_TECHNOLOGY_MASK_B 0x02 /* NFC Technology B */ +# NFA_TECHNOLOGY_MASK_F 0x04 /* NFC Technology F */ +# NFA_TECHNOLOGY_MASK_ISO15693 0x08 /* Proprietary Technology */ +# NFA_TECHNOLOGY_MASK_KOVIO 0x20 /* Proprietary Technology */ +# NFA_TECHNOLOGY_MASK_ACTIVE 0x40 /* NFC Technology Active */ +POLLING_TECH_MASK=0x6F + +############################################################################### +# Force P2P to only listen for the following technology(s). +# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h. +# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_F | +#NFA_TECHNOLOGY_MASK_ACTIVE +# +# Notable bits: +# NFA_TECHNOLOGY_MASK_A 0x01 /* NFC Technology A */ +# NFA_TECHNOLOGY_MASK_F 0x04 /* NFC Technology F */ +#NFA_TECHNOLOGY_MASK_ACTIVE 0x40 /* NFC Technology Active */ +P2P_LISTEN_TECH_MASK=0x45 + +PRESERVE_STORAGE=0x01 + +############################################################################### +# Deactivate notification wait time out in seconds used in ETSI Reader mode +# 0 - Infinite wait +NFA_DM_DISC_NTF_TIMEOUT=100 + +############################################################################### +# AID_MATCHING constants +# AID_MATCHING_EXACT_ONLY 0x00 +# AID_MATCHING_EXACT_OR_PREFIX 0x01 +# AID_MATCHING_PREFIX_ONLY 0x02 +# AID_MATCHING_EXACT_OR_SUBSET_OR_PREFIX 0x03 +AID_MATCHING_MODE=0x03 + +############################################################################### +#Set the default Felica T3T System Code : +#This settings will be used when application does not set this parameter +DEFAULT_SYS_CODE={FE:FE} + +############################################################################### diff --git a/nfc/libnfc-nxp.conf b/nfc/libnfc-nxp.conf new file mode 100644 index 00000000..22cabba2 --- /dev/null +++ b/nfc/libnfc-nxp.conf @@ -0,0 +1,666 @@ +###############################################################################
+## Modified by Motorola Mobility LLC
+## Version : nio.5 (2020/12/29)
+###############################################################################
+
+## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn547)
+## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn547)
+###############################################################################
+# Application options
+# Logging Levels
+# NXPLOG_DEFAULT_LOGLEVEL 0x01
+# ANDROID_LOG_DEBUG 0x03
+# ANDROID_LOG_WARN 0x02
+# ANDROID_LOG_ERROR 0x01
+# ANDROID_LOG_SILENT 0x00
+NXPLOG_EXTNS_LOGLEVEL=0x03
+NXPLOG_NCIHAL_LOGLEVEL=0x03
+NXPLOG_NCIX_LOGLEVEL=0x03
+NXPLOG_NCIR_LOGLEVEL=0x03
+NXPLOG_FWDNLD_LOGLEVEL=0x03
+NXPLOG_TML_LOGLEVEL=0x03
+
+###############################################################################
+# Nfc Device Node name
+NXP_NFC_DEV_NODE="/dev/nq-nci"
+
+###############################################################################
+# Extension for Mifare reader enable
+# Disabled - 0x00
+# Enabled - 0x01
+MIFARE_READER_ENABLE=0x01
+
+###############################################################################
+# Vzw Feature enable
+# Disabled - 0x00
+# Enabled - 0x01
+VZW_FEATURE_ENABLE=0x00
+
+###############################################################################
+# File name for Firmware
+NXP_FW_NAME="libpn557_fw.so"
+
+###############################################################################
+# System clock source selection configuration
+#define CLK_SRC_XTAL 1
+#define CLK_SRC_PLL 2
+NXP_SYS_CLK_SRC_SEL=0x02
+
+###############################################################################
+# System clock frequency selection configuration
+#define CLK_FREQ_13MHZ 1
+#define CLK_FREQ_19_2MHZ 2
+#define CLK_FREQ_24MHZ 3
+#define CLK_FREQ_26MHZ 4
+#define CLK_FREQ_32MHZ 5
+#define CLK_FREQ_38_4MHZ 6
+#define CLK_FREQ_52MHZ 7
+NXP_SYS_CLK_FREQ_SEL=0x02
+
+###############################################################################
+# The timeout value to be used for clock request acknowledgment
+# min value = 0x01 to max = 0x06
+NXP_SYS_CLOCK_TO_CFG=0x06
+
+###############################################################################
+# NXP proprietary settings
+NXP_ACT_PROP_EXTN={2F, 02, 00}
+
+###############################################################################
+# NFC forum profile settings
+NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00}
+
+###############################################################################
+# Standby enable settings
+# Disabled - 0x00
+# Enabled - 0x01
+# NXP_CORE_STANDBY={2F, 00, 01, 01}
+
+###############################################################################
+# NXP TVDD configurations settings
+# Allow NFCC to configure External TVDD, two configurations (1 and 2) supported,
+# out of them only one can be configured at a time.
+#supported(hardware dependancy).
+# Config 1: VUP connected to VBAT
+# Config 2: VUP connected to external 5V
+#
+NXP_EXT_TVDD_CFG=0x02
+
+###############################################################################
+#config1:SLALM, 3.3V for both RM and CM
+NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, 01, 31, 00, 00, 00, 21, 00, 10, 0C}
+
+###############################################################################
+#config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
+#monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
+NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, F2, 00, BA, 1E, 1A, 00, D0, 0C}
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+################################################################################
+# NXP RF Eval1_SLALM_CFG2_EFM_40x20 configuration settings for FW Version = 12.01.12
+#
+# A0, 35, 01, 00, RF_CLIF_CFG_BOOT
+# A0, 0D, 03, 00, 43, A0, RF_CLIF_CFG_BOOT CLIF_ANA_PBF_CONTROL_REG
+# A0, 0D, 04, 00, 42, FF, FF, RF_CLIF_CFG_BOOT CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 06, 04, 44, 00, 08, F6, 00, RF_CLIF_CFG_IDLE CLIF_ANA_RX_REG
+# A0, 0D, 06, 04, 45, 80, 40, 00, 00, RF_CLIF_CFG_IDLE CLIF_ANA_CM_CONFIG_REG
+# A0, 0D, 06, 04, 4A, 00, 00, 00, 00, RF_CLIF_CFG_IDLE CLIF_ANA_TX_SHAPE_CONTROL_REG
+# A0, 0D, 03, 04, 47, 00, RF_CLIF_CFG_IDLE CLIF_ANA_AGC_REG
+# A0, 0D, 06, 04, 35, 00, 3E, 00, 00, RF_CLIF_CFG_IDLE CLIF_AGC_INPUT_REG
+# A0, 0D, 06, 04, 33, 0F, 40, 04, 00, RF_CLIF_CFG_IDLE CLIF_AGC_CONFIG0_REG
+# A0, 0D, 03, 04, 40, 00, RF_CLIF_CFG_IDLE CLIF_ANA_NFCLD_REG
+# A0, 0D, 06, 06, 35, F4, 05, 70, 02, RF_CLIF_CFG_INITIATOR CLIF_AGC_INPUT_REG
+# A0, 0D, 06, 06, 42, F8, 40, FF, FF, RF_CLIF_CFG_INITIATOR CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 06, C2, 35, 00, 3E, 00, 03, RF_CLIF_EXT_FIELD_ON CLIF_AGC_INPUT_REG
+# A0, 0D, 06, C2, 34, F7, 7F, 10, 08, RF_CLIF_EXT_FIELD_ON CLIF_AGC_CONFIG1_REG
+# A0, 0D, 06, C2, 33, 03, 40, 04, 80, RF_CLIF_EXT_FIELD_ON CLIF_AGC_CONFIG0_REG
+# A0, 0D, 06, 08, 2D, 0D, 25, 2C, 01, RF_CLIF_CFG_TARGET CLIF_SIGPRO_RM_CONFIG1_REG
+# A0, 0D, 06, 08, 44, 04, 04, C4, 00, RF_CLIF_CFG_TARGET CLIF_ANA_RX_REG
+# A0, 0D, 06, 08, 30, 70, 00, 18, 00, RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+# A0, 0D, 06, 08, 45, 83, 60, 40, 05, RF_CLIF_CFG_TARGET CLIF_ANA_CM_CONFIG_REG
+# A0, 0D, 06, 08, 42, 00, 02, FF, FF, RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 06, 08, 16, AE, 00, 1F, 00, RF_CLIF_CFG_TARGET CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 08, 15, 00, RF_CLIF_CFG_TARGET CLIF_TX_OVERSHOOT_CONFIG_REG
+# A0, 0D, 06, 08, 37, 08, 76, 00, 00, RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG
+# A0, 0D, 06, 09, 30, 00, 00, 00, 00, RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+# A0, 0D, 06, 09, 37, 00, 00, 00, 00, RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG
+# A0, 0D, 06, 09, 42, 01, 10, FF, FF, RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 03, 72, 03, 3D, RF_CLIF_CFG_BR_106_I_TXA CLIF_TRANSCEIVE_CONTROL_REG
+# A0, 0D, 04, 72, 42, F8, 40, RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 03, 72, 16, 01, RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 72, 15, 01, RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
+# A0, 0D, 06, 72, 4A, 53, 07, 00, 1B, RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
+# A0, 0D, 03, 72, 0D, 24, RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_DATA_MOD_REG
+# A0, 0D, 03, 72, 14, 24, RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_SYMBOL23_MOD_REG
+# A0, 0D, 06, 3C, 2D, DC, 40, 04, 00, RF_CLIF_CFG_BR_106_I_RXA_P CLIF_SIGPRO_RM_CONFIG1_REG
+# A0, 0D, 06, 3C, 44, 66, 0A, 00, 00, RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG
+# A0, 0D, 06, 74, 4A, 56, 07, 01, 1B, RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
+# A0, 0D, 04, 74, 42, 68, 40, RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 03, 74, 16, 00, RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 74, 15, 00, RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
+# A0, 0D, 03, 74, 0D, 11, RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_DATA_MOD_REG
+# A0, 0D, 03, 74, 14, 11, RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_SYMBOL23_MOD_REG
+# A0, 0D, 06, 3E, 2D, 05, 35, 1E, 01, RF_CLIF_CFG_BR_212_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
+# A0, 0D, 06, 3E, 44, 65, 09, 00, 00, RF_CLIF_CFG_BR_212_I_RXA CLIF_ANA_RX_REG
+# A0, 0D, 06, 76, 4A, 56, 07, 01, 1B, RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
+# A0, 0D, 04, 76, 42, 68, 40, RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 03, 76, 16, 00, RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 76, 15, 00, RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
+# A0, 0D, 03, 76, 0D, 08, RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_DATA_MOD_REG
+# A0, 0D, 03, 76, 14, 08, RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_SYMBOL23_MOD_REG
+# A0, 0D, 06, 40, 2D, 05, 45, 1E, 01, RF_CLIF_CFG_BR_424_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
+# A0, 0D, 06, 40, 44, 65, 09, 00, 00, RF_CLIF_CFG_BR_424_I_RXA CLIF_ANA_RX_REG
+# A0, 0D, 04, 78, 42, F0, 40, RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 06, 78, 4A, 11, 07, 01, 1B, RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
+# A0, 0D, 03, 78, 16, 00, RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 78, 15, 00, RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
+# A0, 0D, 03, 78, 0D, 04, RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_DATA_MOD_REG
+# A0, 0D, 03, 78, 14, 04, RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_SYMBOL23_MOD_REG
+# A0, 0D, 06, 4C, 44, 65, 0A, 00, 00, RF_CLIF_CFG_BR_106_I_RXB CLIF_ANA_RX_REG
+# A0, 0D, 06, 4C, 2D, 15, 34, 1F, 01, RF_CLIF_CFG_BR_106_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
+# A0, 0D, 06, 82, 4A, 33, 07, 00, 07, RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
+# A0, 0D, 04, 82, 42, 68, 40, RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 06, 82, 0F, 6C, 01, 04, 00, RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_SYMBOL_CONFIG_REG
+# A0, 0D, 03, 82, 16, 00, RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 82, 15, 00, RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
+# A0, 0D, 06, 4E, 44, 65, 09, 00, 00, RF_CLIF_CFG_BR_212_I_RXB CLIF_ANA_RX_REG
+# A0, 0D, 06, 4E, 2D, 05, 35, 1E, 01, RF_CLIF_CFG_BR_212_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
+# A0, 0D, 06, 84, 4A, 13, 07, 01, 07, RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
+# A0, 0D, 04, 84, 42, 68, 40, RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 03, 84, 16, 00, RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 84, 15, 00, RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
+# A0, 0D, 06, 50, 44, 65, 09, 00, 00, RF_CLIF_CFG_BR_424_I_RXB CLIF_ANA_RX_REG
+# A0, 0D, 06, 50, 2D, 05, 35, 1E, 01, RF_CLIF_CFG_BR_424_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
+# A0, 0D, 06, 86, 4A, 12, 07, 01, 07, RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
+# A0, 0D, 04, 86, 42, 68, 40, RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 03, 86, 16, 00, RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 86, 15, 00, RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
+# A0, 0D, 06, 5E, 2D, 0D, 48, 0C, 01, RF_CLIF_CFG_BR_212_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
+# A0, 0D, 06, 5E, 44, 55, 08, 00, 00, RF_CLIF_CFG_BR_212_I_RXF_P CLIF_ANA_RX_REG
+# A0, 0D, 06, 60, 2D, 0D, 5A, 0C, 01, RF_CLIF_CFG_BR_424_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
+# A0, 0D, 06, 60, 44, 55, 08, 00, 00, RF_CLIF_CFG_BR_424_I_RXF_P CLIF_ANA_RX_REG
+# A0, 0D, 04, 94, 42, 78, 40, RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 06, 94, 4A, 43, 07, 00, 07, RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG
+# A0, 0D, 03, 94, 16, 00, RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 94, 15, 00, RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG
+# A0, 0D, 04, 96, 42, 80, 40, RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 06, 96, 4A, 11, 07, 01, 07, RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG
+# A0, 0D, 03, 96, 16, 00, RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 96, 15, 00, RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG
+# A0, 0D, 06, 1C, 44, 05, 04, C4, 00, RF_CLIF_CFG_TECHNO_T_RXF CLIF_ANA_RX_REG
+# A0, 0D, 03, 24, 03, 7F, RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_TRANSCEIVE_CONTROL_REG
+# A0, 0D, 06, 70, 16, 8E, 00, 1F, 00, RF_CLIF_CFG_BR_848_T_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 28, 16, 00, RF_CLIF_CFG_TECHNO_T_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 2C, 16, 00, RF_CLIF_CFG_TECHNO_T_TXF_P CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 06, 34, 44, 04, 04, C4, 00, RF_CLIF_CFG_BR_106_T_RXA CLIF_ANA_RX_REG
+# A0, 0D, 06, 36, 30, E0, 00, 30, 00, RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+# A0, 0D, 03, 36, 45, 70, RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_CM_CONFIG_REG
+# A0, 0D, 03, 37, 45, 60, RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_CM_CONFIG_REG
+# A0, 0D, 06, 38, 30, 40, 00, 20, 00, RF_CLIF_CFG_BR_424_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+# A0, 0D, 06, 38, 44, 02, 04, C4, 00, RF_CLIF_CFG_BR_424_T_RXA CLIF_ANA_RX_REG
+# A0, 0D, 06, 3A, 30, 26, 00, 08, 00, RF_CLIF_CFG_BR_848_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+# A0, 0D, 06, 3A, 44, 11, 00, C4, 00, RF_CLIF_CFG_BR_848_T_RXA CLIF_ANA_RX_REG
+# A0, 0D, 06, 44, 30, 70, 00, 18, 00, RF_CLIF_CFG_BR_106_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+# A0, 0D, 06, 44, 44, 04, 04, C4, 00, RF_CLIF_CFG_BR_106_T_RXB CLIF_ANA_RX_REG
+# A0, 0D, 06, 46, 30, B0, 00, 45, 00, RF_CLIF_CFG_BR_212_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+# A0, 0D, 06, 48, 30, B0, 00, 45, 00, RF_CLIF_CFG_BR_424_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+# A0, 0D, 06, 4A, 30, 70, 00, 18, 00, RF_CLIF_CFG_BR_848_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+# A0, 0D, 03, 56, 30, 00, RF_CLIF_CFG_BR_212_T_RXF CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+# A0, 0D, 06, 0C, 45, C3, 82, 71, 05, RF_CLIF_CFG_I_PASSIVE CLIF_ANA_CM_CONFIG_REG
+# A0, 0D, 03, 10, 44, 60, RF_CLIF_CFG_I_ACTIVE CLIF_ANA_RX_REG
+# A0, 0D, 06, 10, 30, 70, 00, 18, 00, RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+# A0, 0D, 03, 10, 48, 10, RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CLK_MAN_REG
+# A0, 0D, 06, 10, 45, 80, 40, 00, 00, RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CM_CONFIG_REG
+# A0, 0D, 06, 10, 2D, 0D, 25, 2C, 01, RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_RM_CONFIG1_REG
+# A0, 0D, 03, 10, 35, 0C, RF_CLIF_CFG_I_ACTIVE CLIF_AGC_INPUT_REG
+# A0, 0D, 06, 11, 30, 00, 00, 00, 00, RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+# A0, 0D, 03, 11, 48, 00, RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CLK_MAN_REG
+# A0, 0D, 06, 11, 85, 00, 00, 00, 00, RF_CLIF_CFG_I_ACTIVE CLIF_BBA_CONTROL_REG
+# A0, 0D, 06, 22, 44, 05, 04, C4, 00, RF_CLIF_CFG_TECHNO_I_RXF_A CLIF_ANA_RX_REG
+# A0, 0D, 06, 62, 44, 04, 04, C4, 00, RF_CLIF_CFG_BR_106_I_RXA_A CLIF_ANA_RX_REG
+# A0, 0D, 03, 12, 16, 00, RF_CLIF_CFG_T_ACTIVE CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 06, 12, 37, 00, 00, 00, 00, RF_CLIF_CFG_T_ACTIVE CLIF_TX_CONTROL_REG
+# A0, 0D, 03, 12, 35, 0C, RF_CLIF_CFG_T_ACTIVE CLIF_AGC_INPUT_REG
+# A0, 0D, 06, CC, 42, F8, 40, FF, FF, RF_CLIF_WL_106_T_TXA_A CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 06, CC, 4A, 53, 07, 00, 1B, RF_CLIF_WL_106_T_TXA_A CLIF_ANA_TX_SHAPE_CONTROL_REG
+# A0, 0D, 06, CE, 42, 78, 40, FF, FF, RF_CLIF_WL_212_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 06, CE, 4A, 43, 07, 00, 07, RF_CLIF_WL_212_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG
+# A0, 0D, 06, D0, 42, 80, 40, FF, FF, RF_CLIF_WL_424_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 06, D0, 4A, 11, 07, 01, 07, RF_CLIF_WL_424_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG
+# A0, 0D, 03, 98, 16, 01, RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 98, 15, 01, RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_OVERSHOOT_CONFIG_REG
+# A0, 0D, 03, 9A, 16, 00, RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 9A, 15, 00, RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG
+# A0, 0D, 03, 9C, 16, 00, RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG
+# A0, 0D, 03, 9C, 15, 00, RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG
+# A0, 0D, 04, CA, 42, 68, 40, RF_CLIF_CFG_STAG CLIF_ANA_TX_AMPLITUDE_REG
+# A0, 0D, 06, CA, 44, 65, 0A, 00, 00, RF_CLIF_CFG_STAG CLIF_ANA_RX_REG
+# A0, 0D, 06, CA, 2D, 15, 34, 1F, 01, RF_CLIF_CFG_STAG CLIF_SIGPRO_RM_CONFIG1_REG
+#
+# *** Eval1_SLALM_CFG2_EFM_40x20 FW VERSION = 12.01.12 ***
+NXP_RF_CONF_BLK_1={20, 02, F0, 1C,
+ A0, 0D, 06, 08, 37, 08, 76, 00, 00,
+ A0, 0D, 03, 24, 03, 7E,
+ A0, 0D, 06, 08, 42, 00, 02, F6, F6,
+ A0, 0D, 06, 08, 16, AE, 00, 1F, 00,
+ A0, 0D, 06, 04, 35, 00, 3E, 00, 00,
+ A0, 0D, 06, 06, 35, F4, 05, 70, 02,
+ A0, 0D, 06, C2, 35, 00, 3E, 00, 03,
+ A0, 0D, 06, 06, 42, F8, 40, FF, FF,
+ A0, 0D, 04, 72, 42, F8, 40,
+ A0, 0D, 04, 82, 42, 68, 40,
+ A0, 0D, 04, 94, 42, 78, 40,
+ A0, 0D, 04, 96, 42, 80, 40,
+ A0, 0D, 04, CA, 42, 68, 40,
+ A0, 0D, 06, 72, 4A, 53, 07, 00, 1B,
+ A0, 0D, 06, 82, 4A, 33, 07, 00, 07,
+ A0, 0D, 06, 94, 4A, 43, 07, 00, 07,
+ A0, 0D, 06, 96, 4A, 11, 07, 01, 07,
+ A0, 0D, 06, 3C, 44, 66, 0A, 00, 00,
+ A0, 0D, 06, 4C, 44, 65, 0A, 00, 00,
+ A0, 0D, 06, 5E, 44, 55, 08, 00, 00,
+ A0, 0D, 06, 60, 44, 55, 08, 00, 00,
+ A0, 0D, 06, CA, 44, 65, 0A, 00, 00,
+ A0, 0D, 06, 44, 44, 04, 04, C4, 00,
+ A0, 0D, 06, 3C, 2D, DC, 40, 04, 00,
+ A0, 0D, 06, 4C, 2D, 15, 34, 1F, 01,
+ A0, 0D, 06, 5E, 2D, 0D, 48, 0C, 01,
+ A0, 0D, 06, 60, 2D, 0D, 5A, 0C, 01,
+ A0, 0D, 06, CA, 2D, 15, 34, 1F, 01
+}
+# DLMA OFF
+NXP_RF_CONF_BLK_2={
+20, 02, 10, 01, A0, AF, 0C, 03, C0, 80, A0, 00, 03, C0, 80, A0, 00,00, 08
+}
+# DPC OFF
+NXP_RF_CONF_BLK_3={
+ 20, 02, 5B, 01, A0, 0B, 57, 11, 11, 90, 5A, 0F, 4E, 00, 47, 15, B7, AA, 47, 9F, A7, 99, 5C, 9F, 97, 99, 67, 9F, 97, 99, 69, 9F, 97, 00, 73, 9F, 07, 00, 75, 9F, 07, 00, 80, 9F, 07, 00, 84, 9F, 07, 00, 8D, 9F, 07, 00, 8F, 9F, 07, 00, 99, 9F, 04, 00, 9B, 9F, 04, 00, A6, 9F, 04, 00, A8, 9F, 04, 00, B2, 9F, 02, 00, BB, 9F, 00, 00, C1, 9F, 00, 00, CC, 1F, 00, 00, D6, 1F, 00, 00
+}
+
+
+
+###############################################################################
+# Core configuration extensions
+# It includes
+# Wired mode settings A0ED, A0EE
+# Tag Detector A040, A041, A043
+# Low Power mode A007
+# Clock settings A002, A003
+# PbF settings A008
+# Clock timeout settings A004
+# UICC SWP_INT1_EN_CFG - A0, EC
+# UICC2 SWP_INT2_EN_CFG - A0, ED,
+# eSE (SVDD) PWR REQ settings A0F2
+# How eSE connected to PN553 A012
+# UICC2 bit rate A0D1
+# SWP1A interface A0D4
+# DWP intf behavior config, SVDD Load activated by default if set to 0x31 - A037
+# For Symmetric baud rate UICC's set A086 to 77
+NXP_CORE_CONF_EXTN={20, 02, 6C, 11,
+ A0, EC, 01, 01,
+ A0, ED, 01, 00,
+ A0, 5E, 01, 01,
+ A0, 12, 01, 02,
+ A0, 40, 01, 01,
+ A0, 41, 01, 06,
+ A0, 42, 01, 0F,
+ A0, 43, 01, 03,
+ A0, DD, 01, 2D,
+ A0, D1, 01, 06,
+ A0, D4, 01, 01,
+ A0, 37, 01, 35,
+ A0, 86, 01, 77,
+ A0, 38, 04, 14, 08, 08, 00,
+ A0, 18, 08, BE, 06, 96, 03, 1E, FA, 51, 03,
+ A0, 3A, 08, 5A, 00, 5A, 00, 5A, 00, 5A, 00,
+ A0, 29, 17, 19, 07, 00, 1F, 00, 02, 00, 1F, 00, 02, 00, 43, F3, F3, 00, 43, F3, F3, 28, 70, 00, 00, 03
+ }
+
+###############################################################################
+# Core configuration settings
+# It includes
+# 18 - Poll Mode NFC-F: PF_BIT_RATE
+# 21 - Poll Mode ISO-DEP: PI_BIT_RATE
+# 28 - Poll Mode NFC-DEP: PN_NFC_DEP_SPEED
+# 30 - Lis. Mode NFC-A: LA_BIT_FRAME_SDD
+# 31 - Lis. Mode NFC-A: LA_PLATFORM_CONFIG
+# 33 - Lis. Mode NFC-A: LA_NFCID1
+# 50 - Lis. Mode NFC-F: LF_PROTOCOL_TYPE
+# 54 - Lis. Mode NFC-F: LF_CON_BITR_F
+# 5B - Lis. Mode ISO-DEP: LI_BIT_RATE
+# 60 - Lis. Mode NFC-DEP: LN_WT
+# 80 - Other Param.: RF_FIELD_INFO
+# 81 - Other Param.: RF_NFCEE_ACTION
+# 82 - Other Param.: NFCDEP_OP
+NXP_CORE_CONF={ 20, 02, 30, 10,
+ 28, 01, 00,
+ 21, 01, 00,
+ 30, 01, 08,
+ 31, 01, 03,
+ 32, 01, 20,
+ 38, 01, 01,
+ 33, 00,
+ 54, 01, 06,
+ 50, 01, 02,
+ 5B, 01, 00,
+ 80, 01, 01,
+ 81, 01, 01,
+ 82, 01, 0E,
+ 18, 01, 01,
+ 68, 01, 01,
+ 85, 01, 01
+ }
+###############################################################################
+###############################################################################
+# Set configuration optimization decision setting
+# Enable = 0x01
+# Disable = 0x00
+NXP_SET_CONFIG_ALWAYS=0x01
+
+###############################################################################
+# Core configuration rf field filter settings to enable set to 01 to disable set
+# to 00 last bit
+NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 00 }
+
+###############################################################################
+# To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set
+# to 0x00
+# Disable = 0x00
+# Enable = 0x01
+NXP_I2C_FRAGMENTATION_ENABLED=0x00
+
+###############################################################################
+# Mifare Classic Key settings
+#NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5,
+# A0, 52, 06, D3, F7, D3, F7, D3, F7,
+# A0, 53, 06, FF, FF, FF, FF, FF, FF,
+# A0, 54, 06, 00, 00, 00, 00, 00, 00}
+
+###############################################################################
+#Enable SWP full power mode when phone is power off
+# Disable = 0x00
+# Enable = 0x01
+NXP_SWP_FULL_PWR_ON=0x00
+
+###############################################################################
+#### Select the CHIP ####
+#PN547C2 0x01
+#PN65T 0x02
+#PN548AD 0x03
+#PN66T 0x04
+#PN551 0x05
+#PN67T 0x06
+#PN553 0x07
+#PN80T 0x08
+#PN557 0x09
+#PN81T 0x0A
+NXP_NFC_CHIP=0x09
+
+###############################################################################
+# CE when Screen state is locked
+# This setting is for DEFAULT_AID_ROUTE,
+# DEFAULT_DESFIRE_ROUTE and DEFAULT_MIFARE_CLT_ROUTE
+# Disable 0x00
+# Enable 0x01
+NXP_CE_ROUTE_STRICT_DISABLE=0x01
+
+###############################################################################
+#Timeout in secs to get NFCEE Discover notification
+NXP_DEFAULT_NFCEE_DISC_TIMEOUT=20
+
+###############################################################################
+NXP_DEFAULT_NFCEE_TIMEOUT=20
+
+###############################################################################
+#Timeout in secs
+NXP_SWP_RD_START_TIMEOUT=0x0A
+
+###############################################################################
+#Timeout in secs
+NXP_SWP_RD_TAG_OP_TIMEOUT=0x01
+
+###############################################################################
+#Set the default AID route Location :
+#This settings will be used when application does not set this parameter
+# host 0x00
+# eSE 0x01
+# UICC 0x02
+DEFAULT_AID_ROUTE=0x02
+
+###############################################################################
+# Configure the default NfcA/IsoDep techology and protocol route. Can be
+# either a secure element (e.g. 0xF4) or the host (0x00)
+# host 0x00
+# eSE 0x01
+# UICC 0x02
+DEFAULT_ISODEP_ROUTE=0x02
+
+###############################################################################
+# Configure the single default SE to use. The default is to use the first
+# SE that is detected by the stack. This value might be used when the phone
+# supports multiple SE (e.g. 0xC0 and 0x80) but you want to force it to use
+# one of them (e.g. 0xC0).
+# host 0x00
+# eSE 0x01
+# UICC 0x02
+DEFAULT_OFFHOST_ROUTE=0x02
+
+###############################################################################
+# Configure the single default SE to use. The default is to use the first
+# SE that is detected by the stack. This value might be used when the phone
+# supports multiple SE (e.g. 0xF3 and 0xF4) but you want to force it to use
+# one of them (e.g. 0xF4).
+# host 0x00
+# eSE 0x01
+# UICC 0x02
+DEFAULT_TECH_ABF_ROUTE=0x02
+
+###############################################################################
+#Set the default Felica T3T System Code OffHost route Location :
+#This settings will be used when application does not set this parameter
+# host 0x00
+# eSE 0x01
+DEFAULT_SYS_CODE_ROUTE=0x00
+
+###############################################################################
+#Set the default AID Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Screen On lock
+# bit pos 4 = Screen off unlock
+# bit pos 5 = Screen Off lock
+DEFAULT_AID_PWR_STATE=0x3B
+
+###############################################################################
+#Set the Mifare Desfire Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Switched On Sub-State 1 : Screen is off and device is unlocked
+# bit pos 4 = Switched On Sub-State 2 : Screen is on and device is locked
+# bit pos 5 = Switched On Sub-State 3 : Screen is off and device is locked
+DEFAULT_ISODEP_PWR_STATE=0x3B
+
+###############################################################################
+#Set the Mifare CLT Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Switched On Sub-State 1 : Screen is off and device is unlocked
+# bit pos 4 = Switched On Sub-State 2 : Screen is on and device is locked
+# bit pos 5 = Switched On Sub-State 3 : Screen is off and device is locked
+DEFAULT_OFFHOST_PWR_STATE=0x3B
+
+###############################################################################
+#Set Tech A,B,F Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Switched On Sub-State 1 : Screen is off and device is unlocked
+# bit pos 4 = Switched On Sub-State 2 : Screen is on and device is locked
+# bit pos 5 = Switched On Sub-State 3 : Screen is off and device is locked
+DEFAULT_TECH_ABF_PWR_STATE=0x3B
+
+###############################################################################
+#Set the SYS_CODE Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Switched On Sub-State 1 : Screen is off and device is unlocked
+# bit pos 4 = Switched On Sub-State 2 : Screen is on and device is locked
+# bit pos 5 = Switched On Sub-State 3 : Screen is off and device is locked
+DEFAULT_SYS_CODE_PWR_STATE=0x3B
+
+###############################################################################
+# Configure the NFC Extras to open and use a static pipe. If the value is
+# not set or set to 0, then the default is use a dynamic pipe based on a
+# destination gate (see NFA_HCI_DEFAULT_DEST_GATE). Note there is a value
+# for each UICC (where F3="UICC0" and F4="UICC1")
+OFF_HOST_ESE_PIPE_ID=0x19
+OFF_HOST_SIM_PIPE_ID=0x0A
+
+###############################################################################
+# Bail out mode
+# If set to 1, NFCC is using bail out mode for either Type A or Type B poll.
+NFA_POLL_BAIL_OUT_MODE=0x01
+
+###############################################################################
+# AID Matching platform options
+# AID_MATCHING_L 0x01
+# AID_MATCHING_K 0x02
+AID_MATCHING_PLATFORM=0x01
+
+###############################################################################
+#CHINA_TIANJIN_RF_SETTING
+#Enable 0x01
+#Disable 0x00
+NXP_CHINA_TIANJIN_RF_ENABLED=0x01
+
+###############################################################################
+#SWP_SWITCH_TIMEOUT_SETTING
+# Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60].
+# Timeout in milliseconds, for example
+# No Timeout 0x00
+# 10 millisecond timeout 0x0A
+NXP_SWP_SWITCH_TIMEOUT=0x0A
+
+###############################################################################
+#Timeout value in milliseconds for NFCC standby mode.The range is between 5000
+#msec to 20000 msec and zero is to disable.
+NXP_NFCC_STANDBY_TIMEOUT=20000
+
+###############################################################################
+#Dynamic RSSI feature enable
+# Disable 0x00
+# Enable 0x01
+NXP_AGC_DEBUG_ENABLE=0x00
+
+###############################################################################
+#Config to allow adding aids
+#NFC on/off is required after this config
+#1 = enabling adding aid to NFCC routing table.
+#0 = disabling adding aid to NFCC routing table.
+NXP_ENABLE_ADD_AID=0x01
+
+###############################################################################
+# Enable/Disable checking default proto SE Id
+# Disable 0x00
+# Enable 0x01
+NXP_CHECK_DEFAULT_PROTO_SE_ID=0x01
+
+###############################################################################
+#NXP_CN_TRANSIT_CMA_BYPASSMODE_ENABLE
+#Enable this config it prevents EMVCo PICC compliancy and Mifare backward compatibility works
+#Disable this config EMVCo PICC compliancy works and Mifare backward compatibility will not work
+#Default config is Disable
+#Enable 0x01
+#Disable 0x00
+NXP_CN_TRANSIT_CMA_BYPASSMODE_ENABLE=0x00
+
+###############################################################################
+#NXP_CN_TRANSIT_BLK_NUM_CHECK_ENABLE
+#Enable/Disable block number checks for china transit use case
+#Enable 0x01
+#Disable 0x00
+NXP_CN_TRANSIT_BLK_NUM_CHECK_ENABLE=0x01
+
+###############################################################################
+#Enable NXP NCI runtime parser library
+#Enable 0x01
+#Disable 0x00
+NXP_NCI_PARSER_LIBRARY=0x00
+
+###############################################################################
+#This config will enable different level of Rf transaction debugs based on the
+#following values provided. Decoded information will be printed in adb logcat
+#Debug Mode Levels
+#Disable Debug 0x00
+#L1 Debug 0x01
+#L2 Debug 0x02
+#L1 & L2 Debug 0x03
+#L1 & L2 & RSSI 0x04
+#L1 & L2 & Felica 0x05
+#NXP_CORE_PROP_SYSTEM_DEBUG=0x00
+
+###############################################################################
+# Enable/Disable Block Route feature.
+# Block Route will restrict routing to first matched rule
+# Block Route enable 0x01
+# Block Route disable 0x00
+AID_BLOCK_ROUTE=0x01
+
+##############################################################################
+# Timeout value in milliseconds to send response for Felica command received
+NXP_HCEF_CMD_RSP_TIMEOUT_VALUE=5000
+
+###############################################################################
+# Enable or Disable RF_STATUS_UPDATE to EseHal module
+# Disable 0x00
+# Enable 0x01
+RF_STATUS_UPDATE_ENABLE=0x00
+
+###############################################################################
+# Vendor Specific Proprietary Protocol & Discovery Configuration
+# Set to 0xFF if unsupported
+# byte[0] NCI_PROTOCOL_18092_ACTIVE
+# byte[1] NCI_PROTOCOL_B_PRIME
+# byte[2] NCI_PROTOCOL_DUAL
+# byte[3] NCI_PROTOCOL_15693
+# byte[4] NCI_PROTOCOL_KOVIO
+# byte[5] NCI_PROTOCOL_MIFARE
+# byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO
+# byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME
+# byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME
+NFA_PROPRIETARY_CFG={05, FF, FF, 06, 81, 80, 70, FF, FF}
+
+###############################################################################
+#White list of Hosts
+#This values will be the Hosts(NFCEEs) in the HCI Network.
+DEVICE_HOST_WHITE_LIST={80:81}
+
+###############################################################################
+#OffHost UICC route location for MultiSE
+#UICC1 = 02
+#UICC2 = 03
+OFFHOST_ROUTE_UICC={02}
+
+###############################################################################
+# Choose the presence-check algorithm for type-4 tag. If not defined, the default value is 1.
+# 0 NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm
+# 1 NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block
+# 2 NFA_RW_PRES_CHK_ISO_DEP_NAK; Type - 4 tag protocol iso-dep nak presence check
+PRESENCE_CHECK_ALGORITHM=2
+
+###############################################################################
+# Extended APDU length for ISO_DEP
+ISO_DEP_MAX_TRANSCEIVE=0xFEFF
+
+###############################################################################
+
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