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* Support callee save floating point registers on x64.Nicolas Geoffray2015-01-231-2/+0
| | | | | | | | | - Share the computation of core_spill_mask and fpu_spill_mask between backends. - Remove explicit stack overflow check support: we need to adjust them and since they are not tested, they will easily bitrot. Change-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a
* Enable core callee-save on x64.Nicolas Geoffray2015-01-211-1/+1
| | | | | | Will work on other architectures and FP support in other CLs. Change-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d
* Record implicit null checks at the actual invoke time.Calin Juravle2015-01-211-1/+2
| | | | | | | | | | | | | ImplicitNullChecks are recorded only for instructions directly (see NB below) preceeded by NullChecks in the graph. This way we avoid recording redundant safepoints and minimize the code size increase. NB: ParallalelMoves might be inserted by the register allocator between the NullChecks and their uses. These modify the environment and the correct action would be to reverse their modification. This will be addressed in a follow-up CL. Change-Id: Ie50006e5a4bd22932dcf11348f5a655d253cd898
* Add implicit null checks for the optimizing compilerCalin Juravle2015-01-161-4/+8
| | | | | | | | | - for backends: arm, arm64, x86, x86_64 - fixed parameter passing for CodeGenerator - 003-omnibus-opcodes test verifies that NullPointerExceptions work as expected Change-Id: I1b302acd353342504716c9169a80706cf3aba2c8
* Merge "[optimizing compiler] Compute live spill size"Nicolas Geoffray2015-01-151-0/+5
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| * [optimizing compiler] Compute live spill sizeMark Mendell2015-01-151-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current stack frame calculation assumes that each live register to be saved/restored has the word size of the machine. This fails for X86, where a double in an XMM register takes up 8 bytes. Change the calculation to keep track of the number of core registers and number of fp registers to handle this distinction. This is slightly pessimal, as the registers may not be active at the same time, but the only way to handle this would be to allocate both classes of registers simultaneously, or remember all the active intervals, matching them up and compute the size of each safepoint interval. Change-Id: If7860aa319b625c214775347728cdf49a56946eb Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | Skip r1 on arm if first parameter is a long.Nicolas Geoffray2015-01-131-6/+0
|/ | | | Change-Id: I16d927ee0a0b55031ade4c92c0095fd74e18ed5b
* Implement double and float support for arm in register allocator.Nicolas Geoffray2015-01-081-0/+6
| | | | | | | | | | | | The basic approach is: - An instruction that needs two registers gets two intervals. - When allocating the low part, we also allocate the high part. - When splitting a low (or high) interval, we also split the high (or low) equivalent. - Allocation follows the (S/D register) requirement that low registers are always even and the high equivalent is low + 1. Change-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797
* Look at instruction set features when generating volatiles codeCalin Juravle2015-01-051-1/+6
| | | | Change-Id: Ia882405719fdd60b63e4102af7e085f7cbe0bb2a
* [optimizing compiler] Add support for volatileCalin Juravle2014-12-191-0/+12
| | | | | | | | | | | | - for backends: arm, x86, x86_64 - added necessary instructions to assemblies - clean up code gen for field set/get - fixed InstructionDataEquals for some instructions - fixed comments in compiler_enums * 003-opcode test verifies basic volatile functionality Change-Id: I144393efa312dfb2c332cb84056b00edffee338a
* [optimizing compiler] Add shiftsCalin Juravle2014-11-241-0/+2
| | | | | | Added SHL, SHR, USHR for arm, x86, x86_64. Change-Id: I971f594e270179457e6958acf1401ff7630df07e
* Consistently use k{InstructionSet}WordSize.Nicolas Geoffray2014-11-191-1/+2
| | | | | | | | These constants were defined prior to k{InstructionSet}PointerSize. So use them consistently in optimizing as a first step. We can discuss whether we should remove them in a second step. Change-Id: If129de1a3bb8b65f8d9c816a8ad466815fb202e6
* Merge "Do a parallel move in BoundsCheckSlowPath."Nicolas Geoffray2014-11-131-1/+1
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| * Do a parallel move in BoundsCheckSlowPath.Nicolas Geoffray2014-11-121-1/+1
| | | | | | | | | | | | | | | | The two locations of the index and length could overlap, so we need a parallel move. Also factorize the code for doing a parallel move based on two locations. Change-Id: Iee8b3459e2eed6704d45e9a564fb2cd050741ea4
* | Implement and/or/xor in optimizing.Nicolas Geoffray2014-11-121-1/+3
|/ | | | Change-Id: I7cf6da1fd334a7177a5580931b8f174dd40b7cec
* Implement try/catch/throw in optimizing.Nicolas Geoffray2014-11-061-24/+28
| | | | | | | | - We currently don't run optimizations in the presence of a try/catch. - We therefore implement Quick's mapping table. - Also fix a missing null check on array-length. Change-Id: I6917dfcb868e75c1cf6eff32b7cbb60b6cfbd68f
* Implement CONST_CLASS in optimizing compiler.Nicolas Geoffray2014-11-041-0/+2
| | | | Change-Id: Ia8c8dfbef87cb2f7893bfb6e178466154eec9efd
* Add support for static fields in optimizing compiler.Nicolas Geoffray2014-10-291-1/+6
| | | | Change-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9
* Support hard float on arm in optimizing compiler.Nicolas Geoffray2014-10-271-4/+10
| | | | | | Also bump oat version, needed after latest hard float switch. Change-Id: Idf5acfb36c07e74acff00edab998419a3c6b2965
* Implement register allocator for floating point registers.Nicolas Geoffray2014-10-211-2/+2
| | | | | | | | Also: - Fix misuses of emitting the rex prefix in the x86_64 assembler. - Fix movaps code generation in the x86_64 assembler. Change-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe
* Add multiplication for integral typesCalin Juravle2014-10-171-0/+4
| | | | | | | This also fixes an issue where we could allocate a pair register even if one of its parts was already blocked. Change-Id: I4869175933409add2a56f1ccfb369c3d3dd3cb01
* Don't use assembler classes in code_generator.h.Nicolas Geoffray2014-10-161-1/+11
| | | | | | | | | The arm64 backend uses its own assembler and does not share the same classes as the other backends. To avoid conflicts or unnecessary mappings, just don't use those classes in the shared part of the code generator. Change-Id: I9e5fa40c1021d2e83a4ef14c52cd1ccd03f2f73d
* Cleanup baseline register allocator.Nicolas Geoffray2014-10-101-12/+2
| | | | | | | | - Use three arrays for blocking regsters instead of one and computing offsets in that array.] - Don't pass blocked_registers_ to methods, just use the field. Change-Id: Ib698564c31127c59b5a64c80f4262394b8394dc6
* Fix code generation of materialized conditions.Nicolas Geoffray2014-10-091-2/+2
| | | | | | | | | | | | | Move the logic for knowing if a condition needs to be materialized in an optimization pass (so that the information does not change as a side effect of another optimization). Also clean-up arm and x86_64 codegen: - arm: ldr and str are for power-users when a constant is in play. We should use LoadFromOffset and StoreToOffset. - x86_64: fix misuses of movq instead of movl. Change-Id: I01a03b91803624be2281a344a13ad5efbf4f3ef3
* Stop converting from Location to ManagedRegister.Nicolas Geoffray2014-10-091-1/+1
| | | | | | | Now the source of truth is the Location object that knows which register (core, pair, fpu) it needs to refer to. Change-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1
* Add support for floats and doubles.Nicolas Geoffray2014-10-071-2/+7
| | | | | | | - Follows Quick conventions. - Currently only works with baseline register allocator. Change-Id: Ie4b8e298f4f5e1cd82364da83e4344d4fc3621a3
* Merge "Optimize suspend checks in optimizing compiler."Nicolas Geoffray2014-09-251-0/+5
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| * Optimize suspend checks in optimizing compiler.Nicolas Geoffray2014-09-251-0/+5
| | | | | | | | | | | | | | | | | | | | - Remove the ones added during graph build (they were added for the baseline code generator). - Emit them at loop back edges after phi moves, so that the test can directly jump to the loop header. - Fix x86 and x86_64 suspend check by using cmpw instead of cmpl. Change-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a
* | Optimizing compiler: remove unnecessary `explicit' keywords.Roland Levillain2014-09-251-1/+1
|/ | | | Change-Id: I5927fd92d53308c81e14edbd6e7d1c943bfa085b
* Support for saving and restoring live registers in a slow path.Nicolas Geoffray2014-09-231-0/+2
| | | | | | And use it in suspend check slow paths. Change-Id: I79caf28f334c145a36180c79a6e2fceae3990c31
* Implement invoke virtual in optimizing compiler.Nicolas Geoffray2014-09-171-0/+2
| | | | | | | Also refactor 004 tests to make them work with both Quick and Optimizing. Change-Id: I87e275cb0ae0258fc3bb32b612140000b1d2adf8
* Fix valgrind errors.Nicolas Geoffray2014-09-111-1/+1
| | | | | | | | For now just stack allocate the code generator. Will think about cleaning up the root problem later (CodeGenerator being an arena object). Change-Id: I161a6f61c5f27ea88851b446f3c1e12ee9c594d7
* Implement array get and array put in optimizing.Nicolas Geoffray2014-07-281-1/+4
| | | | | | Also fix a couple of assembler/disassembler issues. Change-Id: I705c8572988c1a9c4df3172b304678529636d5f6
* Add assembly operations with constants in optimizing compiler.Nicolas Geoffray2014-07-211-2/+2
| | | | Change-Id: I5bcc35ab50d4457186effef5592a75d7f4e5b65f
* Use the thumb2 assembler for the optimizing compiler.Nicolas Geoffray2014-07-161-3/+3
| | | | Change-Id: I2b058f4433504dc3299c06f5cb0b5ab12f34aa82
* Fix a braino in the stack layout.Nicolas Geoffray2014-07-151-3/+2
| | | | | | Also do some refactoring to have this code be just in CodeGenerator. Change-Id: I88de109889138af8d60027973c12a64bee813cb7
* Support fields in optimizing compiler.Nicolas Geoffray2014-07-141-0/+1
| | | | | | | | - Required support for temporaries, to be only used by baseline compiler. - Also fixed a few invalid assumptions around locations and instructions that don't need materialization. These instructions should not have an Out. Change-Id: Idc4a30dd95dd18015137300d36bec55fc024cf62
* Support longs in the register allocator for x86_64.Nicolas Geoffray2014-07-021-0/+4
| | | | Change-Id: I7fb6dfb761bc5cf9e5705682032855a0a70ca867
* Re-enable tests with the optimizing compiler.Nicolas Geoffray2014-06-261-2/+2
| | | | | | | | | | | Tests run ok on my host/target. I reverted the move to using thumb2, because tests were crashing. But I could not reproduce file limits issues. Make SignalTest as crashing for optimizing. We need to implement stack overflow checks. Change-Id: Ieda575501eaf30af7aaa2c44e71544c9c467c24f
* Revert "Re-enable tests with the optimizing compiler."Nicolas Geoffray2014-06-251-2/+2
| | | | | | This reverts commit 20550910e608ed7d86db97927d2ce9d2191061a4. Change-Id: Ic28b719946c795378838a18162a2a2b2cf41a0e8
* Re-enable tests with the optimizing compiler.Nicolas Geoffray2014-06-251-2/+2
| | | | | | | | Tests run ok on my host/target. I reverted the move to using thumb2, because tests were crashing. But I could not reproduce file limits issues. Change-Id: I26bc4ec1eb6c227750d11210e012d9d3b1d824af
* Add some more instruction support to optimizing compiler.Dave Allison2014-06-241-2/+2
| | | | | | | | | | | | | | | This adds a few more DEX instructions to the optimizing compiler's builder (constants, moves, if_xx, etc). Also: * Changes the codegen for IF_XX instructions to use a condition rather than comparing a value against 0. * Fixes some instructions in the ARM disassembler. * Fixes PushList and PopList in the thumb2 assembler. * Switches the assembler for the optimizing compiler to thumb2 rather than ARM. Change-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f
* Enable the register allocator on ARM.Nicolas Geoffray2014-06-121-0/+27
| | | | | | | | - Also fixes a few bugs/wrong assumptions in code not hit by x86. - We need to differentiate between moves due to connecting siblings within a block, and moves due to control flow resolution. Change-Id: Idd05cf138a71c8f36f5531c473de613c0166fe38
* Final CL to enable register allocation on x86.Nicolas Geoffray2014-06-121-0/+1
| | | | | | | | | | | | This CL implements: 1) Resolution after allocation: connecting the locations allocated to an interval within a block and between blocks. 2) Handling of fixed registers: some instructions require inputs/output to be at a specific location, and the allocator needs to deal with them in a special way. 3) ParallelMoveResolver::EmitNativeCode for x86. Change-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858
* Thumb2 assembler for JNI compiler and optimizing compilerDave Allison2014-06-051-2/+2
| | | | | | | | | | | | | | | | | | | | This provides a programmatic assembler for the thumb2 instruction set for ARM. The interface is the same as the ARM assembler and the ARM assembler has been moved into Arm32Assembler. The assembler handles most 16 and 32 bit instructions and also allows relocations due to branch expansion. It will also rewrite cbz/cbnz instructions if they go out of range. It also changes the JNI compiler to use the thumb2 assembler as opposed to forcing it to use ARM32. The trampoline compiler still uses ARM due to the way it returns the address of its generated code. A trampoline in thumb2 is the same size as that in ARM anyway (8 bytes). Provides gtest for testing the thumb2 instruction output. This gtest only runs on the host as it uses arm-eabi-objdump to disassemble the generated code. On the target the output is not checked but the assembler will still be run to perform all its checks. Change-Id: Icd9742b6f13541bec5b23097896727392e3a6fb6
* Add a linear scan register allocator to the optimizing compiler.Nicolas Geoffray2014-05-261-0/+11
| | | | | | | | | | | | This is a "by-the-book" implementation. It currently only deals with allocating registers, with no hint optimizations. The changes remaining to make it functional are: - Allocate spill slots. - Resolution and placements of Move instructions. - Connect it to the code generator. Change-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4
* Setup policies for register allocation.Nicolas Geoffray2014-04-291-4/+7
| | | | Change-Id: I857e77530fca3e2fb872fc142a916af1b48400dc
* Code cleanup in preparation for x64 backend.Nicolas Geoffray2014-04-171-0/+32
| | | | | | | | | - Use InvokeDexCallingConventionVisitor for setting up HParameterValues - Use kVregSize instead of kX86WordSize when dealing with virtual registers. Change-Id: Ia520223010194c70a3ff0ed659077f55cec4e7d8
* Long support in optimizing compiler.Nicolas Geoffray2014-04-161-4/+12
| | | | | | | | | - Add stack locations to the Location class. - Change logic of parameter passing/setup by setting the location of such instructions the ones for the calling convention. Change-Id: I4730ad58732813dcb9c238f44f55dfc0baa18799
* Use target-specific word instead of runtime word.Nicolas Geoffray2014-04-041-4/+6
| | | | Change-Id: Ia11dc3cc520a1a5c7bd017013e5699af9570ce91
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