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* Remove MIPS support from Optimizing.Vladimir Marko2020-02-131-736/+0
| | | | | | | | Test: aosp_taimen-userdebug boots. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Bug: 147346243 Change-Id: I97fdc15e568ae3fe390efb1da690343025f84944
* Revert "Make compiler/optimizing/ symbols hidden."Vladimir Marko2019-10-141-2/+1
| | | | | | | | | This reverts commit e2727154f25e0db9a5bb92af494d8e47b181dfcf. Reason for revert: Breaks ASAN tests (ODR violation). Bug: 142365358 Change-Id: I38103d74a1297256c81d90872b6902ff1e9ef7a4
* Make compiler/optimizing/ symbols hidden.Vladimir Marko2019-10-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | Make symbols in compiler/optimizing hidden by a namespace attribute. The unit intrinsic_objects.{h,cc} is excluded as it is needed by dex2oat. As the symbols are no longer exported, gtests are now linked with the static version of the libartd-compiler library. libart-compiler.so size: - before: arm: 2396152 arm64: 3345280 - after: arm: 2016176 (-371KiB, -15.9%) arm64: 2874480 (-460KiB, -14.1%) Test: m test-art-host-gtest Test: testrunner.py --host --optimizing --jit Bug: 142365358 Change-Id: I1fb04a33351f53f00b389a1642e81a68e40912a8
* ART: ARM64: Optimize frame size for SIMD graphs.Artem Serov2019-08-021-1/+5
| | | | | | | | | | | | | For SIMD graphs allocate 64 bit instead of 128 bit on stack for each FP register to be preserved by the callee in the frame entry as ABI suggests (currently 64-bit registers are preserved but more space on stack is allocated). Note: slow paths still require spilling full 128-bit Q-Registers for SIMD graphs due to register allocator restrictions. Test: test-art-target. Change-Id: Ie0b12e4b769158445f3d0f4562c70d4fb0ea7744
* Clean up linker patches in codegens.Vladimir Marko2019-07-161-4/+4
| | | | | | | | | | | | | In preparation for introducing boot image extension, make sure that we can use both kBootImageLinkTimePcRelative and kBootImageRelRo load kinds at the same time. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Test: aosp_taimen-userdebug boots Test: run-gtests.sh Test: testrunner.py --target --optimizing Change-Id: I340f2d7d19e1c20699b37b0304d2e487d497da98
* Remove sharpening as an optimization pass.Nicolas Geoffray2018-09-191-1/+1
| | | | | | | | Make the last sharpening helper (methods) like the other helpers: being invoked by the instruction builder. Test: test.py Change-Id: Ic80a454f9b59b0b4ef7825590b24402500ba851c
* Use 'final' and 'override' specifiers directly in ART.Roland Levillain2018-08-281-55/+55
| | | | | | | | | | | | | | | Remove all uses of macros 'FINAL' and 'OVERRIDE' and replace them with 'final' and 'override' specifiers. Remove all definitions of these macros as well, which were located in these files: - libartbase/base/macros.h - test/913-heaps/heaps.cc - test/ti-agent/ti_macros.h ART is now using C++14; the 'final' and 'override' specifiers have been introduced in C++11. Test: mmma art Change-Id: I256c7758155a71a2940ef2574925a44076feeebf
* Implement Integer.valueOf() intrinsic for boot image.Vladimir Marko2018-06-291-1/+6
| | | | | | | | | | | | And generate only one "boot image live objects" array rather than one per boot*.art file. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Test: Pixel 2 XL boots. Test: testrunner.py --target --optimizing Bug: 71526895 Change-Id: I23af7f47fea5150805f801cd2512f2d152ee5b73
* Move instruction_set_ to CompilerOptions.Vladimir Marko2018-06-251-5/+1
| | | | | | | | | | | | Removes CompilerDriver dependency from ImageWriter and several other classes. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Test: Pixel 2 XL boots. Test: m test-art-target-gtest Test: testrunner.py --target --optimizing Change-Id: I3c5b8ff73732128b9c4fad9405231a216ea72465
* Implement Integer.valueOf() intrinsic for PIC.Vladimir Marko2018-06-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | And fix the intrinsic for JIT even in case when someone messes up the IntegerCache using reflection. Two cases are exposed with a regression test (one that previously failed randomly and one that failed 100%) but other crashes were possible; for example, we would need a read barrier for array reads when elements are not guaranteed to be in the boot image. The new approach loads references only from the boot image live objects array which cannot be touched by reflection. The referenced objects and IntegerCache.cache are exposed and can lead to weird behavior but not crashes. On x86, the pc_relative_fixups_86 actually checks the cache an additional time but discrepancies between this check and the location building at the beginning of codegen should be OK as the HIsX86ComputeBaseMethodAddress should be added for PIC regardless of whether pc_relative_fixups_86 thinks the method is intrinsified or not. Test: 717-integer-value-of Test: Pixel 2 XL boots. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing --pictest --npictest Test: testrunner.py --host --jit Test: testrunner.py --target --optimizing --pictest --npictest Test: testrunner.py --target --jit Bug: 71526895 Change-Id: I89b3245a62aba22980c86a99e2af480bfa250af1
* Revert^4 "Compiler changes for bitstring based type checks."Vladimir Marko2018-03-271-0/+1
| | | | | | | | | | | | Disabled the build time flag. (No image version bump needed.) Bug: 26687569 Bug: 64692057 Bug: 76420366 This reverts commit 3fbd3ad99fad077e5c760e7238bcd55b07d4c06e. Change-Id: I5d83c4ce8a7331c435d5155ac6e0ce1c77d60004
* Revert^3 "Compiler changes for bitstring based type checks."Andreas Gampe2018-03-261-1/+0
| | | | | | | | | | | This reverts commit 3f41323cc9da335e9aa4f3fbad90a86caa82ee4d. Reason for revert: Fails sporadically. Bug: 26687569 Bug: 64692057 Bug: 76420366 Change-Id: I84d1e9e46c58aeecf17591ff71fbac6a1e583909
* Revert^2 "Compiler changes for bitstring based type checks."Vladimir Marko2018-03-221-0/+1
| | | | | | | | | | | | | | | | | | Add extra output for debugging failures and re-enable the bitstring type checks. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing --jit Test: testrunner.py --host -t 670-bitstring-type-check Test: Pixel 2 XL boots. Test: testrunner.py --target --optimizing --jit Test: testrunner.py --target -t 670-bitstring-type-check Bug: 64692057 Bug: 26687569 This reverts commit bff7a52e2c6c9e988c3ed1f12a2da0fa5fd37cfb. Change-Id: I090e241983f3ac6ed8394d842e17716087d169ac
* Move some remaining dex utilitiesDavid Sehr2018-03-191-2/+2
| | | | | | | | | There were several utilities related to building/walking/testing dex files that were not in libdexfile. This change consolidates these. Bug: 22322814 Test: make -j 50 test-art-host Change-Id: Id76e9179d03b8ec7d67f7e0f267121f54f0ec2e0
* Merge "Retrieve String/Class references from .data.bimg.rel.ro."Vladimir Marko2018-03-091-1/+2
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| * Retrieve String/Class references from .data.bimg.rel.ro.Vladimir Marko2018-03-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | For PIC AOT-compiled app, use the .data.bimg.rel.ro to load the boot image String/Class references instead of using the mmapped boot image ClassTable and InternTable. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing --pictest --npictest Test: Pixel 2 XL boots. Test: testrunner.py --target --optimizing --pictest --npictest Bug: 71526895 Change-Id: Id5703229777aecb589a933a41f92e44d3ec02a3d
* | Merge "Load ArtMethod* from .data.bimg.rel.ro entries."Vladimir Marko2018-03-081-1/+3
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| * Load ArtMethod* from .data.bimg.rel.ro entries.Vladimir Marko2018-03-081-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a new .data.bimg.rel.ro section in oat files where we store offsets of boot image objects from the beginning of the boot image. At runtime we relocate these entries using the actual boot image address to turn offsets to pointers. Use the .data.bimg.rel.ro to prepare the boot image methods used by HInvokeStaticOrDirect for PIC AOT app compilation. Loading the ArtMethod* from .data.bimg.rel.ro instead of the .bss avoids the initial call to the resolution trampoline. Test: Additional test in 522-checker-sharpening Test: m test-art-host-gtest Test: testrunner.py --host --optimizing --pictest --npictest Test: Pixel 2 XL boots. Test: testrunner.py --target --optimizing --pictest --npictest Bug: 71526895 Change-Id: Ie5f5b1f622704877b36730377146e59092e46c0c
* | Minor cleanup of MIN/MAX code.Aart Bik2018-03-071-1/+2
| | | | | | | | | | | | | | | | | | | | Rationale: Share the type dispatching code better. Bug: b/65164101 Test: test-art-host,target Change-Id: Ib06c915d570fd0a53f7734cdb316d2d16310db74
* | Introduce MIN/MAX/ABS as HIR nodes.Aart Bik2018-03-071-0/+2
|/ | | | | | | | | | | | | | | | | Rationale: Having explicit MIN/MAX/ABS operations (in contrast with intrinsics) simplifies recognition and optimization of these common operations (e.g. constant folding, hoisting, detection of saturation arithmetic). Furthermore, mapping conditionals, selectors, intrinsics, etc. (some still TBD) onto these operations generalizes the way they are optimized downstream substantially. Bug: b/65164101 Test: test-art-host,target Change-Id: I69240683339356e5a012802f179298f0b04c6726
* Introduce ABS as HIR nodes.Aart Bik2018-03-011-0/+2
| | | | | | | | | | | | | | | | | | | NOTE: step 1 of 2 for "Introduce MIN/MAX/ABS as HIR nodes." Rationale: Having explicit MIN/MAX/ABS operations (in contrast with intrinsics) simplifies recognition and optimization of these common operations (e.g. constant folding, hoisting, detection of saturation arithmetic). Furthermore, mapping conditionals, selectors, intrinsics, etc. (some still TBD) onto these operations generalizes the way they are optimized downstream substantially. Bug: b/65164101 Test: test-art-host,target Change-Id: I9c93987197216158ba02c8aca2385086adedabc4
* ART: Clean up patching data in codegens.Vladimir Marko2018-02-201-24/+18
| | | | | | | | | | | | | | Reuse PatchInfo<> for additional architectures and make the naming more consistent across architectures. Change the DexFile reference to pointer in preparation for patching references to the upcoming .data.bimg.rel.ro section. Update obsolete comments; instead of referencing dex cache arrays which were used in the past, reference the .bss and the .data.bimg.rel.ro which shall be used in upcoming CLs. Test: Rely on TreeHugger. Change-Id: I03be4c4118918189e55c62105bb594500c6a42c1
* Revert "Compiler changes for bitstring based type checks."Nicolas Geoffray2018-01-251-1/+0
| | | | | | | | | | Bug: 64692057 Bug: 71853552 Bug: 26687569 This reverts commit eb0ebed72432b3c6b8c7b38f8937d7ba736f4567. Change-Id: I7daeaa077960ba41b2ed42bc47f17501621be4be
* Compiler changes for bitstring based type checks.Vladimir Marko2018-01-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We guard the use of this feature with a compile-time flag, set to true in this CL. Boot image size for aosp_taimen-userdebug in AOSP master: - before: arm boot*.oat: 63604740 arm64 boot*.oat: 74237864 - after: arm boot*.oat: 63531172 (-72KiB, -0.1%) arm64 boot*.oat: 74135008 (-100KiB, -0.1%) The new TypeCheckBenchmark yields the following changes using the little cores of taimen fixed at 1.4016GHz: 32-bit 64-bit timeCheckCastLevel1ToLevel1 11.48->15.80 11.47->15.78 timeCheckCastLevel2ToLevel1 15.08->15.79 15.08->15.79 timeCheckCastLevel3ToLevel1 19.01->15.82 17.94->15.81 timeCheckCastLevel9ToLevel1 42.55->15.79 42.63->15.81 timeCheckCastLevel9ToLevel2 39.70->14.36 39.70->14.35 timeInstanceOfLevel1ToLevel1 13.74->17.93 13.76->17.95 timeInstanceOfLevel2ToLevel1 17.02->17.95 16.99->17.93 timeInstanceOfLevel3ToLevel1 24.03->17.95 24.45->17.95 timeInstanceOfLevel9ToLevel1 47.13->17.95 47.14->18.00 timeInstanceOfLevel9ToLevel2 44.19->16.52 44.27->16.51 This suggests that the bitstring typecheck should not be used for exact type checks which would be equivalent to the "Level1ToLevel1" benchmark. Whether the implementation is a beneficial replacement for the kClassHierarchyCheck and kAbstractClassCheck on average depends on how many levels from the target class (or Object for a negative result) is a typical object's class. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing --jit Test: testrunner.py --host -t 670-bitstring-type-check Test: Pixel 2 XL boots. Test: testrunner.py --target --optimizing --jit Test: testrunner.py --target -t 670-bitstring-type-check Bug: 64692057 Bug: 71853552 Bug: 26687569 Change-Id: I538d7e036b5a8ae2cc3fe77662a5903d74854562
* Create dex subdirectoryDavid Sehr2018-01-051-1/+1
| | | | | | | | | Move all the DexFile related source to a common subdirectory dex/ of runtime. Bug: 71361973 Test: make -j 50 test-art-host Change-Id: I59e984ed660b93e0776556308be3d653722f5223
* MIPS: Support swaps between 128-bit locationsGoran Jakovljevic2017-12-151-0/+1
| | | | | | | | | | | | | | Add support for swaps between two SIMDStackSlots, two VectorRegisters (extended FpuRegister) and between a SIMDStackSlot and a VectorRegister. This fixes test 623-checker-loop-regressions for MIPS64R6 and MIPS32R6. Test: ./testrunner.py --optimizing --target in QEMU (MIPS64R6) Test: ./testrunner.py --optimizing --target in QEMU (MIPS32R6) Change-Id: I36aa209f79790fb6c08b9a171f810769a6b40afc
* Use ScopedArenaAllocator for code generation.Vladimir Marko2017-10-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | Reuse the memory previously allocated on the ArenaStack by optimization passes. This CL handles only the architecture-independent codegen and slow paths, architecture-dependent codegen allocations shall be moved to the ScopedArenaAllocator in a follow-up. Memory needed to compile the two most expensive methods for aosp_angler-userdebug boot image: BatteryStats.dumpCheckinLocked() : 19.6MiB -> 18.5MiB (-1189KiB) BatteryStats.dumpLocked(): 39.3MiB -> 37.0MiB (-2379KiB) Also move definitions of functions that use bit_vector-inl.h from bit_vector.h also to bit_vector-inl.h . Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Bug: 64312607 Change-Id: I84688c3a5a95bf90f56bd3a150bc31fedc95f29c
* ART: Introduce compiler data type.Vladimir Marko2017-09-251-16/+16
| | | | | | | | | | | | Replace most uses of the runtime's Primitive in compiler with a new class DataType. This prepares for introducing new types, such as Uint8, that the runtime does not need to know about. Test: m test-art-host-gtest Test: testrunner.py --host Bug: 23964345 Change-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c
* Refactor compiled_method.h .Vladimir Marko2017-09-201-3/+3
| | | | | | | | | | | Move LinkerPatch to compiler/linker/linker_patch.h . Move SrcMapElem to compiler/debug/src_map_elem.h . Introduce compiled_method-inl.h to reduce the number of `#include`s in compiled_method.h . Test: m test-art-host-gtest Test: testrunner.py --host Change-Id: Id211cdf94a63ad265bf4709f1a5e06dffbe30f64
* Use mmapped boot image intern table for PIC app HLoadString.Vladimir Marko2017-09-071-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement new HLoadString load kind for boot image strings referenced by PIC-compiled apps (i.e. prebuilts) that uses PC-relative load from a boot image InternTable mmapped into the apps .bss. This reduces the size of the PIC prebuilts that reference boot image strings compared to the kBssEntry as we can completely avoid the slow path and stack map. We separate the InternedStrings and ClassTable sections of the boot image (.art) file from the rest, aligning the start of the InternedStrings section to a page boundary. This may actually increase the size of the boot image file by a page but it also allows mprotecting() these tables as read-only. The ClassTable section is included in anticipation of a similar load kind for HLoadClass. Prebuilt services.odex for aosp_angler-userdebug (arm64): - before: 20862776 - after: 20308512 (-541KiB) Note that 92KiB savings could have been achieved by simply avoiding the read barrier, similar to the HLoadClass flag IsInBootImage(). Such flag is now unnecessary. Test: m test-art-host-gtest Test: testrunner.py --host Test: testrunner.py --host --pictest Test: testrunner.py --target on Nexus 6P. Test: testrunner.py --target --pictest on Nexus 6P. Test: Nexus 6P boots. Bug: 31951624 Change-Id: I5f2bf1fc0bb36a8483244317cfdfa69e192ef6c5
* MIPS32: Allow some patched instructions in delay slotsAlexey Frunze2017-08-181-2/+1
| | | | | | | | | | | Test: test-art-host-gtest Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-gtest32 Test: testrunner.py --target --optimizing --32 Test: same tests as above on CI20 Test: booted MIPS32R2 in QEMU Change-Id: I7e1ba59993008014d0115ae20c56e0a71fef0fb0
* MIPS: Reduce Baker read barrier code size overheadAlexey Frunze2017-07-191-3/+5
| | | | | | | | | | | | | | Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-gtest Test: testrunner.py --target --optimizing Test: same tests as above on CI20 Test: booted MIPS32 and MIPS64 in QEMU with poisoning in configurations: - with Baker read barrier thunks - without Baker read barrier thunks - ART_READ_BARRIER_TYPE=TABLELOOKUP Change-Id: I79f320bf8862a04215c76cfeff3118ebc87f7ef2
* MIPS32: ART VectorizerLena Djokic2017-07-131-0/+4
| | | | | | | | | | | MIPS32 implementation which uses MSA extension. Note: Testing is done with checker parts of tests 640, 645, 646 and 651, locally changed to cover MIPS32 cases. These changes can't be included in this patch since MSA is not a default option. Test: ./testrunner.py --target --optimizing -j1 in QEMU (mips32r6) Change-Id: Ieba28f94c48c943d5444017bede9a5d409149762
* MIPS32: Saves 128-bit vector registers along SuspendCheckSlowPathLena Djokic2017-07-061-1/+7
| | | | | | | | | We need to save 128 bits of data. This is only done for vector registers that are live, so overhead is not too big. Test: mma test-art-host-gtest Test: ./testrunner.py --optimizing --target in QEMU (MIPS) Change-Id: I0f792e9c98011be3e24d5fad35a8244faafcb9a0
* Merge "MIPS: Shorten .bss string/class loads"Treehugger Robot2017-07-031-14/+52
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| * MIPS: Shorten .bss string/class loadsAlexey Frunze2017-06-081-14/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a follow-up to https://android-review.googlesource.com/#/c/384033/. Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: testrunner.py --target --optimizing Test: same tests as above on CI20 Test: booted MIPS32R2 and MIPS64 in QEMU in configurations: ART_USE_READ_BARRIER=false, ART_READ_BARRIER_TYPE=TABLELOOKUP Change-Id: I4cb2f4ded13c0d9fc960c7eac55396f7931c1e38
* | MIPS32: MoveLocation refactoringLena Djokic2017-06-281-2/+0
|/ | | | | | | | | | | Move32 and Move64 are removed so MoveLocation now handles all cases. Reason for this are 128-bit (SIMDStackSlot, VectorRegister) moves which will be added in follow-up patch. Test: mma test-art-host-gtest Test: ./testrunner.py --optimizing --target in QEMU Change-Id: I93496e74874f77337b11b2265aa4b470bc7c6ce2
* Use ArtMethod* .bss entries for HInvokeStaticOrDirect.Vladimir Marko2017-06-071-4/+3
| | | | | | | | | | Test: m test-art-host-gtest Test: testrunner.py --host Test: testrunner.py --target Test: Nexus 6P boots. Test: Build aosp_mips64-userdebug. Bug: 30627598 Change-Id: I0e54fdd2e91e983d475b7a04d40815ba89ae3d4f
* Replace invoke kind kDexCacheViaMethod with kRuntimeCall.Vladimir Marko2017-06-061-2/+4
| | | | | | | | | | | | | | | | In preparation for replacing the dex cache method array with a hash-based array, get rid of one unnecessary use. This method load kind is currently used only on mips for irreducible loops and OSR, so this should have no impact on x86/x86-64/arm/arm64. Test: m test-art-host-gtest Test: testrunner.py --host Test: Repeat the above tests with manually changing kDexCachePcRelative to kRuntimeCall in sharpening.cc. (Ignore failures in 552-checker-sharpening.) Bug: 30627598 Change-Id: Ifce42645f2dcc350bbb88c2f4642e88fc5f98152
* Refactor profiles to use TypeReference instead of ClassReferenceMathieu Chartier2017-05-251-1/+1
| | | | | | | | | | | Refactor type reference into runtime and use it for profiles. ClassReference was just duplicated code since it wasn't even using the class def indexes. Test: test-art-host Bug: 62040831 Change-Id: Ia92f21c0e85c00321f52c97bb7a90158d882849b
* Use PC-relative pointer to boot image methods.Vladimir Marko2017-05-221-4/+8
| | | | | | | | | | | | | | In preparation for adding ArtMethod entries to the .bss section, add direct PC-relative pointers to methods so that the number of needed .bss entries for boot image is small. Test: m test-art-host-gtest Test: testrunner.py --host Test: testrunner.py --target on Nexus 6P Test: Nexus 6P boots. Test: Build aosp_mips64-userdebug Bug: 30627598 Change-Id: Ia89f5f9975b741ddac2816e1570077ba4b4c020f
* Remove LoadString/Class kind kBootImageLinkTimeAddress.Vladimir Marko2017-05-161-15/+0
| | | | | | | | | | | | We no longer support non-PIC boot image compilation. Also clean up some obsolete code for method patches and make JIT correctly report itself as non-PIC. Test: testrunner.py --host Test: testrunner.py --target Bug: 33192586 Change-Id: I593289c5c1b0e88b82b86a933038be97bbb15ad2
* Merge "MIPS32: Implement branchless HCondition for longs"Treehugger Robot2017-05-081-0/+1
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| * MIPS32: Implement branchless HCondition for longsTijana Jakovljevic2017-03-081-0/+1
| | | | | | | | | | | | | | | | Test: booted MIPS32 in QEMU Test: mma test-art-target-run-test Test: mma test-art-target-gtest-codegen_test Change-Id: Ie4eac862fa5577905db9f3f0746c2f7dc58f7a2b
* | MIPS: java.lang.Integer.valueOf intrinsic.Chris Larsen2017-04-301-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Test: run-test --64 --optimizing 640-checker-integer-valueof Test: run-test --64 640-checker-integer-valueof Test: run-test --64 --no-prebuild --optimizing 640-checker-integer-valueof Test: run-test --64 --no-prebuild 640-checker-integer-valueof Test: run-test --optimizing 640-checker-integer-valueof Test: run-test 640-checker-integer-valueof Test: run-test --no-prebuild --optimizing 640-checker-integer-valueof Test: run-test --no-prebuild 640-checker-integer-valueof Test: mma test-art-host Test: mma test-art-target Booted on both MIPS32 and MIPS64 emulators. Change-Id: I5b2f21cf2334c392080cff9654150504207f4c01
* | MIPS: Implement read barriers.Alexey Frunze2017-03-281-1/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the core functionality. Further improvements will be done separately. This also adds/moves memory barriers where they belong and removes the UnsafeGetLongVolatile and UnsafePutLongVolatile MIPS32 intrinsics as they need to load/store a pair of registers atomically, which is not supported directly by the CPU. Test: booted MIPS32R2 in QEMU Test: test-art-target-run-test Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: "testrunner.py --target --optimizing -j1" Test: same MIPS64 boot/test with ART_READ_BARRIER_TYPE=TABLELOOKUP Test: "testrunner.py --target --optimizing --32 -j2" on CI20 Test: same CI20 test with ART_READ_BARRIER_TYPE=TABLELOOKUP Change-Id: I0ff91525fefba3ec1cc019f50316478a888acced
* | Merge "Remove --include-patch-information option from dex2oat."Richard Uhler2017-03-091-2/+0
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| * Remove --include-patch-information option from dex2oat.Richard Uhler2017-03-081-2/+0
| | | | | | | | | | | | | | | | | | | | Because we no longer support running patchoat on npic oat files, which means the included patch information is unused . Bug: 33192586 Test: m test-art-host Change-Id: I9e100c4e47dc24d91cd74226c84025e961d30f67
* | MIPS64: Refactor implicit null checks in array/field get/setTijana Jakovljevic2017-03-031-1/+0
|/ | | | | | | | | | | | | | | | Rationale: on MIPS64 64-bit loads and stores may be performed as pairs of 32-bit loads/stores. Implicit null checks must be associated with the first 32-bit load/store in a pair and not the last. This change ensures proper association of said checks (a few were done after the last 32-bit load/store in a pair) and lays ground for further improvements in array/field get/set. Additionally ported to MIPS32. Test: mma test-art-target-run-test in QEMU Test: mma test-art-host-gtest Change-Id: If2612df62c21522959e69c637a36cc4ea962a32e
* MIPS: Support kJitTableAddress kinds of string/class loads.Alexey Frunze2017-02-011-0/+30
| | | | | | | | | | | | Also remove a few stale comments. Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: "make -j1 ART_TEST_DEFAULT_COMPILER=false ART_TEST_OPTIMIZING=false ART_TEST_INTERPRETER=false ART_TEST_JIT=true test-art-target-run-test" Test: booted MIPS32R2 in QEMU Change-Id: I8914b8e6594e030f8137e7fface1ae20b6d6b971
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