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* Patch supports Intel(R) AVX/AVX2 MOV Instructionjaishank2019-04-251-2/+19
* Disassemble saturation arithmetic x86/x86_64.Aart Bik2018-03-121-0/+16
* Bunch of SIMD for x86 and x86_64Aart Bik2017-08-111-0/+5
* Min/max SIMDization support.Aart Bik2017-05-151-1/+65
* SIMD pcmpgtb,w,d,q for x86/x86_64Aart Bik2017-04-041-0/+32
* SIMD pavgb,w for x86/x86_64Aart Bik2017-03-311-0/+16
* Properly disassemble cmpeq for x86/x86_64Aart Bik2017-03-221-0/+18
* x86/string compression: Use TESTB instead of TESTL in String.charAt().Vladimir Marko2017-02-171-1/+1
* Added a few integral SIMD extensions for x86/x86_64 (SSE).Aart Bik2017-02-131-0/+16
* ART: Detach libart-disassembler from libartAndreas Gampe2016-09-081-2/+4
* ART: Add thread offset printing hook to disassemblerAndreas Gampe2016-08-191-3/+2
* Merge "ART: Convert pointer size to enum"Treehugger Robot2016-08-021-2/+2
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| * ART: Convert pointer size to enumAndreas Gampe2016-08-011-2/+2
* | Fixed bug in disassembly of roundss/roundsdAart Bik2016-08-011-2/+2
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* Merge "ART: disassembler_x86 doesn't recognize NOPs"Treehugger Robot2016-07-151-0/+32
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| * ART: disassembler_x86 doesn't recognize NOPsSerdjuk, Nikolay Y2016-01-211-0/+32
* | Implemented BitCount as an intrinsic. With unit test.Aart Bik2016-01-201-0/+5
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* Add X86 bsf and rotate instructionsMark Mendell2015-09-151-0/+5
* Add 'bsr' instruction to x86 and x86_64Mark Mendell2015-08-141-0/+5
* Add rep movsw to x86 and x86_64 instructions.Mark Mendell2015-08-141-0/+3
* Added disassembler support for repe_cmpsw instruction in x86, x86_64agicsaki2015-07-301-0/+3
* Fix for incorrect encode and parse of PEXTRW instructionnikolay serdjuk2015-04-291-0/+8
* Fix for incorrect parse of PEXTRW instructionnikolay serdjuk2015-04-071-1/+1
* [optimizing] Implement x86/x86_64 math intrinsicsMark Mendell2015-04-011-0/+18
* ART: Fix x86 disassemblerAndreas Gampe2015-01-271-10/+16
* Fix crash in x86 disassembler.Nicolas Geoffray2014-12-161-1/+1
* ART: Do not inline elf writer debug symbolsAndreas Gampe2014-12-151-2/+2
* ART: Break up x86 disassembler main functionAndreas Gampe2014-12-151-237/+274
* Tidy x86 disassemblerIan Rogers2014-11-071-24/+84
* Tidy logging code not using UNIMPLEMENTED.Ian Rogers2014-10-241-2/+2
* C++11 related clean-up of DISALLOW_..Ian Rogers2014-10-221-2/+3
* Tidy up logging.Ian Rogers2014-10-221-0/+1
* Enable -Wimplicit-fallthrough.Ian Rogers2014-10-091-1/+1
* ART: Fix some -Wpedantic errorsAndreas Gampe2014-09-291-5/+5
* Avoid printing absolute addresses in oatdumpBrian Carlstrom2014-09-161-3/+5
* ART: Vectorization opcode implementation fixesLupusoru, Razvan A2014-09-031-59/+34
* ART: Add non-temporal store supportJean Christophe Beyler2014-08-261-0/+1
* Implement inlined shift long for 32bitYixin Shou2014-08-141-0/+12
* ART: Correct disassembling of 64bit immediates on x86_64Vladimir Kostyukov2014-07-301-2/+2
* ART: Correct disassembling of regs from opcodesVladimir Kostyukov2014-07-091-3/+5
* Merge "X86 Backend support for vectorized float and byte 16x16 operations"Ian Rogers2014-07-081-3/+17
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| * X86 Backend support for vectorized float and byte 16x16 operationsUdayan Banerji2014-07-081-3/+17
* | x86_64: Clean-up after cmp-long fixSerguei Katkov2014-07-091-4/+6
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* Merge "ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation"Ian Rogers2014-07-071-0/+27
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| * ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generationOlivier Come2014-06-251-0/+27
* | ART: FF-opcodes are target-specificVladimir Kostyukov2014-07-031-8/+15
* | Load 64 bit constant into GPR by single instruction for 64bit modeYixin Shou2014-07-021-2/+12
* | ART: FPU instructions support in disassemblerVladimir Kostyukov2014-07-011-5/+27
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* X86 Dis: Add missing mov byte; Add size suffixesMark Mendell2014-06-211-6/+32
* Add Move with Sign Extend Double to disassemblerMark Mendell2014-06-081-0/+11
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