diff options
| author | Ben Cheng <bccheng@google.com> | 2009-09-11 13:42:05 -0700 |
|---|---|---|
| committer | Ben Cheng <bccheng@google.com> | 2009-09-11 14:21:58 -0700 |
| commit | dcf3e5d43a1831a166f70cb9e0694cd4b0b356b0 (patch) | |
| tree | 52601ee529a5e21c46759521c5d7ba09b41889f2 /vm/compiler/codegen/arm/ArchUtility.c | |
| parent | fc869d7f570750b2318d91f1b047e134a74b8e09 (diff) | |
Model resource usage for each Thumb/Thumb2 instrution.
This is an mid-point checkin to avoid future merge nightmare for the register
allocator work.
Diffstat (limited to 'vm/compiler/codegen/arm/ArchUtility.c')
| -rw-r--r-- | vm/compiler/codegen/arm/ArchUtility.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/vm/compiler/codegen/arm/ArchUtility.c b/vm/compiler/codegen/arm/ArchUtility.c index ab46b449a..551e1f753 100644 --- a/vm/compiler/codegen/arm/ArchUtility.c +++ b/vm/compiler/codegen/arm/ArchUtility.c @@ -204,6 +204,9 @@ static void dumpLIRInsn(LIR *arg, unsigned char *baseAddr) u2 *cPtr = (u2*)baseAddr; /* Handle pseudo-ops individually, and all regular insns as a group */ switch(lir->opCode) { + case ARM_PSEUDO_IT_BOTTOM: + LOGD("-------- IT_Bottom"); + break; case ARM_PSEUDO_EXTENDED_MIR: /* intentional fallthrough */ case ARM_PSEUDO_SSA_REP: @@ -283,7 +286,8 @@ void dvmCompilerCodegenDump(CompilationUnit *cUnit) for (lirInsn = cUnit->wordList; lirInsn; lirInsn = lirInsn->next) { armLIR = (ArmLIR *) lirInsn; LOGD("%p (%04x): .word (0x%x)\n", - (char*)cUnit->baseAddr + armLIR->generic.offset, armLIR->generic.offset, + (char*)cUnit->baseAddr + armLIR->generic.offset, + armLIR->generic.offset, armLIR->operands[0]); } } |