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authorUdayan Banerji <udayan.banerji@intel.com>2013-03-29 14:05:18 -0700
committerElliott Hughes <enh@google.com>2013-04-01 16:34:35 -0700
commited2876e520bbdf295f894c5fb7c5a58bf90bf60f (patch)
tree7328054d0c2069aa2ca3d57a97f2fcd5086cf733 /vm/compiler/codegen/x86/CodegenInterface.cpp
parent82c80de14da66b80474b298ae99cbff37cdf9b53 (diff)
[x86] Fix errors with WITH_JIT_TUNING defined
This patch makes the necessary changes to pass on correct information to dvmBumpNoChain, so that WITH_JIT_TUNING flag can be enabled for x86 codegen Signed-off-by: Udayan Banerji <udayan.banerji@intel.com> (cherry picked from commit 19eb287ac848f10e03ca2614bf53bd9d1ddd3724) Change-Id: I6871dd0839b3656beed4633e3a0f3df780af98a0
Diffstat (limited to 'vm/compiler/codegen/x86/CodegenInterface.cpp')
-rw-r--r--vm/compiler/codegen/x86/CodegenInterface.cpp8
1 files changed, 7 insertions, 1 deletions
diff --git a/vm/compiler/codegen/x86/CodegenInterface.cpp b/vm/compiler/codegen/x86/CodegenInterface.cpp
index 0f516b311..46f097971 100644
--- a/vm/compiler/codegen/x86/CodegenInterface.cpp
+++ b/vm/compiler/codegen/x86/CodegenInterface.cpp
@@ -327,7 +327,7 @@ static bool inlineCachePatchEnqueue(PredictedChainingCell *cellAddr,
cellAddr->clazz = newContent->clazz;
//cacheflush((intptr_t) cellAddr, (intptr_t) (cellAddr+1), 0);
#endif
-#if defined(IA_JIT_TUNING)
+#if defined(WITH_JIT_TUNING)
gDvmJit.icPatchInit++;
#endif
COMPILER_TRACE_CHAINING(
@@ -720,6 +720,12 @@ static void handleInvokePredictedChainingCell(CompilationUnit *cUnit, int blockI
#ifndef PREDICTED_CHAINING
//assume rPC for callee->insns in %ebx
scratchRegs[0] = PhysicalReg_EAX;
+#if defined(WITH_JIT_TUNING)
+ /* Predicted chaining is not enabled. Fall back to interpreter and
+ * indicate that predicted chaining was not done.
+ */
+ move_imm_to_reg(OpndSize_32, kInlineCacheMiss, PhysicalReg_EDX, true);
+#endif
call_dvmJitToInterpTraceSelectNoChain();
#else
/* make sure section for predicited chaining cell is 4-byte aligned */