[x86] Fix errors with WITH_JIT_TUNING defined

This patch makes the necessary changes to pass on correct information to
dvmBumpNoChain, so that WITH_JIT_TUNING flag can be enabled for x86 codegen

Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>

(cherry picked from commit 19eb287ac848f10e03ca2614bf53bd9d1ddd3724)

Change-Id: I6871dd0839b3656beed4633e3a0f3df780af98a0

1 files changed, 11 insertions, 0 deletions

diff --git a/vm/compiler/codegen/x86/LowerInvoke.cpp b/vm/compiler/codegen/x86/LowerInvoke.cpp
index 3d02190fa..10bc197f1 100644
--- a/vm/compiler/codegen/x86/LowerInvoke.cpp
+++ b/vm/compiler/codegen/x86/LowerInvoke.cpp
@@ -833,6 +833,12 @@ int common_invokeArgsDone(ArgsDoneType form, bool isJitFull) {
         if(callNoChain) {
             scratchRegs[0] = PhysicalReg_EAX;
             load_effective_addr(8, PhysicalReg_ESP, true, PhysicalReg_ESP, true);
+#if defined(WITH_JIT_TUNING)
+            /* Predicted chaining failed. Fall back to interpreter and indicate
+             * inline cache miss.
+             */
+            move_imm_to_reg(OpndSize_32, kInlineCacheMiss, PhysicalReg_EDX, true);
+#endif
             call_dvmJitToInterpTraceSelectNoChain(); //input: rPC in %ebx
         } else {
             //jump to the stub at (%esp)
@@ -906,6 +912,11 @@ void generate_invokeNative(bool generateForNcg) {
         //move rPC by 6 (3 bytecode units for INVOKE)
         alu_binary_imm_reg(OpndSize_32, add_opc, 6, PhysicalReg_EBX, true);
         scratchRegs[0] = PhysicalReg_EAX;
+#if defined(WITH_JIT_TUNING)
+        /* Return address not in code cache. Indicate that continuing with interpreter
+         */
+        move_imm_to_reg(OpndSize_32, kCallsiteInterpreted, PhysicalReg_EDX, true);
+#endif
         call_dvmJitToInterpTraceSelectNoChain(); //rPC in %ebx
     }
     return;