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Add support for customer device extension
Change-Id: I0402a630ba212d1c5e81cda110f61210f7b60384
(cherry picked from commit 11499df326462bfe25890a35c6abbf019ff7784e)
(cherry picked from commit e03b8f8da9cf4eef64cedf39ce9ca90d26ce5124)
(cherry picked from commit fb360be406f35b9591f12c61936657f03cc5880f)
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An leading underscore followed by a capital letter is a reserved
name space in C and C++.
This change also moves any #include directives within the include
guard in some of the compiler/codegen/arm header files.
Change-Id: I9715e2c5301699d31886e61d0fe6e29483555a2a
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Register maps are generated only for a subset of instructions (to
limit memory consumption). The previous interpreter restructuring
was doing suspend checks at locations that had no register maps.
This CL limits suspend checks to instructions that have register
maps, and also expands that set to include foward as well as
backwards branches.
Change-Id: Ia2b2e1096efe524fdb2a5fd4be171a4216b6a3b4
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The invoke-object-init instruction pretends to be a regular invoke
that only knows how to call Object.<init>. As such it always takes
one argument, and if we use the /range version we can specify the
"this" register with 16 bits instead of only 4.
Bug 3486699
Change-Id: I9ee4700c6935beee1dcbaa583b57befd33641414
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Increase the human-readable form to differentiate from HC.
Increase the build number because we need to re-DEX stuff after
some recent changes (e.g. we've increased the number of methods
that need to use return-void-barrier).
Change-Id: I8f2c94694f7a11e86de882963ba509711f668f47
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Minor increase to differentiate HC MR1 from HC.
Change-Id: I2ccd57d4952c19c2df2fe948ce60c476819450d4
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This reverts commit 7ecd89dc02ce00c425788bd4989bdb6cde9a618a.
Change-Id: I427635b7e3f7be45cfde78b8046dab3b23b64562
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Change-Id: I891b63a676b6c3f12fdbc5858ef12f235bc1b9c1
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Increment the minor version post-GB. Increment DALVIK_VM_BUILD, which
should've happened when I added return-void-barrier.
Change-Id: I65480ced9183d0e3c84be2c1eeb9670017bbbc8f
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This adds instructions for {i,s}{get,put}{,-object}-volatile, for a
total of eight new instructions.
On SMP systems, these instructions will be substituted in for existing
field access instructions, either by dexopt or during just-in-time
verification. Unlike the wide-volatile instructions, these will not be
used at all when the VM is not built for SMP.
(Ideally we'd omit the volatile instruction implementations entirely on
non-SMP builds, but that requires a little work in gen-mterp.py.)
The change defines and implements the opcodes and support methods, but
does not cause them to be used.
Also, changed dvmQuasiAtomicRead64's argument to be const.
Change-Id: I9e44fe881e87f27aa41f6c6e898ec4402cb5493e
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This makes it one more than the last one.
Change-Id: I7227f8c08dab5cec8f878a888382a851339fccde
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Fixes all known bugs in our handling of supplementary characters. This change
introduces a performance regression on the assumption that it won't be released
without a corresponding JIT change to enable the code to be inlined back to
pretty much what it used to be.
Bug: 2587122
Change-Id: I3449c9718bbe32ebe53b6c10454ae1dc82105b59
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Before:
benchmark ns logarithmic runtime
IsEmpty 115 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
LengthEqualsZero 21 XXXXX||||||||||||||
With C intrinsic:
IsEmpty 30 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
LengthEqualsZero 20 XXXXXXXXXXXXXXXXXXXX||||||
With assembler intrinsic:
IsEmpty 15 XXXXXXXXXXXXXXXXXXXX||||||
LengthEqualsZero 21 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
(All times on passion.)
Change-Id: Ifcc37fe7b8efdd377675a448e0085e490d6767bc
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This adds four new instructions for accessing volatile wide fields (long
and double). The JLS requires that such accesses are atomic, but the
VM doesn't otherwise make guarantees about the atomicity of reads and
writes on 64-bit fields.
There are no behavioral changes. This just adds definitions for the new
instructions and a couple of tests. The current implementation is just
the non-volatile form of the instructions or a C stub, but since we're
not generating them it doesn't really matter yet.
Also:
- bumped Dalvik version to 1.3.0
- added a note to the x86-atom TODO list
For bug 1633591.
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Like "execute-inline", this is an instruction generated by dexopt that
replaces a method invoke instruction. It's useful for small, frequently
called methods in the core libs.
As with execute-inline, we allow at most 4 arguments, but with /range
we're no longer limited to the low 16 registers.
Also: marked execute-inline as being able to throw an exception.
Needed: native x86 implementation; support in JIT.
For bug 2268232.
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Also, send correct version in JDWP VirtualMachine.Version packet.
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This provides an inline-native version of String.indexOf(int) and
String.indexOf(int, int), i.e. the functions that work like strchr().
Has a fairly solid impact on specific benchmarks. Might give a boost to
an app somewhere.
Added some indexOf tests to 020-string.
Added hard-coded field offsets for String. These are verified during
startup. Improves some of our String micro-benchmarks by ~10%.
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The code was assuming that the reference type could always be inferred
from the error code, but in two cases it couldn't. This resulted in a
weird string appearing where the class name should be in the exception.
The type is now explicitly stuffed into the replacement instruction.
I added one additional test to 075; with this, plus 003 and 077, I think
we have full coverage.
For bug 2084560.
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For a first pass, I inlined the various flavors of abs(), min()/max() on
integers, sqrt(), cos(), and sin(). These were selected based on a
static analysis of a few of our jar files.
A test of repeated sin/cos/sqrt calls on a G1-class device showed an
improvement of 28%. This would improve more on devices with VFP
support if the VM is compiled with -mfpu=vfp.
Also: clarified a warning and removed some "#if 0" stuff.
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This should have been incremented when OP_THROW_VERIFICATION_ERROR was
added, since older VMs won't be able to handle the odex we generate.
Dropped the log level on the warning.
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Give it a bump for JIT and precise GC.
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