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* | Fix Thumb2 codegen.Dan Bornstein2010-11-111-2/+3
| | | | | | | | | | | | My local build wasn't doing Thumb2. Unsurprising in retrospect. Change-Id: I38ab4dc80e1115cf459f6d890c7d0eb2705fa7c9
* | Add a new index type table for instruction decoding.Dan Bornstein2010-11-101-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is in prep for -- recurring theme here -- adding the new extended opcode formats. It turns out that we can avoid a lot of duplicated code if we determine the type of thing referred to in index-bearing instructions inside the general instruction decoder. To do so straightforwardly, this means adding a new opcode info table and then passing it into the decoder. Rather than add another argument to the decoder, I defined a struct to contain all the info tables together, and a pointer to that can get passed in. I simplified the setting up of the info tables, too, so all the allocation is handled within InstrUtils, rather than being (partially) duplicated in a couple places. The only downside is that dexdump will construct one more table than it actually needs, but given that construction is quick and the table is only 256 bytes (though will soon be growing to -- gasp! -- 294 bytes), I figure it's not such a big deal. Most of the files that changed only had edits for how to refer to these info tables. Change-Id: Ia6f1cb25da6e558ac90c6dd3af6bce36b82a6b4d
* | Reharmonize the implementation with the spec.Dan Bornstein2010-11-091-2/+2
|/ | | | | | | | | | | | | | | | In particular, I altered the naming of some instruction format fields as well as the names of instruction formats themselves, all in an attempt to make the implementation be a more straightforward match of the spec. This patch mostly changes comments to reflect the new harmonized reality. The only "code-like" change is the renaming of kFmt3inline and kFmt3rinline to kFmt35mi and kFmt3rmi (respectively), which is what they're called in the spec. Bonus: Added the new extended opcode instruction formats to InstrUtils.h, though I left them commented out for now. Change-Id: I0109f361c1e9b6f0308c45e8cda5320e9ad3060c
* Merge remote branch 'goog/dalvik-dev' into dalvik-dev-to-masterBrian Carlstrom2010-11-0317-1625/+279
|\ | | | | | | Change-Id: I0731a0f623694d15d311dae1450a50e105905421
| * JIT - support for return-void-barrier [Issue 2992352]buzbee2010-11-016-13/+15
| | | | | | | | | | | | | | | | Slight reworking of the memory barrier instruction generation to generalize it, and then add "dmb st" for the new return-void-barrier instruction. Change-Id: Iad95aa5b0ba9b616a17dcbe4c6ca2e3906bb49dc
| * Fine-tune the instructions on the method invocation path.Ben Cheng2010-10-121-1/+8
| | | | | | | | | | | | | | | | | | | | | | 1) Initialize the register and out sizes for callee methods through constant moves. 2) Eliminate an unnecessary load of Dalvik PC for chained and native callees. Improved method invocation performance by ~3%. Change-Id: Iead1276eed0ba527e82eb876f08d169ab9b496b2
| * Merge "Re-organize target-independent JIT code." into dalvik-devbuzbee2010-10-066-360/+134
| |\
| | * Re-organize target-independent JIT code.buzbee2010-09-266-360/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | Most of CodegenFactory.c is at a high-enough abstraction level to reuse for other targets. This CL moves the target-depending routines into a new source file (ArchFactory.c) and what's left up a level into the target-independent directory. Change-Id: I792d5dc6b2dc8aa6aaa384039da464db2c766123
| * | am 7c1f9b34: resolved conflicts for merge of 6d55b332 to masterbuzbee2010-09-301-4/+4
| |\ \ | |/ / |/| | | | | | | | | | | | | | Merge commit '7c1f9b34d49aa7cea9b830226e33e95d7608cf76' into dalvik-dev * commit '7c1f9b34d49aa7cea9b830226e33e95d7608cf76': GC Card marking fix for SPUT_OBJECT - use correct object head
| * | Change GC card making to use object head, bug fix for volatile sput objbuzbee2010-09-281-5/+14
| |/ | | | | | | | | | | | | | | | | This CL changes the way we mark GC card to consistently use the object head (previously, we marked somewhere in the object - often the head, but not always). Also, previously a coding error caused us to skip the card mark for OP_APUT_OBJECT_VOLATILES. Fixed here. Change-Id: I53eb333b9bd0b770201af0dc617d9a8f38afa699
| * Merge "JIT: Remove stray (but harmless) line of code" into dalvik-devbuzbee2010-09-241-1/+0
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| | * JIT: Remove stray (but harmless) line of codebuzbee2010-09-241-1/+0
| | | | | | | | | | | | Change-Id: I5319418678b5390b75267af9cc2c9fa6f35f3bdb
| * | JIT: Source code reorganization to isolate target independent codebuzbee2010-09-249-1250/+122
| |/ | | | | | | | | | | | | Much of the register utility code is target independent. Move it up a level so the x86 JIT can use it. Change-Id: Id9895a42281fd836cb1a2c942e106de94df62a9a
* | resolved conflicts for merge of 6d55b332 to masterbuzbee2010-09-301-4/+4
|\ \ | | | | | | | | | Change-Id: I21e35d4cdf2636ae3cd7facd45ad4f5c4ab82e7b
| * | GC Card marking fix for SPUT_OBJECT - use correct object headbuzbee2010-09-301-4/+4
| | | | | | | | | | | | Change-Id: I8b84a4f1e1690f5b62de7404ea6ede00317848bb
* | | resolved conflicts for merge of 2e75e47d to masterbuzbee2010-09-281-5/+14
|\| | | |/ |/| | | Change-Id: I644b3cd50e3c63b209741c8b818b4c1435ee8218
| * Change GC card making to use object head, bug fix for volatile sput objbuzbee2010-09-281-5/+14
| | | | | | | | | | | | | | | | | | This CL changes the way we mark GC card to consistently use the object head (previously, we marked somewhere in the object - often the head, but not always). Also, previously a coding error caused us to skip the card mark for OP_APUT_OBJECT_VOLATILES. Fixed here. Change-Id: I133ef6395c51a0466c9708209b08e79c3083aff2
| * JIT: Fix inconsistent handling of sub-word instance git/putbuzbee2010-09-091-19/+5
| | | | | | | | | | | | | | | | | | | | | | | | The portable interpreter and fast interpreter use 32-bit accesses for all sub-word scalars. The JIT generated code to tailor the access to the data size. It doesn't matter which approach is taken, but all interpreters & JIT must be consistent. Changing the JIT to use 32-bit accesses for all sub-word instance scalars. Fix for Issue 2973137 Change-Id: I8b1e9e6be075012c7c174728b77c7a76884975b7
* | Staticify.Andy McFadden2010-09-172-2/+2
| | | | | | | | | | | | Mark some functions "static". Change-Id: Ia80bccab1f72690729e43f99783d34fe366108b2
* | Add return-void-barrier instruction.Andy McFadden2010-09-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces the return-void-barrier instruction, which is identical to return-void on UP systems, but provides an additional store/store barrier on SMP. This is intended for use in constructors of objects with final fields. The assembler doesn't like "dmb st", and we don't have an ANDROID_MEMBAR_STORE barrier defined, so this currently uses full fences. This just defines the new instruction. It's not actually used yet. Also, removed some stale "unused" files from the x86 and x86-atom directories. Bug 2965743. Change-Id: I072e372fd2d57f2617a8d4fff5fd4b38bdda75d1
* | JIT: Fix inconsistent handling of sub-word instance git/putbuzbee2010-09-091-19/+5
| | | | | | | | | | | | | | | | | | | | | | | | The portable interpreter and fast interpreter use 32-bit accesses for all sub-word scalars. The JIT generated code to tailor the access to the data size. It doesn't matter which approach is taken, but all interpreters & JIT must be consistent. Changing the JIT to use 32-bit accesses for all sub-word instance scalars. Fix for Issue 2973137 Change-Id: I6108ccc98c1b43974373764913d5f8d0d8723cd4
* | am 8ef4d4f3: am 58a661c4: am ddc7d29b: Correct Volatile SGET/SPUT format ↵buzbee2010-09-031-0/+2
|\| | | | | | | | | | | | | | | | | tag, add missing cases for JIT Merge commit '8ef4d4f3d050b0130dbf723285990b045f04d5f3' into dalvik-dev * commit '8ef4d4f3d050b0130dbf723285990b045f04d5f3': Correct Volatile SGET/SPUT format tag, add missing cases for JIT
| * Correct Volatile SGET/SPUT format tag, add missing cases for JITbuzbee2010-09-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix for http://b/issue?id=2971877, which was identified via debug tracing on http://b/issue?id=2971569. There were a couple of problems: first, the volatile sget/sput byte codes had the wrong format tag (22c instead of 21c). Second, the JIT was missing a couple of case statments to handle these. As far as the JIT goes, this would not have caused correctness problems, but would have been slower than necessary. Change-Id: I57a41c4e063642b0c19acba5bb0855dd8ce2d4ba
| * Intrinsics for float/int and double/long conversions.Elliott Hughes2010-09-011-1/+27
| | | | | | | | | | | | | | [cherry-picked e22bd84c8c8a57ddd86c21a1f65137d549b07935 from dalvik-dev to gingerbread] Bug: 2935622 Change-Id: Ib4de19033dc4a08f41bf0eb0f7a21dcde216aae3
| * JIT: Add memory barriers on monitor enter/exit [issue 2951403]buzbee2010-08-271-0/+2
| | | | | | | | | | | | Possibly the cause of [2950977 error in onDraw() method for stingray] Change-Id: I3237c95a34daa75cd680b73d426dde11f3611a0e
| * Make JIT inliner work under single-stepping mode.Ben Cheng2010-08-261-5/+1
| | | | | | | | | | | | | | | | Bug: 2936661 (cherry-picked from dalvik-dev) Change-Id: I35a012bd4dba2a2f9541b96a2e787687bbc7cd19
* | JIT: Add new compare-immed-and-branch primative & drop useless clrexbuzbee2010-08-315-51/+45
| | | | | | | | | | | | | | This allows better use of cbz/cbnz on Thumb2 targets. Also, removed the clrex from the inline monitor enter code (not necessary). Change-Id: I3bfa90bcdf34f6ef3e2447c9c6f1b49a98a89e58
* | Make JIT inliner work under single-stepping mode.Ben Cheng2010-08-261-5/+1
| | | | | | | | | | Bug: 2936661 Change-Id: Id85530db5281e0ea28ffb31e8769f3bfec8be54a
* | am 6ba7529b: JIT: Add memory barriers on monitor enter/exit [issue 2951403]buzbee2010-08-261-0/+2
|\ \ | | | | | | | | | | | | | | | | | | Merge commit '6ba7529b233837a243cbdb4a6fd62520ab60a22f' into dalvik-dev * commit '6ba7529b233837a243cbdb4a6fd62520ab60a22f': JIT: Add memory barriers on monitor enter/exit [issue 2951403]
| * | JIT: Add memory barriers on monitor enter/exit [issue 2951403]buzbee2010-08-261-0/+2
| |/ | | | | | | | | | | Possibly the cause of [2950977 error in onDraw() method for stingray] Change-Id: I84da4dcb04735ccbedc21fa84c11c3ee8c4aa4e9
* / Intrinsics for float/int and double/long conversions.Elliott Hughes2010-08-231-1/+27
|/ | | | | Bug: 2935622 Change-Id: I0f9e564f1f94ccf6596a37a6f1c10253481d5062
* JIT: Fix for armv5te-VFP bug [Issue 2916682]buzbee2010-08-131-20/+20
| | | | | | | Temp register was clobbered after explicit use rather than before. Affects only armv5te-vfp builds. Change-Id: I0a1c3f69a299f31bd50f3ec95ae83681b89ae6f1
* JIT: Correct conversion of cb[n]z to cmp/cond_br pairbuzbee2010-08-101-1/+1
| | | | | | | | | This fixes the regression introduced in the fast assembly retry that was causing excessive bailouts. The good news is that with this fix, we're seeing a ~5% boost in Linpack because of the cb[n]z usage. Change-Id: Ib4a48dcba809af4343456eae49a90b4a1e3aee9d
* Print callee information in the JIT profile outoutBen Cheng2010-08-061-0/+19
| | | | | | | | | | | For example: TRACEPROFILE 0x48bbb2d4 11057 0.55% [0x45d(+1), 14011] ... -> Ljava/util/HashMap$HashIterator;hasNext;()Z It means the trace ends with a call to hasNext(), and inlining probably won't help the overall performance more than 0.55%. Change-Id: I9bf2a79c48d6cb569a9fe2e329022edf968664bb
* JIT: Fix for lightweight assembler retry mechanism.buzbee2010-08-061-6/+1
| | | | | | | | | | Removed a special path in the assembler that took in sideband info on some instructions and used it to modify pc-relative load addresses. This mechanism (used in some older chaining cells) is no longer needed, and was causing a problem for the new lightweight assembler retry mechanism. Change-Id: I1cca5b719bcdea0810831d889ebe2f935c61966f
* JIT: Fix for 2898397 assert in JIT (chain cell offset)buzbee2010-08-061-0/+2
| | | | | | | | My previous change to allow for lightweight assembler retries neglected to restore a sanity check cookie when re-assembling without fully rebuilding the trace. Change-Id: Ief7eb76263e272b9cd79345f8344bd35926f5b10
* More SMP fixes.Andy McFadden2010-08-061-2/+2
| | | | | | | | | | | Convert some ANDROID_MEMBAR_FULL uses into equivalent atomic ops. A couple of "bool" had to convert to "int" since we don't have atomic ops for bools. Replaced a local implementation of atomic inc with a call to the atomic inc function. Change-Id: I948b8080d743552bde014d3a6e716ed2c30ebef8
* JIT: Support for shift field in disassembler [issue 2465170]buzbee2010-08-052-8/+23
| | | | | | | | Many Thumb2 instructions allow for an optional shift to be applied to operand 2. This cl enhances the disassembler to show a non-zero shift in the dump output. Change-Id: I6cbfec46cd45e3f2acc9553f880e80764a1eb65d
* JIT: Reworked the assembler to be smarter about short instruction formsbuzbee2010-08-044-42/+70
| | | | | | | | | | | | | | | Previously, the JIT wasn't generating short-form compare and branch on zero/not zero instructions for Thumb2. The reason was that these only allow a 1-byte displacement, and when they didn't reach the assembler would abort the trace, split it in half and try again. This change re-enables cbz, cbnz generation and introduces a relatively lightweight retry mechanism. Also includes changes for Thumb2 to always generate large displacement literal loads and conditional branches to minimize the number of retry attempts. Change-Id: Icf066836fad203f5c0fcbbb2ae8e1aa73d1cf816
* Bug fixes for JIT loop detection and formationBen Cheng2010-08-041-2/+2
| | | | | | | | | | | Specifically: - Don't apply loop optimization if the basic induction variable is manipulated (ie excluding cases like "i+=0") - Fix a case where variables reloaded with constants in the body are not considered as loop invariants Bug: 2804188 Change-Id: Ia5ebb29bc6814b1be069e23794585f8313900b7d
* am baf196a7: Fix for 2892472 jit spew: No free temp registersbuzbee2010-08-041-0/+6
|\ | | | | | | | | | | | | Merge commit 'baf196a7b259704137cccf4058b78da15d4c3998' into dalvik-dev * commit 'baf196a7b259704137cccf4058b78da15d4c3998': Fix for 2892472 jit spew: No free temp registers
| * Fix for 2892472 jit spew: No free temp registersbuzbee2010-08-041-0/+6
| | | | | | | | | | | | | | Neglected some register allocation hygene, which caused a problem on armv5te builds. Change-Id: I666b39b88822c4d3d3d7f0e84386aca2920bb9f1
* | Implement method inlining for getters/settersBen Cheng2010-08-023-42/+256
|/ | | | | | | | | | | | | | | | | | Changes include: 1) Force the trace that ends with an invoke instruction to include the next instruction if it is a move-result (because both need to be turned into no-ops if callee is inlined). 2) Interpreter entry point/trace builder changes so that return target won't automatically be considered as trace starting points (to avoid duplicate traces that include the move result instructions). 3) Codegen changes to handle getters/setters invoked from both monomorphic and polymorphic callsites. 4) Extend/fix self-verification to form identical trace regions and handle traces with inlined callees. 5) Apply touchups to the method based parsing - still not in use. Change-Id: I116b934df01bf9ada6d5a25187510e352bccd13c
* JIT: Fix for Issue 2881687 - fix volatiles and re-enable JITbuzbee2010-07-301-15/+43
| | | | Change-Id: I2ccb4b46d92b729d5504ea9c1b771a5147096858
* JIT: Support for Dalvik volatiles (issue 2781881)buzbee2010-07-218-20/+126
| | | | | | Also, on SMP systems generate memory barriers. Change-Id: If64f7c98a8de426930b8f36ac77913e53b7b2d7a
* Interpreter & JIT support for write barriersbuzbee2010-07-131-6/+42
| | | | | | | | | In this iteration, cards are marked on either the store address or the object head (whichever leads to faster code). In all cases, though, card marks are deferred until after the associated store has completed. Change-Id: I633d6e8c3bebdb80bde92efb4fa6fc7cc84f60fc
* JIT: Fix for 2813841, use core regs for sub-word dataBill Buzbee2010-07-074-15/+38
| | | | | | | | | | | In an attempt to avoid unnecessary register copies, the JIT allows data items to live in either floating point or core registers until an instruction is used which requires one or the other. The bug here was that sub-word data was allowed to live in floating point registers at the point of a load or store. This cl forces the use of core registers in those cases. Change-Id: I60c2a0d1df9a299f6c5130371f44f2be9c348ded
* Add missing ']'s in ARM disassembler output.Elliott Hughes2010-06-291-20/+20
| | | | | | Also insert missing spaces after commas in some loads and stores. Change-Id: I1dad10eb86ef8dc0d0ab4b3b98c94d3a7663861e
* Jit: Fix for 2793725 SIGSEGV in JIT code cacheBill Buzbee2010-06-231-0/+2
| | | | | | | r8 was missing from the handler clobber set, and is stepped on by the handlers for inline string compareto and indexof. Change-Id: I6e5d6f46b595d638863b27edcc8718157a3e411f
* Relocate OpCodeNames.[ch].Andy McFadden2010-06-227-7/+7
| | | | | | | The JIT was pulling it out of the dexdump directory, which is Just Plain Wrong[tm]. Now it's part of libdex, for all to enjoy. Change-Id: Ic1e4c981eb2d70ccc3c841ceb5a54f4f77af2008
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