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* dalvik: Disable loop hoisting optimization on perf buildsSteve Kondik2014-05-081-0/+4
| | | | | | * Fixes VSCO Cam array traversal crash when perf is enabled. Change-Id: I57e59e407a538c4cc48972f4cf3167c505d7ded4
* Merge "Revert "Revert "Initialize callTgt variable""" into kitkatDavor Bertovic2014-04-011-1/+1
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| * Revert "Revert "Initialize callTgt variable""Davor Bertovic2014-04-011-1/+1
| | | | | | | | | | | | This reverts commit 5d1ce32a68a9d4e8eaef82ce7e5362d583604a24. Change-Id: Ibc369bee8d9ab982bbf527f74ad0998255125f3e
* | Merge "Revert "Initialize callTgt variable"" into kitkatDavor Bertovic2014-03-301-1/+1
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| * Revert "Initialize callTgt variable"Davor Bertovic2014-03-301-1/+1
| | | | | | | | | | | | This reverts commit 2ad51eaac2ce87c15593269ad842763bd4dc4da9. Change-Id: I8163b2af3e5082b184f495e1e30e29193d4fde7a
* | dalvik: add placeholder for future changesWei Wang2014-03-282-1/+10
|/ | | | | | add placeholder for future changes Change-Id: I09dd704a60857de71cafd7e6b64ee750c5cb95b1
* Initialize callTgt variableBernhard Rosenkränzer2014-03-281-1/+1
| | | | | | | | | | | | This silcences a clang build failure: dalvik/vm/compiler/codegen/arm/armv7-a-neon/../CodegenDriver.cpp:904:41: error: variable 'callTgt' is uninitialized when used here [-Werror,-Wuninitialized] LOAD_FUNC_ADDR(cUnit, r2, (int) callTgt); ^~~~~~~ Change-Id: Ic5b3bb492f19b842743bf7d6214c89301ff524e7 Signed-off-by: Bernhard Rosenkränzer <Bernhard.Rosenkranzer@linaro.org>
* vm: Enable fast multiply on perf builds tooSteve Kondik2014-03-245-13/+2
| | | | Change-Id: I74d152ea9cfe5b15daa9a8353ca27d8afa7474d2
* Dalvik: DMB Optimisations for TracingJITDavid Butcher2013-12-182-9/+9
| | | | | | | | Makes DMB domain ISH or ISHST instead of the implicit System. ISH (Inner Shareable) should be sufficient for all cores/clusters, but is not sufficient for GPU or other memory-mapped peripherals Change-Id: Id159228daba97bc3692d2eb1ee2786bae2ee34a7
* Merge branch 'kk_2.7_rb1.11' of git://codeaurora.org/platform/dalvik into ↵Steve Kondik2013-11-301-5/+11
|\ | | | | | | cm-11.0
| * dalvik: use T3 branch when target offset is too largeWei Wang2013-11-191-5/+11
| | | | | | | | | | | | | | | | T1 branch has offset limit of [-256, 254]. T3 branch has offset limit of [-1048576, 1048574]. Use T3 branch when target offset falls outside T1 range to avoid compiliation abort. Change-Id: I86809e08236b1f5f5102e3fce4df4b1e72e4b96c
* | Merge branch 'kk_2.7_rb1.9' of git://codeaurora.org/platform/dalvik into cafSteve Kondik2013-11-1123-153/+1409
|\| | | | | | | Change-Id: I885fab2470352d0a625c9946d0d5c9111486b713
| * dalvik: dalvik device extension pack.Xin Qi2013-10-3123-154/+1082
| | | | | | | | | | | | | | | | | | Add support for customer device extension Change-Id: I0402a630ba212d1c5e81cda110f61210f7b60384 (cherry picked from commit 11499df326462bfe25890a35c6abbf019ff7784e) (cherry picked from commit e03b8f8da9cf4eef64cedf39ce9ca90d26ce5124) (cherry picked from commit fb360be406f35b9591f12c61936657f03cc5880f)
* | Merge tag 'android-4.4_r1' into cm-11.0Ricardo Cerqueira2013-11-0132-1098/+157
|\| | | | | | | Android 4.4 Release 1.0
| * Fix the protection of code cache for x86 JITJun Tian2013-08-092-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | During generation of code into code cache an unprotected region of memory does not correspond to protected one, The patch fixes that. Author: Katkov Serguei <serguei.i.katkov@intel.com> (cherry picked from commit 74a62214ef262380371bc21be2a1c42295046fb2) Change-Id: I362a10897564b987c8a3b2dfc9ded8f0a9efd56a
| * resolved conflicts for merge of ae77d6b6 to masterBrian Carlstrom2013-08-021-1/+1
| |\ | | | | | | | | | Change-Id: If7712cbddd6786c91648c4fc31f04e96937d4670
| | * Remove dependency on frameworks/nativeBrian Carlstrom2013-08-011-1/+1
| | | | | | | | | | | | Change-Id: I66e226f8390bd499e956b00e4088bc0e1e150cb1
| * | am 73a09433: Merge "Minor code cleanup to address warnings found by Clang."Ben Cheng2013-07-291-1/+1
| |\| | | | | | | | | | | | | * commit '73a0943392a2927dae96195f5293940877f11c05': Minor code cleanup to address warnings found by Clang.
| | * Minor code cleanup to address warnings found by Clang.Ben Cheng2013-07-291-1/+1
| | | | | | | | | | | | | | | | | | | | | cherry-picked from internal Android branch 55617c82a73d84ff3695bdd5526159448262d009 Change-Id: I0f78ca6b8293c13d7dbb535556543f6ea9f4dd45
| * | libenc: remove libutils dependencyAlex Ray2013-07-231-1/+1
| | | | | | | | | | | | Change-Id: I679fd6f06e007921251d15d7003615d7b0d91c52
| * | am bbd903de: am 28702c58: am ae2fb913: Merge "JIT: Use rsb and shift in easy ↵Elliott Hughes2013-06-175-4/+23
| |\| | | | | | | | | | | | | | | | | | | multiply." * commit 'bbd903dec7c25859849fa447aaeef365f20440d4': JIT: Use rsb and shift in easy multiply.
| | * JIT: Use rsb and shift in easy multiply.Anders O Nilsson2013-06-145-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For easy multiplication using reverse subtract (when lit is 2^n-1) use the barrel shifter for rsb. This improves arithmetic performance for code executing in Dalvik. E.g String.hashCode. Change-Id: Ifb086dcec344b30fd3e392ac21d508b43e820cdc Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
| * | am 15139109: am 6529809b: Merge "JIT: Allow use of cbz/cbnz for conditional ↵Elliott Hughes2013-06-131-4/+2
| |\| | | | | | | | | | | | | | | | | | | branch gen." * commit '151391097e94585d4dd062098438e5c894b98d6d': JIT: Allow use of cbz/cbnz for conditional branch gen.
| | * Merge "JIT: Allow use of cbz/cbnz for conditional branch gen."Elliott Hughes2013-06-131-4/+2
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| | | * JIT: Allow use of cbz/cbnz for conditional branch gen.Anders O Nilsson2013-04-181-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize conditional branch generation when comparing with zero for ARM JIT. When possible use cbz/cbnz instead of cmp+beq/cmp+bne. This improves performance for usecases involving code execution in Dalvik. Change-Id: I8f7c44c87eb73d4da00a48fd86220a62cb0515f5 Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
| * | | am de241376: am 91027c67: Merge "Remove unused compiler templates for armv7-a*"Elliott Hughes2013-06-0510-1004/+10
| |\| | | | | | | | | | | | | | | | | | * commit 'de2413762e3626039cadf270479f30dea6307fe8': Remove unused compiler templates for armv7-a*
| | * | Merge "Remove unused compiler templates for armv7-a*"Elliott Hughes2013-06-0510-1004/+10
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| | | * | Remove unused compiler templates for armv7-a*You Kim2013-05-1710-1004/+10
| | | |/ | | | | | | | | | | | | Change-Id: I68e344c2f2689347d6eeb943030b7263a55cd0bd
| * | | am b91f922c: am f3079bda: Merge "Rename unreasonable function name ↵Elliott Hughes2013-06-0510-20/+20
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | dmvCompilerTemplateEnd" * commit 'b91f922c80b454fa579deaee262bdd51225b82ee': Rename unreasonable function name dmvCompilerTemplateEnd
| | * | Rename unreasonable function name dmvCompilerTemplateEndYanchuan Nian2013-06-0510-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In dalvik, most function names start with "dvm" except dmvCompilerTemplateEnd. Convert it to dvmCompilerTemplateEnd in order to follow the rule. Change-Id: I09c41f8c9d55058013fbdb62ac5922ccd067ce39
| | * | Fix JIT bug related to immediate doublesbuzbee2013-04-261-1/+2
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change 256211 (JIT: Performance Fix for const doubles) introduced a defect that can cause the JIT to use the wrong floating point double constant in traces in which the following conditions hold: o Two (or more) different 64-bit floating point constants are used. o The physical register holding the first constant is still live at the time the second constant is used. o The low 32 bits of the two constants are identical. In this situation, the load/copy optimization pass will incorrectly determine that the two constants are the same, delete the load of the second constant and re-use the first constant value. Note: this problem only occurs with 64-bit floating point literals. 64-bit long literals are unaffected. This CL works around the problem, and a subsequent CL will rework disambiguation of 64-bit immediates in a somewhat cleaner fashion. (cherry-pick of c1757a6deab0ca0bfd42c38612d92b2f26c41dbe.) Change-Id: I795b4b753550d2745cbbdd83ae25f4a7088990f6
| | * Merge "Tiny optimization for complier templates for arm."Elliott Hughes2013-04-027-44/+44
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| | | * Tiny optimization for complier templates for arm.You Kim2013-04-037-44/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Remove possible bubble in TEMPLATE_STRING_INDEXOF.S 2. Remove 1 instruction and reorder the opcodes TEMPLATE_MUL_LONG.S 3. Reorder ldr r2 instruction in TEMPLATE_RETURN.S Change-Id: I571c1278aa72cb1e6dbc6efe433932d5e9591b80
| | * | Fix a minor leaks caused by failed initializations.(typo)You Kim2013-04-031-1/+3
| | |/ | | | | | | | | | Change-Id: I62bc3ea48938a4f54e9f47218d4025e954a6d566
| | * Merge "[x86] Fix errors with WITH_JIT_TUNING defined"Elliott Hughes2013-04-014-2/+37
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| | | * [x86] Fix errors with WITH_JIT_TUNING definedUdayan Banerji2013-03-294-2/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes the necessary changes to pass on correct information to dvmBumpNoChain, so that WITH_JIT_TUNING flag can be enabled for x86 codegen Change-Id: Ia5e5c0406433bf645ef67143d0f1a11a28153a66 Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
| | * | Merge "[x86] Terminate trace if SGET/SPUT have unresolved fields in codegen"Elliott Hughes2013-04-011-1/+11
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| | | * | [x86] Terminate trace if SGET/SPUT have unresolved fields in codegenUdayan Banerji2013-03-291-1/+11
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The interpreter doesn't allow SGET/SPUT bytecodes in a trace till the field is resolved. However, exhaustTrace can pick up bytecodes beyond the trace sent by the interpreter. Terminate the loop formation if this is seen. Change-Id: I0f38d6690b3501111bd16103623fa545d0ec1873 Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
| | * / [x86] FPU stack needs to be reset after double conversionUdayan Banerji2013-04-011-16/+34
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | The x86 codegen uses the FPU stack for double/float to long conversions. We need to clear out the FPU stack after done, to prevent an eventual stack overflow. Change-Id: I2f306d7c228ad3da2b84faf9f08326769a9417af Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
| | * [x86] Disable Method-JIT for x86 targetUdayan Banerji2013-03-291-0/+3
| | | | | | | | | | | | | | | | | | | | | Disable Method JIT when compiling for x86 target. Change-Id: Ide0dbd1f602ffd955b901cc152de1e05771fd529 Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
| * | JIT tuning; set cache size on command linebuzbee2013-05-238-7/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tuning knobs for triggering trace compilation for the JIT had not been revisited for several years. In that time, the working set of some applications have significantly increased, leading to frequent cache overlows & flushes. This CL adds the ability to set the maximum size of the JIT's cache on the command line, and we expect to use different settings depending on device configuration (rule of thumb: 1K for each 1M for system RAM, with 2M limit). Additionally, the trace compilation trigger has been tightened to limit the compilation of cold traces. Change-Id: Ice22c5d9d46a93e465c57dd83f50ca3912f1672e
| * | Revert "Revert "Tiny optimization for complier templates for arm.""Elliott Hughes2013-05-037-44/+44
| | | | | | | | | | | | This reverts commit 4afb260cf1f312382541e30cab5766bff890e6fe.
* | | Revert "Move verification of class access flags to libdex"Ricardo Cerqueira2013-11-016-317/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit aa897b06230453519c4ec636f229c72ac0015897. Revert "Reject dex files that attempt to use unspecified class access flags" This reverts commit 2f824d3e4835479409724ea02d0a23114cd4ff81. Revert "If dalvik wants ASCII casing, it needs to ask for it." This reverts commit d91250308fc4c423d11955174c21566fa19df07c. Revert "JIT: Combine add with shift and offset for array load & store." This reverts commit a9ecd84e5f5423a1ba6bbb2bb9256b0dc382de44. Revert "JIT: Use rsb and shift in easy multiply." This reverts commit 25b94295a57290623e34882e7fd86ea10928a54e. Revert "Excessive JNI: Dump HPROF dump." This reverts commit 8d30a7402d48c4ffe2bf28ede78c6b3b52b15304. Revert "dalvik/vm: Dalvik startup with a low memory footprint" This reverts commit 15726c81059b74bf2352db29a3decfc4ea9c1428.
* | | JIT: Combine add with shift and offset for array load & store.Anders O Nilsson2013-07-244-143/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize long and double array load / store for ARM JIT. Array load / store performs a logical shift left and add, replace it with add capable of performing shift in the same instruction. Array load / store performs an add instead of using offset for vldr/vstr. Replace the add and vldr/vstr with a vldr/vstr that is capable of handling offset. This improves performance for usecases involving long and double array code execution in Dalvik. E.g WindowOrientation. Change-Id: I90220c349ab936cdba1987139ccdf4dc31d7bbb0 Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
* | | JIT: Combine add with shift.Anders O Nilsson2013-07-242-0/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize logical shift for ARM JIT. Whenever logical shift is followed by an add, try to replace it with an add capable of performing the shift in the same instruction. This improves performance for usecases involving code executing in Dalvik. Change-Id: I3cb807b6d6ef4b053a19e2703676a93a930eb963 Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
* | | JIT: Hoist loop load operations above loop.Henrik Smiding2013-07-243-1/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hoists Dalvik frame load operations outside of loops, when possible. This improves performance in most loops, and is noticable in many applications. Change-Id: Ibe42b509b50a13f19758fd923f31d703e33a51c6 Signed-off-by: Henrik Smiding <henrik.smiding@stericsson.com> Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
* | | JIT: Use rsb and shift in easy multiply.Anders O Nilsson2013-07-245-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For easy multiplication using reverse subtract (when lit is 2^n-1) use the barrel shifter for rsb. This improves arithmetic performance for code executing in Dalvik. E.g String.hashCode. Change-Id: Ifb086dcec344b30fd3e392ac21d508b43e820cdc Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
* | | JIT: Combine shift & sub for monitor unlock.Anders O Nilsson2013-07-241-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize monitor unlock for ARM Thumb2 JIT. Monitor unlock performs a logical shift left and sub, replace it with a sub capable of performing the shift in the same instruction. This improves performance for usecases involving code executing in Dalvik. Change-Id: Iaf062d750c3bc941926f3c3b8a64dc9c7984a477 Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
* | | JIT: Allow use of cbz/cbnz for conditional branch gen.Anders O Nilsson2013-07-241-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize conditional branch generation when comparing with zero for ARM JIT. When possible use cbz/cbnz instead of cmp+beq/cmp+bne. This improves performance for usecases involving code execution in Dalvik. Change-Id: Iffd455d9cbb3ef0b1f87caafdae1b72ba3f0d2fc Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
* | | dalvik: update ARMv6 code to bring in line with ARMv5Lalit Maganti2013-07-249-113/+115
| | | | | | | | | | | | Change-Id: I9c60645a4d3fff3567b4b88acd4a6be98a774927
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