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authorJoy Huang <joy_huang@asus.com>2012-06-05 20:18:23 +0800
committerRamanan Rajeswaran <ramanan@google.com>2012-06-08 09:19:48 -0700
commitae52325834f74c9d366a4295341bfd1a786eaf9b (patch)
tree3acc70686ab152eea8e880ac304eae4e1c1f1785 /nfc
parent7d20b82aaa8b95c1f52edff05f44d8f28b6458cf (diff)
Add the RF setting and enable the hybrid polling mode.
Change-Id: I6e78c1083e0f71343f5071e9623e480a4c158aec
Diffstat (limited to 'nfc')
-rw-r--r--nfc/nfc_hw.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/nfc/nfc_hw.c b/nfc/nfc_hw.c
index 2c774c3..b137b68 100644
--- a/nfc/nfc_hw.c
+++ b/nfc/nfc_hw.c
@@ -33,7 +33,11 @@ static uint8_t pn544_eedata_settings[][4] = {
,{0x00,0x9B,0xDD,0x1C} // GSP setting for this threshold
,{0x00,0x9B,0x84,0x13} // ANACM2 setting
,{0x00,0x99,0x81,0x7F} // ANAVMID setting PCD
+ ,{0x00,0x99,0x7A,0x04} // ANATXMODGSPON
+ ,{0x00,0x99,0x77,0x40} // ANATXCWGSPON
,{0x00,0x99,0x31,0x70} // ANAVMID setting PICC
+ ,{0x00,0x99,0x2A,0xF5} // ANATXMODGSN-TYPEB
+ ,{0x00,0x99,0x29,0xF5} // ANATXMODGSN-TYPEA
// For tegra we don't override load modulation settings.
// Enable PBTF
@@ -46,7 +50,7 @@ static uint8_t pn544_eedata_settings[][4] = {
,{0x00,0x99,0x23,0x00} // Default Value is 0x01
// Low-power polling
- ,{0x00,0x9E,0x74,0x00} // Default Value is 0x00, bits 0->2: sensitivity (0==max, 6==min),
+ ,{0x00,0x9E,0x74,0xB0} // Default Value is 0x00, bits 0->2: sensitivity (0==max, 6==min),
// bit 3: RFU,
// bits 4,5 hybrid low-power: # of low-power polls per regular poll
// bit 6: RFU