diff options
| author | Michael Bestas <mkbestas@lineageos.org> | 2025-09-14 17:11:03 +0300 |
|---|---|---|
| committer | Siluxsept <ronny.horn.rh@gmail.com> | 2025-09-22 16:42:58 +0200 |
| commit | e51eea6bc93e82ea59eadf6bed086a6f0e42c46c (patch) | |
| tree | 55b6b3fdcf08006fe028b0a906392528dc8fe901 | |
| parent | 18e605558bd7223f8144752cc804b851c5d4b763 (diff) | |
b4s4: Drop unused in-tree kernel headers
Change-Id: If871800764cdb47a4423c615c57267dea964bbe8
188 files changed, 0 insertions, 58945 deletions
@@ -674,8 +674,6 @@ PRODUCT_COPY_FILES += \ device/google/bonito/vibrator/cs40l20/cs40l20.wmfw:$(TARGET_COPY_OUT_VENDOR)/firmware/cs40l20.wmfw \ device/google/bonito/vibrator/cs40l20/cs40l20.bin:$(TARGET_COPY_OUT_VENDOR)/firmware/cs40l20.bin -PRODUCT_VENDOR_KERNEL_HEADERS := device/google/bonito/sdm710/kernel-headers - # Audio ACDB data PRODUCT_COPY_FILES += \ device/google/bonito/acdbdata/OEM/sdm670-intcodec-b4-snd-card/Bluetooth_cal.acdb:$(TARGET_COPY_OUT_VENDOR)/etc/acdbdata/OEM/sdm670-intcodec-b4-snd-card/Bluetooth_cal.acdb \ diff --git a/sdm710/kernel-headers/asm-generic/ioctls.h b/sdm710/kernel-headers/asm-generic/ioctls.h deleted file mode 100644 index 9cdc364d..00000000 --- a/sdm710/kernel-headers/asm-generic/ioctls.h +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __ASM_GENERIC_IOCTLS_H -#define __ASM_GENERIC_IOCTLS_H -#include <linux/ioctl.h> -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 -#define TIOCSBRK 0x5427 -#define TIOCCBRK 0x5428 -#define TIOCGSID 0x5429 -#define TCGETS2 _IOR('T', 0x2A, struct termios2) -#define TCSETS2 _IOW('T', 0x2B, struct termios2) -#define TCSETSW2 _IOW('T', 0x2C, struct termios2) -#define TCSETSF2 _IOW('T', 0x2D, struct termios2) -#define TIOCGRS485 0x542E -#ifndef TIOCSRS485 -#define TIOCSRS485 0x542F -#endif -#define TIOCGPTN _IOR('T', 0x30, unsigned int) -#define TIOCSPTLCK _IOW('T', 0x31, int) -#define TIOCGDEV _IOR('T', 0x32, unsigned int) -#define TCGETX 0x5432 -#define TCSETX 0x5433 -#define TCSETXF 0x5434 -#define TCSETXW 0x5435 -#define TIOCSIG _IOW('T', 0x36, int) -#define TIOCVHANGUP 0x5437 -#define TIOCGPKT _IOR('T', 0x38, int) -#define TIOCGPTLCK _IOR('T', 0x39, int) -#define TIOCGEXCL _IOR('T', 0x40, int) -#define TIOCPMGET 0x5441 -#define TIOCPMPUT 0x5442 -#define TIOCPMACT 0x5443 -#define FIONCLEX 0x5450 -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 -#define TIOCSERGETLSR 0x5459 -#define TIOCSERGETMULTI 0x545A -#define TIOCSERSETMULTI 0x545B -#define TIOCMIWAIT 0x545C -#define TIOCGICOUNT 0x545D -#ifndef FIOQSIZE -#define FIOQSIZE 0x5460 -#endif -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 -#define TIOCSER_TEMT 0x01 -#endif - diff --git a/sdm710/kernel-headers/drm/msm_drm.h b/sdm710/kernel-headers/drm/msm_drm.h deleted file mode 100644 index 820a65dc..00000000 --- a/sdm710/kernel-headers/drm/msm_drm.h +++ /dev/null @@ -1,217 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __MSM_DRM_H__ -#define __MSM_DRM_H__ -#include "drm.h" -#include "sde_drm.h" -#ifdef __cplusplus -#endif -#define MSM_PIPE_NONE 0x00 -#define MSM_PIPE_2D0 0x01 -#define MSM_PIPE_2D1 0x02 -#define MSM_PIPE_3D0 0x10 -#define MSM_PIPE_ID_MASK 0xffff -#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) -#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) -struct drm_msm_timespec { - __s64 tv_sec; - __s64 tv_nsec; -}; -#define HDR_PRIMARIES_COUNT 3 -#define HDR_EOTF_SDR_LUM_RANGE 0x0 -#define HDR_EOTF_HDR_LUM_RANGE 0x1 -#define HDR_EOTF_SMTPE_ST2084 0x2 -#define HDR_EOTF_HLG 0x3 -#define DRM_MSM_EXT_HDR_METADATA -struct drm_msm_ext_hdr_metadata { - __u32 hdr_state; - __u32 eotf; - __u32 hdr_supported; - __u32 display_primaries_x[HDR_PRIMARIES_COUNT]; - __u32 display_primaries_y[HDR_PRIMARIES_COUNT]; - __u32 white_point_x; - __u32 white_point_y; - __u32 max_luminance; - __u32 min_luminance; - __u32 max_content_light_level; - __u32 max_average_light_level; -}; -#define DRM_MSM_EXT_HDR_PROPERTIES -struct drm_msm_ext_hdr_properties { - __u8 hdr_metadata_type_one; - __u32 hdr_supported; - __u32 hdr_eotf; - __u32 hdr_max_luminance; - __u32 hdr_avg_luminance; - __u32 hdr_min_luminance; -}; -#define MSM_PARAM_GPU_ID 0x01 -#define MSM_PARAM_GMEM_SIZE 0x02 -#define MSM_PARAM_CHIP_ID 0x03 -#define MSM_PARAM_MAX_FREQ 0x04 -#define MSM_PARAM_TIMESTAMP 0x05 -struct drm_msm_param { - __u32 pipe; - __u32 param; - __u64 value; -}; -#define MSM_BO_SCANOUT 0x00000001 -#define MSM_BO_GPU_READONLY 0x00000002 -#define MSM_BO_CACHE_MASK 0x000f0000 -#define MSM_BO_CACHED 0x00010000 -#define MSM_BO_WC 0x00020000 -#define MSM_BO_UNCACHED 0x00040000 -#define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED) -struct drm_msm_gem_new { - __u64 size; - __u32 flags; - __u32 handle; -}; -struct drm_msm_gem_info { - __u32 handle; - __u32 pad; - __u64 offset; -}; -#define MSM_PREP_READ 0x01 -#define MSM_PREP_WRITE 0x02 -#define MSM_PREP_NOSYNC 0x04 -#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) -struct drm_msm_gem_cpu_prep { - __u32 handle; - __u32 op; - struct drm_msm_timespec timeout; -}; -struct drm_msm_gem_cpu_fini { - __u32 handle; -}; -struct drm_msm_gem_submit_reloc { - __u32 submit_offset; - __u32 or; - __s32 shift; - __u32 reloc_idx; - __u64 reloc_offset; -}; -#define MSM_SUBMIT_CMD_BUF 0x0001 -#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 -#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 -struct drm_msm_gem_submit_cmd { - __u32 type; - __u32 submit_idx; - __u32 submit_offset; - __u32 size; - __u32 pad; - __u32 nr_relocs; - __u64 relocs; -}; -#define MSM_SUBMIT_BO_READ 0x0001 -#define MSM_SUBMIT_BO_WRITE 0x0002 -#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) -struct drm_msm_gem_submit_bo { - __u32 flags; - __u32 handle; - __u64 presumed; -}; -#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 -#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 -#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 -#define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | 0) -struct drm_msm_gem_submit { - __u32 flags; - __u32 fence; - __u32 nr_bos; - __u32 nr_cmds; - __u64 bos; - __u64 cmds; - __s32 fence_fd; -}; -struct drm_msm_wait_fence { - __u32 fence; - __u32 pad; - struct drm_msm_timespec timeout; -}; -#define MSM_MADV_WILLNEED 0 -#define MSM_MADV_DONTNEED 1 -#define __MSM_MADV_PURGED 2 -struct drm_msm_gem_madvise { - __u32 handle; - __u32 madv; - __u32 retained; -}; -#define DISPLAY_PRIMARIES_WX 0 -#define DISPLAY_PRIMARIES_WY 1 -#define DISPLAY_PRIMARIES_RX 2 -#define DISPLAY_PRIMARIES_RY 3 -#define DISPLAY_PRIMARIES_GX 4 -#define DISPLAY_PRIMARIES_GY 5 -#define DISPLAY_PRIMARIES_BX 6 -#define DISPLAY_PRIMARIES_BY 7 -#define DISPLAY_PRIMARIES_MAX 8 -struct drm_panel_hdr_properties { - __u32 hdr_enabled; - __u32 display_primaries[DISPLAY_PRIMARIES_MAX]; - __u32 peak_brightness; - __u32 blackness_level; -}; -struct drm_msm_event_req { - __u32 object_id; - __u32 object_type; - __u32 event; - __u64 client_context; - __u32 index; -}; -struct drm_msm_event_resp { - struct drm_event base; - struct drm_msm_event_req info; - __u8 data[]; -}; -#define DRM_MSM_GET_PARAM 0x00 -#define DRM_MSM_GEM_NEW 0x02 -#define DRM_MSM_GEM_INFO 0x03 -#define DRM_MSM_GEM_CPU_PREP 0x04 -#define DRM_MSM_GEM_CPU_FINI 0x05 -#define DRM_MSM_GEM_SUBMIT 0x06 -#define DRM_MSM_WAIT_FENCE 0x07 -#define DRM_MSM_GEM_MADVISE 0x08 -#define DRM_SDE_WB_CONFIG 0x40 -#define DRM_MSM_REGISTER_EVENT 0x41 -#define DRM_MSM_DEREGISTER_EVENT 0x42 -#define DRM_MSM_RMFB2 0x43 -#define DRM_EVENT_HISTOGRAM 0x80000000 -#define DRM_EVENT_AD_BACKLIGHT 0x80000001 -#define DRM_EVENT_CRTC_POWER 0x80000002 -#define DRM_EVENT_SYS_BACKLIGHT 0x80000003 -#define DRM_EVENT_SDE_POWER 0x80000004 -#define DRM_EVENT_IDLE_NOTIFY 0x80000005 -#define DRM_EVENT_PANEL_DEAD 0x80000006 -#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) -#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) -#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) -#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) -#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) -#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) -#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) -#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) -#define DRM_IOCTL_SDE_WB_CONFIG DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg) -#define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req) -#define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req) -#define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_RMFB2), unsigned int) -#ifdef __cplusplus -#endif -#endif - diff --git a/sdm710/kernel-headers/drm/msm_drm_pp.h b/sdm710/kernel-headers/drm/msm_drm_pp.h deleted file mode 100644 index e12ed709..00000000 --- a/sdm710/kernel-headers/drm/msm_drm_pp.h +++ /dev/null @@ -1,297 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _MSM_DRM_PP_H_ -#define _MSM_DRM_PP_H_ -#include <linux/types.h> -struct drm_msm_pcc_coeff { - __u32 c; - __u32 r; - __u32 g; - __u32 b; - __u32 rg; - __u32 gb; - __u32 rb; - __u32 rgb; -}; -#define DRM_MSM_PCC3 -struct drm_msm_pcc { - __u64 flags; - struct drm_msm_pcc_coeff r; - struct drm_msm_pcc_coeff g; - struct drm_msm_pcc_coeff b; - __u32 r_rr; - __u32 r_gg; - __u32 r_bb; - __u32 g_rr; - __u32 g_gg; - __u32 g_bb; - __u32 b_rr; - __u32 b_gg; - __u32 b_bb; -}; -#define PA_VLUT_SIZE 256 -struct drm_msm_pa_vlut { - __u64 flags; - __u32 val[PA_VLUT_SIZE]; -}; -#define PA_HSIC_HUE_ENABLE (1 << 0) -#define PA_HSIC_SAT_ENABLE (1 << 1) -#define PA_HSIC_VAL_ENABLE (1 << 2) -#define PA_HSIC_CONT_ENABLE (1 << 3) -#define DRM_MSM_PA_HSIC -struct drm_msm_pa_hsic { - __u64 flags; - __u32 hue; - __u32 saturation; - __u32 value; - __u32 contrast; -}; -#define MEMCOL_PROT_HUE (1 << 0) -#define MEMCOL_PROT_SAT (1 << 1) -#define MEMCOL_PROT_VAL (1 << 2) -#define MEMCOL_PROT_CONT (1 << 3) -#define MEMCOL_PROT_SIXZONE (1 << 4) -#define MEMCOL_PROT_BLEND (1 << 5) -#define DRM_MSM_MEMCOL -struct drm_msm_memcol { - __u64 prot_flags; - __u32 color_adjust_p0; - __u32 color_adjust_p1; - __u32 color_adjust_p2; - __u32 blend_gain; - __u32 sat_hold; - __u32 val_hold; - __u32 hue_region; - __u32 sat_region; - __u32 val_region; -}; -#define DRM_MSM_SIXZONE -#define SIXZONE_LUT_SIZE 384 -#define SIXZONE_HUE_ENABLE (1 << 0) -#define SIXZONE_SAT_ENABLE (1 << 1) -#define SIXZONE_VAL_ENABLE (1 << 2) -struct drm_msm_sixzone_curve { - __u32 p1; - __u32 p0; -}; -struct drm_msm_sixzone { - __u64 flags; - __u32 threshold; - __u32 adjust_p0; - __u32 adjust_p1; - __u32 sat_hold; - __u32 val_hold; - struct drm_msm_sixzone_curve curve[SIXZONE_LUT_SIZE]; -}; -#define GAMUT_3D_MODE_17 1 -#define GAMUT_3D_MODE_5 2 -#define GAMUT_3D_MODE_13 3 -#define GAMUT_3D_MODE17_TBL_SZ 1229 -#define GAMUT_3D_MODE5_TBL_SZ 32 -#define GAMUT_3D_MODE13_TBL_SZ 550 -#define GAMUT_3D_SCALE_OFF_SZ 16 -#define GAMUT_3D_SCALEB_OFF_SZ 12 -#define GAMUT_3D_TBL_NUM 4 -#define GAMUT_3D_SCALE_OFF_TBL_NUM 3 -#define GAMUT_3D_MAP_EN (1 << 0) -struct drm_msm_3d_col { - __u32 c2_c1; - __u32 c0; -}; -struct drm_msm_3d_gamut { - __u64 flags; - __u32 mode; - __u32 scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ]; - struct drm_msm_3d_col col[GAMUT_3D_TBL_NUM][GAMUT_3D_MODE17_TBL_SZ]; -}; -#define PGC_TBL_LEN 512 -#define PGC_8B_ROUND (1 << 0) -struct drm_msm_pgc_lut { - __u64 flags; - __u32 c0[PGC_TBL_LEN]; - __u32 c1[PGC_TBL_LEN]; - __u32 c2[PGC_TBL_LEN]; -}; -#define IGC_TBL_LEN 256 -#define IGC_DITHER_ENABLE (1 << 0) -struct drm_msm_igc_lut { - __u64 flags; - __u32 c0[IGC_TBL_LEN]; - __u32 c1[IGC_TBL_LEN]; - __u32 c2[IGC_TBL_LEN]; - __u32 strength; -}; -#define HIST_V_SIZE 256 -struct drm_msm_hist { - __u64 flags; - __u32 data[HIST_V_SIZE]; -}; -#define AD4_LUT_GRP0_SIZE 33 -#define AD4_LUT_GRP1_SIZE 32 -struct drm_msm_ad4_init { - __u32 init_param_001[AD4_LUT_GRP0_SIZE]; - __u32 init_param_002[AD4_LUT_GRP0_SIZE]; - __u32 init_param_003[AD4_LUT_GRP0_SIZE]; - __u32 init_param_004[AD4_LUT_GRP0_SIZE]; - __u32 init_param_005[AD4_LUT_GRP1_SIZE]; - __u32 init_param_006[AD4_LUT_GRP1_SIZE]; - __u32 init_param_007[AD4_LUT_GRP0_SIZE]; - __u32 init_param_008[AD4_LUT_GRP0_SIZE]; - __u32 init_param_009; - __u32 init_param_010; - __u32 init_param_011; - __u32 init_param_012; - __u32 init_param_013; - __u32 init_param_014; - __u32 init_param_015; - __u32 init_param_016; - __u32 init_param_017; - __u32 init_param_018; - __u32 init_param_019; - __u32 init_param_020; - __u32 init_param_021; - __u32 init_param_022; - __u32 init_param_023; - __u32 init_param_024; - __u32 init_param_025; - __u32 init_param_026; - __u32 init_param_027; - __u32 init_param_028; - __u32 init_param_029; - __u32 init_param_030; - __u32 init_param_031; - __u32 init_param_032; - __u32 init_param_033; - __u32 init_param_034; - __u32 init_param_035; - __u32 init_param_036; - __u32 init_param_037; - __u32 init_param_038; - __u32 init_param_039; - __u32 init_param_040; - __u32 init_param_041; - __u32 init_param_042; - __u32 init_param_043; - __u32 init_param_044; - __u32 init_param_045; - __u32 init_param_046; - __u32 init_param_047; - __u32 init_param_048; - __u32 init_param_049; - __u32 init_param_050; - __u32 init_param_051; - __u32 init_param_052; - __u32 init_param_053; - __u32 init_param_054; - __u32 init_param_055; - __u32 init_param_056; - __u32 init_param_057; - __u32 init_param_058; - __u32 init_param_059; - __u32 init_param_060; - __u32 init_param_061; - __u32 init_param_062; - __u32 init_param_063; - __u32 init_param_064; - __u32 init_param_065; - __u32 init_param_066; - __u32 init_param_067; - __u32 init_param_068; - __u32 init_param_069; - __u32 init_param_070; - __u32 init_param_071; - __u32 init_param_072; - __u32 init_param_073; - __u32 init_param_074; - __u32 init_param_075; -}; -struct drm_msm_ad4_cfg { - __u32 cfg_param_001; - __u32 cfg_param_002; - __u32 cfg_param_003; - __u32 cfg_param_004; - __u32 cfg_param_005; - __u32 cfg_param_006; - __u32 cfg_param_007; - __u32 cfg_param_008; - __u32 cfg_param_009; - __u32 cfg_param_010; - __u32 cfg_param_011; - __u32 cfg_param_012; - __u32 cfg_param_013; - __u32 cfg_param_014; - __u32 cfg_param_015; - __u32 cfg_param_016; - __u32 cfg_param_017; - __u32 cfg_param_018; - __u32 cfg_param_019; - __u32 cfg_param_020; - __u32 cfg_param_021; - __u32 cfg_param_022; - __u32 cfg_param_023; - __u32 cfg_param_024; - __u32 cfg_param_025; - __u32 cfg_param_026; - __u32 cfg_param_027; - __u32 cfg_param_028; - __u32 cfg_param_029; - __u32 cfg_param_030; - __u32 cfg_param_031; - __u32 cfg_param_032; - __u32 cfg_param_033; - __u32 cfg_param_034; - __u32 cfg_param_035; - __u32 cfg_param_036; - __u32 cfg_param_037; - __u32 cfg_param_038; - __u32 cfg_param_039; - __u32 cfg_param_040; - __u32 cfg_param_041; - __u32 cfg_param_042; - __u32 cfg_param_043; - __u32 cfg_param_044; - __u32 cfg_param_045; - __u32 cfg_param_046; - __u32 cfg_param_047; - __u32 cfg_param_048; - __u32 cfg_param_049; - __u32 cfg_param_050; - __u32 cfg_param_051; - __u32 cfg_param_052; - __u32 cfg_param_053; -}; -#define DITHER_MATRIX_SZ 16 -struct drm_msm_dither { - __u64 flags; - __u32 temporal_en; - __u32 c0_bitdepth; - __u32 c1_bitdepth; - __u32 c2_bitdepth; - __u32 c3_bitdepth; - __u32 matrix[DITHER_MATRIX_SZ]; -}; -#define DRM_MSM_PA_DITHER -struct drm_msm_pa_dither { - __u64 flags; - __u32 strength; - __u32 offset_en; - __u32 matrix[DITHER_MATRIX_SZ]; -}; -#endif - diff --git a/sdm710/kernel-headers/drm/sde_drm.h b/sdm710/kernel-headers/drm/sde_drm.h deleted file mode 100644 index ea75b860..00000000 --- a/sdm710/kernel-headers/drm/sde_drm.h +++ /dev/null @@ -1,181 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _SDE_DRM_H_ -#define _SDE_DRM_H_ -#include "drm.h" -#define SDE_MAX_PLANES 4 -#define SDE_MAX_DE_CURVES 3 -#define FILTER_EDGE_DIRECTED_2D 0x0 -#define FILTER_CIRCULAR_2D 0x1 -#define FILTER_SEPARABLE_1D 0x2 -#define FILTER_BILINEAR 0x3 -#define FILTER_ALPHA_DROP_REPEAT 0x0 -#define FILTER_ALPHA_BILINEAR 0x1 -#define FILTER_ALPHA_2D 0x3 -#define FILTER_BLEND_CIRCULAR_2D 0x0 -#define FILTER_BLEND_SEPARABLE_1D 0x1 -#define SCALER_LUT_SWAP 0x1 -#define SCALER_LUT_DIR_WR 0x2 -#define SCALER_LUT_Y_CIR_WR 0x4 -#define SCALER_LUT_UV_CIR_WR 0x8 -#define SCALER_LUT_Y_SEP_WR 0x10 -#define SCALER_LUT_UV_SEP_WR 0x20 -#define SDE_DRM_BLEND_OP_NOT_DEFINED 0 -#define SDE_DRM_BLEND_OP_OPAQUE 1 -#define SDE_DRM_BLEND_OP_PREMULTIPLIED 2 -#define SDE_DRM_BLEND_OP_COVERAGE 3 -#define SDE_DRM_BLEND_OP_MAX 4 -#define SDE_DRM_DEINTERLACE 0 -#define SDE_DRM_BITMASK_COUNT 64 -#define SDE_DRM_FB_NON_SEC 0 -#define SDE_DRM_FB_SEC 1 -#define SDE_DRM_FB_NON_SEC_DIR_TRANS 2 -#define SDE_DRM_FB_SEC_DIR_TRANS 3 -#define SDE_DRM_SEC_NON_SEC 0 -#define SDE_DRM_SEC_ONLY 1 -struct sde_drm_pix_ext_v1 { - int32_t num_ext_pxls_lr[SDE_MAX_PLANES]; - int32_t num_ext_pxls_tb[SDE_MAX_PLANES]; - int32_t left_ftch[SDE_MAX_PLANES]; - int32_t right_ftch[SDE_MAX_PLANES]; - int32_t top_ftch[SDE_MAX_PLANES]; - int32_t btm_ftch[SDE_MAX_PLANES]; - int32_t left_rpt[SDE_MAX_PLANES]; - int32_t right_rpt[SDE_MAX_PLANES]; - int32_t top_rpt[SDE_MAX_PLANES]; - int32_t btm_rpt[SDE_MAX_PLANES]; -}; -struct sde_drm_scaler_v1 { - struct sde_drm_pix_ext_v1 pe; - int32_t init_phase_x[SDE_MAX_PLANES]; - int32_t phase_step_x[SDE_MAX_PLANES]; - int32_t init_phase_y[SDE_MAX_PLANES]; - int32_t phase_step_y[SDE_MAX_PLANES]; - uint32_t horz_filter[SDE_MAX_PLANES]; - uint32_t vert_filter[SDE_MAX_PLANES]; -}; -struct sde_drm_de_v1 { - uint32_t enable; - int16_t sharpen_level1; - int16_t sharpen_level2; - uint16_t clip; - uint16_t limit; - uint16_t thr_quiet; - uint16_t thr_dieout; - uint16_t thr_low; - uint16_t thr_high; - uint16_t prec_shift; - int16_t adjust_a[SDE_MAX_DE_CURVES]; - int16_t adjust_b[SDE_MAX_DE_CURVES]; - int16_t adjust_c[SDE_MAX_DE_CURVES]; -}; -struct sde_drm_scaler_v2 { - uint32_t enable; - uint32_t dir_en; - struct sde_drm_pix_ext_v1 pe; - uint32_t horz_decimate; - uint32_t vert_decimate; - int32_t init_phase_x[SDE_MAX_PLANES]; - int32_t phase_step_x[SDE_MAX_PLANES]; - int32_t init_phase_y[SDE_MAX_PLANES]; - int32_t phase_step_y[SDE_MAX_PLANES]; - uint32_t preload_x[SDE_MAX_PLANES]; - uint32_t preload_y[SDE_MAX_PLANES]; - uint32_t src_width[SDE_MAX_PLANES]; - uint32_t src_height[SDE_MAX_PLANES]; - uint32_t dst_width; - uint32_t dst_height; - uint32_t y_rgb_filter_cfg; - uint32_t uv_filter_cfg; - uint32_t alpha_filter_cfg; - uint32_t blend_cfg; - uint32_t lut_flag; - uint32_t dir_lut_idx; - uint32_t y_rgb_cir_lut_idx; - uint32_t uv_cir_lut_idx; - uint32_t y_rgb_sep_lut_idx; - uint32_t uv_sep_lut_idx; - struct sde_drm_de_v1 de; -}; -#define SDE_MAX_DS_COUNT 2 -#define SDE_DRM_DESTSCALER_ENABLE 0x1 -#define SDE_DRM_DESTSCALER_SCALE_UPDATE 0x2 -#define SDE_DRM_DESTSCALER_ENHANCER_UPDATE 0x4 -#define SDE_DRM_DESTSCALER_PU_ENABLE 0x8 -struct sde_drm_dest_scaler_cfg { - uint32_t flags; - uint32_t index; - uint32_t lm_width; - uint32_t lm_height; - uint64_t scaler_cfg; -}; -struct sde_drm_dest_scaler_data { - uint32_t num_dest_scaler; - struct sde_drm_dest_scaler_cfg ds_cfg[SDE_MAX_DS_COUNT]; -}; -#define SDE_CSC_MATRIX_COEFF_SIZE 9 -#define SDE_CSC_CLAMP_SIZE 6 -#define SDE_CSC_BIAS_SIZE 3 -struct sde_drm_csc_v1 { - int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE]; - uint32_t pre_bias[SDE_CSC_BIAS_SIZE]; - uint32_t post_bias[SDE_CSC_BIAS_SIZE]; - uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE]; - uint32_t post_clamp[SDE_CSC_CLAMP_SIZE]; -}; -struct sde_drm_color { - uint32_t color_0; - uint32_t color_1; - uint32_t color_2; - uint32_t color_3; -}; -#define SDE_MAX_DIM_LAYERS 7 -#define SDE_DRM_DIM_LAYER_INCLUSIVE 0x1 -#define SDE_DRM_DIM_LAYER_EXCLUSIVE 0x2 -struct sde_drm_dim_layer_cfg { - uint32_t flags; - uint32_t stage; - struct sde_drm_color color_fill; - struct drm_clip_rect rect; -}; -struct sde_drm_dim_layer_v1 { - uint32_t num_layers; - struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS]; -}; -#define SDE_DRM_WB_CFG 0x1 -#define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1 << 0) -struct sde_drm_wb_cfg { - uint32_t flags; - uint32_t connector_id; - uint32_t count_modes; - uint64_t modes; -}; -#define SDE_MAX_ROI_V1 4 -struct sde_drm_roi_v1 { - uint32_t num_rects; - struct drm_clip_rect roi[SDE_MAX_ROI_V1]; -}; -#define SDE_MODE_DPMS_ON 0 -#define SDE_MODE_DPMS_LP1 1 -#define SDE_MODE_DPMS_LP2 2 -#define SDE_MODE_DPMS_STANDBY 3 -#define SDE_MODE_DPMS_SUSPEND 4 -#define SDE_MODE_DPMS_OFF 5 -#endif - diff --git a/sdm710/kernel-headers/linux/avtimer.h b/sdm710/kernel-headers/linux/avtimer.h deleted file mode 100644 index cbcd8247..00000000 --- a/sdm710/kernel-headers/linux/avtimer.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _AVTIMER_H -#define _AVTIMER_H - -#include <linux/ioctl.h> - -#define MAJOR_NUM 100 - -#define IOCTL_GET_AVTIMER_TICK _IOR(MAJOR_NUM, 0, uint64_t) - -#endif diff --git a/sdm710/kernel-headers/linux/ion.h b/sdm710/kernel-headers/linux/ion.h deleted file mode 100644 index 36c46561..00000000 --- a/sdm710/kernel-headers/linux/ion.h +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _LINUX_ION_H -#define _LINUX_ION_H -#include <linux/ioctl.h> -#include <linux/types.h> -typedef int ion_user_handle_t; -enum ion_heap_type { - ION_HEAP_TYPE_SYSTEM, - ION_HEAP_TYPE_SYSTEM_CONTIG, - ION_HEAP_TYPE_CARVEOUT, - ION_HEAP_TYPE_CHUNK, - ION_HEAP_TYPE_DMA, - ION_HEAP_TYPE_CUSTOM, - ION_NUM_HEAPS = 16, -}; -#define ION_HEAP_SYSTEM_MASK ((1 << ION_HEAP_TYPE_SYSTEM)) -#define ION_HEAP_SYSTEM_CONTIG_MASK ((1 << ION_HEAP_TYPE_SYSTEM_CONTIG)) -#define ION_HEAP_CARVEOUT_MASK ((1 << ION_HEAP_TYPE_CARVEOUT)) -#define ION_HEAP_TYPE_DMA_MASK ((1 << ION_HEAP_TYPE_DMA)) -#define ION_NUM_HEAP_IDS (sizeof(unsigned int) * 8) -#define ION_FLAG_CACHED 1 -#define ION_FLAG_CACHED_NEEDS_SYNC 2 -struct ion_allocation_data { - size_t len; - size_t align; - unsigned int heap_id_mask; - unsigned int flags; - ion_user_handle_t handle; -}; -struct ion_fd_data { - ion_user_handle_t handle; - int fd; -}; -struct ion_handle_data { - ion_user_handle_t handle; -}; -struct ion_custom_data { - unsigned int cmd; - unsigned long arg; -}; -#define ION_IOC_MAGIC 'I' -#define ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, struct ion_allocation_data) -#define ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data) -#define ION_IOC_MAP _IOWR(ION_IOC_MAGIC, 2, struct ion_fd_data) -#define ION_IOC_SHARE _IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data) -#define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data) -#define ION_IOC_SYNC _IOWR(ION_IOC_MAGIC, 7, struct ion_fd_data) -#define ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data) -#endif - diff --git a/sdm710/kernel-headers/linux/ipa_qmi_service_v01.h b/sdm710/kernel-headers/linux/ipa_qmi_service_v01.h deleted file mode 100644 index c2592317..00000000 --- a/sdm710/kernel-headers/linux/ipa_qmi_service_v01.h +++ /dev/null @@ -1,610 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef IPA_QMI_SERVICE_V01_H -#define IPA_QMI_SERVICE_V01_H -#define QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01 2 -#define QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01 2 -#define QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01 2 -#define QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01 2 -#define QMI_IPA_MAX_FILTERS_V01 64 -#define QMI_IPA_MAX_FILTERS_EX_V01 128 -#define QMI_IPA_MAX_PIPES_V01 20 -#define QMI_IPA_MAX_APN_V01 8 -#define QMI_IPA_MAX_PER_CLIENTS_V01 64 -#define QMI_IPA_MAX_CLIENT_DST_PIPES_V01 8 -#define QMI_IPA_MAX_UL_FIREWALL_RULES_V01 64 -#define IPA_QMI_SUPPORTS_STATS -#define IPA_INT_MAX ((int) (~0U >> 1)) -#define IPA_INT_MIN (- IPA_INT_MAX - 1) -enum ipa_qmi_result_type_v01 { - IPA_QMI_RESULT_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, - IPA_QMI_RESULT_SUCCESS_V01 = 0, - IPA_QMI_RESULT_FAILURE_V01 = 1, - IPA_QMI_RESULT_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, -}; -enum ipa_qmi_error_type_v01 { - IPA_QMI_ERROR_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, - IPA_QMI_ERR_NONE_V01 = 0x0000, - IPA_QMI_ERR_MALFORMED_MSG_V01 = 0x0001, - IPA_QMI_ERR_NO_MEMORY_V01 = 0x0002, - IPA_QMI_ERR_INTERNAL_V01 = 0x0003, - IPA_QMI_ERR_CLIENT_IDS_EXHAUSTED_V01 = 0x0005, - IPA_QMI_ERR_INVALID_ID_V01 = 0x0029, - IPA_QMI_ERR_ENCODING_V01 = 0x003A, - IPA_QMI_ERR_INCOMPATIBLE_STATE_V01 = 0x005A, - IPA_QMI_ERR_NOT_SUPPORTED_V01 = 0x005E, - IPA_QMI_ERROR_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, -}; -struct ipa_qmi_response_type_v01 { - enum ipa_qmi_result_type_v01 result; - enum ipa_qmi_error_type_v01 error; -}; -enum ipa_platform_type_enum_v01 { - IPA_PLATFORM_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, - QMI_IPA_PLATFORM_TYPE_INVALID_V01 = 0, - QMI_IPA_PLATFORM_TYPE_TN_V01 = 1, - QMI_IPA_PLATFORM_TYPE_LE_V01 = 2, - QMI_IPA_PLATFORM_TYPE_MSM_ANDROID_V01 = 3, - QMI_IPA_PLATFORM_TYPE_MSM_WINDOWS_V01 = 4, - QMI_IPA_PLATFORM_TYPE_MSM_QNX_V01 = 5, - IPA_PLATFORM_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 -}; -struct ipa_hdr_tbl_info_type_v01 { - uint32_t modem_offset_start; - uint32_t modem_offset_end; -}; -struct ipa_route_tbl_info_type_v01 { - uint32_t route_tbl_start_addr; - uint32_t num_indices; -}; -struct ipa_modem_mem_info_type_v01 { - uint32_t block_start_addr; - uint32_t size; -}; -struct ipa_hdr_proc_ctx_tbl_info_type_v01 { - uint32_t modem_offset_start; - uint32_t modem_offset_end; -}; -struct ipa_zip_tbl_info_type_v01 { - uint32_t modem_offset_start; - uint32_t modem_offset_end; -}; -struct ipa_init_modem_driver_req_msg_v01 { - uint8_t platform_type_valid; - enum ipa_platform_type_enum_v01 platform_type; - uint8_t hdr_tbl_info_valid; - struct ipa_hdr_tbl_info_type_v01 hdr_tbl_info; - uint8_t v4_route_tbl_info_valid; - struct ipa_route_tbl_info_type_v01 v4_route_tbl_info; - uint8_t v6_route_tbl_info_valid; - struct ipa_route_tbl_info_type_v01 v6_route_tbl_info; - uint8_t v4_filter_tbl_start_addr_valid; - uint32_t v4_filter_tbl_start_addr; - uint8_t v6_filter_tbl_start_addr_valid; - uint32_t v6_filter_tbl_start_addr; - uint8_t modem_mem_info_valid; - struct ipa_modem_mem_info_type_v01 modem_mem_info; - uint8_t ctrl_comm_dest_end_pt_valid; - uint32_t ctrl_comm_dest_end_pt; - uint8_t is_ssr_bootup_valid; - uint8_t is_ssr_bootup; - uint8_t hdr_proc_ctx_tbl_info_valid; - struct ipa_hdr_proc_ctx_tbl_info_type_v01 hdr_proc_ctx_tbl_info; - uint8_t zip_tbl_info_valid; - struct ipa_zip_tbl_info_type_v01 zip_tbl_info; - uint8_t v4_hash_route_tbl_info_valid; - struct ipa_route_tbl_info_type_v01 v4_hash_route_tbl_info; - uint8_t v6_hash_route_tbl_info_valid; - struct ipa_route_tbl_info_type_v01 v6_hash_route_tbl_info; - uint8_t v4_hash_filter_tbl_start_addr_valid; - uint32_t v4_hash_filter_tbl_start_addr; - uint8_t v6_hash_filter_tbl_start_addr_valid; - uint32_t v6_hash_filter_tbl_start_addr; - uint8_t hw_stats_quota_base_addr_valid; - uint32_t hw_stats_quota_base_addr; - uint8_t hw_stats_quota_size_valid; - uint32_t hw_stats_quota_size; - uint8_t hw_drop_stats_base_addr_valid; - uint32_t hw_drop_stats_base_addr; - uint8_t hw_drop_stats_table_size_valid; - uint32_t hw_drop_stats_table_size; -}; -struct ipa_init_modem_driver_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; - uint8_t ctrl_comm_dest_end_pt_valid; - uint32_t ctrl_comm_dest_end_pt; - uint8_t default_end_pt_valid; - uint32_t default_end_pt; - uint8_t modem_driver_init_pending_valid; - uint8_t modem_driver_init_pending; -}; -struct ipa_init_modem_driver_cmplt_req_msg_v01 { - uint8_t status; -}; -struct ipa_init_modem_driver_cmplt_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; -}; -struct ipa_indication_reg_req_msg_v01 { - uint8_t master_driver_init_complete_valid; - uint8_t master_driver_init_complete; - uint8_t data_usage_quota_reached_valid; - uint8_t data_usage_quota_reached; -}; -struct ipa_indication_reg_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; -}; -struct ipa_master_driver_init_complt_ind_msg_v01 { - struct ipa_qmi_response_type_v01 master_driver_init_status; -}; -struct ipa_ipfltr_range_eq_16_type_v01 { - uint8_t offset; - uint16_t range_low; - uint16_t range_high; -}; -struct ipa_ipfltr_mask_eq_32_type_v01 { - uint8_t offset; - uint32_t mask; - uint32_t value; -}; -struct ipa_ipfltr_eq_16_type_v01 { - uint8_t offset; - uint16_t value; -}; -struct ipa_ipfltr_eq_32_type_v01 { - uint8_t offset; - uint32_t value; -}; -struct ipa_ipfltr_mask_eq_128_type_v01 { - uint8_t offset; - uint8_t mask[16]; - uint8_t value[16]; -}; -struct ipa_filter_rule_type_v01 { - uint16_t rule_eq_bitmap; - uint8_t tos_eq_present; - uint8_t tos_eq; - uint8_t protocol_eq_present; - uint8_t protocol_eq; - uint8_t num_ihl_offset_range_16; - struct ipa_ipfltr_range_eq_16_type_v01 ihl_offset_range_16[QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01]; - uint8_t num_offset_meq_32; - struct ipa_ipfltr_mask_eq_32_type_v01 offset_meq_32[QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01]; - uint8_t tc_eq_present; - uint8_t tc_eq; - uint8_t flow_eq_present; - uint32_t flow_eq; - uint8_t ihl_offset_eq_16_present; - struct ipa_ipfltr_eq_16_type_v01 ihl_offset_eq_16; - uint8_t ihl_offset_eq_32_present; - struct ipa_ipfltr_eq_32_type_v01 ihl_offset_eq_32; - uint8_t num_ihl_offset_meq_32; - struct ipa_ipfltr_mask_eq_32_type_v01 ihl_offset_meq_32[QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01]; - uint8_t num_offset_meq_128; - struct ipa_ipfltr_mask_eq_128_type_v01 offset_meq_128[QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01]; - uint8_t metadata_meq32_present; - struct ipa_ipfltr_mask_eq_32_type_v01 metadata_meq32; - uint8_t ipv4_frag_eq_present; -}; -enum ipa_ip_type_enum_v01 { - IPA_IP_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, - QMI_IPA_IP_TYPE_INVALID_V01 = 0, - QMI_IPA_IP_TYPE_V4_V01 = 1, - QMI_IPA_IP_TYPE_V6_V01 = 2, - QMI_IPA_IP_TYPE_V4V6_V01 = 3, - IPA_IP_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 -}; -enum ipa_filter_action_enum_v01 { - IPA_FILTER_ACTION_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, - QMI_IPA_FILTER_ACTION_INVALID_V01 = 0, - QMI_IPA_FILTER_ACTION_SRC_NAT_V01 = 1, - QMI_IPA_FILTER_ACTION_DST_NAT_V01 = 2, - QMI_IPA_FILTER_ACTION_ROUTING_V01 = 3, - QMI_IPA_FILTER_ACTION_EXCEPTION_V01 = 4, - IPA_FILTER_ACTION_ENUM_MAX_ENUM_VAL_V01 = 2147483647 -}; -struct ipa_filter_spec_type_v01 { - uint32_t filter_spec_identifier; - enum ipa_ip_type_enum_v01 ip_type; - struct ipa_filter_rule_type_v01 filter_rule; - enum ipa_filter_action_enum_v01 filter_action; - uint8_t is_routing_table_index_valid; - uint32_t route_table_index; - uint8_t is_mux_id_valid; - uint32_t mux_id; -}; -struct ipa_filter_spec_ex_type_v01 { - enum ipa_ip_type_enum_v01 ip_type; - struct ipa_filter_rule_type_v01 filter_rule; - enum ipa_filter_action_enum_v01 filter_action; - uint8_t is_routing_table_index_valid; - uint32_t route_table_index; - uint8_t is_mux_id_valid; - uint32_t mux_id; - uint32_t rule_id; - uint8_t is_rule_hashable; -}; -struct ipa_install_fltr_rule_req_msg_v01 { - uint8_t filter_spec_list_valid; - uint32_t filter_spec_list_len; - struct ipa_filter_spec_type_v01 filter_spec_list[QMI_IPA_MAX_FILTERS_V01]; - uint8_t source_pipe_index_valid; - uint32_t source_pipe_index; - uint8_t num_ipv4_filters_valid; - uint32_t num_ipv4_filters; - uint8_t num_ipv6_filters_valid; - uint32_t num_ipv6_filters; - uint8_t xlat_filter_indices_list_valid; - uint32_t xlat_filter_indices_list_len; - uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_V01]; - uint8_t filter_spec_ex_list_valid; - uint32_t filter_spec_ex_list_len; - struct ipa_filter_spec_ex_type_v01 filter_spec_ex_list[QMI_IPA_MAX_FILTERS_V01]; -}; -struct ipa_filter_rule_identifier_to_handle_map_v01 { - uint32_t filter_spec_identifier; - uint32_t filter_handle; -}; -struct ipa_install_fltr_rule_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; - uint8_t filter_handle_list_valid; - uint32_t filter_handle_list_len; - struct ipa_filter_rule_identifier_to_handle_map_v01 filter_handle_list[QMI_IPA_MAX_FILTERS_V01]; - uint8_t rule_id_valid; - uint32_t rule_id_len; - uint32_t rule_id[QMI_IPA_MAX_FILTERS_V01]; -}; -struct ipa_filter_handle_to_index_map_v01 { - uint32_t filter_handle; - uint32_t filter_index; -}; -struct ipa_fltr_installed_notif_req_msg_v01 { - uint32_t source_pipe_index; - enum ipa_qmi_result_type_v01 install_status; - uint32_t filter_index_list_len; - struct ipa_filter_handle_to_index_map_v01 filter_index_list[QMI_IPA_MAX_FILTERS_V01]; - uint8_t embedded_pipe_index_valid; - uint32_t embedded_pipe_index; - uint8_t retain_header_valid; - uint8_t retain_header; - uint8_t embedded_call_mux_id_valid; - uint32_t embedded_call_mux_id; - uint8_t num_ipv4_filters_valid; - uint32_t num_ipv4_filters; - uint8_t num_ipv6_filters_valid; - uint32_t num_ipv6_filters; - uint8_t start_ipv4_filter_idx_valid; - uint32_t start_ipv4_filter_idx; - uint8_t start_ipv6_filter_idx_valid; - uint32_t start_ipv6_filter_idx; - uint8_t rule_id_valid; - uint32_t rule_id_len; - uint32_t rule_id[QMI_IPA_MAX_FILTERS_V01]; - uint8_t dst_pipe_id_valid; - uint32_t dst_pipe_id_len; - uint32_t dst_pipe_id[QMI_IPA_MAX_CLIENT_DST_PIPES_V01]; -}; -struct ipa_fltr_installed_notif_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; -}; -struct ipa_enable_force_clear_datapath_req_msg_v01 { - uint32_t source_pipe_bitmask; - uint32_t request_id; - uint8_t throttle_source_valid; - uint8_t throttle_source; -}; -struct ipa_enable_force_clear_datapath_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; -}; -struct ipa_disable_force_clear_datapath_req_msg_v01 { - uint32_t request_id; -}; -struct ipa_disable_force_clear_datapath_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; -}; -enum ipa_peripheral_speed_enum_v01 { - IPA_PERIPHERAL_SPEED_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, - QMI_IPA_PER_USB_FS_V01 = 1, - QMI_IPA_PER_USB_HS_V01 = 2, - QMI_IPA_PER_USB_SS_V01 = 3, - QMI_IPA_PER_WLAN_V01 = 4, - IPA_PERIPHERAL_SPEED_ENUM_MAX_ENUM_VAL_V01 = 2147483647 -}; -enum ipa_pipe_mode_enum_v01 { - IPA_PIPE_MODE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, - QMI_IPA_PIPE_MODE_HW_V01 = 1, - QMI_IPA_PIPE_MODE_SW_V01 = 2, - IPA_PIPE_MODE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 -}; -enum ipa_peripheral_type_enum_v01 { - IPA_PERIPHERAL_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, - QMI_IPA_PERIPHERAL_USB_V01 = 1, - QMI_IPA_PERIPHERAL_HSIC_V01 = 2, - QMI_IPA_PERIPHERAL_PCIE_V01 = 3, - IPA_PERIPHERAL_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 -}; -struct ipa_config_req_msg_v01 { - uint8_t peripheral_type_valid; - enum ipa_peripheral_type_enum_v01 peripheral_type; - uint8_t hw_deaggr_supported_valid; - uint8_t hw_deaggr_supported; - uint8_t max_aggr_frame_size_valid; - uint32_t max_aggr_frame_size; - uint8_t ipa_ingress_pipe_mode_valid; - enum ipa_pipe_mode_enum_v01 ipa_ingress_pipe_mode; - uint8_t peripheral_speed_info_valid; - enum ipa_peripheral_speed_enum_v01 peripheral_speed_info; - uint8_t dl_accumulation_time_limit_valid; - uint32_t dl_accumulation_time_limit; - uint8_t dl_accumulation_pkt_limit_valid; - uint32_t dl_accumulation_pkt_limit; - uint8_t dl_accumulation_byte_limit_valid; - uint32_t dl_accumulation_byte_limit; - uint8_t ul_accumulation_time_limit_valid; - uint32_t ul_accumulation_time_limit; - uint8_t hw_control_flags_valid; - uint32_t hw_control_flags; - uint8_t ul_msi_event_threshold_valid; - uint32_t ul_msi_event_threshold; - uint8_t dl_msi_event_threshold_valid; - uint32_t dl_msi_event_threshold; - uint8_t ul_fifo_size_valid; - uint32_t ul_fifo_size; - uint8_t dl_fifo_size_valid; - uint32_t dl_fifo_size; - uint8_t dl_buf_size_valid; - uint32_t dl_buf_size; -}; -struct ipa_config_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; -}; -enum ipa_stats_type_enum_v01 { - IPA_STATS_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, - QMI_IPA_STATS_TYPE_INVALID_V01 = 0, - QMI_IPA_STATS_TYPE_PIPE_V01 = 1, - QMI_IPA_STATS_TYPE_FILTER_RULES_V01 = 2, - IPA_STATS_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 -}; -struct ipa_pipe_stats_info_type_v01 { - uint32_t pipe_index; - uint64_t num_ipv4_packets; - uint64_t num_ipv4_bytes; - uint64_t num_ipv6_packets; - uint64_t num_ipv6_bytes; -}; -struct ipa_stats_type_filter_rule_v01 { - uint32_t filter_rule_index; - uint64_t num_packets; -}; -struct ipa_get_data_stats_req_msg_v01 { - enum ipa_stats_type_enum_v01 ipa_stats_type; - uint8_t reset_stats_valid; - uint8_t reset_stats; -}; -struct ipa_get_data_stats_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; - uint8_t ipa_stats_type_valid; - enum ipa_stats_type_enum_v01 ipa_stats_type; - uint8_t ul_src_pipe_stats_list_valid; - uint32_t ul_src_pipe_stats_list_len; - struct ipa_pipe_stats_info_type_v01 ul_src_pipe_stats_list[QMI_IPA_MAX_PIPES_V01]; - uint8_t dl_dst_pipe_stats_list_valid; - uint32_t dl_dst_pipe_stats_list_len; - struct ipa_pipe_stats_info_type_v01 dl_dst_pipe_stats_list[QMI_IPA_MAX_PIPES_V01]; - uint8_t dl_filter_rule_stats_list_valid; - uint32_t dl_filter_rule_stats_list_len; - struct ipa_stats_type_filter_rule_v01 dl_filter_rule_stats_list[QMI_IPA_MAX_FILTERS_V01]; -}; -struct ipa_apn_data_stats_info_type_v01 { - uint32_t mux_id; - uint64_t num_ul_packets; - uint64_t num_ul_bytes; - uint64_t num_dl_packets; - uint64_t num_dl_bytes; -}; -struct ipa_get_apn_data_stats_req_msg_v01 { - uint8_t mux_id_list_valid; - uint32_t mux_id_list_len; - uint32_t mux_id_list[QMI_IPA_MAX_APN_V01]; -}; -struct ipa_get_apn_data_stats_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; - uint8_t apn_data_stats_list_valid; - uint32_t apn_data_stats_list_len; - struct ipa_apn_data_stats_info_type_v01 apn_data_stats_list[QMI_IPA_MAX_APN_V01]; -}; -struct ipa_data_usage_quota_info_type_v01 { - uint32_t mux_id; - uint64_t num_Mbytes; -}; -struct ipa_set_data_usage_quota_req_msg_v01 { - uint8_t apn_quota_list_valid; - uint32_t apn_quota_list_len; - struct ipa_data_usage_quota_info_type_v01 apn_quota_list[QMI_IPA_MAX_APN_V01]; -}; -struct ipa_set_data_usage_quota_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; -}; -struct ipa_data_usage_quota_reached_ind_msg_v01 { - struct ipa_data_usage_quota_info_type_v01 apn; -}; -struct ipa_stop_data_usage_quota_req_msg_v01 { - char __placeholder; -}; -struct ipa_stop_data_usage_quota_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; -}; -struct ipa_install_fltr_rule_req_ex_msg_v01 { - uint8_t filter_spec_ex_list_valid; - uint32_t filter_spec_ex_list_len; - struct ipa_filter_spec_ex_type_v01 filter_spec_ex_list[QMI_IPA_MAX_FILTERS_EX_V01]; - uint8_t source_pipe_index_valid; - uint32_t source_pipe_index; - uint8_t num_ipv4_filters_valid; - uint32_t num_ipv4_filters; - uint8_t num_ipv6_filters_valid; - uint32_t num_ipv6_filters; - uint8_t xlat_filter_indices_list_valid; - uint32_t xlat_filter_indices_list_len; - uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_EX_V01]; -}; -struct ipa_install_fltr_rule_resp_ex_msg_v01 { - struct ipa_qmi_response_type_v01 resp; - uint8_t rule_id_valid; - uint32_t rule_id_len; - uint32_t rule_id[QMI_IPA_MAX_FILTERS_EX_V01]; -}; -struct ipa_enable_per_client_stats_req_msg_v01 { - uint8_t enable_per_client_stats; -}; -struct ipa_enable_per_client_stats_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; -}; -struct ipa_per_client_stats_info_type_v01 { - uint32_t client_id; - uint32_t src_pipe_id; - uint64_t num_ul_ipv4_bytes; - uint64_t num_ul_ipv6_bytes; - uint64_t num_dl_ipv4_bytes; - uint64_t num_dl_ipv6_bytes; - uint32_t num_ul_ipv4_pkts; - uint32_t num_ul_ipv6_pkts; - uint32_t num_dl_ipv4_pkts; - uint32_t num_dl_ipv6_pkts; -}; -struct ipa_get_stats_per_client_req_msg_v01 { - uint32_t client_id; - uint32_t src_pipe_id; - uint8_t reset_stats_valid; - uint8_t reset_stats; -}; -struct ipa_get_stats_per_client_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; - uint8_t per_client_stats_list_valid; - uint32_t per_client_stats_list_len; - struct ipa_per_client_stats_info_type_v01 per_client_stats_list[QMI_IPA_MAX_PER_CLIENTS_V01]; -}; -struct ipa_ul_firewall_rule_type_v01 { - enum ipa_ip_type_enum_v01 ip_type; - struct ipa_filter_rule_type_v01 filter_rule; -}; -struct ipa_configure_ul_firewall_rules_req_msg_v01 { - uint32_t firewall_rules_list_len; - struct ipa_ul_firewall_rule_type_v01 firewall_rules_list[QMI_IPA_MAX_UL_FIREWALL_RULES_V01]; - uint32_t mux_id; - uint8_t disable_valid; - uint8_t disable; - uint8_t are_blacklist_filters_valid; - uint8_t are_blacklist_filters; -}; -struct ipa_configure_ul_firewall_rules_resp_msg_v01 { - struct ipa_qmi_response_type_v01 resp; -}; -enum ipa_ul_firewall_status_enum_v01 { - IPA_UL_FIREWALL_STATUS_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, - QMI_IPA_UL_FIREWALL_STATUS_SUCCESS_V01 = 0, - QMI_IPA_UL_FIREWALL_STATUS_FAILURE_V01 = 1, - IPA_UL_FIREWALL_STATUS_ENUM_MAX_ENUM_VAL_V01 = 2147483647 -}; -struct ipa_ul_firewall_config_result_type_v01 { - enum ipa_ul_firewall_status_enum_v01 is_success; - uint32_t mux_id; -}; -struct ipa_configure_ul_firewall_rules_ind_msg_v01 { - struct ipa_ul_firewall_config_result_type_v01 result; -}; -#define QMI_IPA_INDICATION_REGISTER_REQ_V01 0x0020 -#define QMI_IPA_INDICATION_REGISTER_RESP_V01 0x0020 -#define QMI_IPA_INIT_MODEM_DRIVER_REQ_V01 0x0021 -#define QMI_IPA_INIT_MODEM_DRIVER_RESP_V01 0x0021 -#define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_V01 0x0022 -#define QMI_IPA_INSTALL_FILTER_RULE_REQ_V01 0x0023 -#define QMI_IPA_INSTALL_FILTER_RULE_RESP_V01 0x0023 -#define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_V01 0x0024 -#define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_V01 0x0024 -#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0025 -#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0025 -#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0026 -#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0026 -#define QMI_IPA_CONFIG_REQ_V01 0x0027 -#define QMI_IPA_CONFIG_RESP_V01 0x0027 -#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0028 -#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0028 -#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0029 -#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0029 -#define QMI_IPA_GET_DATA_STATS_REQ_V01 0x0030 -#define QMI_IPA_GET_DATA_STATS_RESP_V01 0x0030 -#define QMI_IPA_GET_APN_DATA_STATS_REQ_V01 0x0031 -#define QMI_IPA_GET_APN_DATA_STATS_RESP_V01 0x0031 -#define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01 0x0032 -#define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_V01 0x0032 -#define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_V01 0x0033 -#define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01 0x0034 -#define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_V01 0x0034 -#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_V01 0x0035 -#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_V01 0x0035 -#define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_V01 0x0037 -#define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_V01 0x0037 -#define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_V01 0x0038 -#define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_V01 0x0038 -#define QMI_IPA_GET_STATS_PER_CLIENT_REQ_V01 0x0039 -#define QMI_IPA_GET_STATS_PER_CLIENT_RESP_V01 0x0039 -#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_V01 0x003A -#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_V01 0x003A -#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_V01 0x003A -#define QMI_IPA_INIT_MODEM_DRIVER_REQ_MAX_MSG_LEN_V01 162 -#define QMI_IPA_INIT_MODEM_DRIVER_RESP_MAX_MSG_LEN_V01 25 -#define QMI_IPA_INDICATION_REGISTER_REQ_MAX_MSG_LEN_V01 8 -#define QMI_IPA_INDICATION_REGISTER_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_INSTALL_FILTER_RULE_REQ_MAX_MSG_LEN_V01 22369 -#define QMI_IPA_INSTALL_FILTER_RULE_RESP_MAX_MSG_LEN_V01 783 -#define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_MAX_MSG_LEN_V01 870 -#define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_MAX_MSG_LEN_V01 7 -#define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_MAX_MSG_LEN_V01 15 -#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 18 -#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 7 -#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_CONFIG_REQ_MAX_MSG_LEN_V01 102 -#define QMI_IPA_CONFIG_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 18 -#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 7 -#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_GET_DATA_STATS_REQ_MAX_MSG_LEN_V01 11 -#define QMI_IPA_GET_DATA_STATS_RESP_MAX_MSG_LEN_V01 2234 -#define QMI_IPA_GET_APN_DATA_STATS_REQ_MAX_MSG_LEN_V01 36 -#define QMI_IPA_GET_APN_DATA_STATS_RESP_MAX_MSG_LEN_V01 299 -#define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 100 -#define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 0 -#define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_MAX_MSG_LEN_V01 4 -#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_MAX_MSG_LEN_V01 22685 -#define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_MAX_MSG_LEN_V01 523 -#define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_MAX_MSG_LEN_V01 4 -#define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_GET_STATS_PER_CLIENT_REQ_MAX_MSG_LEN_V01 18 -#define QMI_IPA_GET_STATS_PER_CLIENT_RESP_MAX_MSG_LEN_V01 3595 -#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_MAX_MSG_LEN_V01 9875 -#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_MAX_MSG_LEN_V01 11 -#endif - diff --git a/sdm710/kernel-headers/linux/mdss_rotator.h b/sdm710/kernel-headers/linux/mdss_rotator.h deleted file mode 100644 index e8c99ba2..00000000 --- a/sdm710/kernel-headers/linux/mdss_rotator.h +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _MDSS_ROTATOR_H_ -#define _MDSS_ROTATOR_H_ -#include <linux/msm_mdp_ext.h> -#define MDSS_ROTATOR_IOCTL_MAGIC 'w' -#define MDSS_ROTATION_OPEN _IOWR(MDSS_ROTATOR_IOCTL_MAGIC, 1, struct mdp_rotation_config *) -#define MDSS_ROTATION_CONFIG _IOWR(MDSS_ROTATOR_IOCTL_MAGIC, 2, struct mdp_rotation_config *) -#define MDSS_ROTATION_REQUEST _IOWR(MDSS_ROTATOR_IOCTL_MAGIC, 3, struct mdp_rotation_request *) -#define MDSS_ROTATION_CLOSE _IOW(MDSS_ROTATOR_IOCTL_MAGIC, 4, unsigned int) -#define MDP_ROTATION_NOP 0x01 -#define MDP_ROTATION_FLIP_LR 0x02 -#define MDP_ROTATION_FLIP_UD 0x04 -#define MDP_ROTATION_90 0x08 -#define MDP_ROTATION_180 (MDP_ROTATION_FLIP_LR | MDP_ROTATION_FLIP_UD) -#define MDP_ROTATION_270 (MDP_ROTATION_90 | MDP_ROTATION_180) -#define MDP_ROTATION_DEINTERLACE 0x10 -#define MDP_ROTATION_BWC_EN 0x40 -#define MDP_ROTATION_SECURE 0x80 -#define MDSS_ROTATION_REQUEST_VALIDATE 0x01 -#define MDP_ROTATION_REQUEST_VERSION_1_0 0x00010000 -#define MDSS_ROTATION_HW_ANY 0xFFFFFFFF -struct mdp_rotation_buf_info { - uint32_t width; - uint32_t height; - uint32_t format; - struct mult_factor comp_ratio; -}; -struct mdp_rotation_config { - uint32_t version; - uint32_t session_id; - struct mdp_rotation_buf_info input; - struct mdp_rotation_buf_info output; - uint32_t frame_rate; - uint32_t flags; - uint32_t reserved[6]; -}; -struct mdp_rotation_item { - uint32_t flags; - struct mdp_rect src_rect; - struct mdp_rect dst_rect; - struct mdp_layer_buffer input; - struct mdp_layer_buffer output; - uint32_t pipe_idx; - uint32_t wb_idx; - uint32_t session_id; - uint32_t reserved[6]; -}; -struct mdp_rotation_request { - uint32_t version; - uint32_t flags; - uint32_t count; - struct mdp_rotation_item * list; - uint32_t reserved[6]; -}; -#endif - diff --git a/sdm710/kernel-headers/linux/mfd/msm-adie-codec.h b/sdm710/kernel-headers/linux/mfd/msm-adie-codec.h deleted file mode 100644 index 80cdc6cf..00000000 --- a/sdm710/kernel-headers/linux/mfd/msm-adie-codec.h +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_MFD_MSM_ADIE_CODEC_H -#define __UAPI_MFD_MSM_ADIE_CODEC_H -#include <linux/types.h> -#define ADIE_CODEC_ACTION_ENTRY 0x1 -#define ADIE_CODEC_ACTION_DELAY_WAIT 0x2 -#define ADIE_CODEC_ACTION_STAGE_REACHED 0x3 -#define ADIE_CODEC_PATH_OFF 0x0050 -#define ADIE_CODEC_DIGITAL_READY 0x0100 -#define ADIE_CODEC_DIGITAL_ANALOG_READY 0x1000 -#define ADIE_CODEC_ANALOG_OFF 0x0750 -#define ADIE_CODEC_DIGITAL_OFF 0x0600 -#define ADIE_CODEC_FLASH_IMAGE 0x0001 -#define ADIE_CODEC_RX 0 -#define ADIE_CODEC_TX 1 -#define ADIE_CODEC_LB 3 -#define ADIE_CODEC_MAX 4 -#define ADIE_CODEC_PACK_ENTRY(reg,mask,val) ((val) | (mask << 8) | (reg << 16)) -#define ADIE_CODEC_UNPACK_ENTRY(packed,reg,mask,val) do { ((reg) = ((packed >> 16) & (0xff))); ((mask) = ((packed >> 8) & (0xff))); ((val) = ((packed) & (0xff))); } while(0); -struct adie_codec_action_unit { - u32 type; - u32 action; -}; -struct adie_codec_hwsetting_entry { - struct adie_codec_action_unit * actions; - u32 action_sz; - u32 freq_plan; - u32 osr; -}; -struct adie_codec_dev_profile { - u32 path_type; - u32 setting_sz; - struct adie_codec_hwsetting_entry * settings; -}; -struct adie_codec_register { - u8 reg; - u8 mask; - u8 val; -}; -struct adie_codec_register_image { - struct adie_codec_register * regs; - u32 img_sz; -}; -struct adie_codec_path; -struct adie_codec_anc_data { - u32 size; - u32 writes[]; -}; -struct adie_codec_operations { - int codec_id; - int(* codec_open) (struct adie_codec_dev_profile * profile, struct adie_codec_path * * path_pptr); - int(* codec_close) (struct adie_codec_path * path_ptr); - int(* codec_setpath) (struct adie_codec_path * path_ptr, u32 freq_plan, u32 osr); - int(* codec_proceed_stage) (struct adie_codec_path * path_ptr, u32 state); - u32(* codec_freq_supported) (struct adie_codec_dev_profile * profile, u32 requested_freq); - int(* codec_enable_sidetone) (struct adie_codec_path * rx_path_ptr, u32 enable); - int(* codec_enable_anc) (struct adie_codec_path * rx_path_ptr, u32 enable, struct adie_codec_anc_data * calibration_writes); - int(* codec_set_device_digital_volume) (struct adie_codec_path * path_ptr, u32 num_channels, u32 vol_percentage); - int(* codec_set_device_analog_volume) (struct adie_codec_path * path_ptr, u32 num_channels, u32 volume); - int(* codec_set_master_mode) (struct adie_codec_path * path_ptr, u8 master); -}; -#endif - diff --git a/sdm710/kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h b/sdm710/kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h deleted file mode 100644 index 50a6aa33..00000000 --- a/sdm710/kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h +++ /dev/null @@ -1,1401 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef WCD9320_REGISTERS_H -#define WCD9320_REGISTERS_H -#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h> -#define TAIKO_A_CHIP_CTL WCD9XXX_A_CHIP_CTL -#define TAIKO_A_CHIP_CTL__POR WCD9XXX_A_CHIP_CTL__POR -#define TAIKO_A_CHIP_STATUS WCD9XXX_A_CHIP_STATUS -#define TAIKO_A_CHIP_STATUS__POR WCD9XXX_A_CHIP_STATUS__POR -#define TAIKO_A_CHIP_ID_BYTE_0 WCD9XXX_A_CHIP_ID_BYTE_0 -#define TAIKO_A_CHIP_ID_BYTE_0__POR WCD9XXX_A_CHIP_ID_BYTE_0__POR -#define TAIKO_A_CHIP_ID_BYTE_1 WCD9XXX_A_CHIP_ID_BYTE_1 -#define TAIKO_A_CHIP_ID_BYTE_1__POR WCD9XXX_A_CHIP_ID_BYTE_1__POR -#define TAIKO_A_CHIP_ID_BYTE_2 WCD9XXX_A_CHIP_ID_BYTE_2 -#define TAIKO_A_CHIP_ID_BYTE_2__POR WCD9XXX_A_CHIP_ID_BYTE_2__POR -#define TAIKO_A_CHIP_ID_BYTE_3 WCD9XXX_A_CHIP_ID_BYTE_3 -#define TAIKO_A_CHIP_ID_BYTE_3__POR WCD9XXX_A_CHIP_ID_BYTE_3__POR -#define TAIKO_A_CHIP_VERSION WCD9XXX_A_CHIP_VERSION -#define TAIKO_A_CHIP_VERSION__POR WCD9XXX_A_CHIP_VERSION__POR -#define TAIKO_A_SB_VERSION WCD9XXX_A_SB_VERSION -#define TAIKO_A_SB_VERSION__POR WCD9XXX_A_SB_VERSION__POR -#define TAIKO_A_SLAVE_ID_1 WCD9XXX_A_SLAVE_ID_1 -#define TAIKO_A_SLAVE_ID_1__POR WCD9XXX_A_SLAVE_ID_1__POR -#define TAIKO_A_SLAVE_ID_2 WCD9XXX_A_SLAVE_ID_2 -#define TAIKO_A_SLAVE_ID_2__POR WCD9XXX_A_SLAVE_ID_2__POR -#define TAIKO_A_SLAVE_ID_3 WCD9XXX_A_SLAVE_ID_3 -#define TAIKO_A_SLAVE_ID_3__POR WCD9XXX_A_SLAVE_ID_3__POR -#define TAIKO_A_PIN_CTL_OE0 (0x010) -#define TAIKO_A_PIN_CTL_OE0__POR (0x00) -#define TAIKO_A_PIN_CTL_OE1 (0x011) -#define TAIKO_A_PIN_CTL_OE1__POR (0x00) -#define TAIKO_A_PIN_CTL_DATA0 (0x012) -#define TAIKO_A_PIN_CTL_DATA0__POR (0x00) -#define TAIKO_A_PIN_CTL_DATA1 (0x013) -#define TAIKO_A_PIN_CTL_DATA1__POR (0x00) -#define TAIKO_A_HDRIVE_GENERIC (0x018) -#define TAIKO_A_HDRIVE_GENERIC__POR (0x00) -#define TAIKO_A_HDRIVE_OVERRIDE (0x019) -#define TAIKO_A_HDRIVE_OVERRIDE__POR (0x08) -#define TAIKO_A_ANA_CSR_WAIT_STATE (0x020) -#define TAIKO_A_ANA_CSR_WAIT_STATE__POR (0x44) -#define TAIKO_A_PROCESS_MONITOR_CTL0 (0x040) -#define TAIKO_A_PROCESS_MONITOR_CTL0__POR (0x80) -#define TAIKO_A_PROCESS_MONITOR_CTL1 (0x041) -#define TAIKO_A_PROCESS_MONITOR_CTL1__POR (0x00) -#define TAIKO_A_PROCESS_MONITOR_CTL2 (0x042) -#define TAIKO_A_PROCESS_MONITOR_CTL2__POR (0x00) -#define TAIKO_A_PROCESS_MONITOR_CTL3 (0x043) -#define TAIKO_A_PROCESS_MONITOR_CTL3__POR (0x01) -#define TAIKO_A_QFUSE_CTL (0x048) -#define TAIKO_A_QFUSE_CTL__POR (0x00) -#define TAIKO_A_QFUSE_STATUS (0x049) -#define TAIKO_A_QFUSE_STATUS__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT0 (0x04A) -#define TAIKO_A_QFUSE_DATA_OUT0__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT1 (0x04B) -#define TAIKO_A_QFUSE_DATA_OUT1__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT2 (0x04C) -#define TAIKO_A_QFUSE_DATA_OUT2__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT3 (0x04D) -#define TAIKO_A_QFUSE_DATA_OUT3__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT4 (0x04E) -#define TAIKO_A_QFUSE_DATA_OUT4__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT5 (0x04F) -#define TAIKO_A_QFUSE_DATA_OUT5__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT6 (0x050) -#define TAIKO_A_QFUSE_DATA_OUT6__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT7 (0x051) -#define TAIKO_A_QFUSE_DATA_OUT7__POR (0x00) -#define TAIKO_A_CDC_CTL WCD9XXX_A_CDC_CTL -#define TAIKO_A_CDC_CTL__POR WCD9XXX_A_CDC_CTL__POR -#define TAIKO_A_LEAKAGE_CTL WCD9XXX_A_LEAKAGE_CTL -#define TAIKO_A_LEAKAGE_CTL__POR WCD9XXX_A_LEAKAGE_CTL__POR -#define TAIKO_A_INTR_MODE (0x090) -#define TAIKO_A_INTR_MODE__POR (0x00) -#define TAIKO_A_INTR_MASK0 (0x094) -#define TAIKO_A_INTR_MASK0__POR (0xFF) -#define TAIKO_A_INTR_MASK1 (0x095) -#define TAIKO_A_INTR_MASK1__POR (0xFF) -#define TAIKO_A_INTR_MASK2 (0x096) -#define TAIKO_A_INTR_MASK2__POR (0x3F) -#define TAIKO_A_INTR_MASK3 (0x097) -#define TAIKO_A_INTR_MASK3__POR (0x3F) -#define TAIKO_A_INTR_STATUS0 (0x098) -#define TAIKO_A_INTR_STATUS0__POR (0x00) -#define TAIKO_A_INTR_STATUS1 (0x099) -#define TAIKO_A_INTR_STATUS1__POR (0x00) -#define TAIKO_A_INTR_STATUS2 (0x09A) -#define TAIKO_A_INTR_STATUS2__POR (0x00) -#define TAIKO_A_INTR_STATUS3 (0x09B) -#define TAIKO_A_INTR_STATUS3__POR (0x00) -#define TAIKO_A_INTR_CLEAR0 (0x09C) -#define TAIKO_A_INTR_CLEAR0__POR (0x00) -#define TAIKO_A_INTR_CLEAR1 (0x09D) -#define TAIKO_A_INTR_CLEAR1__POR (0x00) -#define TAIKO_A_INTR_CLEAR2 (0x09E) -#define TAIKO_A_INTR_CLEAR2__POR (0x00) -#define TAIKO_A_INTR_CLEAR3 (0x09F) -#define TAIKO_A_INTR_CLEAR3__POR (0x00) -#define TAIKO_A_INTR_LEVEL0 (0x0A0) -#define TAIKO_A_INTR_LEVEL0__POR (0x01) -#define TAIKO_A_INTR_LEVEL1 (0x0A1) -#define TAIKO_A_INTR_LEVEL1__POR (0x00) -#define TAIKO_A_INTR_LEVEL2 (0x0A2) -#define TAIKO_A_INTR_LEVEL2__POR (0x00) -#define TAIKO_A_INTR_LEVEL3 (0x0A3) -#define TAIKO_A_INTR_LEVEL3__POR (0x00) -#define TAIKO_A_INTR_TEST0 (0x0A4) -#define TAIKO_A_INTR_TEST0__POR (0x00) -#define TAIKO_A_INTR_TEST1 (0x0A5) -#define TAIKO_A_INTR_TEST1__POR (0x00) -#define TAIKO_A_INTR_TEST2 (0x0A6) -#define TAIKO_A_INTR_TEST2__POR (0x00) -#define TAIKO_A_INTR_TEST3 (0x0A7) -#define TAIKO_A_INTR_TEST3__POR (0x00) -#define TAIKO_A_INTR_SET0 (0x0A8) -#define TAIKO_A_INTR_SET0__POR (0x00) -#define TAIKO_A_INTR_SET1 (0x0A9) -#define TAIKO_A_INTR_SET1__POR (0x00) -#define TAIKO_A_INTR_SET2 (0x0AA) -#define TAIKO_A_INTR_SET2__POR (0x00) -#define TAIKO_A_INTR_SET3 (0x0AB) -#define TAIKO_A_INTR_SET3__POR (0x00) -#define TAIKO_A_INTR_DESTN0 (0x0AC) -#define TAIKO_A_INTR_DESTN0__POR (0x00) -#define TAIKO_A_INTR_DESTN1 (0x0AD) -#define TAIKO_A_INTR_DESTN1__POR (0x00) -#define TAIKO_A_INTR_DESTN2 (0x0AE) -#define TAIKO_A_INTR_DESTN2__POR (0x00) -#define TAIKO_A_INTR_DESTN3 (0x0AF) -#define TAIKO_A_INTR_DESTN3__POR (0x00) -#define TAIKO_A_CDC_TX_I2S_SCK_MODE (0x0C0) -#define TAIKO_A_CDC_TX_I2S_SCK_MODE__POR (0x00) -#define TAIKO_A_CDC_TX_I2S_WS_MODE (0x0C1) -#define TAIKO_A_CDC_TX_I2S_WS_MODE__POR (0x00) -#define TAIKO_A_CDC_DMIC_DATA0_MODE (0x0C4) -#define TAIKO_A_CDC_DMIC_DATA0_MODE__POR (0x00) -#define TAIKO_A_CDC_DMIC_CLK0_MODE (0x0C5) -#define TAIKO_A_CDC_DMIC_CLK0_MODE__POR (0x00) -#define TAIKO_A_CDC_DMIC_DATA1_MODE (0x0C6) -#define TAIKO_A_CDC_DMIC_DATA1_MODE__POR (0x00) -#define TAIKO_A_CDC_DMIC_CLK1_MODE (0x0C7) -#define TAIKO_A_CDC_DMIC_CLK1_MODE__POR (0x00) -#define TAIKO_A_CDC_RX_I2S_SCK_MODE (0x0C8) -#define TAIKO_A_CDC_RX_I2S_SCK_MODE__POR (0x00) -#define TAIKO_A_CDC_RX_I2S_WS_MODE (0x0C9) -#define TAIKO_A_CDC_RX_I2S_WS_MODE__POR (0x00) -#define TAIKO_A_CDC_DMIC_DATA2_MODE (0x0CA) -#define TAIKO_A_CDC_DMIC_DATA2_MODE__POR (0x00) -#define TAIKO_A_CDC_DMIC_CLK2_MODE (0x0CB) -#define TAIKO_A_CDC_DMIC_CLK2_MODE__POR (0x00) -#define TAIKO_A_CDC_INTR1_MODE (0x0CC) -#define TAIKO_A_CDC_INTR1_MODE__POR (0x00) -#define TAIKO_A_CDC_SB_NRZ_SEL_MODE (0x0CD) -#define TAIKO_A_CDC_SB_NRZ_SEL_MODE__POR (0x00) -#define TAIKO_A_CDC_INTR2_MODE (0x0CE) -#define TAIKO_A_CDC_INTR2_MODE__POR (0x00) -#define TAIKO_A_CDC_RF_PA_ON_MODE (0x0CF) -#define TAIKO_A_CDC_RF_PA_ON_MODE__POR (0x00) -#define TAIKO_A_BIAS_REF_CTL (0x100) -#define TAIKO_A_BIAS_REF_CTL__POR (0x1C) -#define TAIKO_A_BIAS_CENTRAL_BG_CTL (0x101) -#define TAIKO_A_BIAS_CENTRAL_BG_CTL__POR (0x50) -#define TAIKO_A_BIAS_PRECHRG_CTL (0x102) -#define TAIKO_A_BIAS_PRECHRG_CTL__POR (0x07) -#define TAIKO_A_BIAS_CURR_CTL_1 (0x103) -#define TAIKO_A_BIAS_CURR_CTL_1__POR (0x52) -#define TAIKO_A_BIAS_CURR_CTL_2 (0x104) -#define TAIKO_A_BIAS_CURR_CTL_2__POR (0x00) -#define TAIKO_A_BIAS_OSC_BG_CTL (0x105) -#define TAIKO_A_BIAS_OSC_BG_CTL__POR (0x16) -#define TAIKO_A_CLK_BUFF_EN1 (0x108) -#define TAIKO_A_CLK_BUFF_EN1__POR (0x04) -#define TAIKO_A_CLK_BUFF_EN2 (0x109) -#define TAIKO_A_CLK_BUFF_EN2__POR (0x02) -#define TAIKO_A_LDO_H_MODE_1 (0x110) -#define TAIKO_A_LDO_H_MODE_1__POR (0x65) -#define TAIKO_A_LDO_H_MODE_2 (0x111) -#define TAIKO_A_LDO_H_MODE_2__POR (0xA8) -#define TAIKO_A_LDO_H_LOOP_CTL (0x112) -#define TAIKO_A_LDO_H_LOOP_CTL__POR (0x6B) -#define TAIKO_A_LDO_H_COMP_1 (0x113) -#define TAIKO_A_LDO_H_COMP_1__POR (0x84) -#define TAIKO_A_LDO_H_COMP_2 (0x114) -#define TAIKO_A_LDO_H_COMP_2__POR (0xE0) -#define TAIKO_A_LDO_H_BIAS_1 (0x115) -#define TAIKO_A_LDO_H_BIAS_1__POR (0x6D) -#define TAIKO_A_LDO_H_BIAS_2 (0x116) -#define TAIKO_A_LDO_H_BIAS_2__POR (0xA5) -#define TAIKO_A_LDO_H_BIAS_3 (0x117) -#define TAIKO_A_LDO_H_BIAS_3__POR (0x60) -#define TAIKO_A_VBAT_CLK (0x118) -#define TAIKO_A_VBAT_CLK__POR (0x03) -#define TAIKO_A_VBAT_LOOP (0x119) -#define TAIKO_A_VBAT_LOOP__POR (0x02) -#define TAIKO_A_VBAT_REF (0x11A) -#define TAIKO_A_VBAT_REF__POR (0x20) -#define TAIKO_A_VBAT_ADC_TEST (0x11B) -#define TAIKO_A_VBAT_ADC_TEST__POR (0x00) -#define TAIKO_A_VBAT_FE (0x11C) -#define TAIKO_A_VBAT_FE__POR (0x48) -#define TAIKO_A_VBAT_BIAS_1 (0x11D) -#define TAIKO_A_VBAT_BIAS_1__POR (0x03) -#define TAIKO_A_VBAT_BIAS_2 (0x11E) -#define TAIKO_A_VBAT_BIAS_2__POR (0x00) -#define TAIKO_A_VBAT_ADC_DATA_MSB (0x11F) -#define TAIKO_A_VBAT_ADC_DATA_MSB__POR (0x00) -#define TAIKO_A_VBAT_ADC_DATA_LSB (0x120) -#define TAIKO_A_VBAT_ADC_DATA_LSB__POR (0x00) -#define TAIKO_A_MICB_CFILT_1_CTL (0x128) -#define TAIKO_A_MICB_CFILT_1_CTL__POR (0x40) -#define TAIKO_A_MICB_CFILT_1_VAL (0x129) -#define TAIKO_A_MICB_CFILT_1_VAL__POR (0x80) -#define TAIKO_A_MICB_CFILT_1_PRECHRG (0x12A) -#define TAIKO_A_MICB_CFILT_1_PRECHRG__POR (0x38) -#define TAIKO_A_MICB_1_CTL (0x12B) -#define TAIKO_A_MICB_1_CTL__POR (0x16) -#define TAIKO_A_MICB_1_INT_RBIAS (0x12C) -#define TAIKO_A_MICB_1_INT_RBIAS__POR (0x24) -#define TAIKO_A_MICB_1_MBHC (0x12D) -#define TAIKO_A_MICB_1_MBHC__POR (0x01) -#define TAIKO_A_MICB_CFILT_2_CTL (0x12E) -#define TAIKO_A_MICB_CFILT_2_CTL__POR (0x40) -#define TAIKO_A_MICB_CFILT_2_VAL (0x12F) -#define TAIKO_A_MICB_CFILT_2_VAL__POR (0x80) -#define TAIKO_A_MICB_CFILT_2_PRECHRG (0x130) -#define TAIKO_A_MICB_CFILT_2_PRECHRG__POR (0x38) -#define TAIKO_A_MICB_2_CTL (0x131) -#define TAIKO_A_MICB_2_CTL__POR (0x16) -#define TAIKO_A_MICB_2_INT_RBIAS (0x132) -#define TAIKO_A_MICB_2_INT_RBIAS__POR (0x24) -#define TAIKO_A_MICB_2_MBHC (0x133) -#define TAIKO_A_MICB_2_MBHC__POR (0x02) -#define TAIKO_A_MICB_CFILT_3_CTL (0x134) -#define TAIKO_A_MICB_CFILT_3_CTL__POR (0x40) -#define TAIKO_A_MICB_CFILT_3_VAL (0x135) -#define TAIKO_A_MICB_CFILT_3_VAL__POR (0x80) -#define TAIKO_A_MICB_CFILT_3_PRECHRG (0x136) -#define TAIKO_A_MICB_CFILT_3_PRECHRG__POR (0x38) -#define TAIKO_A_MICB_3_CTL (0x137) -#define TAIKO_A_MICB_3_CTL__POR (0x16) -#define TAIKO_A_MICB_3_INT_RBIAS (0x138) -#define TAIKO_A_MICB_3_INT_RBIAS__POR (0x24) -#define TAIKO_A_MICB_3_MBHC (0x139) -#define TAIKO_A_MICB_3_MBHC__POR (0x00) -#define TAIKO_A_MICB_4_CTL (0x13D) -#define TAIKO_A_MICB_4_CTL__POR (0x16) -#define TAIKO_A_MICB_4_INT_RBIAS (0x13E) -#define TAIKO_A_MICB_4_INT_RBIAS__POR (0x24) -#define TAIKO_A_MICB_4_MBHC (0x13F) -#define TAIKO_A_MICB_4_MBHC__POR (0x01) -#define TAIKO_A_MBHC_INSERT_DETECT (0x14A) -#define TAIKO_A_MBHC_INSERT_DETECT__POR (0x00) -#define TAIKO_A_MBHC_INSERT_DET_STATUS (0x14B) -#define TAIKO_A_MBHC_INSERT_DET_STATUS__POR (0x00) -#define TAIKO_A_TX_COM_BIAS (0x14C) -#define TAIKO_A_TX_COM_BIAS__POR (0xF0) -#define TAIKO_A_MBHC_SCALING_MUX_1 (0x14E) -#define TAIKO_A_MBHC_SCALING_MUX_1__POR (0x00) -#define TAIKO_A_MBHC_SCALING_MUX_2 (0x14F) -#define TAIKO_A_MBHC_SCALING_MUX_2__POR (0x80) -#define TAIKO_A_MAD_ANA_CTRL (0x150) -#define TAIKO_A_MAD_ANA_CTRL__POR (0xF1) -#define TAIKO_A_TX_SUP_SWITCH_CTRL_1 (0x151) -#define TAIKO_A_TX_SUP_SWITCH_CTRL_1__POR (0x00) -#define TAIKO_A_TX_SUP_SWITCH_CTRL_2 (0x152) -#define TAIKO_A_TX_SUP_SWITCH_CTRL_2__POR (0x80) -#define TAIKO_A_TX_1_2_EN (0x153) -#define TAIKO_A_TX_1_2_EN__POR (0x00) -#define TAIKO_A_TX_1_2_TEST_EN (0x154) -#define TAIKO_A_TX_1_2_TEST_EN__POR (0xCC) -#define TAIKO_A_TX_1_2_ADC_CH1 (0x155) -#define TAIKO_A_TX_1_2_ADC_CH1__POR (0x44) -#define TAIKO_A_TX_1_2_ADC_CH2 (0x156) -#define TAIKO_A_TX_1_2_ADC_CH2__POR (0x44) -#define TAIKO_A_TX_1_2_ATEST_REFCTRL (0x157) -#define TAIKO_A_TX_1_2_ATEST_REFCTRL__POR (0x00) -#define TAIKO_A_TX_1_2_TEST_CTL (0x158) -#define TAIKO_A_TX_1_2_TEST_CTL__POR (0x38) -#define TAIKO_A_TX_1_2_TEST_BLOCK_EN (0x159) -#define TAIKO_A_TX_1_2_TEST_BLOCK_EN__POR (0xFC) -#define TAIKO_A_TX_1_2_TXFE_CLKDIV (0x15A) -#define TAIKO_A_TX_1_2_TXFE_CLKDIV__POR (0x55) -#define TAIKO_A_TX_1_2_SAR_ERR_CH1 (0x15B) -#define TAIKO_A_TX_1_2_SAR_ERR_CH1__POR (0x00) -#define TAIKO_A_TX_1_2_SAR_ERR_CH2 (0x15C) -#define TAIKO_A_TX_1_2_SAR_ERR_CH2__POR (0x00) -#define TAIKO_A_TX_3_4_EN (0x15D) -#define TAIKO_A_TX_3_4_EN__POR (0x00) -#define TAIKO_A_TX_3_4_TEST_EN (0x15E) -#define TAIKO_A_TX_3_4_TEST_EN__POR (0xCC) -#define TAIKO_A_TX_3_4_ADC_CH3 (0x15F) -#define TAIKO_A_TX_3_4_ADC_CH3__POR (0x44) -#define TAIKO_A_TX_3_4_ADC_CH4 (0x160) -#define TAIKO_A_TX_3_4_ADC_CH4__POR (0x44) -#define TAIKO_A_TX_3_4_ATEST_REFCTRL (0x161) -#define TAIKO_A_TX_3_4_ATEST_REFCTRL__POR (0x00) -#define TAIKO_A_TX_3_4_TEST_CTL (0x162) -#define TAIKO_A_TX_3_4_TEST_CTL__POR (0x38) -#define TAIKO_A_TX_3_4_TEST_BLOCK_EN (0x163) -#define TAIKO_A_TX_3_4_TEST_BLOCK_EN__POR (0xFC) -#define TAIKO_A_TX_3_4_TXFE_CKDIV (0x164) -#define TAIKO_A_TX_3_4_TXFE_CKDIV__POR (0x55) -#define TAIKO_A_TX_3_4_SAR_ERR_CH3 (0x165) -#define TAIKO_A_TX_3_4_SAR_ERR_CH3__POR (0x00) -#define TAIKO_A_TX_3_4_SAR_ERR_CH4 (0x166) -#define TAIKO_A_TX_3_4_SAR_ERR_CH4__POR (0x00) -#define TAIKO_A_TX_5_6_EN (0x167) -#define TAIKO_A_TX_5_6_EN__POR (0x11) -#define TAIKO_A_TX_5_6_TEST_EN (0x168) -#define TAIKO_A_TX_5_6_TEST_EN__POR (0xCC) -#define TAIKO_A_TX_5_6_ADC_CH5 (0x169) -#define TAIKO_A_TX_5_6_ADC_CH5__POR (0x44) -#define TAIKO_A_TX_5_6_ADC_CH6 (0x16A) -#define TAIKO_A_TX_5_6_ADC_CH6__POR (0x44) -#define TAIKO_A_TX_5_6_ATEST_REFCTRL (0x16B) -#define TAIKO_A_TX_5_6_ATEST_REFCTRL__POR (0x00) -#define TAIKO_A_TX_5_6_TEST_CTL (0x16C) -#define TAIKO_A_TX_5_6_TEST_CTL__POR (0x38) -#define TAIKO_A_TX_5_6_TEST_BLOCK_EN (0x16D) -#define TAIKO_A_TX_5_6_TEST_BLOCK_EN__POR (0xFC) -#define TAIKO_A_TX_5_6_TXFE_CKDIV (0x16E) -#define TAIKO_A_TX_5_6_TXFE_CKDIV__POR (0x55) -#define TAIKO_A_TX_5_6_SAR_ERR_CH5 (0x16F) -#define TAIKO_A_TX_5_6_SAR_ERR_CH5__POR (0x00) -#define TAIKO_A_TX_5_6_SAR_ERR_CH6 (0x170) -#define TAIKO_A_TX_5_6_SAR_ERR_CH6__POR (0x00) -#define TAIKO_A_TX_7_MBHC_EN (0x171) -#define TAIKO_A_TX_7_MBHC_EN__POR (0x0C) -#define TAIKO_A_TX_7_MBHC_ATEST_REFCTRL (0x172) -#define TAIKO_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00) -#define TAIKO_A_TX_7_MBHC_ADC (0x173) -#define TAIKO_A_TX_7_MBHC_ADC__POR (0x44) -#define TAIKO_A_TX_7_MBHC_TEST_CTL (0x174) -#define TAIKO_A_TX_7_MBHC_TEST_CTL__POR (0x38) -#define TAIKO_A_TX_7_MBHC_SAR_ERR (0x175) -#define TAIKO_A_TX_7_MBHC_SAR_ERR__POR (0x00) -#define TAIKO_A_TX_7_TXFE_CLKDIV (0x176) -#define TAIKO_A_TX_7_TXFE_CLKDIV__POR (0x0B) -#define TAIKO_A_BUCK_MODE_1 (0x181) -#define TAIKO_A_BUCK_MODE_1__POR (0x21) -#define TAIKO_A_BUCK_MODE_2 (0x182) -#define TAIKO_A_BUCK_MODE_2__POR (0xFF) -#define TAIKO_A_BUCK_MODE_3 (0x183) -#define TAIKO_A_BUCK_MODE_3__POR (0xCC) -#define TAIKO_A_BUCK_MODE_4 (0x184) -#define TAIKO_A_BUCK_MODE_4__POR (0x3A) -#define TAIKO_A_BUCK_MODE_5 (0x185) -#define TAIKO_A_BUCK_MODE_5__POR (0x00) -#define TAIKO_A_BUCK_CTRL_VCL_1 (0x186) -#define TAIKO_A_BUCK_CTRL_VCL_1__POR (0x48) -#define TAIKO_A_BUCK_CTRL_VCL_2 (0x187) -#define TAIKO_A_BUCK_CTRL_VCL_2__POR (0xA3) -#define TAIKO_A_BUCK_CTRL_VCL_3 (0x188) -#define TAIKO_A_BUCK_CTRL_VCL_3__POR (0x82) -#define TAIKO_A_BUCK_CTRL_CCL_1 (0x189) -#define TAIKO_A_BUCK_CTRL_CCL_1__POR (0xAB) -#define TAIKO_A_BUCK_CTRL_CCL_2 (0x18A) -#define TAIKO_A_BUCK_CTRL_CCL_2__POR (0xDC) -#define TAIKO_A_BUCK_CTRL_CCL_3 (0x18B) -#define TAIKO_A_BUCK_CTRL_CCL_3__POR (0x6A) -#define TAIKO_A_BUCK_CTRL_CCL_4 (0x18C) -#define TAIKO_A_BUCK_CTRL_CCL_4__POR (0x58) -#define TAIKO_A_BUCK_CTRL_PWM_DRVR_1 (0x18D) -#define TAIKO_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50) -#define TAIKO_A_BUCK_CTRL_PWM_DRVR_2 (0x18E) -#define TAIKO_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64) -#define TAIKO_A_BUCK_CTRL_PWM_DRVR_3 (0x18F) -#define TAIKO_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77) -#define TAIKO_A_BUCK_TMUX_A_D (0x190) -#define TAIKO_A_BUCK_TMUX_A_D__POR (0x00) -#define TAIKO_A_NCP_BUCKREF (0x191) -#define TAIKO_A_NCP_BUCKREF__POR (0x00) -#define TAIKO_A_NCP_EN (0x192) -#define TAIKO_A_NCP_EN__POR (0xFE) -#define TAIKO_A_NCP_CLK (0x193) -#define TAIKO_A_NCP_CLK__POR (0x94) -#define TAIKO_A_NCP_STATIC (0x194) -#define TAIKO_A_NCP_STATIC__POR (0x28) -#define TAIKO_A_NCP_VTH_LOW (0x195) -#define TAIKO_A_NCP_VTH_LOW__POR (0x88) -#define TAIKO_A_NCP_VTH_HIGH (0x196) -#define TAIKO_A_NCP_VTH_HIGH__POR (0xA0) -#define TAIKO_A_NCP_ATEST (0x197) -#define TAIKO_A_NCP_ATEST__POR (0x00) -#define TAIKO_A_NCP_DTEST (0x198) -#define TAIKO_A_NCP_DTEST__POR (0x00) -#define TAIKO_A_NCP_DLY1 (0x199) -#define TAIKO_A_NCP_DLY1__POR (0x06) -#define TAIKO_A_NCP_DLY2 (0x19A) -#define TAIKO_A_NCP_DLY2__POR (0x06) -#define TAIKO_A_RX_AUX_SW_CTL (0x19B) -#define TAIKO_A_RX_AUX_SW_CTL__POR (0x00) -#define TAIKO_A_RX_PA_AUX_IN_CONN (0x19C) -#define TAIKO_A_RX_PA_AUX_IN_CONN__POR (0x00) -#define TAIKO_A_RX_COM_TIMER_DIV (0x19E) -#define TAIKO_A_RX_COM_TIMER_DIV__POR (0xE8) -#define TAIKO_A_RX_COM_OCP_CTL (0x19F) -#define TAIKO_A_RX_COM_OCP_CTL__POR (0x1F) -#define TAIKO_A_RX_COM_OCP_COUNT (0x1A0) -#define TAIKO_A_RX_COM_OCP_COUNT__POR (0x77) -#define TAIKO_A_RX_COM_DAC_CTL (0x1A1) -#define TAIKO_A_RX_COM_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_COM_BIAS (0x1A2) -#define TAIKO_A_RX_COM_BIAS__POR (0x00) -#define TAIKO_A_RX_HPH_AUTO_CHOP (0x1A4) -#define TAIKO_A_RX_HPH_AUTO_CHOP__POR (0x38) -#define TAIKO_A_RX_HPH_CHOP_CTL (0x1A5) -#define TAIKO_A_RX_HPH_CHOP_CTL__POR (0xB4) -#define TAIKO_A_RX_HPH_BIAS_PA (0x1A6) -#define TAIKO_A_RX_HPH_BIAS_PA__POR (0xAA) -#define TAIKO_A_RX_HPH_BIAS_LDO (0x1A7) -#define TAIKO_A_RX_HPH_BIAS_LDO__POR (0x87) -#define TAIKO_A_RX_HPH_BIAS_CNP (0x1A8) -#define TAIKO_A_RX_HPH_BIAS_CNP__POR (0x8A) -#define TAIKO_A_RX_HPH_BIAS_WG_OCP (0x1A9) -#define TAIKO_A_RX_HPH_BIAS_WG_OCP__POR (0x2A) -#define TAIKO_A_RX_HPH_OCP_CTL (0x1AA) -#define TAIKO_A_RX_HPH_OCP_CTL__POR (0x68) -#define TAIKO_A_RX_HPH_CNP_EN (0x1AB) -#define TAIKO_A_RX_HPH_CNP_EN__POR (0x80) -#define TAIKO_A_RX_HPH_CNP_WG_CTL (0x1AC) -#define TAIKO_A_RX_HPH_CNP_WG_CTL__POR (0xDE) -#define TAIKO_A_RX_HPH_CNP_WG_TIME (0x1AD) -#define TAIKO_A_RX_HPH_CNP_WG_TIME__POR (0x2A) -#define TAIKO_A_RX_HPH_L_GAIN (0x1AE) -#define TAIKO_A_RX_HPH_L_GAIN__POR (0x00) -#define TAIKO_A_RX_HPH_L_TEST (0x1AF) -#define TAIKO_A_RX_HPH_L_TEST__POR (0x00) -#define TAIKO_A_RX_HPH_L_PA_CTL (0x1B0) -#define TAIKO_A_RX_HPH_L_PA_CTL__POR (0x40) -#define TAIKO_A_RX_HPH_L_DAC_CTL (0x1B1) -#define TAIKO_A_RX_HPH_L_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_HPH_L_ATEST (0x1B2) -#define TAIKO_A_RX_HPH_L_ATEST__POR (0x00) -#define TAIKO_A_RX_HPH_L_STATUS (0x1B3) -#define TAIKO_A_RX_HPH_L_STATUS__POR (0x00) -#define TAIKO_A_RX_HPH_R_GAIN (0x1B4) -#define TAIKO_A_RX_HPH_R_GAIN__POR (0x00) -#define TAIKO_A_RX_HPH_R_TEST (0x1B5) -#define TAIKO_A_RX_HPH_R_TEST__POR (0x00) -#define TAIKO_A_RX_HPH_R_PA_CTL (0x1B6) -#define TAIKO_A_RX_HPH_R_PA_CTL__POR (0x40) -#define TAIKO_A_RX_HPH_R_DAC_CTL (0x1B7) -#define TAIKO_A_RX_HPH_R_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_HPH_R_ATEST (0x1B8) -#define TAIKO_A_RX_HPH_R_ATEST__POR (0x00) -#define TAIKO_A_RX_HPH_R_STATUS (0x1B9) -#define TAIKO_A_RX_HPH_R_STATUS__POR (0x00) -#define TAIKO_A_RX_EAR_BIAS_PA (0x1BA) -#define TAIKO_A_RX_EAR_BIAS_PA__POR (0xA6) -#define TAIKO_A_RX_EAR_BIAS_CMBUFF (0x1BB) -#define TAIKO_A_RX_EAR_BIAS_CMBUFF__POR (0xA0) -#define TAIKO_A_RX_EAR_EN (0x1BC) -#define TAIKO_A_RX_EAR_EN__POR (0x00) -#define TAIKO_A_RX_EAR_GAIN (0x1BD) -#define TAIKO_A_RX_EAR_GAIN__POR (0x02) -#define TAIKO_A_RX_EAR_CMBUFF (0x1BE) -#define TAIKO_A_RX_EAR_CMBUFF__POR (0x04) -#define TAIKO_A_RX_EAR_ICTL (0x1BF) -#define TAIKO_A_RX_EAR_ICTL__POR (0x40) -#define TAIKO_A_RX_EAR_CCOMP (0x1C0) -#define TAIKO_A_RX_EAR_CCOMP__POR (0x08) -#define TAIKO_A_RX_EAR_VCM (0x1C1) -#define TAIKO_A_RX_EAR_VCM__POR (0x03) -#define TAIKO_A_RX_EAR_CNP (0x1C2) -#define TAIKO_A_RX_EAR_CNP__POR (0xF2) -#define TAIKO_A_RX_EAR_DAC_CTL_ATEST (0x1C3) -#define TAIKO_A_RX_EAR_DAC_CTL_ATEST__POR (0x00) -#define TAIKO_A_RX_EAR_STATUS (0x1C5) -#define TAIKO_A_RX_EAR_STATUS__POR (0x04) -#define TAIKO_A_RX_LINE_BIAS_PA (0x1C6) -#define TAIKO_A_RX_LINE_BIAS_PA__POR (0xA8) -#define TAIKO_A_RX_BUCK_BIAS1 (0x1C7) -#define TAIKO_A_RX_BUCK_BIAS1__POR (0x42) -#define TAIKO_A_RX_BUCK_BIAS2 (0x1C8) -#define TAIKO_A_RX_BUCK_BIAS2__POR (0x84) -#define TAIKO_A_RX_LINE_COM (0x1C9) -#define TAIKO_A_RX_LINE_COM__POR (0x80) -#define TAIKO_A_RX_LINE_CNP_EN (0x1CA) -#define TAIKO_A_RX_LINE_CNP_EN__POR (0x00) -#define TAIKO_A_RX_LINE_CNP_WG_CTL (0x1CB) -#define TAIKO_A_RX_LINE_CNP_WG_CTL__POR (0x00) -#define TAIKO_A_RX_LINE_CNP_WG_TIME (0x1CC) -#define TAIKO_A_RX_LINE_CNP_WG_TIME__POR (0x04) -#define TAIKO_A_RX_LINE_1_GAIN (0x1CD) -#define TAIKO_A_RX_LINE_1_GAIN__POR (0x00) -#define TAIKO_A_RX_LINE_1_TEST (0x1CE) -#define TAIKO_A_RX_LINE_1_TEST__POR (0x00) -#define TAIKO_A_RX_LINE_1_DAC_CTL (0x1CF) -#define TAIKO_A_RX_LINE_1_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_LINE_1_STATUS (0x1D0) -#define TAIKO_A_RX_LINE_1_STATUS__POR (0x00) -#define TAIKO_A_RX_LINE_2_GAIN (0x1D1) -#define TAIKO_A_RX_LINE_2_GAIN__POR (0x00) -#define TAIKO_A_RX_LINE_2_TEST (0x1D2) -#define TAIKO_A_RX_LINE_2_TEST__POR (0x00) -#define TAIKO_A_RX_LINE_2_DAC_CTL (0x1D3) -#define TAIKO_A_RX_LINE_2_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_LINE_2_STATUS (0x1D4) -#define TAIKO_A_RX_LINE_2_STATUS__POR (0x00) -#define TAIKO_A_RX_LINE_3_GAIN (0x1D5) -#define TAIKO_A_RX_LINE_3_GAIN__POR (0x00) -#define TAIKO_A_RX_LINE_3_TEST (0x1D6) -#define TAIKO_A_RX_LINE_3_TEST__POR (0x00) -#define TAIKO_A_RX_LINE_3_DAC_CTL (0x1D7) -#define TAIKO_A_RX_LINE_3_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_LINE_3_STATUS (0x1D8) -#define TAIKO_A_RX_LINE_3_STATUS__POR (0x00) -#define TAIKO_A_RX_LINE_4_GAIN (0x1D9) -#define TAIKO_A_RX_LINE_4_GAIN__POR (0x00) -#define TAIKO_A_RX_LINE_4_TEST (0x1DA) -#define TAIKO_A_RX_LINE_4_TEST__POR (0x00) -#define TAIKO_A_RX_LINE_4_DAC_CTL (0x1DB) -#define TAIKO_A_RX_LINE_4_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_LINE_4_STATUS (0x1DC) -#define TAIKO_A_RX_LINE_4_STATUS__POR (0x00) -#define TAIKO_A_RX_LINE_CNP_DBG (0x1DD) -#define TAIKO_A_RX_LINE_CNP_DBG__POR (0x00) -#define TAIKO_A_SPKR_DRV_EN (0x1DF) -#define TAIKO_A_SPKR_DRV_EN__POR (0x6F) -#define TAIKO_A_SPKR_DRV_GAIN (0x1E0) -#define TAIKO_A_SPKR_DRV_GAIN__POR (0x00) -#define TAIKO_A_SPKR_DRV_DAC_CTL (0x1E1) -#define TAIKO_A_SPKR_DRV_DAC_CTL__POR (0x04) -#define TAIKO_A_SPKR_DRV_OCP_CTL (0x1E2) -#define TAIKO_A_SPKR_DRV_OCP_CTL__POR (0x98) -#define TAIKO_A_SPKR_DRV_CLIP_DET (0x1E3) -#define TAIKO_A_SPKR_DRV_CLIP_DET__POR (0x48) -#define TAIKO_A_SPKR_DRV_IEC (0x1E4) -#define TAIKO_A_SPKR_DRV_IEC__POR (0x20) -#define TAIKO_A_SPKR_DRV_DBG_DAC (0x1E5) -#define TAIKO_A_SPKR_DRV_DBG_DAC__POR (0x05) -#define TAIKO_A_SPKR_DRV_DBG_PA (0x1E6) -#define TAIKO_A_SPKR_DRV_DBG_PA__POR (0x18) -#define TAIKO_A_SPKR_DRV_DBG_PWRSTG (0x1E7) -#define TAIKO_A_SPKR_DRV_DBG_PWRSTG__POR (0x00) -#define TAIKO_A_SPKR_DRV_BIAS_LDO (0x1E8) -#define TAIKO_A_SPKR_DRV_BIAS_LDO__POR (0x45) -#define TAIKO_A_SPKR_DRV_BIAS_INT (0x1E9) -#define TAIKO_A_SPKR_DRV_BIAS_INT__POR (0xA5) -#define TAIKO_A_SPKR_DRV_BIAS_PA (0x1EA) -#define TAIKO_A_SPKR_DRV_BIAS_PA__POR (0x55) -#define TAIKO_A_SPKR_DRV_STATUS_OCP (0x1EB) -#define TAIKO_A_SPKR_DRV_STATUS_OCP__POR (0x00) -#define TAIKO_A_SPKR_DRV_STATUS_PA (0x1EC) -#define TAIKO_A_SPKR_DRV_STATUS_PA__POR (0x00) -#define TAIKO_A_SPKR_PROT_EN (0x1ED) -#define TAIKO_A_SPKR_PROT_EN__POR (0x00) -#define TAIKO_A_SPKR_PROT_ADC_EN (0x1EE) -#define TAIKO_A_SPKR_PROT_ADC_EN__POR (0x44) -#define TAIKO_A_SPKR_PROT_ISENSE_BIAS (0x1EF) -#define TAIKO_A_SPKR_PROT_ISENSE_BIAS__POR (0x44) -#define TAIKO_A_SPKR_PROT_VSENSE_BIAS (0x1F0) -#define TAIKO_A_SPKR_PROT_VSENSE_BIAS__POR (0x44) -#define TAIKO_A_SPKR_PROT_ADC_ATEST_REFCTRL (0x1F1) -#define TAIKO_A_SPKR_PROT_ADC_ATEST_REFCTRL__POR (0x00) -#define TAIKO_A_SPKR_PROT_ADC_TEST_CTL (0x1F2) -#define TAIKO_A_SPKR_PROT_ADC_TEST_CTL__POR (0x38) -#define TAIKO_A_SPKR_PROT_TEST_BLOCK_EN (0x1F3) -#define TAIKO_A_SPKR_PROT_TEST_BLOCK_EN__POR (0xFC) -#define TAIKO_A_SPKR_PROT_ATEST (0x1F4) -#define TAIKO_A_SPKR_PROT_ATEST__POR (0x00) -#define TAIKO_A_SPKR_PROT_V_SAR_ERR (0x1F5) -#define TAIKO_A_SPKR_PROT_V_SAR_ERR__POR (0x00) -#define TAIKO_A_SPKR_PROT_I_SAR_ERR (0x1F6) -#define TAIKO_A_SPKR_PROT_I_SAR_ERR__POR (0x00) -#define TAIKO_A_SPKR_PROT_LDO_CTRL (0x1F7) -#define TAIKO_A_SPKR_PROT_LDO_CTRL__POR (0x00) -#define TAIKO_A_SPKR_PROT_ISENSE_CTRL (0x1F8) -#define TAIKO_A_SPKR_PROT_ISENSE_CTRL__POR (0x00) -#define TAIKO_A_SPKR_PROT_VSENSE_CTRL (0x1F9) -#define TAIKO_A_SPKR_PROT_VSENSE_CTRL__POR (0x00) -#define TAIKO_A_RC_OSC_FREQ (0x1FA) -#define TAIKO_A_RC_OSC_FREQ__POR (0x46) -#define TAIKO_A_RC_OSC_TEST (0x1FB) -#define TAIKO_A_RC_OSC_TEST__POR (0x0A) -#define TAIKO_A_RC_OSC_STATUS (0x1FC) -#define TAIKO_A_RC_OSC_STATUS__POR (0x18) -#define TAIKO_A_RC_OSC_TUNER (0x1FD) -#define TAIKO_A_RC_OSC_TUNER__POR (0x00) -#define TAIKO_A_MBHC_HPH (0x1FE) -#define TAIKO_A_MBHC_HPH__POR (0x44) -#define TAIKO_A_CDC_ANC1_B1_CTL (0x200) -#define TAIKO_A_CDC_ANC1_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_B1_CTL (0x280) -#define TAIKO_A_CDC_ANC2_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_SHIFT (0x201) -#define TAIKO_A_CDC_ANC1_SHIFT__POR (0x00) -#define TAIKO_A_CDC_ANC2_SHIFT (0x281) -#define TAIKO_A_CDC_ANC2_SHIFT__POR (0x00) -#define TAIKO_A_CDC_ANC1_IIR_B1_CTL (0x202) -#define TAIKO_A_CDC_ANC1_IIR_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_IIR_B1_CTL (0x282) -#define TAIKO_A_CDC_ANC2_IIR_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_IIR_B2_CTL (0x203) -#define TAIKO_A_CDC_ANC1_IIR_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_IIR_B2_CTL (0x283) -#define TAIKO_A_CDC_ANC2_IIR_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_IIR_B3_CTL (0x204) -#define TAIKO_A_CDC_ANC1_IIR_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_IIR_B3_CTL (0x284) -#define TAIKO_A_CDC_ANC2_IIR_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_LPF_B1_CTL (0x206) -#define TAIKO_A_CDC_ANC1_LPF_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_LPF_B1_CTL (0x286) -#define TAIKO_A_CDC_ANC2_LPF_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_LPF_B2_CTL (0x207) -#define TAIKO_A_CDC_ANC1_LPF_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_LPF_B2_CTL (0x287) -#define TAIKO_A_CDC_ANC2_LPF_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_SPARE (0x209) -#define TAIKO_A_CDC_ANC1_SPARE__POR (0x00) -#define TAIKO_A_CDC_ANC2_SPARE (0x289) -#define TAIKO_A_CDC_ANC2_SPARE__POR (0x00) -#define TAIKO_A_CDC_ANC1_SMLPF_CTL (0x20A) -#define TAIKO_A_CDC_ANC1_SMLPF_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_SMLPF_CTL (0x28A) -#define TAIKO_A_CDC_ANC2_SMLPF_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_DCFLT_CTL (0x20B) -#define TAIKO_A_CDC_ANC1_DCFLT_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_DCFLT_CTL (0x28B) -#define TAIKO_A_CDC_ANC2_DCFLT_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_GAIN_CTL (0x20C) -#define TAIKO_A_CDC_ANC1_GAIN_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_GAIN_CTL (0x28C) -#define TAIKO_A_CDC_ANC2_GAIN_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_B2_CTL (0x20D) -#define TAIKO_A_CDC_ANC1_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_B2_CTL (0x28D) -#define TAIKO_A_CDC_ANC2_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_TX1_VOL_CTL_TIMER (0x220) -#define TAIKO_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX2_VOL_CTL_TIMER (0x228) -#define TAIKO_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX3_VOL_CTL_TIMER (0x230) -#define TAIKO_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX4_VOL_CTL_TIMER (0x238) -#define TAIKO_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX5_VOL_CTL_TIMER (0x240) -#define TAIKO_A_CDC_TX5_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX6_VOL_CTL_TIMER (0x248) -#define TAIKO_A_CDC_TX6_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX7_VOL_CTL_TIMER (0x250) -#define TAIKO_A_CDC_TX7_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX8_VOL_CTL_TIMER (0x258) -#define TAIKO_A_CDC_TX8_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX9_VOL_CTL_TIMER (0x260) -#define TAIKO_A_CDC_TX9_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX10_VOL_CTL_TIMER (0x268) -#define TAIKO_A_CDC_TX10_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX1_VOL_CTL_GAIN (0x221) -#define TAIKO_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX2_VOL_CTL_GAIN (0x229) -#define TAIKO_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX3_VOL_CTL_GAIN (0x231) -#define TAIKO_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX4_VOL_CTL_GAIN (0x239) -#define TAIKO_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX5_VOL_CTL_GAIN (0x241) -#define TAIKO_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX6_VOL_CTL_GAIN (0x249) -#define TAIKO_A_CDC_TX6_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX7_VOL_CTL_GAIN (0x251) -#define TAIKO_A_CDC_TX7_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX8_VOL_CTL_GAIN (0x259) -#define TAIKO_A_CDC_TX8_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX9_VOL_CTL_GAIN (0x261) -#define TAIKO_A_CDC_TX9_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX10_VOL_CTL_GAIN (0x269) -#define TAIKO_A_CDC_TX10_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX1_VOL_CTL_CFG (0x222) -#define TAIKO_A_CDC_TX1_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX2_VOL_CTL_CFG (0x22A) -#define TAIKO_A_CDC_TX2_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX3_VOL_CTL_CFG (0x232) -#define TAIKO_A_CDC_TX3_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX4_VOL_CTL_CFG (0x23A) -#define TAIKO_A_CDC_TX4_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX5_VOL_CTL_CFG (0x242) -#define TAIKO_A_CDC_TX5_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX6_VOL_CTL_CFG (0x24A) -#define TAIKO_A_CDC_TX6_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX7_VOL_CTL_CFG (0x252) -#define TAIKO_A_CDC_TX7_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX8_VOL_CTL_CFG (0x25A) -#define TAIKO_A_CDC_TX8_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX9_VOL_CTL_CFG (0x262) -#define TAIKO_A_CDC_TX9_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX10_VOL_CTL_CFG (0x26A) -#define TAIKO_A_CDC_TX10_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX1_MUX_CTL (0x223) -#define TAIKO_A_CDC_TX1_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX2_MUX_CTL (0x22B) -#define TAIKO_A_CDC_TX2_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX3_MUX_CTL (0x233) -#define TAIKO_A_CDC_TX3_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX4_MUX_CTL (0x23B) -#define TAIKO_A_CDC_TX4_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX5_MUX_CTL (0x243) -#define TAIKO_A_CDC_TX5_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX6_MUX_CTL (0x24B) -#define TAIKO_A_CDC_TX6_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX7_MUX_CTL (0x253) -#define TAIKO_A_CDC_TX7_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX8_MUX_CTL (0x25B) -#define TAIKO_A_CDC_TX8_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX9_MUX_CTL (0x263) -#define TAIKO_A_CDC_TX9_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX10_MUX_CTL (0x26B) -#define TAIKO_A_CDC_TX10_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX1_CLK_FS_CTL (0x224) -#define TAIKO_A_CDC_TX1_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX2_CLK_FS_CTL (0x22C) -#define TAIKO_A_CDC_TX2_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX3_CLK_FS_CTL (0x234) -#define TAIKO_A_CDC_TX3_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX4_CLK_FS_CTL (0x23C) -#define TAIKO_A_CDC_TX4_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX5_CLK_FS_CTL (0x244) -#define TAIKO_A_CDC_TX5_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX6_CLK_FS_CTL (0x24C) -#define TAIKO_A_CDC_TX6_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX7_CLK_FS_CTL (0x254) -#define TAIKO_A_CDC_TX7_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX8_CLK_FS_CTL (0x25C) -#define TAIKO_A_CDC_TX8_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX9_CLK_FS_CTL (0x264) -#define TAIKO_A_CDC_TX9_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX10_CLK_FS_CTL (0x26C) -#define TAIKO_A_CDC_TX10_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX1_DMIC_CTL (0x225) -#define TAIKO_A_CDC_TX1_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX2_DMIC_CTL (0x22D) -#define TAIKO_A_CDC_TX2_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX3_DMIC_CTL (0x235) -#define TAIKO_A_CDC_TX3_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX4_DMIC_CTL (0x23D) -#define TAIKO_A_CDC_TX4_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX5_DMIC_CTL (0x245) -#define TAIKO_A_CDC_TX5_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX6_DMIC_CTL (0x24D) -#define TAIKO_A_CDC_TX6_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX7_DMIC_CTL (0x255) -#define TAIKO_A_CDC_TX7_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX8_DMIC_CTL (0x25D) -#define TAIKO_A_CDC_TX8_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX9_DMIC_CTL (0x265) -#define TAIKO_A_CDC_TX9_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX10_DMIC_CTL (0x26D) -#define TAIKO_A_CDC_TX10_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B1_CTL (0x278) -#define TAIKO_A_CDC_DEBUG_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B2_CTL (0x279) -#define TAIKO_A_CDC_DEBUG_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B3_CTL (0x27A) -#define TAIKO_A_CDC_DEBUG_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B4_CTL (0x27B) -#define TAIKO_A_CDC_DEBUG_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B5_CTL (0x27C) -#define TAIKO_A_CDC_DEBUG_B5_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B6_CTL (0x27D) -#define TAIKO_A_CDC_DEBUG_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B7_CTL (0x27E) -#define TAIKO_A_CDC_DEBUG_B7_CTL__POR (0x00) -#define TAIKO_A_CDC_SRC1_PDA_CFG (0x2A0) -#define TAIKO_A_CDC_SRC1_PDA_CFG__POR (0x00) -#define TAIKO_A_CDC_SRC2_PDA_CFG (0x2A8) -#define TAIKO_A_CDC_SRC2_PDA_CFG__POR (0x00) -#define TAIKO_A_CDC_SRC1_FS_CTL (0x2A1) -#define TAIKO_A_CDC_SRC1_FS_CTL__POR (0x1B) -#define TAIKO_A_CDC_SRC2_FS_CTL (0x2A9) -#define TAIKO_A_CDC_SRC2_FS_CTL__POR (0x1B) -#define TAIKO_A_CDC_RX1_B1_CTL (0x2B0) -#define TAIKO_A_CDC_RX1_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX2_B1_CTL (0x2B8) -#define TAIKO_A_CDC_RX2_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX3_B1_CTL (0x2C0) -#define TAIKO_A_CDC_RX3_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX4_B1_CTL (0x2C8) -#define TAIKO_A_CDC_RX4_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX5_B1_CTL (0x2D0) -#define TAIKO_A_CDC_RX5_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX6_B1_CTL (0x2D8) -#define TAIKO_A_CDC_RX6_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX7_B1_CTL (0x2E0) -#define TAIKO_A_CDC_RX7_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX1_B2_CTL (0x2B1) -#define TAIKO_A_CDC_RX1_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX2_B2_CTL (0x2B9) -#define TAIKO_A_CDC_RX2_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX3_B2_CTL (0x2C1) -#define TAIKO_A_CDC_RX3_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX4_B2_CTL (0x2C9) -#define TAIKO_A_CDC_RX4_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX5_B2_CTL (0x2D1) -#define TAIKO_A_CDC_RX5_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX6_B2_CTL (0x2D9) -#define TAIKO_A_CDC_RX6_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX7_B2_CTL (0x2E1) -#define TAIKO_A_CDC_RX7_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX1_B3_CTL (0x2B2) -#define TAIKO_A_CDC_RX1_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX2_B3_CTL (0x2BA) -#define TAIKO_A_CDC_RX2_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX3_B3_CTL (0x2C2) -#define TAIKO_A_CDC_RX3_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX4_B3_CTL (0x2CA) -#define TAIKO_A_CDC_RX4_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX5_B3_CTL (0x2D2) -#define TAIKO_A_CDC_RX5_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX6_B3_CTL (0x2DA) -#define TAIKO_A_CDC_RX6_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX7_B3_CTL (0x2E2) -#define TAIKO_A_CDC_RX7_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX1_B4_CTL (0x2B3) -#define TAIKO_A_CDC_RX1_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX2_B4_CTL (0x2BB) -#define TAIKO_A_CDC_RX2_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX3_B4_CTL (0x2C3) -#define TAIKO_A_CDC_RX3_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX4_B4_CTL (0x2CB) -#define TAIKO_A_CDC_RX4_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX5_B4_CTL (0x2D3) -#define TAIKO_A_CDC_RX5_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX6_B4_CTL (0x2DB) -#define TAIKO_A_CDC_RX6_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX7_B4_CTL (0x2E3) -#define TAIKO_A_CDC_RX7_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX1_B5_CTL (0x2B4) -#define TAIKO_A_CDC_RX1_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX2_B5_CTL (0x2BC) -#define TAIKO_A_CDC_RX2_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX3_B5_CTL (0x2C4) -#define TAIKO_A_CDC_RX3_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX4_B5_CTL (0x2CC) -#define TAIKO_A_CDC_RX4_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX5_B5_CTL (0x2D4) -#define TAIKO_A_CDC_RX5_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX6_B5_CTL (0x2DC) -#define TAIKO_A_CDC_RX6_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX7_B5_CTL (0x2E4) -#define TAIKO_A_CDC_RX7_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX1_B6_CTL (0x2B5) -#define TAIKO_A_CDC_RX1_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX2_B6_CTL (0x2BD) -#define TAIKO_A_CDC_RX2_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX3_B6_CTL (0x2C5) -#define TAIKO_A_CDC_RX3_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX4_B6_CTL (0x2CD) -#define TAIKO_A_CDC_RX4_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX5_B6_CTL (0x2D5) -#define TAIKO_A_CDC_RX5_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX6_B6_CTL (0x2DD) -#define TAIKO_A_CDC_RX6_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX7_B6_CTL (0x2E5) -#define TAIKO_A_CDC_RX7_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX1_VOL_CTL_B1_CTL (0x2B6) -#define TAIKO_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX2_VOL_CTL_B1_CTL (0x2BE) -#define TAIKO_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX3_VOL_CTL_B1_CTL (0x2C6) -#define TAIKO_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX4_VOL_CTL_B1_CTL (0x2CE) -#define TAIKO_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX5_VOL_CTL_B1_CTL (0x2D6) -#define TAIKO_A_CDC_RX5_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX6_VOL_CTL_B1_CTL (0x2DE) -#define TAIKO_A_CDC_RX6_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX7_VOL_CTL_B1_CTL (0x2E6) -#define TAIKO_A_CDC_RX7_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL (0x2B7) -#define TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL (0x2BF) -#define TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL (0x2C7) -#define TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL (0x2CF) -#define TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL (0x2D7) -#define TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL (0x2DF) -#define TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL (0x2E7) -#define TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_VBAT_CFG (0x2E8) -#define TAIKO_A_CDC_VBAT_CFG__POR (0x1A) -#define TAIKO_A_CDC_VBAT_ADC_CAL1 (0x2E9) -#define TAIKO_A_CDC_VBAT_ADC_CAL1__POR (0x00) -#define TAIKO_A_CDC_VBAT_ADC_CAL2 (0x2EA) -#define TAIKO_A_CDC_VBAT_ADC_CAL2__POR (0x00) -#define TAIKO_A_CDC_VBAT_ADC_CAL3 (0x2EB) -#define TAIKO_A_CDC_VBAT_ADC_CAL3__POR (0x04) -#define TAIKO_A_CDC_VBAT_PK_EST1 (0x2EC) -#define TAIKO_A_CDC_VBAT_PK_EST1__POR (0xE0) -#define TAIKO_A_CDC_VBAT_PK_EST2 (0x2ED) -#define TAIKO_A_CDC_VBAT_PK_EST2__POR (0x01) -#define TAIKO_A_CDC_VBAT_PK_EST3 (0x2EE) -#define TAIKO_A_CDC_VBAT_PK_EST3__POR (0x40) -#define TAIKO_A_CDC_VBAT_RF_PROC1 (0x2EF) -#define TAIKO_A_CDC_VBAT_RF_PROC1__POR (0x2A) -#define TAIKO_A_CDC_VBAT_RF_PROC2 (0x2F0) -#define TAIKO_A_CDC_VBAT_RF_PROC2__POR (0x86) -#define TAIKO_A_CDC_VBAT_TAC1 (0x2F1) -#define TAIKO_A_CDC_VBAT_TAC1__POR (0x70) -#define TAIKO_A_CDC_VBAT_TAC2 (0x2F2) -#define TAIKO_A_CDC_VBAT_TAC2__POR (0x18) -#define TAIKO_A_CDC_VBAT_TAC3 (0x2F3) -#define TAIKO_A_CDC_VBAT_TAC3__POR (0x18) -#define TAIKO_A_CDC_VBAT_TAC4 (0x2F4) -#define TAIKO_A_CDC_VBAT_TAC4__POR (0x03) -#define TAIKO_A_CDC_VBAT_GAIN_UPD1 (0x2F5) -#define TAIKO_A_CDC_VBAT_GAIN_UPD1__POR (0x01) -#define TAIKO_A_CDC_VBAT_GAIN_UPD2 (0x2F6) -#define TAIKO_A_CDC_VBAT_GAIN_UPD2__POR (0x00) -#define TAIKO_A_CDC_VBAT_GAIN_UPD3 (0x2F7) -#define TAIKO_A_CDC_VBAT_GAIN_UPD3__POR (0x64) -#define TAIKO_A_CDC_VBAT_GAIN_UPD4 (0x2F8) -#define TAIKO_A_CDC_VBAT_GAIN_UPD4__POR (0x01) -#define TAIKO_A_CDC_VBAT_DEBUG1 (0x2F9) -#define TAIKO_A_CDC_VBAT_DEBUG1__POR (0x00) -#define TAIKO_A_CDC_CLK_ANC_RESET_CTL (0x300) -#define TAIKO_A_CDC_CLK_ANC_RESET_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_RX_RESET_CTL (0x301) -#define TAIKO_A_CDC_CLK_RX_RESET_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_TX_RESET_B1_CTL (0x302) -#define TAIKO_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_TX_RESET_B2_CTL (0x303) -#define TAIKO_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_DMIC_B1_CTL (0x304) -#define TAIKO_A_CDC_CLK_DMIC_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_DMIC_B2_CTL (0x305) -#define TAIKO_A_CDC_CLK_DMIC_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_RX_I2S_CTL (0x306) -#define TAIKO_A_CDC_CLK_RX_I2S_CTL__POR (0x03) -#define TAIKO_A_CDC_CLK_TX_I2S_CTL (0x307) -#define TAIKO_A_CDC_CLK_TX_I2S_CTL__POR (0x03) -#define TAIKO_A_CDC_CLK_OTHR_RESET_B1_CTL (0x308) -#define TAIKO_A_CDC_CLK_OTHR_RESET_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL (0x309) -#define TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x30A) -#define TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x30B) -#define TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_OTHR_CTL (0x30C) -#define TAIKO_A_CDC_CLK_OTHR_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL (0x30D) -#define TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_ANC_CLK_EN_CTL (0x30E) -#define TAIKO_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_RX_B1_CTL (0x30F) -#define TAIKO_A_CDC_CLK_RX_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_RX_B2_CTL (0x310) -#define TAIKO_A_CDC_CLK_RX_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_MCLK_CTL (0x311) -#define TAIKO_A_CDC_CLK_MCLK_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_PDM_CTL (0x312) -#define TAIKO_A_CDC_CLK_PDM_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_SD_CTL (0x313) -#define TAIKO_A_CDC_CLK_SD_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_POWER_CTL (0x314) -#define TAIKO_A_CDC_CLK_POWER_CTL__POR (0x00) -#define TAIKO_A_CDC_CLSH_B1_CTL (0x320) -#define TAIKO_A_CDC_CLSH_B1_CTL__POR (0xE4) -#define TAIKO_A_CDC_CLSH_B2_CTL (0x321) -#define TAIKO_A_CDC_CLSH_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CLSH_B3_CTL (0x322) -#define TAIKO_A_CDC_CLSH_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CLSH_BUCK_NCP_VARS (0x323) -#define TAIKO_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00) -#define TAIKO_A_CDC_CLSH_IDLE_HPH_THSD (0x324) -#define TAIKO_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12) -#define TAIKO_A_CDC_CLSH_IDLE_EAR_THSD (0x325) -#define TAIKO_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C) -#define TAIKO_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326) -#define TAIKO_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18) -#define TAIKO_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327) -#define TAIKO_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23) -#define TAIKO_A_CDC_CLSH_K_ADDR (0x328) -#define TAIKO_A_CDC_CLSH_K_ADDR__POR (0x00) -#define TAIKO_A_CDC_CLSH_K_DATA (0x329) -#define TAIKO_A_CDC_CLSH_K_DATA__POR (0xA4) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09) -#define TAIKO_A_CDC_CLSH_V_PA_HD_EAR (0x32E) -#define TAIKO_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00) -#define TAIKO_A_CDC_CLSH_V_PA_HD_HPH (0x32F) -#define TAIKO_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00) -#define TAIKO_A_CDC_CLSH_V_PA_MIN_EAR (0x330) -#define TAIKO_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00) -#define TAIKO_A_CDC_CLSH_V_PA_MIN_HPH (0x331) -#define TAIKO_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B1_CTL (0x340) -#define TAIKO_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B1_CTL (0x350) -#define TAIKO_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B2_CTL (0x341) -#define TAIKO_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B2_CTL (0x351) -#define TAIKO_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B3_CTL (0x342) -#define TAIKO_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B3_CTL (0x352) -#define TAIKO_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B4_CTL (0x343) -#define TAIKO_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B4_CTL (0x353) -#define TAIKO_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B5_CTL (0x344) -#define TAIKO_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B5_CTL (0x354) -#define TAIKO_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B6_CTL (0x345) -#define TAIKO_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B6_CTL (0x355) -#define TAIKO_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B7_CTL (0x346) -#define TAIKO_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B7_CTL (0x356) -#define TAIKO_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B8_CTL (0x347) -#define TAIKO_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B8_CTL (0x357) -#define TAIKO_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_CTL (0x348) -#define TAIKO_A_CDC_IIR1_CTL__POR (0x40) -#define TAIKO_A_CDC_IIR2_CTL (0x358) -#define TAIKO_A_CDC_IIR2_CTL__POR (0x40) -#define TAIKO_A_CDC_IIR1_GAIN_TIMER_CTL (0x349) -#define TAIKO_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_TIMER_CTL (0x359) -#define TAIKO_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_COEF_B1_CTL (0x34A) -#define TAIKO_A_CDC_IIR1_COEF_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_COEF_B1_CTL (0x35A) -#define TAIKO_A_CDC_IIR2_COEF_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_COEF_B2_CTL (0x34B) -#define TAIKO_A_CDC_IIR1_COEF_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_COEF_B2_CTL (0x35B) -#define TAIKO_A_CDC_IIR2_COEF_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_TOP_GAIN_UPDATE (0x360) -#define TAIKO_A_CDC_TOP_GAIN_UPDATE__POR (0x00) -#define TAIKO_A_CDC_COMP0_B1_CTL (0x368) -#define TAIKO_A_CDC_COMP0_B1_CTL__POR (0x30) -#define TAIKO_A_CDC_COMP1_B1_CTL (0x370) -#define TAIKO_A_CDC_COMP1_B1_CTL__POR (0x30) -#define TAIKO_A_CDC_COMP2_B1_CTL (0x378) -#define TAIKO_A_CDC_COMP2_B1_CTL__POR (0x30) -#define TAIKO_A_CDC_COMP0_B2_CTL (0x369) -#define TAIKO_A_CDC_COMP0_B2_CTL__POR (0xB5) -#define TAIKO_A_CDC_COMP1_B2_CTL (0x371) -#define TAIKO_A_CDC_COMP1_B2_CTL__POR (0xB5) -#define TAIKO_A_CDC_COMP2_B2_CTL (0x379) -#define TAIKO_A_CDC_COMP2_B2_CTL__POR (0xB5) -#define TAIKO_A_CDC_COMP0_B3_CTL (0x36A) -#define TAIKO_A_CDC_COMP0_B3_CTL__POR (0x28) -#define TAIKO_A_CDC_COMP1_B3_CTL (0x372) -#define TAIKO_A_CDC_COMP1_B3_CTL__POR (0x28) -#define TAIKO_A_CDC_COMP2_B3_CTL (0x37A) -#define TAIKO_A_CDC_COMP2_B3_CTL__POR (0x28) -#define TAIKO_A_CDC_COMP0_B4_CTL (0x36B) -#define TAIKO_A_CDC_COMP0_B4_CTL__POR (0x3C) -#define TAIKO_A_CDC_COMP1_B4_CTL (0x373) -#define TAIKO_A_CDC_COMP1_B4_CTL__POR (0x3C) -#define TAIKO_A_CDC_COMP2_B4_CTL (0x37B) -#define TAIKO_A_CDC_COMP2_B4_CTL__POR (0x3C) -#define TAIKO_A_CDC_COMP0_B5_CTL (0x36C) -#define TAIKO_A_CDC_COMP0_B5_CTL__POR (0x1F) -#define TAIKO_A_CDC_COMP1_B5_CTL (0x374) -#define TAIKO_A_CDC_COMP1_B5_CTL__POR (0x1F) -#define TAIKO_A_CDC_COMP2_B5_CTL (0x37C) -#define TAIKO_A_CDC_COMP2_B5_CTL__POR (0x1F) -#define TAIKO_A_CDC_COMP0_B6_CTL (0x36D) -#define TAIKO_A_CDC_COMP0_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_COMP1_B6_CTL (0x375) -#define TAIKO_A_CDC_COMP1_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_COMP2_B6_CTL (0x37D) -#define TAIKO_A_CDC_COMP2_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_COMP0_SHUT_DOWN_STATUS (0x36E) -#define TAIKO_A_CDC_COMP0_SHUT_DOWN_STATUS__POR (0x03) -#define TAIKO_A_CDC_COMP1_SHUT_DOWN_STATUS (0x376) -#define TAIKO_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x03) -#define TAIKO_A_CDC_COMP2_SHUT_DOWN_STATUS (0x37E) -#define TAIKO_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x03) -#define TAIKO_A_CDC_COMP0_FS_CFG (0x36F) -#define TAIKO_A_CDC_COMP0_FS_CFG__POR (0x03) -#define TAIKO_A_CDC_COMP1_FS_CFG (0x377) -#define TAIKO_A_CDC_COMP1_FS_CFG__POR (0x03) -#define TAIKO_A_CDC_COMP2_FS_CFG (0x37F) -#define TAIKO_A_CDC_COMP2_FS_CFG__POR (0x03) -#define TAIKO_A_CDC_CONN_RX1_B1_CTL (0x380) -#define TAIKO_A_CDC_CONN_RX1_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX1_B2_CTL (0x381) -#define TAIKO_A_CDC_CONN_RX1_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX1_B3_CTL (0x382) -#define TAIKO_A_CDC_CONN_RX1_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX2_B1_CTL (0x383) -#define TAIKO_A_CDC_CONN_RX2_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX2_B2_CTL (0x384) -#define TAIKO_A_CDC_CONN_RX2_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX2_B3_CTL (0x385) -#define TAIKO_A_CDC_CONN_RX2_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX3_B1_CTL (0x386) -#define TAIKO_A_CDC_CONN_RX3_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX3_B2_CTL (0x387) -#define TAIKO_A_CDC_CONN_RX3_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX4_B1_CTL (0x388) -#define TAIKO_A_CDC_CONN_RX4_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX4_B2_CTL (0x389) -#define TAIKO_A_CDC_CONN_RX4_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX5_B1_CTL (0x38A) -#define TAIKO_A_CDC_CONN_RX5_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX5_B2_CTL (0x38B) -#define TAIKO_A_CDC_CONN_RX5_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX6_B1_CTL (0x38C) -#define TAIKO_A_CDC_CONN_RX6_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX6_B2_CTL (0x38D) -#define TAIKO_A_CDC_CONN_RX6_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX7_B1_CTL (0x38E) -#define TAIKO_A_CDC_CONN_RX7_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX7_B2_CTL (0x38F) -#define TAIKO_A_CDC_CONN_RX7_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX7_B3_CTL (0x390) -#define TAIKO_A_CDC_CONN_RX7_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_ANC_B1_CTL (0x391) -#define TAIKO_A_CDC_CONN_ANC_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_ANC_B2_CTL (0x392) -#define TAIKO_A_CDC_CONN_ANC_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_B1_CTL (0x393) -#define TAIKO_A_CDC_CONN_TX_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_B2_CTL (0x394) -#define TAIKO_A_CDC_CONN_TX_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_B3_CTL (0x395) -#define TAIKO_A_CDC_CONN_TX_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_B4_CTL (0x396) -#define TAIKO_A_CDC_CONN_TX_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ1_B1_CTL (0x397) -#define TAIKO_A_CDC_CONN_EQ1_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ1_B2_CTL (0x398) -#define TAIKO_A_CDC_CONN_EQ1_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ1_B3_CTL (0x399) -#define TAIKO_A_CDC_CONN_EQ1_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ1_B4_CTL (0x39A) -#define TAIKO_A_CDC_CONN_EQ1_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ2_B1_CTL (0x39B) -#define TAIKO_A_CDC_CONN_EQ2_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ2_B2_CTL (0x39C) -#define TAIKO_A_CDC_CONN_EQ2_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ2_B3_CTL (0x39D) -#define TAIKO_A_CDC_CONN_EQ2_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ2_B4_CTL (0x39E) -#define TAIKO_A_CDC_CONN_EQ2_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_SRC1_B1_CTL (0x39F) -#define TAIKO_A_CDC_CONN_SRC1_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_SRC1_B2_CTL (0x3A0) -#define TAIKO_A_CDC_CONN_SRC1_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_SRC2_B1_CTL (0x3A1) -#define TAIKO_A_CDC_CONN_SRC2_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_SRC2_B2_CTL (0x3A2) -#define TAIKO_A_CDC_CONN_SRC2_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B1_CTL (0x3A3) -#define TAIKO_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B2_CTL (0x3A4) -#define TAIKO_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B3_CTL (0x3A5) -#define TAIKO_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B4_CTL (0x3A6) -#define TAIKO_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B5_CTL (0x3A7) -#define TAIKO_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B6_CTL (0x3A8) -#define TAIKO_A_CDC_CONN_TX_SB_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B7_CTL (0x3A9) -#define TAIKO_A_CDC_CONN_TX_SB_B7_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B8_CTL (0x3AA) -#define TAIKO_A_CDC_CONN_TX_SB_B8_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B9_CTL (0x3AB) -#define TAIKO_A_CDC_CONN_TX_SB_B9_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B10_CTL (0x3AC) -#define TAIKO_A_CDC_CONN_TX_SB_B10_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B11_CTL (0x3AD) -#define TAIKO_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX_SB_B1_CTL (0x3AE) -#define TAIKO_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX_SB_B2_CTL (0x3AF) -#define TAIKO_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_CLSH_CTL (0x3B0) -#define TAIKO_A_CDC_CONN_CLSH_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_MISC (0x3B1) -#define TAIKO_A_CDC_CONN_MISC__POR (0x01) -#define TAIKO_A_CDC_CONN_MAD (0x3B2) -#define TAIKO_A_CDC_CONN_MAD__POR (0x01) -#define TAIKO_A_CDC_MBHC_EN_CTL (0x3C0) -#define TAIKO_A_CDC_MBHC_EN_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_FIR_B1_CFG (0x3C1) -#define TAIKO_A_CDC_MBHC_FIR_B1_CFG__POR (0x00) -#define TAIKO_A_CDC_MBHC_FIR_B2_CFG (0x3C2) -#define TAIKO_A_CDC_MBHC_FIR_B2_CFG__POR (0x06) -#define TAIKO_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) -#define TAIKO_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03) -#define TAIKO_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) -#define TAIKO_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09) -#define TAIKO_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) -#define TAIKO_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E) -#define TAIKO_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) -#define TAIKO_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45) -#define TAIKO_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) -#define TAIKO_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04) -#define TAIKO_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) -#define TAIKO_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78) -#define TAIKO_A_CDC_MBHC_B1_STATUS (0x3C9) -#define TAIKO_A_CDC_MBHC_B1_STATUS__POR (0x00) -#define TAIKO_A_CDC_MBHC_B2_STATUS (0x3CA) -#define TAIKO_A_CDC_MBHC_B2_STATUS__POR (0x00) -#define TAIKO_A_CDC_MBHC_B3_STATUS (0x3CB) -#define TAIKO_A_CDC_MBHC_B3_STATUS__POR (0x00) -#define TAIKO_A_CDC_MBHC_B4_STATUS (0x3CC) -#define TAIKO_A_CDC_MBHC_B4_STATUS__POR (0x00) -#define TAIKO_A_CDC_MBHC_B5_STATUS (0x3CD) -#define TAIKO_A_CDC_MBHC_B5_STATUS__POR (0x00) -#define TAIKO_A_CDC_MBHC_B1_CTL (0x3CE) -#define TAIKO_A_CDC_MBHC_B1_CTL__POR (0xC0) -#define TAIKO_A_CDC_MBHC_B2_CTL (0x3CF) -#define TAIKO_A_CDC_MBHC_B2_CTL__POR (0x5D) -#define TAIKO_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) -#define TAIKO_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) -#define TAIKO_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) -#define TAIKO_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) -#define TAIKO_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) -#define TAIKO_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) -#define TAIKO_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) -#define TAIKO_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF) -#define TAIKO_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) -#define TAIKO_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07) -#define TAIKO_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) -#define TAIKO_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF) -#define TAIKO_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) -#define TAIKO_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F) -#define TAIKO_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) -#define TAIKO_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) -#define TAIKO_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80) -#define TAIKO_A_CDC_MBHC_CLK_CTL (0x3DC) -#define TAIKO_A_CDC_MBHC_CLK_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_INT_CTL (0x3DD) -#define TAIKO_A_CDC_MBHC_INT_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_DEBUG_CTL (0x3DE) -#define TAIKO_A_CDC_MBHC_DEBUG_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_SPARE (0x3DF) -#define TAIKO_A_CDC_MBHC_SPARE__POR (0x00) -#define TAIKO_A_CDC_MAD_MAIN_CTL_1 (0x3E0) -#define TAIKO_A_CDC_MAD_MAIN_CTL_1__POR (0x00) -#define TAIKO_A_CDC_MAD_MAIN_CTL_2 (0x3E1) -#define TAIKO_A_CDC_MAD_MAIN_CTL_2__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_1 (0x3E2) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_1__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_2 (0x3E3) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_2__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_3 (0x3E4) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_3__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_4 (0x3E5) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_4__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_5 (0x3E6) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_5__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_6 (0x3E7) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_6__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_7 (0x3E8) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_7__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_8 (0x3E9) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_8__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_PTR (0x3EA) -#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_PTR__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_VAL (0x3EB) -#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_VAL__POR (0x40) -#define TAIKO_A_CDC_MAD_ULTR_CTL_1 (0x3EC) -#define TAIKO_A_CDC_MAD_ULTR_CTL_1__POR (0x00) -#define TAIKO_A_CDC_MAD_ULTR_CTL_2 (0x3ED) -#define TAIKO_A_CDC_MAD_ULTR_CTL_2__POR (0x00) -#define TAIKO_A_CDC_MAD_ULTR_CTL_3 (0x3EE) -#define TAIKO_A_CDC_MAD_ULTR_CTL_3__POR (0x00) -#define TAIKO_A_CDC_MAD_ULTR_CTL_4 (0x3EF) -#define TAIKO_A_CDC_MAD_ULTR_CTL_4__POR (0x00) -#define TAIKO_A_CDC_MAD_ULTR_CTL_5 (0x3F0) -#define TAIKO_A_CDC_MAD_ULTR_CTL_5__POR (0x00) -#define TAIKO_A_CDC_MAD_ULTR_CTL_6 (0x3F1) -#define TAIKO_A_CDC_MAD_ULTR_CTL_6__POR (0x00) -#define TAIKO_A_CDC_MAD_ULTR_CTL_7 (0x3F2) -#define TAIKO_A_CDC_MAD_ULTR_CTL_7__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_1 (0x3F3) -#define TAIKO_A_CDC_MAD_BEACON_CTL_1__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_2 (0x3F4) -#define TAIKO_A_CDC_MAD_BEACON_CTL_2__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_3 (0x3F5) -#define TAIKO_A_CDC_MAD_BEACON_CTL_3__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_4 (0x3F6) -#define TAIKO_A_CDC_MAD_BEACON_CTL_4__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_5 (0x3F7) -#define TAIKO_A_CDC_MAD_BEACON_CTL_5__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_6 (0x3F8) -#define TAIKO_A_CDC_MAD_BEACON_CTL_6__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_7 (0x3F9) -#define TAIKO_A_CDC_MAD_BEACON_CTL_7__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_8 (0x3FA) -#define TAIKO_A_CDC_MAD_BEACON_CTL_8__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_PTR (0x3FB) -#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_PTR__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_VAL (0x3FC) -#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_VAL__POR (0x00) -#define TAIKO_A_CDC_TX_1_GAIN (0x153) -#define TAIKO_A_CDC_TX_1_GAIN__POR (0x02) -#define TAIKO_A_CDC_TX_2_GAIN (0x155) -#define TAIKO_A_CDC_TX_2_GAIN__POR (0x02) -#define TAIKO_A_CDC_TX_1_2_ADC_IB (0x156) -#define TAIKO_A_CDC_TX_1_2_ADC_IB__POR (0x44) -#define TAIKO_A_CDC_TX_3_GAIN (0x15D) -#define TAIKO_A_CDC_TX_3_GAIN__POR (0x02) -#define TAIKO_A_CDC_TX_4_GAIN (0x15F) -#define TAIKO_A_CDC_TX_4_GAIN__POR (0x02) -#define TAIKO_A_CDC_TX_3_4_ADC_IB (0x160) -#define TAIKO_A_CDC_TX_3_4_ADC_IB__POR (0x44) -#define TAIKO_A_CDC_TX_5_GAIN (0x167) -#define TAIKO_A_CDC_TX_5_GAIN__POR (0x02) -#define TAIKO_A_CDC_TX_6_GAIN (0x169) -#define TAIKO_A_CDC_TX_6_GAIN__POR (0x02) -#define TAIKO_A_CDC_TX_5_6_ADC_IB (0x16A) -#define TAIKO_A_CDC_TX_5_6_ADC_IB__POR (0x44) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL0 (0x270) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL0__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL1 (0x271) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL1__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL2 (0x272) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL2__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL3 (0x273) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL3__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL4 (0x274) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL4__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL5 (0x275) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL5__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL6 (0x276) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL6__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL7 (0x277) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL7__POR (0x00) -#define TAIKO_A_CDC_VBAT_GAIN_UPD_MON (0x2FA) -#define TAIKO_A_CDC_VBAT_GAIN_UPD_MON__POR (0x00) -#define TAIKO_A_CDC_VBAT_GAIN_MON_VAL (0x2FB) -#define TAIKO_A_CDC_VBAT_GAIN_MON_VAL__POR (0x00) -#define TAIKO_A_CDC_PA_RAMP_B1_CTL (0x361) -#define TAIKO_A_CDC_PA_RAMP_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_PA_RAMP_B2_CTL (0x362) -#define TAIKO_A_CDC_PA_RAMP_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_PA_RAMP_B3_CTL (0x363) -#define TAIKO_A_CDC_PA_RAMP_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_PA_RAMP_B4_CTL (0x364) -#define TAIKO_A_CDC_PA_RAMP_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_B1_CTL (0x365) -#define TAIKO_A_CDC_SPKR_CLIPDET_B1_CTL__POR (0x00) -#define TAIKO_SLIM_PGD_PORT_INT_EN0 (0x30) -#define TAIKO_SLIM_PGD_PORT_INT_STATUS_RX_0 (0x34) -#define TAIKO_SLIM_PGD_PORT_INT_STATUS_RX_1 (0x35) -#define TAIKO_SLIM_PGD_PORT_INT_STATUS_TX_0 (0x36) -#define TAIKO_SLIM_PGD_PORT_INT_STATUS_TX_1 (0x37) -#define TAIKO_SLIM_PGD_PORT_INT_CLR_RX_0 (0x38) -#define TAIKO_SLIM_PGD_PORT_INT_CLR_RX_1 (0x39) -#define TAIKO_SLIM_PGD_PORT_INT_CLR_TX_0 (0x3A) -#define TAIKO_SLIM_PGD_PORT_INT_CLR_TX_1 (0x3B) -#define TAIKO_SLIM_PGD_PORT_INT_RX_SOURCE0 (0x60) -#define TAIKO_SLIM_PGD_PORT_INT_TX_SOURCE0 (0x70) -#define TAIKO_PACKED_REG_SIZE sizeof(u32) -#define TAIKO_CODEC_PACK_ENTRY(reg,mask,val) ((val & 0xff) | ((mask & 0xff) << 8) | ((reg & 0xffff) << 16)) -#define TAIKO_CODEC_UNPACK_ENTRY(packed,reg,mask,val) do { ((reg) = ((packed >> 16) & (0xffff))); ((mask) = ((packed >> 8) & (0xff))); ((val) = ((packed) & (0xff))); } while(0); -#endif - diff --git a/sdm710/kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h b/sdm710/kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h deleted file mode 100644 index fe6b6b97..00000000 --- a/sdm710/kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h +++ /dev/null @@ -1,364 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef WCD9XXX_CODEC_DIGITAL_H -#define WCD9XXX_CODEC_DIGITAL_H -#define WCD9XXX_A_CHIP_CTL (0x00) -#define WCD9XXX_A_CHIP_CTL__POR (0x00000000) -#define WCD9XXX_A_CHIP_STATUS (0x01) -#define WCD9XXX_A_CHIP_STATUS__POR (0x00000000) -#define WCD9XXX_A_CHIP_ID_BYTE_0 (0x04) -#define WCD9XXX_A_CHIP_ID_BYTE_0__POR (0x00000000) -#define WCD9XXX_A_CHIP_ID_BYTE_1 (0x05) -#define WCD9XXX_A_CHIP_ID_BYTE_1__POR (0x00000000) -#define WCD9XXX_A_CHIP_ID_BYTE_2 (0x06) -#define WCD9XXX_A_CHIP_ID_BYTE_2__POR (0x00000000) -#define WCD9XXX_A_CHIP_ID_BYTE_3 (0x07) -#define WCD9XXX_A_CHIP_ID_BYTE_3__POR (0x00000001) -#define WCD9XXX_A_CHIP_VERSION (0x08) -#define WCD9XXX_A_CHIP_VERSION__POR (0x00000020) -#define WCD9XXX_A_SB_VERSION (0x09) -#define WCD9XXX_A_SB_VERSION__POR (0x00000010) -#define WCD9XXX_A_SLAVE_ID_1 (0x0C) -#define WCD9XXX_A_SLAVE_ID_1__POR (0x00000077) -#define WCD9XXX_A_SLAVE_ID_2 (0x0D) -#define WCD9XXX_A_SLAVE_ID_2__POR (0x00000066) -#define WCD9XXX_A_SLAVE_ID_3 (0x0E) -#define WCD9XXX_A_SLAVE_ID_3__POR (0x00000055) -#define WCD9XXX_A_CDC_CTL (0x80) -#define WCD9XXX_A_CDC_CTL__POR (0x00000000) -#define WCD9XXX_A_LEAKAGE_CTL (0x88) -#define WCD9XXX_A_LEAKAGE_CTL__POR (0x00000004) -#define WCD9XXX_A_INTR_MODE (0x90) -#define WCD9XXX_A_INTR_MASK0 (0x94) -#define WCD9XXX_A_INTR_STATUS0 (0x98) -#define WCD9XXX_A_INTR_CLEAR0 (0x9C) -#define WCD9XXX_A_INTR_LEVEL0 (0xA0) -#define WCD9XXX_A_INTR_LEVEL1 (0xA1) -#define WCD9XXX_A_INTR_LEVEL2 (0xA2) -#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB) -#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80) -#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB) -#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80) -#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL (0x101) -#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL__POR (0x50) -#define WCD9XXX_A_CLK_BUFF_EN1 (0x108) -#define WCD9XXX_A_CLK_BUFF_EN1__POR (0x04) -#define WCD9XXX_A_CLK_BUFF_EN2 (0x109) -#define WCD9XXX_A_CLK_BUFF_EN2__POR (0x02) -#define WCD9XXX_A_RX_COM_BIAS (0x1A2) -#define WCD9XXX_A_RX_COM_BIAS__POR (0x00) -#define WCD9XXX_A_RC_OSC_FREQ (0x1FA) -#define WCD9XXX_A_RC_OSC_FREQ__POR (0x46) -#define WCD9XXX_A_BIAS_OSC_BG_CTL (0x105) -#define WCD9XXX_A_BIAS_OSC_BG_CTL__POR (0x16) -#define WCD9XXX_A_RC_OSC_TEST (0x1FB) -#define WCD9XXX_A_RC_OSC_TEST__POR (0x0A) -#define WCD9XXX_A_CDC_CLK_MCLK_CTL (0x311) -#define WCD9XXX_A_CDC_CLK_MCLK_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_EN_CTL (0x3C0) -#define WCD9XXX_A_CDC_MBHC_EN_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG (0x3C1) -#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG (0x3C2) -#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG__POR (0x06) -#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) -#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03) -#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) -#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09) -#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) -#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E) -#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) -#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45) -#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) -#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04) -#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) -#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78) -#define WCD9XXX_A_CDC_MBHC_B1_STATUS (0x3C9) -#define WCD9XXX_A_CDC_MBHC_B1_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B2_STATUS (0x3CA) -#define WCD9XXX_A_CDC_MBHC_B2_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B3_STATUS (0x3CB) -#define WCD9XXX_A_CDC_MBHC_B3_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B4_STATUS (0x3CC) -#define WCD9XXX_A_CDC_MBHC_B4_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B5_STATUS (0x3CD) -#define WCD9XXX_A_CDC_MBHC_B5_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B1_CTL (0x3CE) -#define WCD9XXX_A_CDC_MBHC_B1_CTL__POR (0xC0) -#define WCD9XXX_A_CDC_MBHC_B2_CTL (0x3CF) -#define WCD9XXX_A_CDC_MBHC_B2_CTL__POR (0x5D) -#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) -#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) -#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) -#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) -#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) -#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) -#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) -#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF) -#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) -#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07) -#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) -#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF) -#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) -#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F) -#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) -#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) -#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80) -#define WCD9XXX_A_CDC_MBHC_CLK_CTL (0x3DC) -#define WCD9XXX_A_CDC_MBHC_CLK_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_INT_CTL (0x3DD) -#define WCD9XXX_A_CDC_MBHC_INT_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL (0x3DE) -#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_SPARE (0x3DF) -#define WCD9XXX_A_CDC_MBHC_SPARE__POR (0x00) -#define WCD9XXX_A_MBHC_SCALING_MUX_1 (0x14E) -#define WCD9XXX_A_MBHC_SCALING_MUX_1__POR (0x00) -#define WCD9XXX_A_RX_HPH_OCP_CTL (0x1AA) -#define WCD9XXX_A_RX_HPH_OCP_CTL__POR (0x68) -#define WCD9XXX_A_MICB_1_CTL (0x12B) -#define WCD9XXX_A_MICB_1_CTL__POR (0x16) -#define WCD9XXX_A_MICB_1_INT_RBIAS (0x12C) -#define WCD9XXX_A_MICB_1_INT_RBIAS__POR (0x24) -#define WCD9XXX_A_MICB_1_MBHC (0x12D) -#define WCD9XXX_A_MICB_1_MBHC__POR (0x01) -#define WCD9XXX_A_MICB_CFILT_2_CTL (0x12E) -#define WCD9XXX_A_MICB_CFILT_2_CTL__POR (0x40) -#define WCD9XXX_A_MICB_CFILT_2_VAL (0x12F) -#define WCD9XXX_A_MICB_CFILT_2_VAL__POR (0x80) -#define WCD9XXX_A_MICB_CFILT_2_PRECHRG (0x130) -#define WCD9XXX_A_MICB_CFILT_2_PRECHRG__POR (0x38) -#define WCD9XXX_A_MICB_2_CTL (0x131) -#define WCD9XXX_A_MICB_2_CTL__POR (0x16) -#define WCD9XXX_A_MICB_2_INT_RBIAS (0x132) -#define WCD9XXX_A_MICB_2_INT_RBIAS__POR (0x24) -#define WCD9XXX_A_MICB_2_MBHC (0x133) -#define WCD9XXX_A_MICB_2_MBHC__POR (0x02) -#define WCD9XXX_A_MICB_CFILT_3_CTL (0x134) -#define WCD9XXX_A_MICB_CFILT_3_CTL__POR (0x40) -#define WCD9XXX_A_MICB_CFILT_3_VAL (0x135) -#define WCD9XXX_A_MICB_CFILT_3_VAL__POR (0x80) -#define WCD9XXX_A_MICB_CFILT_3_PRECHRG (0x136) -#define WCD9XXX_A_MICB_CFILT_3_PRECHRG__POR (0x38) -#define WCD9XXX_A_MICB_3_CTL (0x137) -#define WCD9XXX_A_MICB_3_CTL__POR (0x16) -#define WCD9XXX_A_MICB_3_INT_RBIAS (0x138) -#define WCD9XXX_A_MICB_3_INT_RBIAS__POR (0x24) -#define WCD9XXX_A_MICB_3_MBHC (0x139) -#define WCD9XXX_A_MICB_3_MBHC__POR (0x00) -#define WCD9XXX_A_MICB_4_CTL (0x13D) -#define WCD9XXX_A_MICB_4_CTL__POR (0x16) -#define WCD9XXX_A_MICB_4_INT_RBIAS (0x13E) -#define WCD9XXX_A_MICB_4_INT_RBIAS__POR (0x24) -#define WCD9XXX_A_MICB_4_MBHC (0x13F) -#define WCD9XXX_A_MICB_4_MBHC__POR (0x01) -#define WCD9XXX_A_MICB_CFILT_1_VAL (0x129) -#define WCD9XXX_A_MICB_CFILT_1_VAL__POR (0x80) -#define WCD9XXX_A_RX_HPH_L_STATUS (0x1B3) -#define WCD9XXX_A_RX_HPH_L_STATUS__POR (0x00) -#define WCD9XXX_A_MBHC_HPH (0x1FE) -#define WCD9XXX_A_MBHC_HPH__POR (0x44) -#define WCD9XXX_A_RX_HPH_CNP_WG_TIME (0x1AD) -#define WCD9XXX_A_RX_HPH_CNP_WG_TIME__POR (0x2A) -#define WCD9XXX_A_RX_HPH_R_DAC_CTL (0x1B7) -#define WCD9XXX_A_RX_HPH_R_DAC_CTL__POR (0x00) -#define WCD9XXX_A_RX_HPH_L_DAC_CTL (0x1B1) -#define WCD9XXX_A_RX_HPH_L_DAC_CTL__POR (0x00) -#define WCD9XXX_A_TX_7_MBHC_EN (0x171) -#define WCD9XXX_A_TX_7_MBHC_EN__POR (0x0C) -#define WCD9XXX_A_PIN_CTL_OE0 (0x010) -#define WCD9XXX_A_PIN_CTL_OE0__POR (0x00) -#define WCD9XXX_A_PIN_CTL_OE1 (0x011) -#define WCD9XXX_A_PIN_CTL_OE1__POR (0x00) -#define WCD9XXX_A_MICB_CFILT_1_CTL (0x128) -#define WCD9XXX_A_LDO_H_MODE_1 (0x110) -#define WCD9XXX_A_LDO_H_MODE_1__POR (0x65) -#define WCD9XXX_A_MICB_CFILT_1_CTL__POR (0x40) -#define WCD9XXX_A_TX_7_MBHC_TEST_CTL (0x174) -#define WCD9XXX_A_TX_7_MBHC_TEST_CTL__POR (0x38) -#define WCD9XXX_A_MBHC_SCALING_MUX_2 (0x14F) -#define WCD9XXX_A_MBHC_SCALING_MUX_2__POR (0x80) -#define WCD9XXX_A_TX_COM_BIAS (0x14C) -#define WCD9XXX_A_TX_COM_BIAS__POR (0xF0) -#define WCD9XXX_A_MBHC_INSERT_DETECT (0x14A) -#define WCD9XXX_A_MBHC_INSERT_DETECT__POR (0x00) -#define WCD9XXX_A_MBHC_INSERT_DET_STATUS (0x14B) -#define WCD9XXX_A_MBHC_INSERT_DET_STATUS__POR (0x00) -#define WCD9XXX_A_MAD_ANA_CTRL (0x150) -#define WCD9XXX_A_MAD_ANA_CTRL__POR (0xF1) -#define WCD9XXX_A_CDC_CLK_OTHR_CTL (0x30C) -#define WCD9XXX_A_CDC_CLK_OTHR_CTL__POR (0x00) -#define WCD9XXX_A_BUCK_MODE_1 (0x181) -#define WCD9XXX_A_BUCK_MODE_1__POR (0x21) -#define WCD9XXX_A_BUCK_MODE_2 (0x182) -#define WCD9XXX_A_BUCK_MODE_2__POR (0xFF) -#define WCD9XXX_A_BUCK_MODE_3 (0x183) -#define WCD9XXX_A_BUCK_MODE_3__POR (0xCC) -#define WCD9XXX_A_BUCK_MODE_4 (0x184) -#define WCD9XXX_A_BUCK_MODE_4__POR (0x3A) -#define WCD9XXX_A_BUCK_MODE_5 (0x185) -#define WCD9XXX_A_BUCK_MODE_5__POR (0x00) -#define WCD9XXX_A_BUCK_CTRL_VCL_1 (0x186) -#define WCD9XXX_A_BUCK_CTRL_VCL_1__POR (0x48) -#define WCD9XXX_A_BUCK_CTRL_VCL_2 (0x187) -#define WCD9XXX_A_BUCK_CTRL_VCL_2__POR (0xA3) -#define WCD9XXX_A_BUCK_CTRL_VCL_3 (0x188) -#define WCD9XXX_A_BUCK_CTRL_VCL_3__POR (0x82) -#define WCD9XXX_A_BUCK_CTRL_CCL_1 (0x189) -#define WCD9XXX_A_BUCK_CTRL_CCL_1__POR (0xAB) -#define WCD9XXX_A_BUCK_CTRL_CCL_2 (0x18A) -#define WCD9XXX_A_BUCK_CTRL_CCL_2__POR (0xDC) -#define WCD9XXX_A_BUCK_CTRL_CCL_3 (0x18B) -#define WCD9XXX_A_BUCK_CTRL_CCL_3__POR (0x6A) -#define WCD9XXX_A_BUCK_CTRL_CCL_4 (0x18C) -#define WCD9XXX_A_BUCK_CTRL_CCL_4__POR (0x58) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1 (0x18D) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2 (0x18E) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3 (0x18F) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77) -#define WCD9XXX_A_BUCK_TMUX_A_D (0x190) -#define WCD9XXX_A_BUCK_TMUX_A_D__POR (0x00) -#define WCD9XXX_A_NCP_EN (0x192) -#define WCD9XXX_A_NCP_EN__POR (0xFE) -#define WCD9XXX_A_NCP_STATIC (0x194) -#define WCD9XXX_A_NCP_STATIC__POR (0x28) -#define WCD9XXX_A_NCP_BUCKREF (0x191) -#define WCD9XXX_A_NCP_BUCKREF__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_B1_CTL (0x320) -#define WCD9XXX_A_CDC_CLSH_B1_CTL__POR (0xE4) -#define WCD9XXX_A_CDC_CLSH_B2_CTL (0x321) -#define WCD9XXX_A_CDC_CLSH_B2_CTL__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_B3_CTL (0x322) -#define WCD9XXX_A_CDC_CLSH_B3_CTL__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS (0x323) -#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD (0x324) -#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12) -#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD (0x325) -#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C) -#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326) -#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18) -#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327) -#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23) -#define WCD9XXX_A_CDC_CLSH_K_ADDR (0x328) -#define WCD9XXX_A_CDC_CLSH_K_ADDR__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_K_DATA (0x329) -#define WCD9XXX_A_CDC_CLSH_K_DATA__POR (0xA4) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09) -#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR (0x32E) -#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH (0x32F) -#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR (0x330) -#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH (0x331) -#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00) -#define WCD9XXX_A_CDC_RX1_B6_CTL (0x2B5) -#define WCD9XXX_A_CDC_RX1_B6_CTL__POR (0x80) -#define WCD9XXX_A_CDC_RX2_B6_CTL (0x2BD) -#define WCD9XXX_A_CDC_RX2_B6_CTL__POR (0x80) -#define WCD9XXX_A_RX_HPH_L_GAIN (0x1AE) -#define WCD9XXX_A_RX_HPH_L_GAIN__POR (0x00) -#define WCD9XXX_A_RX_HPH_R_GAIN (0x1B4) -#define WCD9XXX_A_RX_HPH_R_GAIN__POR (0x00) -#define WCD9XXX_A_RX_HPH_CHOP_CTL (0x1A5) -#define WCD9XXX_A_RX_HPH_CHOP_CTL__POR (0xB4) -#define WCD9XXX_A_RX_HPH_BIAS_PA (0x1A6) -#define WCD9XXX_A_RX_HPH_BIAS_PA__POR (0x7A) -#define WCD9XXX_A_RX_HPH_L_TEST (0x1AF) -#define WCD9XXX_A_RX_HPH_L_TEST__POR (0x00) -#define WCD9XXX_A_RX_HPH_R_TEST (0x1B5) -#define WCD9XXX_A_RX_HPH_R_TEST__POR (0x00) -#define WCD9XXX_A_CDC_CLK_RX_B1_CTL (0x30F) -#define WCD9XXX_A_CDC_CLK_RX_B1_CTL__POR (0x00) -#define WCD9XXX_A_NCP_CLK (0x193) -#define WCD9XXX_A_NCP_CLK__POR (0x94) -#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP (0x1A9) -#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP__POR (0x2A) -#define WCD9XXX_A_RX_HPH_CNP_WG_CTL (0x1AC) -#define WCD9XXX_A_RX_HPH_CNP_WG_CTL__POR (0xDE) -#define WCD9XXX_A_RX_HPH_L_PA_CTL (0x1B0) -#define WCD9XXX_A_RX_HPH_L_PA_CTL__POR (0x42) -#define WCD9XXX_A_RX_HPH_R_PA_CTL (0x1B6) -#define WCD9XXX_A_RX_HPH_R_PA_CTL__POR (0x42) -#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL (0x383) -#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL__POR (0x00) -#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL (0x361) -#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL__POR (0x00) -#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL (0x362) -#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL__POR (0x00) -#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL (0x363) -#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL__POR (0x00) -#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL (0x364) -#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL__POR (0x00) -#define WCD9330_A_LEAKAGE_CTL (0x03C) -#define WCD9330_A_LEAKAGE_CTL__POR (0x04) -#define WCD9330_A_CDC_CTL (0x034) -#define WCD9330_A_CDC_CTL__POR (0x00) -#define WCD9XXX_A_CDC_RX0_RX_PATH_CFG0 (0xB42) -#define WCD9XXX_A_CDC_RX1_RX_PATH_CFG0 (0xB56) -#define WCD9XXX_A_CDC_RX2_RX_PATH_CFG0 (0xB6A) -#define WCD9XXX_A_CDC_CLSH_K1_MSB (0xC08) -#define WCD9XXX_A_CDC_CLSH_K1_LSB (0xC09) -#define WCD9XXX_A_ANA_RX_SUPPLIES (0x608) -#define WCD9XXX_A_ANA_HPH (0x609) -#define WCD9XXX_A_CDC_CLSH_CRC (0xC01) -#define WCD9XXX_FLYBACK_EN (0x6A4) -#define WCD9XXX_FLYBACK_VNEG_CTRL_1 (0x6A5) -#define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2 (0x6AF) -#define WCD9XXX_RX_BIAS_FLYB_BUFF (0x6C7) -#define WCD9XXX_HPH_L_EN (0x6D3) -#define WCD9XXX_HPH_R_EN (0x6D6) -#define WCD9XXX_HPH_REFBUFF_UHQA_CTL (0x6DD) -#define WCD9XXX_CLASSH_CTRL_VCL_2 (0x69B) -#define WCD9XXX_CDC_CLSH_HPH_V_PA (0xC04) -#define WCD9XXX_CDC_RX0_RX_PATH_SEC0 (0xB49) -#define WCD9XXX_CDC_RX1_RX_PATH_CTL (0xB55) -#define WCD9XXX_CDC_RX2_RX_PATH_CTL (0xB69) -#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_CONTROL (0xD41) -#define WCD9XXX_CLASSH_CTRL_CCL_1 (0x69C) -#define WCD9XXX_CDC_RX1_RX_VOL_CTL (0xB59) -#define WCD9XXX_CDC_RX1_RX_VOL_MIX_CTL (0xB5C) -#define WCD9XXX_CDC_RX1_RX_PATH_SEC1 (0xB5E) -#define WCD9XXX_CDC_RX2_RX_VOL_CTL (0xB6D) -#define WCD9XXX_CDC_RX2_RX_VOL_MIX_CTL (0xB70) -#define WCD9XXX_CDC_RX2_RX_PATH_SEC1 (0xB72) -#define WCD9XXX_HPH_CNP_WG_CTL (0x06cc) -#define WCD9XXX_FLYBACK_VNEG_CTRL_4 (0x06a8) -#define WCD9XXX_HPH_NEW_INT_PA_MISC2 (0x0738) -#define WCD9XXX_RX_BIAS_HPH_LOWPOWER (0x06bf) -#define WCD9XXX_HPH_PA_CTL1 (0x06d1) -#endif - diff --git a/sdm710/kernel-headers/linux/msm-core-interface.h b/sdm710/kernel-headers/linux/msm-core-interface.h deleted file mode 100644 index 681e0b72..00000000 --- a/sdm710/kernel-headers/linux/msm-core-interface.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __MSM_CORE_LIB_H__ -#define __MSM_CORE_LIB_H__ -#include <linux/ioctl.h> -#define TEMP_DATA_POINTS 13 -#define MAX_NUM_FREQ 200 -enum msm_core_ioctl_params { - MSM_CORE_LEAKAGE, - MSM_CORE_VOLTAGE, -}; -#define MSM_CORE_MAGIC 0x9D -struct sched_params { - uint32_t cpumask; - uint32_t cluster; - uint32_t power[TEMP_DATA_POINTS][MAX_NUM_FREQ]; - uint32_t voltage[MAX_NUM_FREQ]; - uint32_t freq[MAX_NUM_FREQ]; -}; -#define EA_LEAKAGE _IOWR(MSM_CORE_MAGIC, MSM_CORE_LEAKAGE, struct sched_params) -#define EA_VOLT _IOWR(MSM_CORE_MAGIC, MSM_CORE_VOLTAGE, struct sched_params) -#endif - diff --git a/sdm710/kernel-headers/linux/msm_adsp.h b/sdm710/kernel-headers/linux/msm_adsp.h deleted file mode 100644 index 7bf7c76b..00000000 --- a/sdm710/kernel-headers/linux/msm_adsp.h +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _LINUX_MSM_ADSP_H -#define _LINUX_MSM_ADSP_H -#include <linux/types.h> -#include <linux/ioctl.h> -#define ADSP_IOCTL_MAGIC 'q' -struct adsp_command_t { - uint16_t queue; - uint32_t len; - uint8_t * data; -}; -struct adsp_event_t { - uint16_t type; - uint32_t timeout_ms; - uint16_t msg_id; - uint16_t flags; - uint32_t len; - uint8_t * data; -}; -#define ADSP_IOCTL_ENABLE _IOR(ADSP_IOCTL_MAGIC, 1, unsigned) -#define ADSP_IOCTL_DISABLE _IOR(ADSP_IOCTL_MAGIC, 2, unsigned) -#define ADSP_IOCTL_DISABLE_ACK _IOR(ADSP_IOCTL_MAGIC, 3, unsigned) -#define ADSP_IOCTL_WRITE_COMMAND _IOR(ADSP_IOCTL_MAGIC, 4, struct adsp_command_t *) -#define ADSP_IOCTL_GET_EVENT _IOWR(ADSP_IOCTL_MAGIC, 5, struct adsp_event_data_t *) -#define ADSP_IOCTL_SET_CLKRATE _IOR(ADSP_IOCTL_MAGIC, 6, unsigned) -#define ADSP_IOCTL_DISABLE_EVENT_RSP _IOR(ADSP_IOCTL_MAGIC, 10, unsigned) -#define ADSP_IOCTL_REGISTER_PMEM _IOW(ADSP_IOCTL_MAGIC, 13, unsigned) -#define ADSP_IOCTL_UNREGISTER_PMEM _IOW(ADSP_IOCTL_MAGIC, 14, unsigned) -#define ADSP_IOCTL_ABORT_EVENT_READ _IOW(ADSP_IOCTL_MAGIC, 15, unsigned) -#define ADSP_IOCTL_LINK_TASK _IOW(ADSP_IOCTL_MAGIC, 16, unsigned) -#endif - diff --git a/sdm710/kernel-headers/linux/msm_audio.h b/sdm710/kernel-headers/linux/msm_audio.h deleted file mode 100644 index 586738a2..00000000 --- a/sdm710/kernel-headers/linux/msm_audio.h +++ /dev/null @@ -1,353 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _LINUX_MSM_AUDIO_H -#define _LINUX_MSM_AUDIO_H -#include <linux/types.h> -#include <linux/ioctl.h> -#define AUDIO_IOCTL_MAGIC 'a' -#define AUDIO_START _IOW(AUDIO_IOCTL_MAGIC, 0, unsigned int) -#define AUDIO_STOP _IOW(AUDIO_IOCTL_MAGIC, 1, unsigned int) -#define AUDIO_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 2, unsigned int) -#define AUDIO_GET_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 3, struct msm_audio_config) -#define AUDIO_SET_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 4, struct msm_audio_config) -#define AUDIO_GET_STATS _IOR(AUDIO_IOCTL_MAGIC, 5, struct msm_audio_stats) -#define AUDIO_ENABLE_AUDPP _IOW(AUDIO_IOCTL_MAGIC, 6, unsigned int) -#define AUDIO_SET_ADRC _IOW(AUDIO_IOCTL_MAGIC, 7, unsigned int) -#define AUDIO_SET_EQ _IOW(AUDIO_IOCTL_MAGIC, 8, unsigned int) -#define AUDIO_SET_RX_IIR _IOW(AUDIO_IOCTL_MAGIC, 9, unsigned int) -#define AUDIO_SET_VOLUME _IOW(AUDIO_IOCTL_MAGIC, 10, unsigned int) -#define AUDIO_PAUSE _IOW(AUDIO_IOCTL_MAGIC, 11, unsigned int) -#define AUDIO_PLAY_DTMF _IOW(AUDIO_IOCTL_MAGIC, 12, unsigned int) -#define AUDIO_GET_EVENT _IOR(AUDIO_IOCTL_MAGIC, 13, struct msm_audio_event) -#define AUDIO_ABORT_GET_EVENT _IOW(AUDIO_IOCTL_MAGIC, 14, unsigned int) -#define AUDIO_REGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 15, unsigned int) -#define AUDIO_DEREGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 16, unsigned int) -#define AUDIO_ASYNC_WRITE _IOW(AUDIO_IOCTL_MAGIC, 17, struct msm_audio_aio_buf) -#define AUDIO_ASYNC_READ _IOW(AUDIO_IOCTL_MAGIC, 18, struct msm_audio_aio_buf) -#define AUDIO_SET_INCALL _IOW(AUDIO_IOCTL_MAGIC, 19, struct msm_voicerec_mode) -#define AUDIO_GET_NUM_SND_DEVICE _IOR(AUDIO_IOCTL_MAGIC, 20, unsigned int) -#define AUDIO_GET_SND_DEVICES _IOWR(AUDIO_IOCTL_MAGIC, 21, struct msm_snd_device_list) -#define AUDIO_ENABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 22, unsigned int) -#define AUDIO_DISABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 23, unsigned int) -#define AUDIO_ROUTE_STREAM _IOW(AUDIO_IOCTL_MAGIC, 24, struct msm_audio_route_config) -#define AUDIO_GET_PCM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 30, unsigned int) -#define AUDIO_SET_PCM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 31, unsigned int) -#define AUDIO_SWITCH_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 32, unsigned int) -#define AUDIO_SET_MUTE _IOW(AUDIO_IOCTL_MAGIC, 33, unsigned int) -#define AUDIO_UPDATE_ACDB _IOW(AUDIO_IOCTL_MAGIC, 34, unsigned int) -#define AUDIO_START_VOICE _IOW(AUDIO_IOCTL_MAGIC, 35, unsigned int) -#define AUDIO_STOP_VOICE _IOW(AUDIO_IOCTL_MAGIC, 36, unsigned int) -#define AUDIO_REINIT_ACDB _IOW(AUDIO_IOCTL_MAGIC, 39, unsigned int) -#define AUDIO_OUTPORT_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 40, unsigned short) -#define AUDIO_SET_ERR_THRESHOLD_VALUE _IOW(AUDIO_IOCTL_MAGIC, 41, unsigned short) -#define AUDIO_GET_BITSTREAM_ERROR_INFO _IOR(AUDIO_IOCTL_MAGIC, 42, struct msm_audio_bitstream_error_info) -#define AUDIO_SET_SRS_TRUMEDIA_PARAM _IOW(AUDIO_IOCTL_MAGIC, 43, unsigned int) -#define AUDIO_SET_STREAM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 80, struct msm_audio_stream_config) -#define AUDIO_GET_STREAM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 81, struct msm_audio_stream_config) -#define AUDIO_GET_SESSION_ID _IOR(AUDIO_IOCTL_MAGIC, 82, unsigned short) -#define AUDIO_GET_STREAM_INFO _IOR(AUDIO_IOCTL_MAGIC, 83, struct msm_audio_bitstream_info) -#define AUDIO_SET_PAN _IOW(AUDIO_IOCTL_MAGIC, 84, unsigned int) -#define AUDIO_SET_QCONCERT_PLUS _IOW(AUDIO_IOCTL_MAGIC, 85, unsigned int) -#define AUDIO_SET_MBADRC _IOW(AUDIO_IOCTL_MAGIC, 86, unsigned int) -#define AUDIO_SET_VOLUME_PATH _IOW(AUDIO_IOCTL_MAGIC, 87, struct msm_vol_info) -#define AUDIO_SET_MAX_VOL_ALL _IOW(AUDIO_IOCTL_MAGIC, 88, unsigned int) -#define AUDIO_ENABLE_AUDPRE _IOW(AUDIO_IOCTL_MAGIC, 89, unsigned int) -#define AUDIO_SET_AGC _IOW(AUDIO_IOCTL_MAGIC, 90, unsigned int) -#define AUDIO_SET_NS _IOW(AUDIO_IOCTL_MAGIC, 91, unsigned int) -#define AUDIO_SET_TX_IIR _IOW(AUDIO_IOCTL_MAGIC, 92, unsigned int) -#define AUDIO_GET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 93, struct msm_audio_buf_cfg) -#define AUDIO_SET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 94, struct msm_audio_buf_cfg) -#define AUDIO_SET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 95, struct msm_acdb_cmd_device) -#define AUDIO_GET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 96, struct msm_acdb_cmd_device) -#define AUDIO_REGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 97, struct msm_audio_ion_info) -#define AUDIO_DEREGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 98, struct msm_audio_ion_info) -#define AUDIO_SET_EFFECTS_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 99, struct msm_hwacc_effects_config) -#define AUDIO_EFFECTS_SET_BUF_LEN _IOW(AUDIO_IOCTL_MAGIC, 100, struct msm_hwacc_buf_cfg) -#define AUDIO_EFFECTS_GET_BUF_AVAIL _IOW(AUDIO_IOCTL_MAGIC, 101, struct msm_hwacc_buf_avail) -#define AUDIO_EFFECTS_WRITE _IOW(AUDIO_IOCTL_MAGIC, 102, void *) -#define AUDIO_EFFECTS_READ _IOWR(AUDIO_IOCTL_MAGIC, 103, void *) -#define AUDIO_EFFECTS_SET_PP_PARAMS _IOW(AUDIO_IOCTL_MAGIC, 104, void *) -#define AUDIO_PM_AWAKE _IOW(AUDIO_IOCTL_MAGIC, 105, unsigned int) -#define AUDIO_PM_RELAX _IOW(AUDIO_IOCTL_MAGIC, 106, unsigned int) -#define AUDIO_MAX_COMMON_IOCTL_NUM 107 -#define HANDSET_MIC 0x01 -#define HANDSET_SPKR 0x02 -#define HEADSET_MIC 0x03 -#define HEADSET_SPKR_MONO 0x04 -#define HEADSET_SPKR_STEREO 0x05 -#define SPKR_PHONE_MIC 0x06 -#define SPKR_PHONE_MONO 0x07 -#define SPKR_PHONE_STEREO 0x08 -#define BT_SCO_MIC 0x09 -#define BT_SCO_SPKR 0x0A -#define BT_A2DP_SPKR 0x0B -#define TTY_HEADSET_MIC 0x0C -#define TTY_HEADSET_SPKR 0x0D -#define DEFAULT_TX 0x0E -#define DEFAULT_RX 0x0F -#define BT_A2DP_TX 0x10 -#define HEADSET_MONO_PLUS_SPKR_MONO_RX 0x11 -#define HEADSET_MONO_PLUS_SPKR_STEREO_RX 0x12 -#define HEADSET_STEREO_PLUS_SPKR_MONO_RX 0x13 -#define HEADSET_STEREO_PLUS_SPKR_STEREO_RX 0x14 -#define I2S_RX 0x20 -#define I2S_TX 0x21 -#define ADRC_ENABLE 0x0001 -#define EQUALIZER_ENABLE 0x0002 -#define IIR_ENABLE 0x0004 -#define QCONCERT_PLUS_ENABLE 0x0008 -#define MBADRC_ENABLE 0x0010 -#define SRS_ENABLE 0x0020 -#define SRS_DISABLE 0x0040 -#define AGC_ENABLE 0x0001 -#define NS_ENABLE 0x0002 -#define TX_IIR_ENABLE 0x0004 -#define FLUENCE_ENABLE 0x0008 -#define VOC_REC_UPLINK 0x00 -#define VOC_REC_DOWNLINK 0x01 -#define VOC_REC_BOTH 0x02 -struct msm_audio_config { - uint32_t buffer_size; - uint32_t buffer_count; - uint32_t channel_count; - uint32_t sample_rate; - uint32_t type; - uint32_t meta_field; - uint32_t bits; - uint32_t unused[3]; -}; -struct msm_audio_stream_config { - uint32_t buffer_size; - uint32_t buffer_count; -}; -struct msm_audio_buf_cfg { - uint32_t meta_info_enable; - uint32_t frames_per_buf; -}; -struct msm_audio_stats { - uint32_t byte_count; - uint32_t sample_count; - uint32_t unused[2]; -}; -struct msm_audio_ion_info { - int fd; - void * vaddr; -}; -struct msm_audio_pmem_info { - int fd; - void * vaddr; -}; -struct msm_audio_aio_buf { - void * buf_addr; - uint32_t buf_len; - uint32_t data_len; - void * private_data; - unsigned short mfield_sz; -}; -#define SND_IOCTL_MAGIC 's' -#define SND_MUTE_UNMUTED 0 -#define SND_MUTE_MUTED 1 -struct msm_mute_info { - uint32_t mute; - uint32_t path; -}; -struct msm_vol_info { - uint32_t vol; - uint32_t path; -}; -struct msm_voicerec_mode { - uint32_t rec_mode; -}; -struct msm_snd_device_config { - uint32_t device; - uint32_t ear_mute; - uint32_t mic_mute; -}; -#define SND_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_device_config *) -enum cad_device_path_type { - CAD_DEVICE_PATH_RX, - CAD_DEVICE_PATH_TX, - CAD_DEVICE_PATH_RX_TX, - CAD_DEVICE_PATH_LB, - CAD_DEVICE_PATH_MAX -}; -struct cad_devices_type { - uint32_t rx_device; - uint32_t tx_device; - enum cad_device_path_type pathtype; -}; -struct msm_cad_device_config { - struct cad_devices_type device; - uint32_t ear_mute; - uint32_t mic_mute; -}; -#define CAD_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_cad_device_config *) -#define SND_METHOD_VOICE 0 -#define SND_METHOD_MIDI 4 -struct msm_snd_volume_config { - uint32_t device; - uint32_t method; - uint32_t volume; -}; -#define SND_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_snd_volume_config *) -struct msm_cad_volume_config { - struct cad_devices_type device; - uint32_t method; - uint32_t volume; -}; -#define CAD_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_cad_volume_config *) -#define SND_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned int *) -struct msm_snd_endpoint { - int id; - char name[64]; -}; -#define SND_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_snd_endpoint *) -#define SND_AVC_CTL _IOW(SND_IOCTL_MAGIC, 6, unsigned int *) -#define SND_AGC_CTL _IOW(SND_IOCTL_MAGIC, 7, unsigned int *) -#define CAD_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned int *) -struct msm_cad_endpoint { - int id; - char name[64]; -}; -#define CAD_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_cad_endpoint *) -struct msm_audio_pcm_config { - uint32_t pcm_feedback; - uint32_t buffer_count; - uint32_t buffer_size; -}; -#define AUDIO_EVENT_SUSPEND 0 -#define AUDIO_EVENT_RESUME 1 -#define AUDIO_EVENT_WRITE_DONE 2 -#define AUDIO_EVENT_READ_DONE 3 -#define AUDIO_EVENT_STREAM_INFO 4 -#define AUDIO_EVENT_BITSTREAM_ERROR_INFO 5 -#define AUDIO_CODEC_TYPE_MP3 0 -#define AUDIO_CODEC_TYPE_AAC 1 -struct msm_audio_bitstream_info { - uint32_t codec_type; - uint32_t chan_info; - uint32_t sample_rate; - uint32_t bit_stream_info; - uint32_t bit_rate; - uint32_t unused[3]; -}; -struct msm_audio_bitstream_error_info { - uint32_t dec_id; - uint32_t err_msg_indicator; - uint32_t err_type; -}; -union msm_audio_event_payload { - struct msm_audio_aio_buf aio_buf; - struct msm_audio_bitstream_info stream_info; - struct msm_audio_bitstream_error_info error_info; - int reserved; -}; -struct msm_audio_event { - int event_type; - int timeout_ms; - union msm_audio_event_payload event_payload; -}; -#define MSM_SNDDEV_CAP_RX 0x1 -#define MSM_SNDDEV_CAP_TX 0x2 -#define MSM_SNDDEV_CAP_VOICE 0x4 -struct msm_snd_device_info { - uint32_t dev_id; - uint32_t dev_cap; - char dev_name[64]; -}; -struct msm_snd_device_list { - uint32_t num_dev; - struct msm_snd_device_info * list; -}; -struct msm_dtmf_config { - uint16_t path; - uint16_t dtmf_hi; - uint16_t dtmf_low; - uint16_t duration; - uint16_t tx_gain; - uint16_t rx_gain; - uint16_t mixing; -}; -#define AUDIO_ROUTE_STREAM_VOICE_RX 0 -#define AUDIO_ROUTE_STREAM_VOICE_TX 1 -#define AUDIO_ROUTE_STREAM_PLAYBACK 2 -#define AUDIO_ROUTE_STREAM_REC 3 -struct msm_audio_route_config { - uint32_t stream_type; - uint32_t stream_id; - uint32_t dev_id; -}; -#define AUDIO_MAX_EQ_BANDS 12 -struct msm_audio_eq_band { - uint16_t band_idx; - uint32_t filter_type; - uint32_t center_freq_hz; - uint32_t filter_gain; - uint32_t q_factor; -} __attribute__((packed)); -struct msm_audio_eq_stream_config { - uint32_t enable; - uint32_t num_bands; - struct msm_audio_eq_band eq_bands[AUDIO_MAX_EQ_BANDS]; -} __attribute__((packed)); -struct msm_acdb_cmd_device { - uint32_t command_id; - uint32_t device_id; - uint32_t network_id; - uint32_t sample_rate_id; - uint32_t interface_id; - uint32_t algorithm_block_id; - uint32_t total_bytes; - uint32_t * phys_buf; -}; -struct msm_hwacc_data_config { - __u32 buf_size; - __u32 num_buf; - __u32 num_channels; - __u8 channel_map[8]; - __u32 sample_rate; - __u32 bits_per_sample; -}; -struct msm_hwacc_buf_cfg { - __u32 input_len; - __u32 output_len; -}; -struct msm_hwacc_buf_avail { - __u32 input_num_avail; - __u32 output_num_avail; -}; -struct msm_hwacc_effects_config { - struct msm_hwacc_data_config input; - struct msm_hwacc_data_config output; - struct msm_hwacc_buf_cfg buf_cfg; - __u32 meta_mode_enabled; - __u32 overwrite_topology; - __s32 topology; -}; -#define ADSP_STREAM_PP_EVENT 0 -#define ADSP_STREAM_ENCDEC_EVENT 1 -#define ADSP_STREAM_IEC_61937_FMT_UPDATE_EVENT 2 -#define ADSP_STREAM_EVENT_MAX 3 -struct msm_adsp_event_data { - __u32 event_type; - __u32 payload_len; - __u8 payload[0]; -}; -#endif - diff --git a/sdm710/kernel-headers/linux/msm_audio_aac.h b/sdm710/kernel-headers/linux/msm_audio_aac.h deleted file mode 100644 index 8499ac48..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_aac.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef _MSM_AUDIO_AAC_H -#define _MSM_AUDIO_AAC_H - -#include <linux/msm_audio.h> - -#define AUDIO_SET_AAC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_aac_config) -#define AUDIO_GET_AAC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_aac_config) - -#define AUDIO_SET_AAC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_aac_enc_config) - -#define AUDIO_GET_AAC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+4), struct msm_audio_aac_enc_config) - -#define AUDIO_SET_AAC_MIX_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+5), uint32_t) - -#define AUDIO_AAC_FORMAT_ADTS -1 -#define AUDIO_AAC_FORMAT_RAW 0x0000 -#define AUDIO_AAC_FORMAT_PSUEDO_RAW 0x0001 -#define AUDIO_AAC_FORMAT_LOAS 0x0002 -#define AUDIO_AAC_FORMAT_ADIF 0x0003 - -#define AUDIO_AAC_OBJECT_LC 0x0002 -#define AUDIO_AAC_OBJECT_LTP 0x0004 -#define AUDIO_AAC_OBJECT_ERLC 0x0011 -#define AUDIO_AAC_OBJECT_BSAC 0x0016 - -#define AUDIO_AAC_SEC_DATA_RES_ON 0x0001 -#define AUDIO_AAC_SEC_DATA_RES_OFF 0x0000 - -#define AUDIO_AAC_SCA_DATA_RES_ON 0x0001 -#define AUDIO_AAC_SCA_DATA_RES_OFF 0x0000 - -#define AUDIO_AAC_SPEC_DATA_RES_ON 0x0001 -#define AUDIO_AAC_SPEC_DATA_RES_OFF 0x0000 - -#define AUDIO_AAC_SBR_ON_FLAG_ON 0x0001 -#define AUDIO_AAC_SBR_ON_FLAG_OFF 0x0000 - -#define AUDIO_AAC_SBR_PS_ON_FLAG_ON 0x0001 -#define AUDIO_AAC_SBR_PS_ON_FLAG_OFF 0x0000 - -/* Primary channel on both left and right channels */ -#define AUDIO_AAC_DUAL_MONO_PL_PR 0 -/* Secondary channel on both left and right channels */ -#define AUDIO_AAC_DUAL_MONO_SL_SR 1 -/* Primary channel on right channel and 2nd on left channel */ -#define AUDIO_AAC_DUAL_MONO_SL_PR 2 -/* 2nd channel on right channel and primary on left channel */ -#define AUDIO_AAC_DUAL_MONO_PL_SR 3 - -struct msm_audio_aac_config { - signed short format; - unsigned short audio_object; - unsigned short ep_config; /* 0 ~ 3 useful only obj = ERLC */ - unsigned short aac_section_data_resilience_flag; - unsigned short aac_scalefactor_data_resilience_flag; - unsigned short aac_spectral_data_resilience_flag; - unsigned short sbr_on_flag; - unsigned short sbr_ps_on_flag; - unsigned short dual_mono_mode; - unsigned short channel_configuration; - unsigned short sample_rate; -}; - -struct msm_audio_aac_enc_config { - uint32_t channels; - uint32_t sample_rate; - uint32_t bit_rate; - uint32_t stream_format; -}; - -#endif /* _MSM_AUDIO_AAC_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_ac3.h b/sdm710/kernel-headers/linux/msm_audio_ac3.h deleted file mode 100644 index 2203d9e4..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_ac3.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _MSM_AUDIO_AC3_H -#define _MSM_AUDIO_AC3_H - -#include <linux/msm_audio.h> - -#define AUDIO_SET_AC3_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned int) -#define AUDIO_GET_AC3_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned int) - -#define AUDAC3_DEF_WORDSIZE 0 -#define AUDAC3_DEF_USER_DOWNMIX_FLAG 0x0 -#define AUDAC3_DEF_USER_KARAOKE_FLAG 0x0 -#define AUDAC3_DEF_ERROR_CONCEALMENT 0 -#define AUDAC3_DEF_MAX_REPEAT_COUNT 0 - -struct msm_audio_ac3_config { - unsigned short numChans; - unsigned short wordSize; - unsigned short kCapableMode; - unsigned short compMode; - unsigned short outLfeOn; - unsigned short outputMode; - unsigned short stereoMode; - unsigned short dualMonoMode; - unsigned short fsCod; - unsigned short pcmScaleFac; - unsigned short dynRngScaleHi; - unsigned short dynRngScaleLow; - unsigned short user_downmix_flag; - unsigned short user_karaoke_flag; - unsigned short dm_address_high; - unsigned short dm_address_low; - unsigned short ko_address_high; - unsigned short ko_address_low; - unsigned short error_concealment; - unsigned short max_rep_count; - unsigned short channel_routing_mode[6]; -}; - -#endif /* _MSM_AUDIO_AC3_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_alac.h b/sdm710/kernel-headers/linux/msm_audio_alac.h deleted file mode 100644 index 36b96567..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_alac.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef _MSM_AUDIO_ALAC_H -#define _MSM_AUDIO_ALAC_H - -#define AUDIO_GET_ALAC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_alac_config) -#define AUDIO_SET_ALAC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_alac_config) - -struct msm_audio_alac_config { - uint32_t frameLength; - uint8_t compatVersion; - uint8_t bitDepth; - uint8_t pb; /* currently unused */ - uint8_t mb; /* currently unused */ - uint8_t kb; /* currently unused */ - uint8_t channelCount; - uint16_t maxRun; /* currently unused */ - uint32_t maxSize; - uint32_t averageBitRate; - uint32_t sampleRate; - uint32_t channelLayout; -}; - -#endif /* _MSM_AUDIO_ALAC_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_amrnb.h b/sdm710/kernel-headers/linux/msm_audio_amrnb.h deleted file mode 100644 index 04099835..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_amrnb.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef _MSM_AUDIO_AMRNB_H -#define _MSM_AUDIO_AMRNB_H - -#include <linux/msm_audio.h> - -#define AUDIO_GET_AMRNB_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned int) -#define AUDIO_SET_AMRNB_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned int) -#define AUDIO_GET_AMRNB_ENC_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+2), \ - struct msm_audio_amrnb_enc_config_v2) -#define AUDIO_SET_AMRNB_ENC_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+3), \ - struct msm_audio_amrnb_enc_config_v2) - -struct msm_audio_amrnb_enc_config { - unsigned short voicememoencweight1; - unsigned short voicememoencweight2; - unsigned short voicememoencweight3; - unsigned short voicememoencweight4; - unsigned short dtx_mode_enable; /* 0xFFFF - enable, 0- disable */ - unsigned short test_mode_enable; /* 0xFFFF - enable, 0- disable */ - unsigned short enc_mode; /* 0-MR475,1-MR515,2-MR59,3-MR67,4-MR74 - * 5-MR795, 6- MR102, 7- MR122(default) - */ -}; - -struct msm_audio_amrnb_enc_config_v2 { - uint32_t band_mode; - uint32_t dtx_enable; - uint32_t frame_format; -}; -#endif /* _MSM_AUDIO_AMRNB_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_amrwb.h b/sdm710/kernel-headers/linux/msm_audio_amrwb.h deleted file mode 100644 index 0d55397d..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_amrwb.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _MSM_AUDIO_AMRWB_H -#define _MSM_AUDIO_AMRWB_H - -#include <linux/msm_audio.h> - -#define AUDIO_GET_AMRWB_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), \ - struct msm_audio_amrwb_enc_config) -#define AUDIO_SET_AMRWB_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), \ - struct msm_audio_amrwb_enc_config) - -struct msm_audio_amrwb_enc_config { - uint32_t band_mode; - uint32_t dtx_enable; - uint32_t frame_format; -}; -#endif /* _MSM_AUDIO_AMRWB_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_amrwbplus.h b/sdm710/kernel-headers/linux/msm_audio_amrwbplus.h deleted file mode 100644 index 5b8a980a..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_amrwbplus.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _MSM_AUDIO_AMR_WB_PLUS_H -#define _MSM_AUDIO_AMR_WB_PLUS_H - -#define AUDIO_GET_AMRWBPLUS_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+2), struct msm_audio_amrwbplus_config_v2) -#define AUDIO_SET_AMRWBPLUS_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_amrwbplus_config_v2) - -struct msm_audio_amrwbplus_config_v2 { - unsigned int size_bytes; - unsigned int version; - unsigned int num_channels; - unsigned int amr_band_mode; - unsigned int amr_dtx_mode; - unsigned int amr_frame_fmt; - unsigned int amr_lsf_idx; -}; -#endif /* _MSM_AUDIO_AMR_WB_PLUS_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_ape.h b/sdm710/kernel-headers/linux/msm_audio_ape.h deleted file mode 100644 index b14f6852..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_ape.h +++ /dev/null @@ -1,26 +0,0 @@ -/* The following structure has been taken - * from Monkey's Audio SDK with permission - */ - -#ifndef _MSM_AUDIO_APE_H -#define _MSM_AUDIO_APE_H - -#define AUDIO_GET_APE_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_ape_config) -#define AUDIO_SET_APE_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_ape_config) - -struct msm_audio_ape_config { - uint16_t compatibleVersion; - uint16_t compressionLevel; - uint32_t formatFlags; - uint32_t blocksPerFrame; - uint32_t finalFrameBlocks; - uint32_t totalFrames; - uint16_t bitsPerSample; - uint16_t numChannels; - uint32_t sampleRate; - uint32_t seekTablePresent; -}; - -#endif /* _MSM_AUDIO_APE_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_calibration.h b/sdm710/kernel-headers/linux/msm_audio_calibration.h deleted file mode 100644 index 42800d7b..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_calibration.h +++ /dev/null @@ -1,742 +0,0 @@ -#ifndef _MSM_AUDIO_CALIBRATION_H -#define _MSM_AUDIO_CALIBRATION_H - -#include <linux/types.h> -#include <linux/ioctl.h> - -#define CAL_IOCTL_MAGIC 'a' - -#define AUDIO_ALLOCATE_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \ - 200, void *) -#define AUDIO_DEALLOCATE_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \ - 201, void *) -#define AUDIO_PREPARE_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \ - 202, void *) -#define AUDIO_SET_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \ - 203, void *) -#define AUDIO_GET_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \ - 204, void *) -#define AUDIO_POST_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \ - 205, void *) - -/* For Real-Time Audio Calibration */ -#define AUDIO_GET_RTAC_ADM_INFO _IOR(CAL_IOCTL_MAGIC, \ - 207, void *) -#define AUDIO_GET_RTAC_VOICE_INFO _IOR(CAL_IOCTL_MAGIC, \ - 208, void *) -#define AUDIO_GET_RTAC_ADM_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 209, void *) -#define AUDIO_SET_RTAC_ADM_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 210, void *) -#define AUDIO_GET_RTAC_ASM_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 211, void *) -#define AUDIO_SET_RTAC_ASM_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 212, void *) -#define AUDIO_GET_RTAC_CVS_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 213, void *) -#define AUDIO_SET_RTAC_CVS_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 214, void *) -#define AUDIO_GET_RTAC_CVP_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 215, void *) -#define AUDIO_SET_RTAC_CVP_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 216, void *) -#define AUDIO_GET_RTAC_AFE_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 217, void *) -#define AUDIO_SET_RTAC_AFE_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 218, void *) -enum { - CVP_VOC_RX_TOPOLOGY_CAL_TYPE = 0, - CVP_VOC_TX_TOPOLOGY_CAL_TYPE, - CVP_VOCPROC_STATIC_CAL_TYPE, - CVP_VOCPROC_DYNAMIC_CAL_TYPE, - CVS_VOCSTRM_STATIC_CAL_TYPE, - CVP_VOCDEV_CFG_CAL_TYPE, - CVP_VOCPROC_STATIC_COL_CAL_TYPE, - CVP_VOCPROC_DYNAMIC_COL_CAL_TYPE, - CVS_VOCSTRM_STATIC_COL_CAL_TYPE, - - ADM_TOPOLOGY_CAL_TYPE, - ADM_CUST_TOPOLOGY_CAL_TYPE, - ADM_AUDPROC_CAL_TYPE, - ADM_AUDVOL_CAL_TYPE, - - ASM_TOPOLOGY_CAL_TYPE, - ASM_CUST_TOPOLOGY_CAL_TYPE, - ASM_AUDSTRM_CAL_TYPE, - - AFE_COMMON_RX_CAL_TYPE, - AFE_COMMON_TX_CAL_TYPE, - AFE_ANC_CAL_TYPE, - AFE_AANC_CAL_TYPE, - AFE_FB_SPKR_PROT_CAL_TYPE, - AFE_HW_DELAY_CAL_TYPE, - AFE_SIDETONE_CAL_TYPE, - AFE_TOPOLOGY_CAL_TYPE, - AFE_CUST_TOPOLOGY_CAL_TYPE, - - LSM_CUST_TOPOLOGY_CAL_TYPE, - LSM_TOPOLOGY_CAL_TYPE, - LSM_CAL_TYPE, - - ADM_RTAC_INFO_CAL_TYPE, - VOICE_RTAC_INFO_CAL_TYPE, - ADM_RTAC_APR_CAL_TYPE, - ASM_RTAC_APR_CAL_TYPE, - VOICE_RTAC_APR_CAL_TYPE, - - MAD_CAL_TYPE, - ULP_AFE_CAL_TYPE, - ULP_LSM_CAL_TYPE, - - DTS_EAGLE_CAL_TYPE, - AUDIO_CORE_METAINFO_CAL_TYPE, - SRS_TRUMEDIA_CAL_TYPE, - - CORE_CUSTOM_TOPOLOGIES_CAL_TYPE, - ADM_RTAC_AUDVOL_CAL_TYPE, - - ULP_LSM_TOPOLOGY_ID_CAL_TYPE, - AFE_FB_SPKR_PROT_TH_VI_CAL_TYPE, - AFE_FB_SPKR_PROT_EX_VI_CAL_TYPE, - AFE_SIDETONE_IIR_CAL_TYPE, - AFE_LSM_TOPOLOGY_CAL_TYPE, - AFE_LSM_TX_CAL_TYPE, - ADM_LSM_TOPOLOGY_CAL_TYPE, - ADM_LSM_AUDPROC_CAL_TYPE, - MAX_CAL_TYPES, -}; - -#define AFE_FB_SPKR_PROT_TH_VI_CAL_TYPE AFE_FB_SPKR_PROT_TH_VI_CAL_TYPE -#define AFE_FB_SPKR_PROT_EX_VI_CAL_TYPE AFE_FB_SPKR_PROT_EX_VI_CAL_TYPE - -#define AFE_SIDETONE_IIR_CAL_TYPE AFE_SIDETONE_IIR_CAL_TYPE - -#define AFE_LSM_TOPOLOGY_CAL_TYPE AFE_LSM_TOPOLOGY_CAL_TYPE -#define AFE_LSM_TX_CAL_TYPE AFE_LSM_TX_CAL_TYPE -#define ADM_LSM_TOPOLOGY_CAL_TYPE ADM_LSM_TOPOLOGY_CAL_TYPE -#define ADM_LSM_AUDPROC_CAL_TYPE ADM_LSM_AUDPROC_CAL_TYPE -#define LSM_CAL_TYPES - -#define TOPOLOGY_SPECIFIC_CHANNEL_INFO -#define MSM_SPKR_PROT_SPV3 - -enum { - VERSION_0_0, -}; - -enum { - PER_VOCODER_CAL_BIT_MASK = 0x10000, -}; - -#define MAX_IOCTL_CMD_SIZE 512 - -/* common structures */ - -struct audio_cal_header { - int32_t data_size; - int32_t version; - int32_t cal_type; - int32_t cal_type_size; -}; - -struct audio_cal_type_header { - int32_t version; - int32_t buffer_number; -}; - -struct audio_cal_data { - /* Size of cal data at mem_handle allocation or at vaddr */ - int32_t cal_size; - /* If mem_handle if shared memory is used*/ - int32_t mem_handle; - /* size of virtual memory if shared memory not used */ -}; - - -/* AUDIO_ALLOCATE_CALIBRATION */ -struct audio_cal_type_alloc { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; -}; - -struct audio_cal_alloc { - struct audio_cal_header hdr; - struct audio_cal_type_alloc cal_type; -}; - - -/* AUDIO_DEALLOCATE_CALIBRATION */ -struct audio_cal_type_dealloc { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; -}; - -struct audio_cal_dealloc { - struct audio_cal_header hdr; - struct audio_cal_type_dealloc cal_type; -}; - - -/* AUDIO_PREPARE_CALIBRATION */ -struct audio_cal_type_prepare { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; -}; - -struct audio_cal_prepare { - struct audio_cal_header hdr; - struct audio_cal_type_prepare cal_type; -}; - - -/* AUDIO_POST_CALIBRATION */ -struct audio_cal_type_post { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; -}; - -struct audio_cal_post { - struct audio_cal_header hdr; - struct audio_cal_type_post cal_type; -}; - -/*AUDIO_CORE_META_INFO */ - -struct audio_cal_info_metainfo { - uint32_t nKey; -}; - -/* Cal info types */ -enum { - RX_DEVICE, - TX_DEVICE, - MAX_PATH_TYPE -}; - -struct audio_cal_info_adm_top { - int32_t topology; - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t app_type; - int32_t sample_rate; -}; - -struct audio_cal_info_audproc { - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t app_type; - int32_t sample_rate; -}; - -struct audio_cal_info_audvol { - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t app_type; - int32_t vol_index; -}; - -struct audio_cal_info_afe { - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t sample_rate; -}; - -struct audio_cal_info_afe_top { - int32_t topology; - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t sample_rate; -}; - -struct audio_cal_info_asm_top { - int32_t topology; - int32_t app_type; -}; - -struct audio_cal_info_audstrm { - int32_t app_type; -}; - -struct audio_cal_info_aanc { - int32_t acdb_id; -}; - -#define MAX_HW_DELAY_ENTRIES 25 - -struct audio_cal_hw_delay_entry { - uint32_t sample_rate; - uint32_t delay_usec; -}; - -struct audio_cal_hw_delay_data { - uint32_t num_entries; - struct audio_cal_hw_delay_entry entry[MAX_HW_DELAY_ENTRIES]; -}; - -struct audio_cal_info_hw_delay { - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t property_type; - struct audio_cal_hw_delay_data data; -}; - -enum msm_spkr_prot_states { - MSM_SPKR_PROT_CALIBRATED, - MSM_SPKR_PROT_CALIBRATION_IN_PROGRESS, - MSM_SPKR_PROT_DISABLED, - MSM_SPKR_PROT_NOT_CALIBRATED, - MSM_SPKR_PROT_PRE_CALIBRATED, - MSM_SPKR_PROT_IN_FTM_MODE -}; -#define MSM_SPKR_PROT_IN_FTM_MODE MSM_SPKR_PROT_IN_FTM_MODE - -enum msm_spkr_count { - SP_V2_SPKR_1, - SP_V2_SPKR_2, - SP_V2_NUM_MAX_SPKRS -}; - -struct audio_cal_info_spk_prot_cfg { - int32_t r0[SP_V2_NUM_MAX_SPKRS]; - int32_t t0[SP_V2_NUM_MAX_SPKRS]; - uint32_t quick_calib_flag; - uint32_t mode; - /* - * 0 - Start spk prot - * 1 - Start calib - * 2 - Disable spk prot - */ -#ifdef MSM_SPKR_PROT_SPV3 - uint32_t sp_version; - int32_t limiter_th[SP_V2_NUM_MAX_SPKRS]; -#endif -}; - -struct audio_cal_info_sp_th_vi_ftm_cfg { - uint32_t wait_time[SP_V2_NUM_MAX_SPKRS]; - uint32_t ftm_time[SP_V2_NUM_MAX_SPKRS]; - uint32_t mode; - /* - * 0 - normal running mode - * 1 - Calibration - * 2 - FTM mode - */ -}; - -struct audio_cal_info_sp_ex_vi_ftm_cfg { - uint32_t wait_time[SP_V2_NUM_MAX_SPKRS]; - uint32_t ftm_time[SP_V2_NUM_MAX_SPKRS]; - uint32_t mode; - /* - * 0 - normal running mode - * 2 - FTM mode - */ -}; - -struct audio_cal_info_sp_ex_vi_param { - int32_t freq_q20[SP_V2_NUM_MAX_SPKRS]; - int32_t resis_q24[SP_V2_NUM_MAX_SPKRS]; - int32_t qmct_q24[SP_V2_NUM_MAX_SPKRS]; - int32_t status[SP_V2_NUM_MAX_SPKRS]; -}; - -struct audio_cal_info_sp_th_vi_param { - int32_t r_dc_q24[SP_V2_NUM_MAX_SPKRS]; - int32_t temp_q22[SP_V2_NUM_MAX_SPKRS]; - int32_t status[SP_V2_NUM_MAX_SPKRS]; -}; - -struct audio_cal_info_msm_spk_prot_status { - int32_t r0[SP_V2_NUM_MAX_SPKRS]; - int32_t status; -}; - -struct audio_cal_info_sidetone { - uint16_t enable; - uint16_t gain; - int32_t tx_acdb_id; - int32_t rx_acdb_id; - int32_t mid; - int32_t pid; -}; - -#define MAX_SIDETONE_IIR_DATA_SIZE 224 -#define MAX_NO_IIR_FILTER_STAGE 10 - -struct audio_cal_info_sidetone_iir { - uint16_t iir_enable; - uint16_t num_biquad_stages; - uint16_t pregain; - int32_t tx_acdb_id; - int32_t rx_acdb_id; - int32_t mid; - int32_t pid; - uint8_t iir_config[MAX_SIDETONE_IIR_DATA_SIZE]; -}; -struct audio_cal_info_lsm_top { - int32_t topology; - int32_t acdb_id; - int32_t app_type; -}; - - -struct audio_cal_info_lsm { - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t app_type; -}; - -#define VSS_NUM_CHANNELS_MAX 8 - -struct audio_cal_info_voc_top { - int32_t topology; - int32_t acdb_id; -#ifdef TOPOLOGY_SPECIFIC_CHANNEL_INFO - uint32_t num_channels; - uint8_t channel_mapping[VSS_NUM_CHANNELS_MAX]; -#endif -}; - -struct audio_cal_info_vocproc { - int32_t tx_acdb_id; - int32_t rx_acdb_id; - int32_t tx_sample_rate; - int32_t rx_sample_rate; -}; - -enum { - DEFAULT_FEATURE_SET, - VOL_BOOST_FEATURE_SET, -}; - -struct audio_cal_info_vocvol { - int32_t tx_acdb_id; - int32_t rx_acdb_id; - /* DEFAULT_ or VOL_BOOST_FEATURE_SET */ - int32_t feature_set; -}; - -struct audio_cal_info_vocdev_cfg { - int32_t tx_acdb_id; - int32_t rx_acdb_id; -}; - -#define MAX_VOICE_COLUMNS 20 - -union audio_cal_col_na { - uint8_t val8; - uint16_t val16; - uint32_t val32; - uint64_t val64; -} __attribute__((packed)); - -struct audio_cal_col { - uint32_t id; - uint32_t type; - union audio_cal_col_na na_value; -} __attribute__((packed)); - -struct audio_cal_col_data { - uint32_t num_columns; - struct audio_cal_col column[MAX_VOICE_COLUMNS]; -} __attribute__((packed)); - -struct audio_cal_info_voc_col { - int32_t table_id; - int32_t tx_acdb_id; - int32_t rx_acdb_id; - struct audio_cal_col_data data; -}; - -/* AUDIO_SET_CALIBRATION & */ -struct audio_cal_type_basic { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; -}; - -struct audio_cal_basic { - struct audio_cal_header hdr; - struct audio_cal_type_basic cal_type; -}; - -struct audio_cal_type_adm_top { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_adm_top cal_info; -}; - -struct audio_cal_adm_top { - struct audio_cal_header hdr; - struct audio_cal_type_adm_top cal_type; -}; - -struct audio_cal_type_metainfo { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_metainfo cal_info; -}; - -struct audio_core_metainfo { - struct audio_cal_header hdr; - struct audio_cal_type_metainfo cal_type; -}; - -struct audio_cal_type_audproc { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_audproc cal_info; -}; - -struct audio_cal_audproc { - struct audio_cal_header hdr; - struct audio_cal_type_audproc cal_type; -}; - -struct audio_cal_type_audvol { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_audvol cal_info; -}; - -struct audio_cal_audvol { - struct audio_cal_header hdr; - struct audio_cal_type_audvol cal_type; -}; - -struct audio_cal_type_asm_top { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_asm_top cal_info; -}; - -struct audio_cal_asm_top { - struct audio_cal_header hdr; - struct audio_cal_type_asm_top cal_type; -}; - -struct audio_cal_type_audstrm { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_audstrm cal_info; -}; - -struct audio_cal_audstrm { - struct audio_cal_header hdr; - struct audio_cal_type_audstrm cal_type; -}; - -struct audio_cal_type_afe { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_afe cal_info; -}; - -struct audio_cal_afe { - struct audio_cal_header hdr; - struct audio_cal_type_afe cal_type; -}; - -struct audio_cal_type_afe_top { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_afe_top cal_info; -}; - -struct audio_cal_afe_top { - struct audio_cal_header hdr; - struct audio_cal_type_afe_top cal_type; -}; - -struct audio_cal_type_aanc { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_aanc cal_info; -}; - -struct audio_cal_aanc { - struct audio_cal_header hdr; - struct audio_cal_type_aanc cal_type; -}; - -struct audio_cal_type_fb_spk_prot_cfg { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_spk_prot_cfg cal_info; -}; - -struct audio_cal_fb_spk_prot_cfg { - struct audio_cal_header hdr; - struct audio_cal_type_fb_spk_prot_cfg cal_type; -}; - -struct audio_cal_type_sp_th_vi_ftm_cfg { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_sp_th_vi_ftm_cfg cal_info; -}; - -struct audio_cal_sp_th_vi_ftm_cfg { - struct audio_cal_header hdr; - struct audio_cal_type_sp_th_vi_ftm_cfg cal_type; -}; - -struct audio_cal_type_sp_ex_vi_ftm_cfg { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_sp_ex_vi_ftm_cfg cal_info; -}; - -struct audio_cal_sp_ex_vi_ftm_cfg { - struct audio_cal_header hdr; - struct audio_cal_type_sp_ex_vi_ftm_cfg cal_type; -}; -struct audio_cal_type_hw_delay { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_hw_delay cal_info; -}; - -struct audio_cal_hw_delay { - struct audio_cal_header hdr; - struct audio_cal_type_hw_delay cal_type; -}; - -struct audio_cal_type_sidetone { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_sidetone cal_info; -}; - -struct audio_cal_sidetone { - struct audio_cal_header hdr; - struct audio_cal_type_sidetone cal_type; -}; - -struct audio_cal_type_sidetone_iir { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_sidetone_iir cal_info; -}; - -struct audio_cal_sidetone_iir { - struct audio_cal_header hdr; - struct audio_cal_type_sidetone_iir cal_type; -}; - -struct audio_cal_type_lsm_top { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_lsm_top cal_info; -}; - -struct audio_cal_lsm_top { - struct audio_cal_header hdr; - struct audio_cal_type_lsm_top cal_type; -}; - -struct audio_cal_type_lsm { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_lsm cal_info; -}; - -struct audio_cal_lsm { - struct audio_cal_header hdr; - struct audio_cal_type_lsm cal_type; -}; - -struct audio_cal_type_voc_top { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_voc_top cal_info; -}; - -struct audio_cal_voc_top { - struct audio_cal_header hdr; - struct audio_cal_type_voc_top cal_type; -}; - -struct audio_cal_type_vocproc { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_vocproc cal_info; -}; - -struct audio_cal_vocproc { - struct audio_cal_header hdr; - struct audio_cal_type_vocproc cal_type; -}; - -struct audio_cal_type_vocvol { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_vocvol cal_info; -}; - -struct audio_cal_vocvol { - struct audio_cal_header hdr; - struct audio_cal_type_vocvol cal_type; -}; - -struct audio_cal_type_vocdev_cfg { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_vocdev_cfg cal_info; -}; - -struct audio_cal_vocdev_cfg { - struct audio_cal_header hdr; - struct audio_cal_type_vocdev_cfg cal_type; -}; - -struct audio_cal_type_voc_col { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_voc_col cal_info; -}; - -struct audio_cal_voc_col { - struct audio_cal_header hdr; - struct audio_cal_type_voc_col cal_type; -}; - -/* AUDIO_GET_CALIBRATION */ -struct audio_cal_type_fb_spk_prot_status { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_msm_spk_prot_status cal_info; -}; - -struct audio_cal_fb_spk_prot_status { - struct audio_cal_header hdr; - struct audio_cal_type_fb_spk_prot_status cal_type; -}; - -struct audio_cal_type_sp_th_vi_param { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_sp_th_vi_param cal_info; -}; - -struct audio_cal_sp_th_vi_param { - struct audio_cal_header hdr; - struct audio_cal_type_sp_th_vi_param cal_type; -}; -struct audio_cal_type_sp_ex_vi_param { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_sp_ex_vi_param cal_info; -}; - -struct audio_cal_sp_ex_vi_param { - struct audio_cal_header hdr; - struct audio_cal_type_sp_ex_vi_param cal_type; -}; -#endif /* _MSM_AUDIO_CALIBRATION_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_g711.h b/sdm710/kernel-headers/linux/msm_audio_g711.h deleted file mode 100644 index 658c1a59..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_g711.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _MSM_AUDIO_G711_H -#define _MSM_AUDIO_G711_H - -#include <linux/msm_audio.h> - -struct msm_audio_g711_enc_config { - uint32_t sample_rate; -}; - -#define AUDIO_SET_G711_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_g711_enc_config) - -#define AUDIO_GET_G711_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_g711_enc_config) - - -#endif /* _MSM_AUDIO_G711_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_g711_dec.h b/sdm710/kernel-headers/linux/msm_audio_g711_dec.h deleted file mode 100644 index a597a94f..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_g711_dec.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _MSM_AUDIO_G711_H -#define _MSM_AUDIO_G711_H - -#include <linux/msm_audio.h> - -struct msm_audio_g711_dec_config { - uint32_t sample_rate; -}; - -#define AUDIO_SET_G711_DEC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_g711_dec_config) - -#define AUDIO_GET_G711_DEC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_g711_dec_config) - -#endif /* _MSM_AUDIO_G711_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_mvs.h b/sdm710/kernel-headers/linux/msm_audio_mvs.h deleted file mode 100644 index 36d3b55b..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_mvs.h +++ /dev/null @@ -1,155 +0,0 @@ -#ifndef _MSM_AUDIO_MVS_H -#define _MSM_AUDIO_MVS_H - -#include <linux/msm_audio.h> - -#define AUDIO_GET_MVS_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM + 0), unsigned int) -#define AUDIO_SET_MVS_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM + 1), unsigned int) - -/* MVS modes */ -#define MVS_MODE_IS733 0x1 /*QCELP 13K*/ -#define MVS_MODE_IS127 0x2 /*EVRC-8k*/ -#define MVS_MODE_4GV_NB 0x3 /*EVRC-B*/ -#define MVS_MODE_4GV_WB 0x4 /*EVRC-WB*/ -#define MVS_MODE_AMR 0x5 -#define MVS_MODE_EFR 0x6 -#define MVS_MODE_FR 0x7 -#define MVS_MODE_HR 0x8 -#define MVS_MODE_LINEAR_PCM 0x9 -#define MVS_MODE_G711 0xA -#define MVS_MODE_PCM 0xC -#define MVS_MODE_AMR_WB 0xD -#define MVS_MODE_G729A 0xE -#define MVS_MODE_G711A 0xF -#define MVS_MODE_G722 0x10 -#define MVS_MODE_PCM_WB 0x12 - -enum msm_audio_amr_mode { - MVS_AMR_MODE_0475, /* AMR 4.75 kbps */ - MVS_AMR_MODE_0515, /* AMR 5.15 kbps */ - MVS_AMR_MODE_0590, /* AMR 5.90 kbps */ - MVS_AMR_MODE_0670, /* AMR 6.70 kbps */ - MVS_AMR_MODE_0740, /* AMR 7.40 kbps */ - MVS_AMR_MODE_0795, /* AMR 7.95 kbps */ - MVS_AMR_MODE_1020, /* AMR 10.20 kbps */ - MVS_AMR_MODE_1220, /* AMR 12.20 kbps */ - MVS_AMR_MODE_0660, /* AMR-WB 6.60 kbps */ - MVS_AMR_MODE_0885, /* AMR-WB 8.85 kbps */ - MVS_AMR_MODE_1265, /* AMR-WB 12.65 kbps */ - MVS_AMR_MODE_1425, /* AMR-WB 14.25 kbps */ - MVS_AMR_MODE_1585, /* AMR-WB 15.85 kbps */ - MVS_AMR_MODE_1825, /* AMR-WB 18.25 kbps */ - MVS_AMR_MODE_1985, /* AMR-WB 19.85 kbps */ - MVS_AMR_MODE_2305, /* AMR-WB 23.05 kbps */ - MVS_AMR_MODE_2385, /* AMR-WB 23.85 kbps */ - MVS_AMR_MODE_UNDEF -}; - -/* The MVS VOC rate type is used to identify the rate of QCELP 13K(IS733), - * EVRC(IS127), 4GV, or 4GV-WB frame. - */ -enum msm_audio_voc_rate { - MVS_VOC_0_RATE, /* Blank frame */ - MVS_VOC_8_RATE, /* 1/8 rate */ - MVS_VOC_4_RATE, /* 1/4 rate */ - MVS_VOC_2_RATE, /* 1/2 rate */ - MVS_VOC_1_RATE, /* Full rate */ - MVS_VOC_ERASURE, /* erasure frame */ - MVS_VOC_RATE_MAX, - MVS_VOC_RATE_UNDEF = MVS_VOC_RATE_MAX -}; - -enum msm_audio_amr_frame_type { - MVS_AMR_SPEECH_GOOD, /* Good speech frame */ - MVS_AMR_SPEECH_DEGRADED, /* Speech degraded */ - MVS_AMR_ONSET, /* Onset */ - MVS_AMR_SPEECH_BAD, /* Corrupt speech frame (bad CRC) */ - MVS_AMR_SID_FIRST, /* First silence descriptor */ - MVS_AMR_SID_UPDATE, /* Comfort noise frame */ - MVS_AMR_SID_BAD, /* Corrupt SID frame (bad CRC) */ - MVS_AMR_NO_DATA, /* Nothing to transmit */ - MVS_AMR_SPEECH_LOST /* Downlink speech lost */ -}; - -enum msm_audio_g711a_mode { - MVS_G711A_MODE_MULAW, - MVS_G711A_MODE_ALAW -}; - -enum msm_audio_g711_mode { - MVS_G711_MODE_MULAW, - MVS_G711_MODE_ALAW -}; - -enum mvs_g722_mode_type { - MVS_G722_MODE_01, - MVS_G722_MODE_02, - MVS_G722_MODE_03, - MVS_G722_MODE_MAX, - MVS_G722_MODE_UNDEF -}; - -enum msm_audio_g711a_frame_type { - MVS_G711A_SPEECH_GOOD, - MVS_G711A_SID, - MVS_G711A_NO_DATA, - MVS_G711A_ERASURE -}; - -enum msm_audio_g729a_frame_type { - MVS_G729A_NO_DATA, - MVS_G729A_SPEECH_GOOD, - MVS_G729A_SID, - MVS_G729A_ERASURE -}; - -struct min_max_rate { - uint32_t min_rate; - uint32_t max_rate; -}; - -struct msm_audio_mvs_config { - uint32_t mvs_mode; - uint32_t rate_type; - struct min_max_rate min_max_rate; - uint32_t dtx_mode; -}; - -#define MVS_MAX_VOC_PKT_SIZE 640 - -struct gsm_header { - uint8_t bfi; - uint8_t sid; - uint8_t taf; - uint8_t ufi; -}; - -struct q6_msm_audio_mvs_frame { - union { - uint32_t frame_type; - uint32_t packet_rate; - struct gsm_header gsm_frame_type; - } header; - uint32_t len; - uint8_t voc_pkt[MVS_MAX_VOC_PKT_SIZE]; - -}; - -struct msm_audio_mvs_frame { - uint32_t frame_type; - uint32_t len; - uint8_t voc_pkt[MVS_MAX_VOC_PKT_SIZE]; - -}; - -#define Q5V2_MVS_MAX_VOC_PKT_SIZE 320 - -struct q5v2_msm_audio_mvs_frame { - uint32_t frame_type; - uint32_t len; - uint8_t voc_pkt[Q5V2_MVS_MAX_VOC_PKT_SIZE]; - -}; -#endif /* _MSM_AUDIO_MVS_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_qcp.h b/sdm710/kernel-headers/linux/msm_audio_qcp.h deleted file mode 100644 index de8552a2..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_qcp.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef _MSM_AUDIO_QCP_H -#define _MSM_AUDIO_QCP_H - -#include <linux/msm_audio.h> - -#define AUDIO_SET_QCELP_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - 0, struct msm_audio_qcelp_enc_config) - -#define AUDIO_GET_QCELP_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - 1, struct msm_audio_qcelp_enc_config) - -#define AUDIO_SET_EVRC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - 2, struct msm_audio_evrc_enc_config) - -#define AUDIO_GET_EVRC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - 3, struct msm_audio_evrc_enc_config) - -#define CDMA_RATE_BLANK 0x00 -#define CDMA_RATE_EIGHTH 0x01 -#define CDMA_RATE_QUARTER 0x02 -#define CDMA_RATE_HALF 0x03 -#define CDMA_RATE_FULL 0x04 -#define CDMA_RATE_ERASURE 0x05 - -struct msm_audio_qcelp_enc_config { - uint32_t cdma_rate; - uint32_t min_bit_rate; - uint32_t max_bit_rate; -}; - -struct msm_audio_evrc_enc_config { - uint32_t cdma_rate; - uint32_t min_bit_rate; - uint32_t max_bit_rate; -}; - -#endif /* _MSM_AUDIO_QCP_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_sbc.h b/sdm710/kernel-headers/linux/msm_audio_sbc.h deleted file mode 100644 index 206b183c..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_sbc.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef _MSM_AUDIO_SBC_H -#define _MSM_AUDIO_SBC_H - -#include <linux/msm_audio.h> - -#define AUDIO_SET_SBC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_sbc_enc_config) - -#define AUDIO_GET_SBC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_sbc_enc_config) - -#define AUDIO_SBC_BA_LOUDNESS 0x0 -#define AUDIO_SBC_BA_SNR 0x1 - -#define AUDIO_SBC_MODE_MONO 0x0 -#define AUDIO_SBC_MODE_DUAL 0x1 -#define AUDIO_SBC_MODE_STEREO 0x2 -#define AUDIO_SBC_MODE_JSTEREO 0x3 - -#define AUDIO_SBC_BANDS_8 0x1 - -#define AUDIO_SBC_BLOCKS_4 0x0 -#define AUDIO_SBC_BLOCKS_8 0x1 -#define AUDIO_SBC_BLOCKS_12 0x2 -#define AUDIO_SBC_BLOCKS_16 0x3 - -struct msm_audio_sbc_enc_config { - uint32_t channels; - uint32_t sample_rate; - uint32_t bit_allocation; - uint32_t number_of_subbands; - uint32_t number_of_blocks; - uint32_t bit_rate; - uint32_t mode; -}; -#endif /* _MSM_AUDIO_SBC_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_voicememo.h b/sdm710/kernel-headers/linux/msm_audio_voicememo.h deleted file mode 100644 index 50e1696f..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_voicememo.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef _MSM_AUDIO_VOICEMEMO_H -#define _MSM_AUDIO_VOICEMEMO_H - -#include <linux/msm_audio.h> - -#define AUDIO_GET_VOICEMEMO_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned int) -#define AUDIO_SET_VOICEMEMO_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned int) - -/* rec_type */ -enum rpc_voc_rec_dir_type { - RPC_VOC_REC_NONE, - RPC_VOC_REC_FORWARD, - RPC_VOC_REC_REVERSE, - RPC_VOC_REC_BOTH, - RPC_VOC_MAX_REC_TYPE -}; - -/* capability */ -enum rpc_voc_capability_type { - RPC_VOC_CAP_IS733 = 4, - RPC_VOC_CAP_IS127 = 8, - RPC_VOC_CAP_AMR = 64, - RPC_VOC_CAP_32BIT_DUMMY = 2147483647 -}; - -/* Rate */ -enum rpc_voc_rate_type { - RPC_VOC_0_RATE = 0, - RPC_VOC_8_RATE, - RPC_VOC_4_RATE, - RPC_VOC_2_RATE, - RPC_VOC_1_RATE, - RPC_VOC_ERASURE, - RPC_VOC_ERR_RATE, - RPC_VOC_AMR_RATE_475 = 0, - RPC_VOC_AMR_RATE_515 = 1, - RPC_VOC_AMR_RATE_590 = 2, - RPC_VOC_AMR_RATE_670 = 3, - RPC_VOC_AMR_RATE_740 = 4, - RPC_VOC_AMR_RATE_795 = 5, - RPC_VOC_AMR_RATE_1020 = 6, - RPC_VOC_AMR_RATE_1220 = 7, -}; - -/* frame_format */ -enum rpc_voc_pb_len_rate_var_type { - RPC_VOC_PB_NATIVE_QCP = 3, - RPC_VOC_PB_AMR, - RPC_VOC_PB_EVB -}; - -struct msm_audio_voicememo_config { - uint32_t rec_type; - uint32_t rec_interval_ms; - uint32_t auto_stop_ms; - uint32_t capability; - uint32_t max_rate; - uint32_t min_rate; - uint32_t frame_format; - uint32_t dtx_enable; - uint32_t data_req_ms; -}; - -#endif /* _MSM_AUDIO_VOICEMEMO_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_wma.h b/sdm710/kernel-headers/linux/msm_audio_wma.h deleted file mode 100644 index 8f46f2c6..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_wma.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef _MSM_AUDIO_WMA_H -#define _MSM_AUDIO_WMA_H - -#define AUDIO_GET_WMA_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned int) -#define AUDIO_SET_WMA_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned int) - -#define AUDIO_GET_WMA_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+2), struct msm_audio_wma_config_v2) -#define AUDIO_SET_WMA_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_wma_config_v2) - -struct msm_audio_wma_config { - unsigned short armdatareqthr; - unsigned short channelsdecoded; - unsigned short wmabytespersec; - unsigned short wmasamplingfreq; - unsigned short wmaencoderopts; -}; - -struct msm_audio_wma_config_v2 { - unsigned short format_tag; - unsigned short numchannels; - uint32_t samplingrate; - uint32_t avgbytespersecond; - unsigned short block_align; - unsigned short validbitspersample; - uint32_t channelmask; - unsigned short encodeopt; -}; - -#endif /* _MSM_AUDIO_WMA_H */ diff --git a/sdm710/kernel-headers/linux/msm_audio_wmapro.h b/sdm710/kernel-headers/linux/msm_audio_wmapro.h deleted file mode 100644 index 7559a877..00000000 --- a/sdm710/kernel-headers/linux/msm_audio_wmapro.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef _MSM_AUDIO_WMAPRO_H -#define _MSM_AUDIO_WMAPRO_H - -#define AUDIO_GET_WMAPRO_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_wmapro_config) -#define AUDIO_SET_WMAPRO_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_wmapro_config) - -struct msm_audio_wmapro_config { - unsigned short armdatareqthr; - uint8_t validbitspersample; - uint8_t numchannels; - unsigned short formattag; - uint32_t samplingrate; - uint32_t avgbytespersecond; - unsigned short asfpacketlength; - uint32_t channelmask; - unsigned short encodeopt; - unsigned short advancedencodeopt; - uint32_t advancedencodeopt2; -}; -#endif /* _MSM_AUDIO_WMAPRO_H */ diff --git a/sdm710/kernel-headers/linux/msm_dsps.h b/sdm710/kernel-headers/linux/msm_dsps.h deleted file mode 100644 index 7e04490c..00000000 --- a/sdm710/kernel-headers/linux/msm_dsps.h +++ /dev/null @@ -1,29 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _DSPS_H_ -#define _DSPS_H_ -#include <linux/ioctl.h> -#define DSPS_IOCTL_MAGIC 'd' -#define DSPS_IOCTL_ON _IO(DSPS_IOCTL_MAGIC, 1) -#define DSPS_IOCTL_OFF _IO(DSPS_IOCTL_MAGIC, 2) -#define DSPS_IOCTL_READ_SLOW_TIMER _IOR(DSPS_IOCTL_MAGIC, 3, unsigned int *) -#define DSPS_IOCTL_READ_FAST_TIMER _IOR(DSPS_IOCTL_MAGIC, 4, unsigned int *) -#define DSPS_IOCTL_RESET _IO(DSPS_IOCTL_MAGIC, 5) -#endif - diff --git a/sdm710/kernel-headers/linux/msm_ion.h b/sdm710/kernel-headers/linux/msm_ion.h deleted file mode 100644 index 4f4399da..00000000 --- a/sdm710/kernel-headers/linux/msm_ion.h +++ /dev/null @@ -1,138 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _MSM_ION_H -#define _MSM_ION_H -#include "ion.h" -#define ION_BIT(nr) (1UL << (nr)) -enum msm_ion_heap_types { - ION_HEAP_TYPE_MSM_START = ION_HEAP_TYPE_CUSTOM + 1, - ION_HEAP_TYPE_SECURE_DMA = ION_HEAP_TYPE_MSM_START, - ION_HEAP_TYPE_SYSTEM_SECURE, - ION_HEAP_TYPE_HYP_CMA, - ION_HEAP_TYPE_SECURE_CARVEOUT, -}; -enum ion_heap_ids { - INVALID_HEAP_ID = - 1, - ION_CP_MM_HEAP_ID = 8, - ION_SECURE_HEAP_ID = 9, - ION_SECURE_DISPLAY_HEAP_ID = 10, - ION_CP_MFC_HEAP_ID = 12, - ION_SPSS_HEAP_ID = 13, - ION_SECURE_CARVEOUT_HEAP_ID = 14, - ION_CP_WB_HEAP_ID = 16, - ION_QSECOM_TA_HEAP_ID = 19, - ION_CAMERA_HEAP_ID = 20, - ION_SYSTEM_CONTIG_HEAP_ID = 21, - ION_ADSP_HEAP_ID = 22, - ION_PIL1_HEAP_ID = 23, - ION_SF_HEAP_ID = 24, - ION_SYSTEM_HEAP_ID = 25, - ION_PIL2_HEAP_ID = 26, - ION_QSECOM_HEAP_ID = 27, - ION_AUDIO_HEAP_ID = 28, - ION_MM_FIRMWARE_HEAP_ID = 29, - ION_GOOGLE_HEAP_ID = 30, - ION_HEAP_ID_RESERVED = 31 -}; -#define ION_IOMMU_HEAP_ID ION_SYSTEM_HEAP_ID -#define ION_HEAP_TYPE_IOMMU ION_HEAP_TYPE_SYSTEM -#define ION_SPSS_HEAP_ID ION_SPSS_HEAP_ID -enum ion_fixed_position { - NOT_FIXED, - FIXED_LOW, - FIXED_MIDDLE, - FIXED_HIGH, -}; -enum cp_mem_usage { - VIDEO_BITSTREAM = 0x1, - VIDEO_PIXEL = 0x2, - VIDEO_NONPIXEL = 0x3, - DISPLAY_SECURE_CP_USAGE = 0x4, - CAMERA_SECURE_CP_USAGE = 0x5, - MAX_USAGE = 0x6, - UNKNOWN = 0x7FFFFFFF, -}; -#define ION_FLAG_CP_TOUCH ION_BIT(17) -#define ION_FLAG_CP_BITSTREAM ION_BIT(18) -#define ION_FLAG_CP_PIXEL ION_BIT(19) -#define ION_FLAG_CP_NON_PIXEL ION_BIT(20) -#define ION_FLAG_CP_CAMERA ION_BIT(21) -#define ION_FLAG_CP_HLOS ION_BIT(22) -#define ION_FLAG_CP_SPSS_SP ION_BIT(23) -#define ION_FLAG_CP_SPSS_SP_SHARED ION_BIT(24) -#define ION_FLAG_CP_SEC_DISPLAY ION_BIT(25) -#define ION_FLAG_CP_APP ION_BIT(26) -#define ION_FLAG_CP_CAMERA_PREVIEW ION_BIT(27) -#define ION_FLAG_CP_CDSP ION_BIT(29) -#define ION_FLAG_CP_SPSS_HLOS_SHARED ION_BIT(30) -#define ION_FLAG_ALLOW_NON_CONTIG ION_BIT(28) -#define ION_FLAG_SECURE ION_BIT(ION_HEAP_ID_RESERVED) -#define ION_FLAG_POOL_FORCE_ALLOC ION_BIT(16) -#define ION_SECURE ION_FLAG_SECURE -#define ION_HEAP(bit) ION_BIT(bit) -#define ION_ADSP_HEAP_NAME "adsp" -#define ION_SYSTEM_HEAP_NAME "system" -#define ION_VMALLOC_HEAP_NAME ION_SYSTEM_HEAP_NAME -#define ION_KMALLOC_HEAP_NAME "kmalloc" -#define ION_AUDIO_HEAP_NAME "audio" -#define ION_SF_HEAP_NAME "sf" -#define ION_MM_HEAP_NAME "mm" -#define ION_CAMERA_HEAP_NAME "camera_preview" -#define ION_IOMMU_HEAP_NAME "iommu" -#define ION_MFC_HEAP_NAME "mfc" -#define ION_SPSS_HEAP_NAME "spss" -#define ION_SECURE_CARVEOUT_HEAP_NAME "secure_carveout" -#define ION_WB_HEAP_NAME "wb" -#define ION_MM_FIRMWARE_HEAP_NAME "mm_fw" -#define ION_GOOGLE_HEAP_NAME "easel_mem" -#define ION_PIL1_HEAP_NAME "pil_1" -#define ION_PIL2_HEAP_NAME "pil_2" -#define ION_QSECOM_HEAP_NAME "qsecom" -#define ION_QSECOM_TA_HEAP_NAME "qsecom_ta" -#define ION_SECURE_HEAP_NAME "secure_heap" -#define ION_SECURE_DISPLAY_HEAP_NAME "secure_display" -#define ION_SET_CACHED(__cache) ((__cache) | ION_FLAG_CACHED) -#define ION_SET_UNCACHED(__cache) ((__cache) & ~ION_FLAG_CACHED) -#define ION_IS_CACHED(__flags) ((__flags) & ION_FLAG_CACHED) -struct ion_flush_data { - ion_user_handle_t handle; - int fd; - void * vaddr; - unsigned int offset; - unsigned int length; -}; -struct ion_prefetch_regions { - unsigned int vmid; - size_t * sizes; - unsigned int nr_sizes; -}; -struct ion_prefetch_data { - int heap_id; - unsigned long len; - struct ion_prefetch_regions * regions; - unsigned int nr_regions; -}; -#define ION_IOC_MSM_MAGIC 'M' -#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MSM_MAGIC, 0, struct ion_flush_data) -#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 1, struct ion_flush_data) -#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 2, struct ion_flush_data) -#define ION_IOC_PREFETCH _IOWR(ION_IOC_MSM_MAGIC, 3, struct ion_prefetch_data) -#define ION_IOC_DRAIN _IOWR(ION_IOC_MSM_MAGIC, 4, struct ion_prefetch_data) -#endif - diff --git a/sdm710/kernel-headers/linux/msm_ipa.h b/sdm710/kernel-headers/linux/msm_ipa.h deleted file mode 100644 index 89e7eb0b..00000000 --- a/sdm710/kernel-headers/linux/msm_ipa.h +++ /dev/null @@ -1,969 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _MSM_IPA_H_ -#define _MSM_IPA_H_ -#include <stdint.h> -#include <stddef.h> -#include <sys/stat.h> -#include <linux/ioctl.h> -#include <linux/types.h> -#include <linux/if_ether.h> -#define IPA_IOC_MAGIC 0xCF -#define IPA_DEV_NAME "/dev/ipa" -#define IPA_NAT_DEV_NAME "ipaNatTable" -#define IPA_IPV6CT_DEV_NAME "ipaIpv6CTTable" -#define IPA_DFLT_RT_TBL_NAME "ipa_dflt_rt" -#define IPA_IOCTL_ADD_HDR 0 -#define IPA_IOCTL_DEL_HDR 1 -#define IPA_IOCTL_ADD_RT_RULE 2 -#define IPA_IOCTL_DEL_RT_RULE 3 -#define IPA_IOCTL_ADD_FLT_RULE 4 -#define IPA_IOCTL_DEL_FLT_RULE 5 -#define IPA_IOCTL_COMMIT_HDR 6 -#define IPA_IOCTL_RESET_HDR 7 -#define IPA_IOCTL_COMMIT_RT 8 -#define IPA_IOCTL_RESET_RT 9 -#define IPA_IOCTL_COMMIT_FLT 10 -#define IPA_IOCTL_RESET_FLT 11 -#define IPA_IOCTL_DUMP 12 -#define IPA_IOCTL_GET_RT_TBL 13 -#define IPA_IOCTL_PUT_RT_TBL 14 -#define IPA_IOCTL_COPY_HDR 15 -#define IPA_IOCTL_QUERY_INTF 16 -#define IPA_IOCTL_QUERY_INTF_TX_PROPS 17 -#define IPA_IOCTL_QUERY_INTF_RX_PROPS 18 -#define IPA_IOCTL_GET_HDR 19 -#define IPA_IOCTL_PUT_HDR 20 -#define IPA_IOCTL_SET_FLT 21 -#define IPA_IOCTL_ALLOC_NAT_MEM 22 -#define IPA_IOCTL_V4_INIT_NAT 23 -#define IPA_IOCTL_TABLE_DMA_CMD 24 -#define IPA_IOCTL_NAT_DMA IPA_IOCTL_TABLE_DMA_CMD -#define IPA_IOCTL_INIT_IPV6CT_TABLE 25 -#define IPA_IOCTL_V4_DEL_NAT 26 -#define IPA_IOCTL_PULL_MSG 27 -#define IPA_IOCTL_GET_NAT_OFFSET 28 -#define IPA_IOCTL_RM_ADD_DEPENDENCY 29 -#define IPA_IOCTL_RM_DEL_DEPENDENCY 30 -#define IPA_IOCTL_GENERATE_FLT_EQ 31 -#define IPA_IOCTL_QUERY_INTF_EXT_PROPS 32 -#define IPA_IOCTL_QUERY_EP_MAPPING 33 -#define IPA_IOCTL_QUERY_RT_TBL_INDEX 34 -#define IPA_IOCTL_WRITE_QMAPID 35 -#define IPA_IOCTL_MDFY_FLT_RULE 36 -#define IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_ADD 37 -#define IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_DEL 38 -#define IPA_IOCTL_NOTIFY_WAN_EMBMS_CONNECTED 39 -#define IPA_IOCTL_ADD_HDR_PROC_CTX 40 -#define IPA_IOCTL_DEL_HDR_PROC_CTX 41 -#define IPA_IOCTL_MDFY_RT_RULE 42 -#define IPA_IOCTL_ADD_RT_RULE_AFTER 43 -#define IPA_IOCTL_ADD_FLT_RULE_AFTER 44 -#define IPA_IOCTL_GET_HW_VERSION 45 -#define IPA_IOCTL_ADD_RT_RULE_EXT 46 -#define IPA_IOCTL_ADD_VLAN_IFACE 47 -#define IPA_IOCTL_DEL_VLAN_IFACE 48 -#define IPA_IOCTL_ADD_L2TP_VLAN_MAPPING 49 -#define IPA_IOCTL_DEL_L2TP_VLAN_MAPPING 50 -#define IPA_IOCTL_NAT_MODIFY_PDN 51 -#define IPA_IOCTL_ALLOC_NAT_TABLE 52 -#define IPA_IOCTL_ALLOC_IPV6CT_TABLE 53 -#define IPA_IOCTL_DEL_NAT_TABLE 54 -#define IPA_IOCTL_DEL_IPV6CT_TABLE 55 -#define IPA_IOCTL_CLEANUP 56 -#define IPA_IOCTL_QUERY_WLAN_CLIENT 57 -#define IPA_IOCTL_GET_VLAN_MODE 58 -#define IPA_HDR_MAX_SIZE 64 -#define IPA_RESOURCE_NAME_MAX 32 -#define IPA_NUM_PROPS_MAX 35 -#define IPA_MAC_ADDR_SIZE 6 -#define IPA_MBIM_MAX_STREAM_NUM 8 -#define IPA_WAN_MSG_IPv6_ADDR_GW_LEN 4 -#define IPA_MAX_NUM_HW_PATH_CLIENTS 16 -#define QMI_IPA_MAX_CLIENT_DST_PIPES 4 -#define IPA_FLT_TOS (1ul << 0) -#define IPA_FLT_PROTOCOL (1ul << 1) -#define IPA_FLT_SRC_ADDR (1ul << 2) -#define IPA_FLT_DST_ADDR (1ul << 3) -#define IPA_FLT_SRC_PORT_RANGE (1ul << 4) -#define IPA_FLT_DST_PORT_RANGE (1ul << 5) -#define IPA_FLT_TYPE (1ul << 6) -#define IPA_FLT_CODE (1ul << 7) -#define IPA_FLT_SPI (1ul << 8) -#define IPA_FLT_SRC_PORT (1ul << 9) -#define IPA_FLT_DST_PORT (1ul << 10) -#define IPA_FLT_TC (1ul << 11) -#define IPA_FLT_FLOW_LABEL (1ul << 12) -#define IPA_FLT_NEXT_HDR (1ul << 13) -#define IPA_FLT_META_DATA (1ul << 14) -#define IPA_FLT_FRAGMENT (1ul << 15) -#define IPA_FLT_TOS_MASKED (1ul << 16) -#define IPA_FLT_MAC_SRC_ADDR_ETHER_II (1ul << 17) -#define IPA_FLT_MAC_DST_ADDR_ETHER_II (1ul << 18) -#define IPA_FLT_MAC_SRC_ADDR_802_3 (1ul << 19) -#define IPA_FLT_MAC_DST_ADDR_802_3 (1ul << 20) -#define IPA_FLT_MAC_ETHER_TYPE (1ul << 21) -#define IPA_FLT_MAC_DST_ADDR_L2TP (1ul << 22) -#define IPA_FLT_TCP_SYN (1ul << 23) -#define IPA_FLT_TCP_SYN_L2TP (1ul << 24) -#define IPA_FLT_L2TP_INNER_IP_TYPE (1ul << 25) -#define IPA_FLT_L2TP_INNER_IPV4_DST_ADDR (1ul << 26) -#define IPA_MAX_PDN_NUM 5 -enum ipa_client_type { - IPA_CLIENT_HSIC1_PROD = 0, - IPA_CLIENT_HSIC1_CONS = 1, - IPA_CLIENT_HSIC2_PROD = 2, - IPA_CLIENT_HSIC2_CONS = 3, - IPA_CLIENT_HSIC3_PROD = 4, - IPA_CLIENT_HSIC3_CONS = 5, - IPA_CLIENT_HSIC4_PROD = 6, - IPA_CLIENT_HSIC4_CONS = 7, - IPA_CLIENT_HSIC5_PROD = 8, - IPA_CLIENT_HSIC5_CONS = 9, - IPA_CLIENT_WLAN1_PROD = 10, - IPA_CLIENT_WLAN1_CONS = 11, - IPA_CLIENT_A5_WLAN_AMPDU_PROD = 12, - IPA_CLIENT_WLAN2_CONS = 13, - IPA_CLIENT_WLAN3_CONS = 15, - IPA_CLIENT_WLAN4_CONS = 17, - IPA_CLIENT_USB_PROD = 18, - IPA_CLIENT_USB_CONS = 19, - IPA_CLIENT_USB2_PROD = 20, - IPA_CLIENT_USB2_CONS = 21, - IPA_CLIENT_USB3_PROD = 22, - IPA_CLIENT_USB3_CONS = 23, - IPA_CLIENT_USB4_PROD = 24, - IPA_CLIENT_USB4_CONS = 25, - IPA_CLIENT_UC_USB_PROD = 26, - IPA_CLIENT_USB_DPL_CONS = 27, - IPA_CLIENT_A2_EMBEDDED_PROD = 28, - IPA_CLIENT_A2_EMBEDDED_CONS = 29, - IPA_CLIENT_A2_TETHERED_PROD = 30, - IPA_CLIENT_A2_TETHERED_CONS = 31, - IPA_CLIENT_APPS_LAN_PROD = 32, - IPA_CLIENT_APPS_LAN_CONS = 33, - IPA_CLIENT_APPS_WAN_PROD = 34, - IPA_CLIENT_APPS_LAN_WAN_PROD = IPA_CLIENT_APPS_WAN_PROD, - IPA_CLIENT_APPS_WAN_CONS = 35, - IPA_CLIENT_APPS_CMD_PROD = 36, - IPA_CLIENT_A5_LAN_WAN_CONS = 37, - IPA_CLIENT_ODU_PROD = 38, - IPA_CLIENT_ODU_EMB_CONS = 39, - IPA_CLIENT_ODU_TETH_CONS = 41, - IPA_CLIENT_MHI_PROD = 42, - IPA_CLIENT_MHI_CONS = 43, - IPA_CLIENT_MEMCPY_DMA_SYNC_PROD = 44, - IPA_CLIENT_MEMCPY_DMA_SYNC_CONS = 45, - IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD = 46, - IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS = 47, - IPA_CLIENT_ETHERNET_PROD = 48, - IPA_CLIENT_ETHERNET_CONS = 49, - IPA_CLIENT_Q6_LAN_PROD = 50, - IPA_CLIENT_Q6_LAN_CONS = 51, - IPA_CLIENT_Q6_WAN_PROD = 52, - IPA_CLIENT_Q6_WAN_CONS = 53, - IPA_CLIENT_Q6_CMD_PROD = 54, - IPA_CLIENT_Q6_DUN_CONS = 55, - IPA_CLIENT_Q6_DECOMP_PROD = 56, - IPA_CLIENT_Q6_DECOMP_CONS = 57, - IPA_CLIENT_Q6_DECOMP2_PROD = 58, - IPA_CLIENT_Q6_DECOMP2_CONS = 59, - IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS = 61, - IPA_CLIENT_TEST_PROD = 62, - IPA_CLIENT_TEST_CONS = 63, - IPA_CLIENT_TEST1_PROD = 64, - IPA_CLIENT_TEST1_CONS = 65, - IPA_CLIENT_TEST2_PROD = 66, - IPA_CLIENT_TEST2_CONS = 67, - IPA_CLIENT_TEST3_PROD = 68, - IPA_CLIENT_TEST3_CONS = 69, - IPA_CLIENT_TEST4_PROD = 70, - IPA_CLIENT_TEST4_CONS = 71, - IPA_CLIENT_DUMMY_CONS = 73 -}; -#define IPA_CLIENT_MAX (IPA_CLIENT_DUMMY_CONS + 1) -#define IPA_CLIENT_IS_APPS_CONS(client) ((client) == IPA_CLIENT_APPS_LAN_CONS || (client) == IPA_CLIENT_APPS_WAN_CONS) -#define IPA_CLIENT_IS_USB_CONS(client) ((client) == IPA_CLIENT_USB_CONS || (client) == IPA_CLIENT_USB2_CONS || (client) == IPA_CLIENT_USB3_CONS || (client) == IPA_CLIENT_USB_DPL_CONS || (client) == IPA_CLIENT_USB4_CONS) -#define IPA_CLIENT_IS_WLAN_CONS(client) ((client) == IPA_CLIENT_WLAN1_CONS || (client) == IPA_CLIENT_WLAN2_CONS || (client) == IPA_CLIENT_WLAN3_CONS || (client) == IPA_CLIENT_WLAN4_CONS) -#define IPA_CLIENT_IS_ODU_CONS(client) ((client) == IPA_CLIENT_ODU_EMB_CONS || (client) == IPA_CLIENT_ODU_TETH_CONS) -#define IPA_CLIENT_IS_Q6_CONS(client) ((client) == IPA_CLIENT_Q6_LAN_CONS || (client) == IPA_CLIENT_Q6_WAN_CONS || (client) == IPA_CLIENT_Q6_DUN_CONS || (client) == IPA_CLIENT_Q6_DECOMP_CONS || (client) == IPA_CLIENT_Q6_DECOMP2_CONS || (client) == IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS) -#define IPA_CLIENT_IS_Q6_PROD(client) ((client) == IPA_CLIENT_Q6_LAN_PROD || (client) == IPA_CLIENT_Q6_WAN_PROD || (client) == IPA_CLIENT_Q6_CMD_PROD || (client) == IPA_CLIENT_Q6_DECOMP_PROD || (client) == IPA_CLIENT_Q6_DECOMP2_PROD) -#define IPA_CLIENT_IS_Q6_NON_ZIP_CONS(client) ((client) == IPA_CLIENT_Q6_LAN_CONS || (client) == IPA_CLIENT_Q6_WAN_CONS || (client) == IPA_CLIENT_Q6_DUN_CONS || (client) == IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS) -#define IPA_CLIENT_IS_Q6_ZIP_CONS(client) ((client) == IPA_CLIENT_Q6_DECOMP_CONS || (client) == IPA_CLIENT_Q6_DECOMP2_CONS) -#define IPA_CLIENT_IS_Q6_NON_ZIP_PROD(client) ((client) == IPA_CLIENT_Q6_LAN_PROD || (client) == IPA_CLIENT_Q6_WAN_PROD || (client) == IPA_CLIENT_Q6_CMD_PROD) -#define IPA_CLIENT_IS_Q6_ZIP_PROD(client) ((client) == IPA_CLIENT_Q6_DECOMP_PROD || (client) == IPA_CLIENT_Q6_DECOMP2_PROD) -#define IPA_CLIENT_IS_MEMCPY_DMA_CONS(client) ((client) == IPA_CLIENT_MEMCPY_DMA_SYNC_CONS || (client) == IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS) -#define IPA_CLIENT_IS_MEMCPY_DMA_PROD(client) ((client) == IPA_CLIENT_MEMCPY_DMA_SYNC_PROD || (client) == IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD) -#define IPA_CLIENT_IS_MHI_CONS(client) ((client) == IPA_CLIENT_MHI_CONS) -#define IPA_CLIENT_IS_MHI(client) ((client) == IPA_CLIENT_MHI_CONS || (client) == IPA_CLIENT_MHI_PROD) -#define IPA_CLIENT_IS_TEST_PROD(client) ((client) == IPA_CLIENT_TEST_PROD || (client) == IPA_CLIENT_TEST1_PROD || (client) == IPA_CLIENT_TEST2_PROD || (client) == IPA_CLIENT_TEST3_PROD || (client) == IPA_CLIENT_TEST4_PROD) -#define IPA_CLIENT_IS_TEST_CONS(client) ((client) == IPA_CLIENT_TEST_CONS || (client) == IPA_CLIENT_TEST1_CONS || (client) == IPA_CLIENT_TEST2_CONS || (client) == IPA_CLIENT_TEST3_CONS || (client) == IPA_CLIENT_TEST4_CONS) -#define IPA_CLIENT_IS_TEST(client) (IPA_CLIENT_IS_TEST_PROD(client) || IPA_CLIENT_IS_TEST_CONS(client)) -enum ipa_ip_type { - IPA_IP_v4, - IPA_IP_v6, - IPA_IP_MAX -}; -enum ipa_rule_type { - IPA_RULE_HASHABLE, - IPA_RULE_NON_HASHABLE, -}; -#define IPA_RULE_TYPE_MAX (IPA_RULE_NON_HASHABLE + 1) -enum ipa_flt_action { - IPA_PASS_TO_ROUTING, - IPA_PASS_TO_SRC_NAT, - IPA_PASS_TO_DST_NAT, - IPA_PASS_TO_EXCEPTION -}; -enum ipa_wlan_event { - WLAN_CLIENT_CONNECT, - WLAN_CLIENT_DISCONNECT, - WLAN_CLIENT_POWER_SAVE_MODE, - WLAN_CLIENT_NORMAL_MODE, - SW_ROUTING_ENABLE, - SW_ROUTING_DISABLE, - WLAN_AP_CONNECT, - WLAN_AP_DISCONNECT, - WLAN_STA_CONNECT, - WLAN_STA_DISCONNECT, - WLAN_CLIENT_CONNECT_EX, - WLAN_SWITCH_TO_SCC, - WLAN_SWITCH_TO_MCC, - WLAN_WDI_ENABLE, - WLAN_WDI_DISABLE, - IPA_WLAN_EVENT_MAX -}; -enum ipa_wan_event { - WAN_UPSTREAM_ROUTE_ADD = IPA_WLAN_EVENT_MAX, - WAN_UPSTREAM_ROUTE_DEL, - WAN_EMBMS_CONNECT, - WAN_XLAT_CONNECT, - IPA_WAN_EVENT_MAX -}; -enum ipa_ecm_event { - ECM_CONNECT = IPA_WAN_EVENT_MAX, - ECM_DISCONNECT, - IPA_ECM_EVENT_MAX, -}; -enum ipa_tethering_stats_event { - IPA_TETHERING_STATS_UPDATE_STATS = IPA_ECM_EVENT_MAX, - IPA_TETHERING_STATS_UPDATE_NETWORK_STATS, - IPA_TETHERING_STATS_EVENT_MAX, -}; -enum ipa_quota_event { - IPA_QUOTA_REACH = IPA_TETHERING_STATS_EVENT_MAX, - IPA_QUOTA_EVENT_MAX, -}; -enum ipa_ssr_event { - IPA_SSR_BEFORE_SHUTDOWN = IPA_QUOTA_EVENT_MAX, - IPA_SSR_AFTER_POWERUP, - IPA_SSR_EVENT_MAX -}; -enum ipa_vlan_l2tp_event { - ADD_VLAN_IFACE = IPA_SSR_EVENT_MAX, - DEL_VLAN_IFACE, - ADD_L2TP_VLAN_MAPPING, - DEL_L2TP_VLAN_MAPPING, - IPA_VLAN_L2TP_EVENT_MAX, -}; -enum ipa_per_client_stats_event { - IPA_PER_CLIENT_STATS_CONNECT_EVENT = IPA_VLAN_L2TP_EVENT_MAX, - IPA_PER_CLIENT_STATS_DISCONNECT_EVENT, - IPA_PER_CLIENT_STATS_EVENT_MAX -}; -enum ipa_wlan_fw_ssr_event { - WLAN_FWR_SSR_BEFORE_SHUTDOWN = IPA_PER_CLIENT_STATS_EVENT_MAX, - IPA_WLAN_FW_SSR_EVENT_MAX, -#define IPA_WLAN_FW_SSR_EVENT_MAX IPA_WLAN_FW_SSR_EVENT_MAX -}; -#define IPA_EVENT_MAX_NUM (IPA_WLAN_FW_SSR_EVENT_MAX) -#define IPA_EVENT_MAX ((int) IPA_EVENT_MAX_NUM) -enum ipa_rm_resource_name { - IPA_RM_RESOURCE_Q6_PROD = 0, - IPA_RM_RESOURCE_Q6_CONS = 1, - IPA_RM_RESOURCE_USB_PROD = 2, - IPA_RM_RESOURCE_USB_CONS = 3, - IPA_RM_RESOURCE_USB_DPL_DUMMY_PROD = 4, - IPA_RM_RESOURCE_USB_DPL_CONS = 5, - IPA_RM_RESOURCE_HSIC_PROD = 6, - IPA_RM_RESOURCE_HSIC_CONS = 7, - IPA_RM_RESOURCE_STD_ECM_PROD = 8, - IPA_RM_RESOURCE_APPS_CONS = 9, - IPA_RM_RESOURCE_RNDIS_PROD = 10, - IPA_RM_RESOURCE_WWAN_0_PROD = 12, - IPA_RM_RESOURCE_WLAN_PROD = 14, - IPA_RM_RESOURCE_WLAN_CONS = 15, - IPA_RM_RESOURCE_ODU_ADAPT_PROD = 16, - IPA_RM_RESOURCE_ODU_ADAPT_CONS = 17, - IPA_RM_RESOURCE_MHI_PROD = 18, - IPA_RM_RESOURCE_MHI_CONS = 19, - IPA_RM_RESOURCE_ETHERNET_PROD = 20, - IPA_RM_RESOURCE_ETHERNET_CONS = 21, -}; -#define IPA_RM_RESOURCE_MAX (IPA_RM_RESOURCE_ETHERNET_CONS + 1) -enum ipa_hw_type { - IPA_HW_None = 0, - IPA_HW_v1_0 = 1, - IPA_HW_v1_1 = 2, - IPA_HW_v2_0 = 3, - IPA_HW_v2_1 = 4, - IPA_HW_v2_5 = 5, - IPA_HW_v2_6 = IPA_HW_v2_5, - IPA_HW_v2_6L = 6, - IPA_HW_v3_0 = 10, - IPA_HW_v3_1 = 11, - IPA_HW_v3_5 = 12, - IPA_HW_v3_5_1 = 13, - IPA_HW_v4_0 = 14, -}; -#define IPA_HW_MAX (IPA_HW_v4_0 + 1) -#define IPA_HW_v4_0 IPA_HW_v4_0 -struct ipa_rule_attrib { - uint32_t attrib_mask; - uint16_t src_port_lo; - uint16_t src_port_hi; - uint16_t dst_port_lo; - uint16_t dst_port_hi; - uint8_t type; - uint8_t code; - uint8_t tos_value; - uint8_t tos_mask; - uint32_t spi; - uint16_t src_port; - uint16_t dst_port; - uint32_t meta_data; - uint32_t meta_data_mask; - uint8_t src_mac_addr[ETH_ALEN]; - uint8_t src_mac_addr_mask[ETH_ALEN]; - uint8_t dst_mac_addr[ETH_ALEN]; - uint8_t dst_mac_addr_mask[ETH_ALEN]; - uint16_t ether_type; - union { - struct { - uint8_t tos; - uint8_t protocol; - uint32_t src_addr; - uint32_t src_addr_mask; - uint32_t dst_addr; - uint32_t dst_addr_mask; - } v4; - struct { - uint8_t tc; - uint32_t flow_label; - uint8_t next_hdr; - uint32_t src_addr[4]; - uint32_t src_addr_mask[4]; - uint32_t dst_addr[4]; - uint32_t dst_addr_mask[4]; - } v6; - } u; -}; -#define IPA_IPFLTR_NUM_MEQ_32_EQNS 2 -#define IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS 2 -#define IPA_IPFLTR_NUM_MEQ_128_EQNS 2 -#define IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS 2 -struct ipa_ipfltr_eq_16 { - int8_t offset; - uint16_t value; -}; -struct ipa_ipfltr_eq_32 { - int8_t offset; - uint32_t value; -}; -struct ipa_ipfltr_mask_eq_128 { - int8_t offset; - uint8_t mask[16]; - uint8_t value[16]; -}; -struct ipa_ipfltr_mask_eq_32 { - int8_t offset; - uint32_t mask; - uint32_t value; -}; -struct ipa_ipfltr_range_eq_16 { - int8_t offset; - uint16_t range_low; - uint16_t range_high; -}; -struct ipa_ipfltri_rule_eq { - uint16_t rule_eq_bitmap; - uint8_t tos_eq_present; - uint8_t tos_eq; - uint8_t protocol_eq_present; - uint8_t protocol_eq; - uint8_t num_ihl_offset_range_16; - struct ipa_ipfltr_range_eq_16 ihl_offset_range_16[IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS]; - uint8_t num_offset_meq_32; - struct ipa_ipfltr_mask_eq_32 offset_meq_32[IPA_IPFLTR_NUM_MEQ_32_EQNS]; - uint8_t tc_eq_present; - uint8_t tc_eq; - uint8_t fl_eq_present; - uint32_t fl_eq; - uint8_t ihl_offset_eq_16_present; - struct ipa_ipfltr_eq_16 ihl_offset_eq_16; - uint8_t ihl_offset_eq_32_present; - struct ipa_ipfltr_eq_32 ihl_offset_eq_32; - uint8_t num_ihl_offset_meq_32; - struct ipa_ipfltr_mask_eq_32 ihl_offset_meq_32[IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS]; - uint8_t num_offset_meq_128; - struct ipa_ipfltr_mask_eq_128 offset_meq_128[IPA_IPFLTR_NUM_MEQ_128_EQNS]; - uint8_t metadata_meq32_present; - struct ipa_ipfltr_mask_eq_32 metadata_meq32; - uint8_t ipv4_frag_eq_present; -}; -struct ipa_flt_rule { - uint8_t retain_hdr; - uint8_t to_uc; - enum ipa_flt_action action; - uint32_t rt_tbl_hdl; - struct ipa_rule_attrib attrib; - struct ipa_ipfltri_rule_eq eq_attrib; - uint32_t rt_tbl_idx; - uint8_t eq_attrib_type; - uint8_t max_prio; - uint8_t hashable; - uint16_t rule_id; - uint8_t set_metadata; - uint8_t pdn_idx; -}; -enum ipa_hdr_l2_type { - IPA_HDR_L2_NONE, - IPA_HDR_L2_ETHERNET_II, - IPA_HDR_L2_802_3, - IPA_HDR_L2_802_1Q, -}; -#define IPA_HDR_L2_MAX (IPA_HDR_L2_802_1Q + 1) -#define IPA_HDR_L2_802_1Q IPA_HDR_L2_802_1Q -enum ipa_hdr_proc_type { - IPA_HDR_PROC_NONE, - IPA_HDR_PROC_ETHII_TO_ETHII, - IPA_HDR_PROC_ETHII_TO_802_3, - IPA_HDR_PROC_802_3_TO_ETHII, - IPA_HDR_PROC_802_3_TO_802_3, - IPA_HDR_PROC_L2TP_HEADER_ADD, - IPA_HDR_PROC_L2TP_HEADER_REMOVE -}; -#define IPA_HDR_PROC_MAX (IPA_HDR_PROC_L2TP_HEADER_REMOVE + 1) -struct ipa_rt_rule { - enum ipa_client_type dst; - uint32_t hdr_hdl; - uint32_t hdr_proc_ctx_hdl; - struct ipa_rule_attrib attrib; - uint8_t max_prio; - uint8_t hashable; - uint8_t retain_hdr; -}; -struct ipa_hdr_add { - char name[IPA_RESOURCE_NAME_MAX]; - uint8_t hdr[IPA_HDR_MAX_SIZE]; - uint8_t hdr_len; - enum ipa_hdr_l2_type type; - uint8_t is_partial; - uint32_t hdr_hdl; - int status; - uint8_t is_eth2_ofst_valid; - uint16_t eth2_ofst; -}; -struct ipa_ioc_add_hdr { - uint8_t commit; - uint8_t num_hdrs; - struct ipa_hdr_add hdr[0]; -}; -struct ipa_l2tp_header_add_procparams { - uint32_t eth_hdr_retained : 1; - uint32_t input_ip_version : 1; - uint32_t output_ip_version : 1; - uint32_t reserved : 29; -}; -struct ipa_l2tp_header_remove_procparams { - uint32_t hdr_len_remove : 8; - uint32_t eth_hdr_retained : 1; - uint32_t hdr_ofst_pkt_size_valid : 1; - uint32_t hdr_ofst_pkt_size : 6; - uint32_t hdr_endianness : 1; - uint32_t reserved : 15; -}; -struct ipa_l2tp_hdr_proc_ctx_params { - struct ipa_l2tp_header_add_procparams hdr_add_param; - struct ipa_l2tp_header_remove_procparams hdr_remove_param; - uint8_t is_dst_pipe_valid; - enum ipa_client_type dst_pipe; -}; -#define L2TP_USER_SPACE_SPECIFY_DST_PIPE -struct ipa_hdr_proc_ctx_add { - enum ipa_hdr_proc_type type; - uint32_t hdr_hdl; - uint32_t proc_ctx_hdl; - int status; - struct ipa_l2tp_hdr_proc_ctx_params l2tp_params; -}; -#define IPA_L2TP_HDR_PROC_SUPPORT -struct ipa_ioc_add_hdr_proc_ctx { - uint8_t commit; - uint8_t num_proc_ctxs; - struct ipa_hdr_proc_ctx_add proc_ctx[0]; -}; -struct ipa_ioc_copy_hdr { - char name[IPA_RESOURCE_NAME_MAX]; - uint8_t hdr[IPA_HDR_MAX_SIZE]; - uint8_t hdr_len; - enum ipa_hdr_l2_type type; - uint8_t is_partial; - uint8_t is_eth2_ofst_valid; - uint16_t eth2_ofst; -}; -struct ipa_ioc_get_hdr { - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t hdl; -}; -struct ipa_hdr_del { - uint32_t hdl; - int status; -}; -struct ipa_ioc_del_hdr { - uint8_t commit; - uint8_t num_hdls; - struct ipa_hdr_del hdl[0]; -}; -struct ipa_hdr_proc_ctx_del { - uint32_t hdl; - int status; -}; -struct ipa_ioc_del_hdr_proc_ctx { - uint8_t commit; - uint8_t num_hdls; - struct ipa_hdr_proc_ctx_del hdl[0]; -}; -struct ipa_rt_rule_add { - struct ipa_rt_rule rule; - uint8_t at_rear; - uint32_t rt_rule_hdl; - int status; -}; -struct ipa_ioc_add_rt_rule { - uint8_t commit; - enum ipa_ip_type ip; - char rt_tbl_name[IPA_RESOURCE_NAME_MAX]; - uint8_t num_rules; - struct ipa_rt_rule_add rules[0]; -}; -struct ipa_ioc_add_rt_rule_after { - uint8_t commit; - enum ipa_ip_type ip; - char rt_tbl_name[IPA_RESOURCE_NAME_MAX]; - uint8_t num_rules; - uint32_t add_after_hdl; - struct ipa_rt_rule_add rules[0]; -}; -struct ipa_rt_rule_mdfy { - struct ipa_rt_rule rule; - uint32_t rt_rule_hdl; - int status; -}; -struct ipa_ioc_mdfy_rt_rule { - uint8_t commit; - enum ipa_ip_type ip; - uint8_t num_rules; - struct ipa_rt_rule_mdfy rules[0]; -}; -struct ipa_rt_rule_del { - uint32_t hdl; - int status; -}; -struct ipa_rt_rule_add_ext { - struct ipa_rt_rule rule; - uint8_t at_rear; - uint32_t rt_rule_hdl; - int status; - uint16_t rule_id; -}; -struct ipa_ioc_add_rt_rule_ext { - uint8_t commit; - enum ipa_ip_type ip; - char rt_tbl_name[IPA_RESOURCE_NAME_MAX]; - uint8_t num_rules; - struct ipa_rt_rule_add_ext rules[0]; -}; -struct ipa_ioc_del_rt_rule { - uint8_t commit; - enum ipa_ip_type ip; - uint8_t num_hdls; - struct ipa_rt_rule_del hdl[0]; -}; -struct ipa_ioc_get_rt_tbl_indx { - enum ipa_ip_type ip; - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t idx; -}; -struct ipa_flt_rule_add { - struct ipa_flt_rule rule; - uint8_t at_rear; - uint32_t flt_rule_hdl; - int status; -}; -struct ipa_ioc_add_flt_rule { - uint8_t commit; - enum ipa_ip_type ip; - enum ipa_client_type ep; - uint8_t global; - uint8_t num_rules; - struct ipa_flt_rule_add rules[0]; -}; -struct ipa_ioc_add_flt_rule_after { - uint8_t commit; - enum ipa_ip_type ip; - enum ipa_client_type ep; - uint8_t num_rules; - uint32_t add_after_hdl; - struct ipa_flt_rule_add rules[0]; -}; -struct ipa_flt_rule_mdfy { - struct ipa_flt_rule rule; - uint32_t rule_hdl; - int status; -}; -struct ipa_ioc_mdfy_flt_rule { - uint8_t commit; - enum ipa_ip_type ip; - uint8_t num_rules; - struct ipa_flt_rule_mdfy rules[0]; -}; -struct ipa_flt_rule_del { - uint32_t hdl; - int status; -}; -struct ipa_ioc_del_flt_rule { - uint8_t commit; - enum ipa_ip_type ip; - uint8_t num_hdls; - struct ipa_flt_rule_del hdl[0]; -}; -struct ipa_ioc_get_rt_tbl { - enum ipa_ip_type ip; - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t hdl; -}; -struct ipa_ioc_query_intf { - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t num_tx_props; - uint32_t num_rx_props; - uint32_t num_ext_props; - enum ipa_client_type excp_pipe; -}; -struct ipa_ioc_tx_intf_prop { - enum ipa_ip_type ip; - struct ipa_rule_attrib attrib; - enum ipa_client_type dst_pipe; - enum ipa_client_type alt_dst_pipe; - char hdr_name[IPA_RESOURCE_NAME_MAX]; - enum ipa_hdr_l2_type hdr_l2_type; -}; -struct ipa_ioc_query_intf_tx_props { - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t num_tx_props; - struct ipa_ioc_tx_intf_prop tx[0]; -}; -struct ipa_ioc_ext_intf_prop { - enum ipa_ip_type ip; - struct ipa_ipfltri_rule_eq eq_attrib; - enum ipa_flt_action action; - uint32_t rt_tbl_idx; - uint8_t mux_id; - uint32_t filter_hdl; - uint8_t is_xlat_rule; - uint32_t rule_id; - uint8_t is_rule_hashable; -}; -struct ipa_ioc_query_intf_ext_props { - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t num_ext_props; - struct ipa_ioc_ext_intf_prop ext[0]; -}; -struct ipa_ioc_rx_intf_prop { - enum ipa_ip_type ip; - struct ipa_rule_attrib attrib; - enum ipa_client_type src_pipe; - enum ipa_hdr_l2_type hdr_l2_type; -}; -struct ipa_ioc_query_intf_rx_props { - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t num_rx_props; - struct ipa_ioc_rx_intf_prop rx[0]; -}; -struct ipa_ioc_nat_alloc_mem { - char dev_name[IPA_RESOURCE_NAME_MAX]; - size_t size; - off_t offset; -}; -struct ipa_ioc_nat_ipv6ct_table_alloc { - size_t size; - off_t offset; -}; -struct ipa_ioc_v4_nat_init { - uint8_t tbl_index; - uint32_t ipv4_rules_offset; - uint32_t expn_rules_offset; - uint32_t index_offset; - uint32_t index_expn_offset; - uint16_t table_entries; - uint16_t expn_table_entries; - uint32_t ip_addr; -}; -struct ipa_ioc_ipv6ct_init { - uint32_t base_table_offset; - uint32_t expn_table_offset; - uint16_t table_entries; - uint16_t expn_table_entries; - uint8_t tbl_index; -}; -struct ipa_ioc_v4_nat_del { - uint8_t table_index; - uint32_t public_ip_addr; -}; -struct ipa_ioc_nat_ipv6ct_table_del { - uint8_t table_index; -}; -struct ipa_ioc_nat_dma_one { - uint8_t table_index; - uint8_t base_addr; - uint32_t offset; - uint16_t data; -}; -struct ipa_ioc_nat_dma_cmd { - uint8_t entries; - struct ipa_ioc_nat_dma_one dma[0]; -}; -struct ipa_ioc_nat_pdn_entry { - uint8_t pdn_index; - uint32_t public_ip; - uint32_t src_metadata; - uint32_t dst_metadata; -}; -struct ipa_ioc_vlan_iface_info { - char name[IPA_RESOURCE_NAME_MAX]; - uint8_t vlan_id; -}; -struct ipa_ioc_l2tp_vlan_mapping_info { - enum ipa_ip_type iptype; - char l2tp_iface_name[IPA_RESOURCE_NAME_MAX]; - uint8_t l2tp_session_id; - char vlan_iface_name[IPA_RESOURCE_NAME_MAX]; -}; -struct ipa_msg_meta { - uint8_t msg_type; - uint8_t rsvd; - uint16_t msg_len; -}; -struct ipa_wlan_msg { - char name[IPA_RESOURCE_NAME_MAX]; - uint8_t mac_addr[IPA_MAC_ADDR_SIZE]; -}; -enum ipa_wlan_hdr_attrib_type { - WLAN_HDR_ATTRIB_MAC_ADDR, - WLAN_HDR_ATTRIB_STA_ID -}; -struct ipa_wlan_hdr_attrib_val { - enum ipa_wlan_hdr_attrib_type attrib_type; - uint8_t offset; - union { - uint8_t mac_addr[IPA_MAC_ADDR_SIZE]; - uint8_t sta_id; - } u; -}; -struct ipa_wlan_msg_ex { - char name[IPA_RESOURCE_NAME_MAX]; - uint8_t num_of_attribs; - struct ipa_wlan_hdr_attrib_val attribs[0]; -}; -struct ipa_ecm_msg { - char name[IPA_RESOURCE_NAME_MAX]; - int ifindex; -}; -struct ipa_wan_msg { - char upstream_ifname[IPA_RESOURCE_NAME_MAX]; - char tethered_ifname[IPA_RESOURCE_NAME_MAX]; - enum ipa_ip_type ip; - uint32_t ipv4_addr_gw; - uint32_t ipv6_addr_gw[IPA_WAN_MSG_IPv6_ADDR_GW_LEN]; -}; -struct ipa_ioc_rm_dependency { - enum ipa_rm_resource_name resource_name; - enum ipa_rm_resource_name depends_on_name; -}; -struct ipa_ioc_generate_flt_eq { - enum ipa_ip_type ip; - struct ipa_rule_attrib attrib; - struct ipa_ipfltri_rule_eq eq_attrib; -}; -struct ipa_ioc_write_qmapid { - enum ipa_client_type client; - uint8_t qmap_id; -}; -enum ipacm_client_enum { - IPACM_CLIENT_USB = 1, - IPACM_CLIENT_WLAN, - IPACM_CLIENT_MAX -}; -enum ipacm_per_client_device_type { - IPACM_CLIENT_DEVICE_TYPE_USB = 0, - IPACM_CLIENT_DEVICE_TYPE_WLAN = 1, - IPACM_CLIENT_DEVICE_TYPE_ETH = 2 -}; -#define IPACM_MAX_CLIENT_DEVICE_TYPES 3 -struct ipa_lan_client_msg { - char lanIface[IPA_RESOURCE_NAME_MAX]; - uint8_t mac[IPA_MAC_ADDR_SIZE]; -}; -struct ipa_lan_client { - uint8_t mac[IPA_MAC_ADDR_SIZE]; - int8_t client_idx; - uint8_t inited; -}; -struct ipa_tether_device_info { - int32_t ul_src_pipe; - uint8_t hdr_len; - uint32_t num_clients; - struct ipa_lan_client lan_client[IPA_MAX_NUM_HW_PATH_CLIENTS]; -}; -enum ipa_vlan_ifaces { - IPA_VLAN_IF_ETH, - IPA_VLAN_IF_RNDIS, - IPA_VLAN_IF_ECM -}; -#define IPA_VLAN_IF_EMAC IPA_VLAN_IF_ETH -#define IPA_VLAN_IF_MAX (IPA_VLAN_IF_ECM + 1) -struct ipa_ioc_get_vlan_mode { - enum ipa_vlan_ifaces iface; - uint32_t is_vlan_mode; -}; -#define IPA_IOC_ADD_HDR _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_HDR, struct ipa_ioc_add_hdr *) -#define IPA_IOC_DEL_HDR _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_HDR, struct ipa_ioc_del_hdr *) -#define IPA_IOC_ADD_RT_RULE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_RT_RULE, struct ipa_ioc_add_rt_rule *) -#define IPA_IOC_ADD_RT_RULE_EXT _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_RT_RULE_EXT, struct ipa_ioc_add_rt_rule_ext *) -#define IPA_IOC_ADD_RT_RULE_AFTER _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_RT_RULE_AFTER, struct ipa_ioc_add_rt_rule_after *) -#define IPA_IOC_DEL_RT_RULE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_RT_RULE, struct ipa_ioc_del_rt_rule *) -#define IPA_IOC_ADD_FLT_RULE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_FLT_RULE, struct ipa_ioc_add_flt_rule *) -#define IPA_IOC_ADD_FLT_RULE_AFTER _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_FLT_RULE_AFTER, struct ipa_ioc_add_flt_rule_after *) -#define IPA_IOC_DEL_FLT_RULE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_FLT_RULE, struct ipa_ioc_del_flt_rule *) -#define IPA_IOC_COMMIT_HDR _IO(IPA_IOC_MAGIC, IPA_IOCTL_COMMIT_HDR) -#define IPA_IOC_RESET_HDR _IO(IPA_IOC_MAGIC, IPA_IOCTL_RESET_HDR) -#define IPA_IOC_COMMIT_RT _IOW(IPA_IOC_MAGIC, IPA_IOCTL_COMMIT_RT, enum ipa_ip_type) -#define IPA_IOC_RESET_RT _IOW(IPA_IOC_MAGIC, IPA_IOCTL_RESET_RT, enum ipa_ip_type) -#define IPA_IOC_COMMIT_FLT _IOW(IPA_IOC_MAGIC, IPA_IOCTL_COMMIT_FLT, enum ipa_ip_type) -#define IPA_IOC_RESET_FLT _IOW(IPA_IOC_MAGIC, IPA_IOCTL_RESET_FLT, enum ipa_ip_type) -#define IPA_IOC_DUMP _IO(IPA_IOC_MAGIC, IPA_IOCTL_DUMP) -#define IPA_IOC_GET_RT_TBL _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_GET_RT_TBL, struct ipa_ioc_get_rt_tbl *) -#define IPA_IOC_PUT_RT_TBL _IOW(IPA_IOC_MAGIC, IPA_IOCTL_PUT_RT_TBL, uint32_t) -#define IPA_IOC_COPY_HDR _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_COPY_HDR, struct ipa_ioc_copy_hdr *) -#define IPA_IOC_QUERY_INTF _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_INTF, struct ipa_ioc_query_intf *) -#define IPA_IOC_QUERY_INTF_TX_PROPS _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_INTF_TX_PROPS, struct ipa_ioc_query_intf_tx_props *) -#define IPA_IOC_QUERY_INTF_RX_PROPS _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_INTF_RX_PROPS, struct ipa_ioc_query_intf_rx_props *) -#define IPA_IOC_QUERY_INTF_EXT_PROPS _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_INTF_EXT_PROPS, struct ipa_ioc_query_intf_ext_props *) -#define IPA_IOC_GET_HDR _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_GET_HDR, struct ipa_ioc_get_hdr *) -#define IPA_IOC_PUT_HDR _IOW(IPA_IOC_MAGIC, IPA_IOCTL_PUT_HDR, uint32_t) -#define IPA_IOC_ALLOC_NAT_MEM _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ALLOC_NAT_MEM, struct ipa_ioc_nat_alloc_mem *) -#define IPA_IOC_ALLOC_NAT_TABLE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ALLOC_NAT_TABLE, struct ipa_ioc_nat_ipv6ct_table_alloc *) -#define IPA_IOC_ALLOC_IPV6CT_TABLE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ALLOC_IPV6CT_TABLE, struct ipa_ioc_nat_ipv6ct_table_alloc *) -#define IPA_IOC_V4_INIT_NAT _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_V4_INIT_NAT, struct ipa_ioc_v4_nat_init *) -#define IPA_IOC_INIT_IPV6CT_TABLE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_INIT_IPV6CT_TABLE, struct ipa_ioc_ipv6ct_init *) -#define IPA_IOC_NAT_DMA _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_NAT_DMA, struct ipa_ioc_nat_dma_cmd *) -#define IPA_IOC_TABLE_DMA_CMD _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_TABLE_DMA_CMD, struct ipa_ioc_nat_dma_cmd *) -#define IPA_IOC_V4_DEL_NAT _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_V4_DEL_NAT, struct ipa_ioc_v4_nat_del *) -#define IPA_IOC_DEL_NAT_TABLE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_NAT_TABLE, struct ipa_ioc_nat_ipv6ct_table_del *) -#define IPA_IOC_DEL_IPV6CT_TABLE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_IPV6CT_TABLE, struct ipa_ioc_nat_ipv6ct_table_del *) -#define IPA_IOC_GET_NAT_OFFSET _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_GET_NAT_OFFSET, uint32_t *) -#define IPA_IOC_NAT_MODIFY_PDN _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_NAT_MODIFY_PDN, struct ipa_ioc_nat_pdn_entry *) -#define IPA_IOC_SET_FLT _IOW(IPA_IOC_MAGIC, IPA_IOCTL_SET_FLT, uint32_t) -#define IPA_IOC_PULL_MSG _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_PULL_MSG, struct ipa_msg_meta *) -#define IPA_IOC_RM_ADD_DEPENDENCY _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_RM_ADD_DEPENDENCY, struct ipa_ioc_rm_dependency *) -#define IPA_IOC_RM_DEL_DEPENDENCY _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_RM_DEL_DEPENDENCY, struct ipa_ioc_rm_dependency *) -#define IPA_IOC_GENERATE_FLT_EQ _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_GENERATE_FLT_EQ, struct ipa_ioc_generate_flt_eq *) -#define IPA_IOC_QUERY_EP_MAPPING _IOR(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_EP_MAPPING, uint32_t) -#define IPA_IOC_QUERY_RT_TBL_INDEX _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_RT_TBL_INDEX, struct ipa_ioc_get_rt_tbl_indx *) -#define IPA_IOC_WRITE_QMAPID _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_WRITE_QMAPID, struct ipa_ioc_write_qmapid *) -#define IPA_IOC_MDFY_FLT_RULE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_MDFY_FLT_RULE, struct ipa_ioc_mdfy_flt_rule *) -#define IPA_IOC_MDFY_RT_RULE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_MDFY_RT_RULE, struct ipa_ioc_mdfy_rt_rule *) -#define IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_ADD _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_ADD, struct ipa_wan_msg *) -#define IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_DEL _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_DEL, struct ipa_wan_msg *) -#define IPA_IOC_NOTIFY_WAN_EMBMS_CONNECTED _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_NOTIFY_WAN_EMBMS_CONNECTED, struct ipa_wan_msg *) -#define IPA_IOC_ADD_HDR_PROC_CTX _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_HDR_PROC_CTX, struct ipa_ioc_add_hdr_proc_ctx *) -#define IPA_IOC_DEL_HDR_PROC_CTX _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_HDR_PROC_CTX, struct ipa_ioc_del_hdr_proc_ctx *) -#define IPA_IOC_GET_HW_VERSION _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_GET_HW_VERSION, enum ipa_hw_type *) -#define IPA_IOC_ADD_VLAN_IFACE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_VLAN_IFACE, struct ipa_ioc_vlan_iface_info *) -#define IPA_IOC_DEL_VLAN_IFACE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_VLAN_IFACE, struct ipa_ioc_vlan_iface_info *) -#define IPA_IOC_ADD_L2TP_VLAN_MAPPING _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_L2TP_VLAN_MAPPING, struct ipa_ioc_l2tp_vlan_mapping_info *) -#define IPA_IOC_DEL_L2TP_VLAN_MAPPING _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_L2TP_VLAN_MAPPING, struct ipa_ioc_l2tp_vlan_mapping_info *) -#define IPA_IOC_CLEANUP _IO(IPA_IOC_MAGIC, IPA_IOCTL_CLEANUP) -#define IPA_IOC_QUERY_WLAN_CLIENT _IO(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_WLAN_CLIENT) -#define IPA_IOC_GET_VLAN_MODE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_GET_VLAN_MODE, struct ipa_ioc_get_vlan_mode *) -#define TETH_BRIDGE_IOC_MAGIC 0xCE -#define TETH_BRIDGE_IOCTL_SET_BRIDGE_MODE 0 -#define TETH_BRIDGE_IOCTL_SET_AGGR_PARAMS 1 -#define TETH_BRIDGE_IOCTL_GET_AGGR_PARAMS 2 -#define TETH_BRIDGE_IOCTL_GET_AGGR_CAPABILITIES 3 -#define TETH_BRIDGE_IOCTL_MAX 4 -enum teth_link_protocol_type { - TETH_LINK_PROTOCOL_IP, - TETH_LINK_PROTOCOL_ETHERNET, - TETH_LINK_PROTOCOL_MAX, -}; -enum teth_aggr_protocol_type { - TETH_AGGR_PROTOCOL_NONE, - TETH_AGGR_PROTOCOL_MBIM, - TETH_AGGR_PROTOCOL_TLP, - TETH_AGGR_PROTOCOL_MAX, -}; -struct teth_aggr_params_link { - enum teth_aggr_protocol_type aggr_prot; - uint32_t max_transfer_size_byte; - uint32_t max_datagrams; -}; -struct teth_aggr_params { - struct teth_aggr_params_link ul; - struct teth_aggr_params_link dl; -}; -struct teth_aggr_capabilities { - uint16_t num_protocols; - struct teth_aggr_params_link prot_caps[0]; -}; -struct teth_ioc_set_bridge_mode { - enum teth_link_protocol_type link_protocol; - uint16_t lcid; -}; -struct teth_ioc_aggr_params { - struct teth_aggr_params aggr_params; - uint16_t lcid; -}; -#define TETH_BRIDGE_IOC_SET_BRIDGE_MODE _IOW(TETH_BRIDGE_IOC_MAGIC, TETH_BRIDGE_IOCTL_SET_BRIDGE_MODE, struct teth_ioc_set_bridge_mode *) -#define TETH_BRIDGE_IOC_SET_AGGR_PARAMS _IOW(TETH_BRIDGE_IOC_MAGIC, TETH_BRIDGE_IOCTL_SET_AGGR_PARAMS, struct teth_ioc_aggr_params *) -#define TETH_BRIDGE_IOC_GET_AGGR_PARAMS _IOR(TETH_BRIDGE_IOC_MAGIC, TETH_BRIDGE_IOCTL_GET_AGGR_PARAMS, struct teth_ioc_aggr_params *) -#define TETH_BRIDGE_IOC_GET_AGGR_CAPABILITIES _IOWR(TETH_BRIDGE_IOC_MAGIC, TETH_BRIDGE_IOCTL_GET_AGGR_CAPABILITIES, struct teth_aggr_capabilities *) -#define ODU_BRIDGE_IOC_MAGIC 0xCD -#define ODU_BRIDGE_IOCTL_SET_MODE 0 -#define ODU_BRIDGE_IOCTL_SET_LLV6_ADDR 1 -#define ODU_BRIDGE_IOCTL_MAX 2 -enum odu_bridge_mode { - ODU_BRIDGE_MODE_ROUTER, - ODU_BRIDGE_MODE_BRIDGE, - ODU_BRIDGE_MODE_MAX, -}; -#define ODU_BRIDGE_IOC_SET_MODE _IOW(ODU_BRIDGE_IOC_MAGIC, ODU_BRIDGE_IOCTL_SET_MODE, enum odu_bridge_mode) -#define ODU_BRIDGE_IOC_SET_LLV6_ADDR _IOW(ODU_BRIDGE_IOC_MAGIC, ODU_BRIDGE_IOCTL_SET_LLV6_ADDR, struct in6_addr *) -#endif - diff --git a/sdm710/kernel-headers/linux/msm_kgsl.h b/sdm710/kernel-headers/linux/msm_kgsl.h deleted file mode 100644 index c88e9a9b..00000000 --- a/sdm710/kernel-headers/linux/msm_kgsl.h +++ /dev/null @@ -1,773 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _MSM_KGSL_H -#define _MSM_KGSL_H -#include <linux/types.h> -#include <linux/ioctl.h> -#define KGSL_VERSION_MAJOR 3 -#define KGSL_VERSION_MINOR 14 -#define KGSL_CONTEXT_SAVE_GMEM 0x00000001 -#define KGSL_CONTEXT_NO_GMEM_ALLOC 0x00000002 -#define KGSL_CONTEXT_SUBMIT_IB_LIST 0x00000004 -#define KGSL_CONTEXT_CTX_SWITCH 0x00000008 -#define KGSL_CONTEXT_PREAMBLE 0x00000010 -#define KGSL_CONTEXT_TRASH_STATE 0x00000020 -#define KGSL_CONTEXT_PER_CONTEXT_TS 0x00000040 -#define KGSL_CONTEXT_USER_GENERATED_TS 0x00000080 -#define KGSL_CONTEXT_END_OF_FRAME 0x00000100 -#define KGSL_CONTEXT_NO_FAULT_TOLERANCE 0x00000200 -#define KGSL_CONTEXT_SYNC 0x00000400 -#define KGSL_CONTEXT_PWR_CONSTRAINT 0x00000800 -#define KGSL_CONTEXT_PRIORITY_MASK 0x0000F000 -#define KGSL_CONTEXT_PRIORITY_SHIFT 12 -#define KGSL_CONTEXT_PRIORITY_UNDEF 0 -#define KGSL_CONTEXT_IFH_NOP 0x00010000 -#define KGSL_CONTEXT_SECURE 0x00020000 -#define KGSL_CONTEXT_NO_SNAPSHOT 0x00040000 -#define KGSL_CONTEXT_SPARSE 0x00080000 -#define KGSL_CONTEXT_PREEMPT_STYLE_MASK 0x0E000000 -#define KGSL_CONTEXT_PREEMPT_STYLE_SHIFT 25 -#define KGSL_CONTEXT_PREEMPT_STYLE_DEFAULT 0x0 -#define KGSL_CONTEXT_PREEMPT_STYLE_RINGBUFFER 0x1 -#define KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN 0x2 -#define KGSL_CONTEXT_TYPE_MASK 0x01F00000 -#define KGSL_CONTEXT_TYPE_SHIFT 20 -#define KGSL_CONTEXT_TYPE_ANY 0 -#define KGSL_CONTEXT_TYPE_GL 1 -#define KGSL_CONTEXT_TYPE_CL 2 -#define KGSL_CONTEXT_TYPE_C2D 3 -#define KGSL_CONTEXT_TYPE_RS 4 -#define KGSL_CONTEXT_TYPE_UNKNOWN 0x1E -#define KGSL_CONTEXT_INVALIDATE_ON_FAULT 0x10000000 -#define KGSL_CONTEXT_INVALID 0xffffffff -#define KGSL_CMDBATCH_MEMLIST 0x00000001 -#define KGSL_CMDBATCH_MARKER 0x00000002 -#define KGSL_CMDBATCH_SUBMIT_IB_LIST KGSL_CONTEXT_SUBMIT_IB_LIST -#define KGSL_CMDBATCH_CTX_SWITCH KGSL_CONTEXT_CTX_SWITCH -#define KGSL_CMDBATCH_PROFILING 0x00000010 -#define KGSL_CMDBATCH_PROFILING_KTIME 0x00000020 -#define KGSL_CMDBATCH_END_OF_FRAME KGSL_CONTEXT_END_OF_FRAME -#define KGSL_CMDBATCH_SYNC KGSL_CONTEXT_SYNC -#define KGSL_CMDBATCH_PWR_CONSTRAINT KGSL_CONTEXT_PWR_CONSTRAINT -#define KGSL_CMDBATCH_SPARSE 0x1000 -#define KGSL_CMDLIST_IB 0x00000001U -#define KGSL_CMDLIST_CTXTSWITCH_PREAMBLE 0x00000002U -#define KGSL_CMDLIST_IB_PREAMBLE 0x00000004U -#define KGSL_OBJLIST_MEMOBJ 0x00000008U -#define KGSL_OBJLIST_PROFILE 0x00000010U -#define KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP 0 -#define KGSL_CMD_SYNCPOINT_TYPE_FENCE 1 -#define KGSL_MEMFLAGS_SECURE 0x00000008ULL -#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000U -#define KGSL_MEMFLAGS_GPUWRITEONLY 0x02000000U -#define KGSL_MEMFLAGS_FORCE_32BIT 0x100000000ULL -#define KGSL_SPARSE_BIND_MULTIPLE_TO_PHYS 0x400000000ULL -#define KGSL_SPARSE_BIND 0x1ULL -#define KGSL_SPARSE_UNBIND 0x2ULL -#define KGSL_CACHEMODE_MASK 0x0C000000U -#define KGSL_CACHEMODE_SHIFT 26 -#define KGSL_CACHEMODE_WRITECOMBINE 0 -#define KGSL_CACHEMODE_UNCACHED 1 -#define KGSL_CACHEMODE_WRITETHROUGH 2 -#define KGSL_CACHEMODE_WRITEBACK 3 -#define KGSL_MEMFLAGS_USE_CPU_MAP 0x10000000ULL -#define KGSL_MEMFLAGS_SPARSE_PHYS 0x20000000ULL -#define KGSL_MEMFLAGS_SPARSE_VIRT 0x40000000ULL -#define KGSL_MEMFLAGS_IOCOHERENT 0x80000000ULL -#define KGSL_MEMTYPE_MASK 0x0000FF00 -#define KGSL_MEMTYPE_SHIFT 8 -#define KGSL_MEMTYPE_OBJECTANY 0 -#define KGSL_MEMTYPE_FRAMEBUFFER 1 -#define KGSL_MEMTYPE_RENDERBUFFER 2 -#define KGSL_MEMTYPE_ARRAYBUFFER 3 -#define KGSL_MEMTYPE_ELEMENTARRAYBUFFER 4 -#define KGSL_MEMTYPE_VERTEXARRAYBUFFER 5 -#define KGSL_MEMTYPE_TEXTURE 6 -#define KGSL_MEMTYPE_SURFACE 7 -#define KGSL_MEMTYPE_EGL_SURFACE 8 -#define KGSL_MEMTYPE_GL 9 -#define KGSL_MEMTYPE_CL 10 -#define KGSL_MEMTYPE_CL_BUFFER_MAP 11 -#define KGSL_MEMTYPE_CL_BUFFER_NOMAP 12 -#define KGSL_MEMTYPE_CL_IMAGE_MAP 13 -#define KGSL_MEMTYPE_CL_IMAGE_NOMAP 14 -#define KGSL_MEMTYPE_CL_KERNEL_STACK 15 -#define KGSL_MEMTYPE_COMMAND 16 -#define KGSL_MEMTYPE_2D 17 -#define KGSL_MEMTYPE_EGL_IMAGE 18 -#define KGSL_MEMTYPE_EGL_SHADOW 19 -#define KGSL_MEMTYPE_MULTISAMPLE 20 -#define KGSL_MEMTYPE_KERNEL 255 -#define KGSL_MEMALIGN_MASK 0x00FF0000 -#define KGSL_MEMALIGN_SHIFT 16 -enum kgsl_user_mem_type { - KGSL_USER_MEM_TYPE_PMEM = 0x00000000, - KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001, - KGSL_USER_MEM_TYPE_ADDR = 0x00000002, - KGSL_USER_MEM_TYPE_ION = 0x00000003, - KGSL_USER_MEM_TYPE_DMABUF = 0x00000003, - KGSL_USER_MEM_TYPE_MAX = 0x00000007, -}; -#define KGSL_MEMFLAGS_USERMEM_MASK 0x000000e0 -#define KGSL_MEMFLAGS_USERMEM_SHIFT 5 -#define KGSL_USERMEM_FLAG(x) (((x) + 1) << KGSL_MEMFLAGS_USERMEM_SHIFT) -#define KGSL_MEMFLAGS_NOT_USERMEM 0 -#define KGSL_MEMFLAGS_USERMEM_PMEM KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_PMEM) -#define KGSL_MEMFLAGS_USERMEM_ASHMEM KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ASHMEM) -#define KGSL_MEMFLAGS_USERMEM_ADDR KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ADDR) -#define KGSL_MEMFLAGS_USERMEM_ION KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ION) -#define KGSL_FLAGS_NORMALMODE 0x00000000 -#define KGSL_FLAGS_SAFEMODE 0x00000001 -#define KGSL_FLAGS_INITIALIZED0 0x00000002 -#define KGSL_FLAGS_INITIALIZED 0x00000004 -#define KGSL_FLAGS_STARTED 0x00000008 -#define KGSL_FLAGS_ACTIVE 0x00000010 -#define KGSL_FLAGS_RESERVED0 0x00000020 -#define KGSL_FLAGS_RESERVED1 0x00000040 -#define KGSL_FLAGS_RESERVED2 0x00000080 -#define KGSL_FLAGS_SOFT_RESET 0x00000100 -#define KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS 0x00000200 -#define KGSL_SYNCOBJ_SERVER_TIMEOUT 2000 -#define KGSL_UBWC_NONE 0 -#define KGSL_UBWC_1_0 1 -#define KGSL_UBWC_2_0 2 -#define KGSL_UBWC_3_0 3 -enum kgsl_ctx_reset_stat { - KGSL_CTX_STAT_NO_ERROR = 0x00000000, - KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 0x00000001, - KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 0x00000002, - KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 0x00000003 -}; -#define KGSL_CONVERT_TO_MBPS(val) (val * 1000 * 1000U) -enum kgsl_deviceid { - KGSL_DEVICE_3D0 = 0x00000000, - KGSL_DEVICE_MAX -}; -struct kgsl_devinfo { - unsigned int device_id; - unsigned int chip_id; - unsigned int mmu_enabled; - unsigned long gmem_gpubaseaddr; - unsigned int gpu_id; - size_t gmem_sizebytes; -}; -struct kgsl_devmemstore { - __volatile__ unsigned int soptimestamp; - unsigned int sbz; - __volatile__ unsigned int eoptimestamp; - unsigned int sbz2; - __volatile__ unsigned int preempted; - unsigned int sbz3; - __volatile__ unsigned int ref_wait_ts; - unsigned int sbz4; - unsigned int current_context; - unsigned int sbz5; -}; -#define KGSL_MEMSTORE_OFFSET(ctxt_id,field) ((ctxt_id) * sizeof(struct kgsl_devmemstore) + offsetof(struct kgsl_devmemstore, field)) -enum kgsl_timestamp_type { - KGSL_TIMESTAMP_CONSUMED = 0x00000001, - KGSL_TIMESTAMP_RETIRED = 0x00000002, - KGSL_TIMESTAMP_QUEUED = 0x00000003, -}; -#define KGSL_PROP_DEVICE_INFO 0x1 -#define KGSL_PROP_DEVICE_SHADOW 0x2 -#define KGSL_PROP_DEVICE_POWER 0x3 -#define KGSL_PROP_SHMEM 0x4 -#define KGSL_PROP_SHMEM_APERTURES 0x5 -#define KGSL_PROP_MMU_ENABLE 0x6 -#define KGSL_PROP_INTERRUPT_WAITS 0x7 -#define KGSL_PROP_VERSION 0x8 -#define KGSL_PROP_GPU_RESET_STAT 0x9 -#define KGSL_PROP_PWRCTRL 0xE -#define KGSL_PROP_PWR_CONSTRAINT 0x12 -#define KGSL_PROP_UCHE_GMEM_VADDR 0x13 -#define KGSL_PROP_SP_GENERIC_MEM 0x14 -#define KGSL_PROP_UCODE_VERSION 0x15 -#define KGSL_PROP_GPMU_VERSION 0x16 -#define KGSL_PROP_HIGHEST_BANK_BIT 0x17 -#define KGSL_PROP_DEVICE_BITNESS 0x18 -#define KGSL_PROP_DEVICE_QDSS_STM 0x19 -#define KGSL_PROP_MIN_ACCESS_LENGTH 0x1A -#define KGSL_PROP_UBWC_MODE 0x1B -#define KGSL_PROP_DEVICE_QTIMER 0x20 -#define KGSL_PROP_L3_PWR_CONSTRAINT 0x22 -struct kgsl_shadowprop { - unsigned long gpuaddr; - size_t size; - unsigned int flags; -}; -struct kgsl_qdss_stm_prop { - uint64_t gpuaddr; - uint64_t size; -}; -struct kgsl_qtimer_prop { - uint64_t gpuaddr; - uint64_t size; -}; -struct kgsl_version { - unsigned int drv_major; - unsigned int drv_minor; - unsigned int dev_major; - unsigned int dev_minor; -}; -struct kgsl_sp_generic_mem { - uint64_t local; - uint64_t pvt; -}; -struct kgsl_ucode_version { - unsigned int pfp; - unsigned int pm4; -}; -struct kgsl_gpmu_version { - unsigned int major; - unsigned int minor; - unsigned int features; -}; -#define KGSL_PERFCOUNTER_GROUP_CP 0x0 -#define KGSL_PERFCOUNTER_GROUP_RBBM 0x1 -#define KGSL_PERFCOUNTER_GROUP_PC 0x2 -#define KGSL_PERFCOUNTER_GROUP_VFD 0x3 -#define KGSL_PERFCOUNTER_GROUP_HLSQ 0x4 -#define KGSL_PERFCOUNTER_GROUP_VPC 0x5 -#define KGSL_PERFCOUNTER_GROUP_TSE 0x6 -#define KGSL_PERFCOUNTER_GROUP_RAS 0x7 -#define KGSL_PERFCOUNTER_GROUP_UCHE 0x8 -#define KGSL_PERFCOUNTER_GROUP_TP 0x9 -#define KGSL_PERFCOUNTER_GROUP_SP 0xA -#define KGSL_PERFCOUNTER_GROUP_RB 0xB -#define KGSL_PERFCOUNTER_GROUP_PWR 0xC -#define KGSL_PERFCOUNTER_GROUP_VBIF 0xD -#define KGSL_PERFCOUNTER_GROUP_VBIF_PWR 0xE -#define KGSL_PERFCOUNTER_GROUP_MH 0xF -#define KGSL_PERFCOUNTER_GROUP_PA_SU 0x10 -#define KGSL_PERFCOUNTER_GROUP_SQ 0x11 -#define KGSL_PERFCOUNTER_GROUP_SX 0x12 -#define KGSL_PERFCOUNTER_GROUP_TCF 0x13 -#define KGSL_PERFCOUNTER_GROUP_TCM 0x14 -#define KGSL_PERFCOUNTER_GROUP_TCR 0x15 -#define KGSL_PERFCOUNTER_GROUP_L2 0x16 -#define KGSL_PERFCOUNTER_GROUP_VSC 0x17 -#define KGSL_PERFCOUNTER_GROUP_CCU 0x18 -#define KGSL_PERFCOUNTER_GROUP_LRZ 0x19 -#define KGSL_PERFCOUNTER_GROUP_CMP 0x1A -#define KGSL_PERFCOUNTER_GROUP_ALWAYSON 0x1B -#define KGSL_PERFCOUNTER_GROUP_SP_PWR 0x1C -#define KGSL_PERFCOUNTER_GROUP_TP_PWR 0x1D -#define KGSL_PERFCOUNTER_GROUP_RB_PWR 0x1E -#define KGSL_PERFCOUNTER_GROUP_CCU_PWR 0x1F -#define KGSL_PERFCOUNTER_GROUP_UCHE_PWR 0x20 -#define KGSL_PERFCOUNTER_GROUP_CP_PWR 0x21 -#define KGSL_PERFCOUNTER_GROUP_GPMU_PWR 0x22 -#define KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR 0x23 -#define KGSL_PERFCOUNTER_GROUP_MAX 0x24 -#define KGSL_PERFCOUNTER_NOT_USED 0xFFFFFFFF -#define KGSL_PERFCOUNTER_BROKEN 0xFFFFFFFE -struct kgsl_ibdesc { - unsigned long gpuaddr; - unsigned long __pad; - size_t sizedwords; - unsigned int ctrl; -}; -struct kgsl_cmdbatch_profiling_buffer { - uint64_t wall_clock_s; - uint64_t wall_clock_ns; - uint64_t gpu_ticks_queued; - uint64_t gpu_ticks_submitted; - uint64_t gpu_ticks_retired; -}; -#define KGSL_IOC_TYPE 0x09 -struct kgsl_device_getproperty { - unsigned int type; - void * value; - size_t sizebytes; -}; -#define IOCTL_KGSL_DEVICE_GETPROPERTY _IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty) -struct kgsl_device_waittimestamp { - unsigned int timestamp; - unsigned int timeout; -}; -#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP _IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp) -struct kgsl_device_waittimestamp_ctxtid { - unsigned int context_id; - unsigned int timestamp; - unsigned int timeout; -}; -#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID _IOW(KGSL_IOC_TYPE, 0x7, struct kgsl_device_waittimestamp_ctxtid) -struct kgsl_ringbuffer_issueibcmds { - unsigned int drawctxt_id; - unsigned long ibdesc_addr; - unsigned int numibs; - unsigned int timestamp; - unsigned int flags; -}; -#define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS _IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds) -struct kgsl_cmdstream_readtimestamp { - unsigned int type; - unsigned int timestamp; -}; -#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD _IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) -#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP _IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) -struct kgsl_cmdstream_freememontimestamp { - unsigned long gpuaddr; - unsigned int type; - unsigned int timestamp; -}; -#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP _IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) -#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD _IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) -struct kgsl_drawctxt_create { - unsigned int flags; - unsigned int drawctxt_id; -}; -#define IOCTL_KGSL_DRAWCTXT_CREATE _IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create) -struct kgsl_drawctxt_destroy { - unsigned int drawctxt_id; -}; -#define IOCTL_KGSL_DRAWCTXT_DESTROY _IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy) -struct kgsl_map_user_mem { - int fd; - unsigned long gpuaddr; - size_t len; - size_t offset; - unsigned long hostptr; - enum kgsl_user_mem_type memtype; - unsigned int flags; -}; -#define IOCTL_KGSL_MAP_USER_MEM _IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem) -struct kgsl_cmdstream_readtimestamp_ctxtid { - unsigned int context_id; - unsigned int type; - unsigned int timestamp; -}; -#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID _IOWR(KGSL_IOC_TYPE, 0x16, struct kgsl_cmdstream_readtimestamp_ctxtid) -struct kgsl_cmdstream_freememontimestamp_ctxtid { - unsigned int context_id; - unsigned long gpuaddr; - unsigned int type; - unsigned int timestamp; -}; -#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID _IOW(KGSL_IOC_TYPE, 0x17, struct kgsl_cmdstream_freememontimestamp_ctxtid) -struct kgsl_sharedmem_from_pmem { - int pmem_fd; - unsigned long gpuaddr; - unsigned int len; - unsigned int offset; -}; -#define IOCTL_KGSL_SHAREDMEM_FROM_PMEM _IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem) -struct kgsl_sharedmem_free { - unsigned long gpuaddr; -}; -#define IOCTL_KGSL_SHAREDMEM_FREE _IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free) -struct kgsl_cff_user_event { - unsigned char cff_opcode; - unsigned int op1; - unsigned int op2; - unsigned int op3; - unsigned int op4; - unsigned int op5; - unsigned int __pad[2]; -}; -#define IOCTL_KGSL_CFF_USER_EVENT _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event) -struct kgsl_gmem_desc { - unsigned int x; - unsigned int y; - unsigned int width; - unsigned int height; - unsigned int pitch; -}; -struct kgsl_buffer_desc { - void * hostptr; - unsigned long gpuaddr; - int size; - unsigned int format; - unsigned int pitch; - unsigned int enabled; -}; -struct kgsl_bind_gmem_shadow { - unsigned int drawctxt_id; - struct kgsl_gmem_desc gmem_desc; - unsigned int shadow_x; - unsigned int shadow_y; - struct kgsl_buffer_desc shadow_buffer; - unsigned int buffer_id; -}; -#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW _IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow) -struct kgsl_sharedmem_from_vmalloc { - unsigned long gpuaddr; - unsigned int hostptr; - unsigned int flags; -}; -#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC _IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc) -#define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE _IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free) -struct kgsl_drawctxt_set_bin_base_offset { - unsigned int drawctxt_id; - unsigned int offset; -}; -#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET _IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset) -enum kgsl_cmdwindow_type { - KGSL_CMDWINDOW_MIN = 0x00000000, - KGSL_CMDWINDOW_2D = 0x00000000, - KGSL_CMDWINDOW_3D = 0x00000001, - KGSL_CMDWINDOW_MMU = 0x00000002, - KGSL_CMDWINDOW_ARBITER = 0x000000FF, - KGSL_CMDWINDOW_MAX = 0x000000FF, -}; -struct kgsl_cmdwindow_write { - enum kgsl_cmdwindow_type target; - unsigned int addr; - unsigned int data; -}; -#define IOCTL_KGSL_CMDWINDOW_WRITE _IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write) -struct kgsl_gpumem_alloc { - unsigned long gpuaddr; - size_t size; - unsigned int flags; -}; -#define IOCTL_KGSL_GPUMEM_ALLOC _IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc) -struct kgsl_cff_syncmem { - unsigned long gpuaddr; - size_t len; - unsigned int __pad[2]; -}; -#define IOCTL_KGSL_CFF_SYNCMEM _IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem) -struct kgsl_timestamp_event { - int type; - unsigned int timestamp; - unsigned int context_id; - void * priv; - size_t len; -}; -#define IOCTL_KGSL_TIMESTAMP_EVENT_OLD _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_timestamp_event) -#define KGSL_TIMESTAMP_EVENT_GENLOCK 1 -struct kgsl_timestamp_event_genlock { - int handle; -}; -#define KGSL_TIMESTAMP_EVENT_FENCE 2 -struct kgsl_timestamp_event_fence { - int fence_fd; -}; -#define IOCTL_KGSL_SETPROPERTY _IOW(KGSL_IOC_TYPE, 0x32, struct kgsl_device_getproperty) -#define IOCTL_KGSL_TIMESTAMP_EVENT _IOWR(KGSL_IOC_TYPE, 0x33, struct kgsl_timestamp_event) -struct kgsl_gpumem_alloc_id { - unsigned int id; - unsigned int flags; - size_t size; - size_t mmapsize; - unsigned long gpuaddr; - unsigned long __pad[2]; -}; -#define IOCTL_KGSL_GPUMEM_ALLOC_ID _IOWR(KGSL_IOC_TYPE, 0x34, struct kgsl_gpumem_alloc_id) -struct kgsl_gpumem_free_id { - unsigned int id; - unsigned int __pad; -}; -#define IOCTL_KGSL_GPUMEM_FREE_ID _IOWR(KGSL_IOC_TYPE, 0x35, struct kgsl_gpumem_free_id) -struct kgsl_gpumem_get_info { - unsigned long gpuaddr; - unsigned int id; - unsigned int flags; - size_t size; - size_t mmapsize; - unsigned long useraddr; - unsigned long __pad[4]; -}; -#define IOCTL_KGSL_GPUMEM_GET_INFO _IOWR(KGSL_IOC_TYPE, 0x36, struct kgsl_gpumem_get_info) -struct kgsl_gpumem_sync_cache { - unsigned long gpuaddr; - unsigned int id; - unsigned int op; - size_t offset; - size_t length; -}; -#define KGSL_GPUMEM_CACHE_CLEAN (1 << 0) -#define KGSL_GPUMEM_CACHE_TO_GPU KGSL_GPUMEM_CACHE_CLEAN -#define KGSL_GPUMEM_CACHE_INV (1 << 1) -#define KGSL_GPUMEM_CACHE_FROM_GPU KGSL_GPUMEM_CACHE_INV -#define KGSL_GPUMEM_CACHE_FLUSH (KGSL_GPUMEM_CACHE_CLEAN | KGSL_GPUMEM_CACHE_INV) -#define KGSL_GPUMEM_CACHE_RANGE (1 << 31U) -#define IOCTL_KGSL_GPUMEM_SYNC_CACHE _IOW(KGSL_IOC_TYPE, 0x37, struct kgsl_gpumem_sync_cache) -struct kgsl_perfcounter_get { - unsigned int groupid; - unsigned int countable; - unsigned int offset; - unsigned int offset_hi; - unsigned int __pad; -}; -#define IOCTL_KGSL_PERFCOUNTER_GET _IOWR(KGSL_IOC_TYPE, 0x38, struct kgsl_perfcounter_get) -struct kgsl_perfcounter_put { - unsigned int groupid; - unsigned int countable; - unsigned int __pad[2]; -}; -#define IOCTL_KGSL_PERFCOUNTER_PUT _IOW(KGSL_IOC_TYPE, 0x39, struct kgsl_perfcounter_put) -struct kgsl_perfcounter_query { - unsigned int groupid; - unsigned int * countables; - unsigned int count; - unsigned int max_counters; - unsigned int __pad[2]; -}; -#define IOCTL_KGSL_PERFCOUNTER_QUERY _IOWR(KGSL_IOC_TYPE, 0x3A, struct kgsl_perfcounter_query) -struct kgsl_perfcounter_read_group { - unsigned int groupid; - unsigned int countable; - unsigned long long value; -}; -struct kgsl_perfcounter_read { - struct kgsl_perfcounter_read_group * reads; - unsigned int count; - unsigned int __pad[2]; -}; -#define IOCTL_KGSL_PERFCOUNTER_READ _IOWR(KGSL_IOC_TYPE, 0x3B, struct kgsl_perfcounter_read) -struct kgsl_gpumem_sync_cache_bulk { - unsigned int * id_list; - unsigned int count; - unsigned int op; - unsigned int __pad[2]; -}; -#define IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK _IOWR(KGSL_IOC_TYPE, 0x3C, struct kgsl_gpumem_sync_cache_bulk) -struct kgsl_cmd_syncpoint_timestamp { - unsigned int context_id; - unsigned int timestamp; -}; -struct kgsl_cmd_syncpoint_fence { - int fd; -}; -struct kgsl_cmd_syncpoint { - int type; - void * priv; - size_t size; -}; -#define KGSL_IBDESC_MEMLIST 0x1 -#define KGSL_IBDESC_PROFILING_BUFFER 0x2 -struct kgsl_submit_commands { - unsigned int context_id; - unsigned int flags; - struct kgsl_ibdesc * cmdlist; - unsigned int numcmds; - struct kgsl_cmd_syncpoint * synclist; - unsigned int numsyncs; - unsigned int timestamp; - unsigned int __pad[4]; -}; -#define IOCTL_KGSL_SUBMIT_COMMANDS _IOWR(KGSL_IOC_TYPE, 0x3D, struct kgsl_submit_commands) -struct kgsl_device_constraint { - unsigned int type; - unsigned int context_id; - void * data; - size_t size; -}; -#define KGSL_CONSTRAINT_NONE 0 -#define KGSL_CONSTRAINT_PWRLEVEL 1 -#define KGSL_CONSTRAINT_L3_NONE 2 -#define KGSL_CONSTRAINT_L3_PWRLEVEL 3 -#define KGSL_CONSTRAINT_PWR_MIN 0 -#define KGSL_CONSTRAINT_PWR_MAX 1 -#define KGSL_CONSTRAINT_L3_PWR_MED 0 -#define KGSL_CONSTRAINT_L3_PWR_MAX 1 -struct kgsl_device_constraint_pwrlevel { - unsigned int level; -}; -struct kgsl_syncsource_create { - unsigned int id; - unsigned int __pad[3]; -}; -#define IOCTL_KGSL_SYNCSOURCE_CREATE _IOWR(KGSL_IOC_TYPE, 0x40, struct kgsl_syncsource_create) -struct kgsl_syncsource_destroy { - unsigned int id; - unsigned int __pad[3]; -}; -#define IOCTL_KGSL_SYNCSOURCE_DESTROY _IOWR(KGSL_IOC_TYPE, 0x41, struct kgsl_syncsource_destroy) -struct kgsl_syncsource_create_fence { - unsigned int id; - int fence_fd; - unsigned int __pad[4]; -}; -#define IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE _IOWR(KGSL_IOC_TYPE, 0x42, struct kgsl_syncsource_create_fence) -struct kgsl_syncsource_signal_fence { - unsigned int id; - int fence_fd; - unsigned int __pad[4]; -}; -#define IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE _IOWR(KGSL_IOC_TYPE, 0x43, struct kgsl_syncsource_signal_fence) -struct kgsl_cff_sync_gpuobj { - uint64_t offset; - uint64_t length; - unsigned int id; -}; -#define IOCTL_KGSL_CFF_SYNC_GPUOBJ _IOW(KGSL_IOC_TYPE, 0x44, struct kgsl_cff_sync_gpuobj) -struct kgsl_gpuobj_alloc { - uint64_t size; - uint64_t flags; - uint64_t va_len; - uint64_t mmapsize; - unsigned int id; - unsigned int metadata_len; - uint64_t metadata; -}; -#define KGSL_GPUOBJ_ALLOC_METADATA_MAX 64 -#define IOCTL_KGSL_GPUOBJ_ALLOC _IOWR(KGSL_IOC_TYPE, 0x45, struct kgsl_gpuobj_alloc) -struct kgsl_gpuobj_free { - uint64_t flags; - uint64_t priv; - unsigned int id; - unsigned int type; - unsigned int len; -}; -#define KGSL_GPUOBJ_FREE_ON_EVENT 1 -#define KGSL_GPU_EVENT_TIMESTAMP 1 -#define KGSL_GPU_EVENT_FENCE 2 -struct kgsl_gpu_event_timestamp { - unsigned int context_id; - unsigned int timestamp; -}; -struct kgsl_gpu_event_fence { - int fd; -}; -#define IOCTL_KGSL_GPUOBJ_FREE _IOW(KGSL_IOC_TYPE, 0x46, struct kgsl_gpuobj_free) -struct kgsl_gpuobj_info { - uint64_t gpuaddr; - uint64_t flags; - uint64_t size; - uint64_t va_len; - uint64_t va_addr; - unsigned int id; -}; -#define IOCTL_KGSL_GPUOBJ_INFO _IOWR(KGSL_IOC_TYPE, 0x47, struct kgsl_gpuobj_info) -struct kgsl_gpuobj_import { - uint64_t priv; - uint64_t priv_len; - uint64_t flags; - unsigned int type; - unsigned int id; -}; -struct kgsl_gpuobj_import_dma_buf { - int fd; -}; -struct kgsl_gpuobj_import_useraddr { - uint64_t virtaddr; -}; -#define IOCTL_KGSL_GPUOBJ_IMPORT _IOWR(KGSL_IOC_TYPE, 0x48, struct kgsl_gpuobj_import) -struct kgsl_gpuobj_sync_obj { - uint64_t offset; - uint64_t length; - unsigned int id; - unsigned int op; -}; -struct kgsl_gpuobj_sync { - uint64_t objs; - unsigned int obj_len; - unsigned int count; -}; -#define IOCTL_KGSL_GPUOBJ_SYNC _IOW(KGSL_IOC_TYPE, 0x49, struct kgsl_gpuobj_sync) -struct kgsl_command_object { - uint64_t offset; - uint64_t gpuaddr; - uint64_t size; - unsigned int flags; - unsigned int id; -}; -struct kgsl_command_syncpoint { - uint64_t priv; - uint64_t size; - unsigned int type; -}; -struct kgsl_gpu_command { - uint64_t flags; - uint64_t cmdlist; - unsigned int cmdsize; - unsigned int numcmds; - uint64_t objlist; - unsigned int objsize; - unsigned int numobjs; - uint64_t synclist; - unsigned int syncsize; - unsigned int numsyncs; - unsigned int context_id; - unsigned int timestamp; -}; -#define IOCTL_KGSL_GPU_COMMAND _IOWR(KGSL_IOC_TYPE, 0x4A, struct kgsl_gpu_command) -struct kgsl_preemption_counters_query { - uint64_t counters; - unsigned int size_user; - unsigned int size_priority_level; - unsigned int max_priority_level; -}; -#define IOCTL_KGSL_PREEMPTIONCOUNTER_QUERY _IOWR(KGSL_IOC_TYPE, 0x4B, struct kgsl_preemption_counters_query) -#define KGSL_GPUOBJ_SET_INFO_METADATA (1 << 0) -#define KGSL_GPUOBJ_SET_INFO_TYPE (1 << 1) -struct kgsl_gpuobj_set_info { - uint64_t flags; - uint64_t metadata; - unsigned int id; - unsigned int metadata_len; - unsigned int type; -}; -#define IOCTL_KGSL_GPUOBJ_SET_INFO _IOW(KGSL_IOC_TYPE, 0x4C, struct kgsl_gpuobj_set_info) -struct kgsl_sparse_phys_alloc { - uint64_t size; - uint64_t pagesize; - uint64_t flags; - unsigned int id; -}; -#define IOCTL_KGSL_SPARSE_PHYS_ALLOC _IOWR(KGSL_IOC_TYPE, 0x50, struct kgsl_sparse_phys_alloc) -struct kgsl_sparse_phys_free { - unsigned int id; -}; -#define IOCTL_KGSL_SPARSE_PHYS_FREE _IOW(KGSL_IOC_TYPE, 0x51, struct kgsl_sparse_phys_free) -struct kgsl_sparse_virt_alloc { - uint64_t size; - uint64_t pagesize; - uint64_t flags; - uint64_t gpuaddr; - unsigned int id; -}; -#define IOCTL_KGSL_SPARSE_VIRT_ALLOC _IOWR(KGSL_IOC_TYPE, 0x52, struct kgsl_sparse_virt_alloc) -struct kgsl_sparse_virt_free { - unsigned int id; -}; -#define IOCTL_KGSL_SPARSE_VIRT_FREE _IOW(KGSL_IOC_TYPE, 0x53, struct kgsl_sparse_virt_free) -struct kgsl_sparse_binding_object { - uint64_t virtoffset; - uint64_t physoffset; - uint64_t size; - uint64_t flags; - unsigned int id; -}; -struct kgsl_sparse_bind { - uint64_t list; - unsigned int id; - unsigned int size; - unsigned int count; -}; -#define IOCTL_KGSL_SPARSE_BIND _IOW(KGSL_IOC_TYPE, 0x54, struct kgsl_sparse_bind) -struct kgsl_gpu_sparse_command { - uint64_t flags; - uint64_t sparselist; - uint64_t synclist; - unsigned int sparsesize; - unsigned int numsparse; - unsigned int syncsize; - unsigned int numsyncs; - unsigned int context_id; - unsigned int timestamp; - unsigned int id; -}; -#define IOCTL_KGSL_GPU_SPARSE_COMMAND _IOWR(KGSL_IOC_TYPE, 0x55, struct kgsl_gpu_sparse_command) -#endif - diff --git a/sdm710/kernel-headers/linux/msm_mdp.h b/sdm710/kernel-headers/linux/msm_mdp.h deleted file mode 100644 index a7d21135..00000000 --- a/sdm710/kernel-headers/linux/msm_mdp.h +++ /dev/null @@ -1,1150 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _MSM_MDP_H_ -#define _MSM_MDP_H_ -#include <stdint.h> -#include <linux/fb.h> -#define MSMFB_IOCTL_MAGIC 'm' -#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) -#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) -#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) -#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) -#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) -#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) -#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) -#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) -#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) -#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, struct mdp_overlay) -#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) -#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, struct msmfb_overlay_data) -#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY -#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, struct mdp_page_protection) -#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, struct mdp_page_protection) -#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, struct mdp_overlay) -#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) -#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, struct msmfb_overlay_blt) -#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) -#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, struct mdp_histogram_start_req) -#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) -#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) -#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, struct msmfb_overlay_3d) -#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, struct msmfb_mixer_info_req) -#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, struct msmfb_overlay_data) -#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) -#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) -#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) -#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, struct msmfb_data) -#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, struct msmfb_data) -#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) -#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) -#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) -#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) -#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) -#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) -#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, struct mdp_display_commit) -#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) -#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) -#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, unsigned int) -#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) -#define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, struct mdp_overlay_list) -#define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) -#define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, struct mdp_pp_feature_version) -#define FB_TYPE_3D_PANEL 0x10101010 -#define MDP_IMGTYPE2_START 0x10000 -#define MSMFB_DRIVER_VERSION 0xF9E8D701 -#define MDP_IMGTYPE_END 0x100 -#define MDSS_GET_MAJOR(rev) ((rev) >> 28) -#define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) -#define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) -#define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) -#define IS_MDSS_MAJOR_MINOR_SAME(rev1,rev2) (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) -#define MDSS_MDP_REV(major,minor,step) ((((major) & 0x000F) << 28) | (((minor) & 0x0FFF) << 16) | ((step) & 0xFFFF)) -#define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) -#define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) -#define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) -#define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) -#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) -#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) -#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) -#define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) -#define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) -#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) -#define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) -#define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) -#define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) -#define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) -#define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) -#define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) -#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) -#define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) -#define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) -#define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) -#define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) -#define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) -#define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) -enum { - NOTIFY_UPDATE_INIT, - NOTIFY_UPDATE_DEINIT, - NOTIFY_UPDATE_START, - NOTIFY_UPDATE_STOP, - NOTIFY_UPDATE_POWER_OFF, -}; -enum { - NOTIFY_TYPE_NO_UPDATE, - NOTIFY_TYPE_SUSPEND, - NOTIFY_TYPE_UPDATE, - NOTIFY_TYPE_BL_UPDATE, - NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, -}; -enum { - MDP_RGB_565, - MDP_XRGB_8888, - MDP_Y_CBCR_H2V2, - MDP_Y_CBCR_H2V2_ADRENO, - MDP_ARGB_8888, - MDP_RGB_888, - MDP_Y_CRCB_H2V2, - MDP_YCRYCB_H2V1, - MDP_CBYCRY_H2V1, - MDP_Y_CRCB_H2V1, - MDP_Y_CBCR_H2V1, - MDP_Y_CRCB_H1V2, - MDP_Y_CBCR_H1V2, - MDP_RGBA_8888, - MDP_BGRA_8888, - MDP_RGBX_8888, - MDP_Y_CRCB_H2V2_TILE, - MDP_Y_CBCR_H2V2_TILE, - MDP_Y_CR_CB_H2V2, - MDP_Y_CR_CB_GH2V2, - MDP_Y_CB_CR_H2V2, - MDP_Y_CRCB_H1V1, - MDP_Y_CBCR_H1V1, - MDP_YCRCB_H1V1, - MDP_YCBCR_H1V1, - MDP_BGR_565, - MDP_BGR_888, - MDP_Y_CBCR_H2V2_VENUS, - MDP_BGRX_8888, - MDP_RGBA_8888_TILE, - MDP_ARGB_8888_TILE, - MDP_ABGR_8888_TILE, - MDP_BGRA_8888_TILE, - MDP_RGBX_8888_TILE, - MDP_XRGB_8888_TILE, - MDP_XBGR_8888_TILE, - MDP_BGRX_8888_TILE, - MDP_YCBYCR_H2V1, - MDP_RGB_565_TILE, - MDP_BGR_565_TILE, - MDP_ARGB_1555, - MDP_RGBA_5551, - MDP_ARGB_4444, - MDP_RGBA_4444, - MDP_RGB_565_UBWC, - MDP_RGBA_8888_UBWC, - MDP_Y_CBCR_H2V2_UBWC, - MDP_RGBX_8888_UBWC, - MDP_Y_CRCB_H2V2_VENUS, - MDP_IMGTYPE_LIMIT, - MDP_RGB_BORDERFILL, - MDP_XRGB_1555, - MDP_RGBX_5551, - MDP_XRGB_4444, - MDP_RGBX_4444, - MDP_ABGR_1555, - MDP_BGRA_5551, - MDP_XBGR_1555, - MDP_BGRX_5551, - MDP_ABGR_4444, - MDP_BGRA_4444, - MDP_XBGR_4444, - MDP_BGRX_4444, - MDP_ABGR_8888, - MDP_XBGR_8888, - MDP_RGBA_1010102, - MDP_ARGB_2101010, - MDP_RGBX_1010102, - MDP_XRGB_2101010, - MDP_BGRA_1010102, - MDP_ABGR_2101010, - MDP_BGRX_1010102, - MDP_XBGR_2101010, - MDP_RGBA_1010102_UBWC, - MDP_RGBX_1010102_UBWC, - MDP_Y_CBCR_H2V2_P010, - MDP_Y_CBCR_H2V2_TP10_UBWC, - MDP_CRYCBY_H2V1, - MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, - MDP_FB_FORMAT = MDP_IMGTYPE2_START, - MDP_IMGTYPE_LIMIT2 -}; -#define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 -enum { - PMEM_IMG, - FB_IMG, -}; -enum { - HSIC_HUE = 0, - HSIC_SAT, - HSIC_INT, - HSIC_CON, - NUM_HSIC_PARAM, -}; -enum mdss_mdp_max_bw_mode { - MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, - MDSS_MAX_BW_LIMIT_CAMERA = 0x2, - MDSS_MAX_BW_LIMIT_HFLIP = 0x4, - MDSS_MAX_BW_LIMIT_VFLIP = 0x8, -}; -#define MDSS_MDP_ROT_ONLY 0x80 -#define MDSS_MDP_RIGHT_MIXER 0x100 -#define MDSS_MDP_DUAL_PIPE 0x200 -#define MDP_ROT_NOP 0 -#define MDP_FLIP_LR 0x1 -#define MDP_FLIP_UD 0x2 -#define MDP_ROT_90 0x4 -#define MDP_ROT_180 (MDP_FLIP_UD | MDP_FLIP_LR) -#define MDP_ROT_270 (MDP_ROT_90 | MDP_FLIP_UD | MDP_FLIP_LR) -#define MDP_DITHER 0x8 -#define MDP_BLUR 0x10 -#define MDP_BLEND_FG_PREMULT 0x20000 -#define MDP_IS_FG 0x40000 -#define MDP_SOLID_FILL 0x00000020 -#define MDP_VPU_PIPE 0x00000040 -#define MDP_DEINTERLACE 0x80000000 -#define MDP_SHARPENING 0x40000000 -#define MDP_NO_DMA_BARRIER_START 0x20000000 -#define MDP_NO_DMA_BARRIER_END 0x10000000 -#define MDP_NO_BLIT 0x08000000 -#define MDP_BLIT_WITH_DMA_BARRIERS 0x000 -#define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) -#define MDP_BLIT_SRC_GEM 0x04000000 -#define MDP_BLIT_DST_GEM 0x02000000 -#define MDP_BLIT_NON_CACHED 0x01000000 -#define MDP_OV_PIPE_SHARE 0x00800000 -#define MDP_DEINTERLACE_ODD 0x00400000 -#define MDP_OV_PLAY_NOWAIT 0x00200000 -#define MDP_SOURCE_ROTATED_90 0x00100000 -#define MDP_OVERLAY_PP_CFG_EN 0x00080000 -#define MDP_BACKEND_COMPOSITION 0x00040000 -#define MDP_BORDERFILL_SUPPORTED 0x00010000 -#define MDP_SECURE_OVERLAY_SESSION 0x00008000 -#define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 -#define MDP_OV_PIPE_FORCE_DMA 0x00004000 -#define MDP_MEMORY_ID_TYPE_FB 0x00001000 -#define MDP_BWC_EN 0x00000400 -#define MDP_DECIMATION_EN 0x00000800 -#define MDP_SMP_FORCE_ALLOC 0x00200000 -#define MDP_TRANSP_NOP 0xffffffff -#define MDP_ALPHA_NOP 0xff -#define MDP_FB_PAGE_PROTECTION_NONCACHED (0) -#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) -#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) -#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) -#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) -#define MDP_FB_PAGE_PROTECTION_INVALID (5) -#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) -#define MDP_DEEP_COLOR_YUV444 0x1 -#define MDP_DEEP_COLOR_RGB30B 0x2 -#define MDP_DEEP_COLOR_RGB36B 0x4 -#define MDP_DEEP_COLOR_RGB48B 0x8 -struct mdp_rect { - uint32_t x; - uint32_t y; - uint32_t w; - uint32_t h; -}; -struct mdp_img { - uint32_t width; - uint32_t height; - uint32_t format; - uint32_t offset; - int memory_id; - uint32_t priv; -}; -struct mult_factor { - uint32_t numer; - uint32_t denom; -}; -#define MDP_CCS_RGB2YUV 0 -#define MDP_CCS_YUV2RGB 1 -#define MDP_CCS_SIZE 9 -#define MDP_BV_SIZE 3 -struct mdp_ccs { - int direction; - uint16_t ccs[MDP_CCS_SIZE]; - uint16_t bv[MDP_BV_SIZE]; -}; -struct mdp_csc { - int id; - uint32_t csc_mv[9]; - uint32_t csc_pre_bv[3]; - uint32_t csc_post_bv[3]; - uint32_t csc_pre_lv[6]; - uint32_t csc_post_lv[6]; -}; -#define MDP_BLIT_REQ_VERSION 3 -struct color { - uint32_t r; - uint32_t g; - uint32_t b; - uint32_t alpha; -}; -struct mdp_blit_req { - struct mdp_img src; - struct mdp_img dst; - struct mdp_rect src_rect; - struct mdp_rect dst_rect; - struct color const_color; - uint32_t alpha; - uint32_t transp_mask; - uint32_t flags; - int sharpening_strength; - uint8_t color_space; - uint32_t fps; -}; -struct mdp_blit_req_list { - uint32_t count; - struct mdp_blit_req req[]; -}; -#define MSMFB_DATA_VERSION 2 -struct msmfb_data { - uint32_t offset; - int memory_id; - int id; - uint32_t flags; - uint32_t priv; - uint32_t iova; -}; -#define MSMFB_NEW_REQUEST - 1 -struct msmfb_overlay_data { - uint32_t id; - struct msmfb_data data; - uint32_t version_key; - struct msmfb_data plane1_data; - struct msmfb_data plane2_data; - struct msmfb_data dst_data; -}; -struct msmfb_img { - uint32_t width; - uint32_t height; - uint32_t format; -}; -#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 -struct msmfb_writeback_data { - struct msmfb_data buf_info; - struct msmfb_img img; -}; -#define MDP_PP_OPS_ENABLE 0x1 -#define MDP_PP_OPS_READ 0x2 -#define MDP_PP_OPS_WRITE 0x4 -#define MDP_PP_OPS_DISABLE 0x8 -#define MDP_PP_IGC_FLAG_ROM0 0x10 -#define MDP_PP_IGC_FLAG_ROM1 0x20 -#define MDSS_PP_DSPP_CFG 0x000 -#define MDSS_PP_SSPP_CFG 0x100 -#define MDSS_PP_LM_CFG 0x200 -#define MDSS_PP_WB_CFG 0x300 -#define MDSS_PP_ARG_MASK 0x3C00 -#define MDSS_PP_ARG_NUM 4 -#define MDSS_PP_ARG_SHIFT 10 -#define MDSS_PP_LOCATION_MASK 0x0300 -#define MDSS_PP_LOGICAL_MASK 0x00FF -#define MDSS_PP_ADD_ARG(var,arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) -#define PP_ARG(x,var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) -#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) -#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) -struct mdp_qseed_cfg { - uint32_t table_num; - uint32_t ops; - uint32_t len; - uint32_t * data; -}; -struct mdp_sharp_cfg { - uint32_t flags; - uint32_t strength; - uint32_t edge_thr; - uint32_t smooth_thr; - uint32_t noise_thr; -}; -struct mdp_qseed_cfg_data { - uint32_t block; - struct mdp_qseed_cfg qseed_data; -}; -#define MDP_OVERLAY_PP_CSC_CFG 0x1 -#define MDP_OVERLAY_PP_QSEED_CFG 0x2 -#define MDP_OVERLAY_PP_PA_CFG 0x4 -#define MDP_OVERLAY_PP_IGC_CFG 0x8 -#define MDP_OVERLAY_PP_SHARP_CFG 0x10 -#define MDP_OVERLAY_PP_HIST_CFG 0x20 -#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 -#define MDP_OVERLAY_PP_PA_V2_CFG 0x80 -#define MDP_OVERLAY_PP_PCC_CFG 0x100 -#define MDP_CSC_FLAG_ENABLE 0x1 -#define MDP_CSC_FLAG_YUV_IN 0x2 -#define MDP_CSC_FLAG_YUV_OUT 0x4 -#define MDP_CSC_MATRIX_COEFF_SIZE 9 -#define MDP_CSC_CLAMP_SIZE 6 -#define MDP_CSC_BIAS_SIZE 3 -struct mdp_csc_cfg { - uint32_t flags; - uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; - uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; - uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; - uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; - uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; -}; -struct mdp_csc_cfg_data { - uint32_t block; - struct mdp_csc_cfg csc_data; -}; -struct mdp_pa_cfg { - uint32_t flags; - uint32_t hue_adj; - uint32_t sat_adj; - uint32_t val_adj; - uint32_t cont_adj; -}; -struct mdp_pa_mem_col_cfg { - uint32_t color_adjust_p0; - uint32_t color_adjust_p1; - uint32_t hue_region; - uint32_t sat_region; - uint32_t val_region; -}; -#define MDP_SIX_ZONE_LUT_SIZE 384 -#define MDP_PP_PA_HUE_ENABLE 0x10 -#define MDP_PP_PA_SAT_ENABLE 0x20 -#define MDP_PP_PA_VAL_ENABLE 0x40 -#define MDP_PP_PA_CONT_ENABLE 0x80 -#define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 -#define MDP_PP_PA_SKIN_ENABLE 0x200 -#define MDP_PP_PA_SKY_ENABLE 0x400 -#define MDP_PP_PA_FOL_ENABLE 0x800 -#define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 -#define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 -#define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 -#define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 -#define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 -#define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 -#define MDP_PP_PA_HUE_MASK 0x1000 -#define MDP_PP_PA_SAT_MASK 0x2000 -#define MDP_PP_PA_VAL_MASK 0x4000 -#define MDP_PP_PA_CONT_MASK 0x8000 -#define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 -#define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 -#define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 -#define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 -#define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 -#define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 -#define MDP_PP_PA_MEM_PROTECT_EN 0x400000 -#define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 -#define MDP_PP_PA_LEFT_HOLD 0x1 -#define MDP_PP_PA_RIGHT_HOLD 0x2 -struct mdp_pa_v2_data { - uint32_t flags; - uint32_t global_hue_adj; - uint32_t global_sat_adj; - uint32_t global_val_adj; - uint32_t global_cont_adj; - struct mdp_pa_mem_col_cfg skin_cfg; - struct mdp_pa_mem_col_cfg sky_cfg; - struct mdp_pa_mem_col_cfg fol_cfg; - uint32_t six_zone_len; - uint32_t six_zone_thresh; - uint32_t * six_zone_curve_p0; - uint32_t * six_zone_curve_p1; -}; -struct mdp_pa_mem_col_data_v1_7 { - uint32_t color_adjust_p0; - uint32_t color_adjust_p1; - uint32_t color_adjust_p2; - uint32_t blend_gain; - uint8_t sat_hold; - uint8_t val_hold; - uint32_t hue_region; - uint32_t sat_region; - uint32_t val_region; -}; -struct mdp_pa_data_v1_7 { - uint32_t mode; - uint32_t global_hue_adj; - uint32_t global_sat_adj; - uint32_t global_val_adj; - uint32_t global_cont_adj; - struct mdp_pa_mem_col_data_v1_7 skin_cfg; - struct mdp_pa_mem_col_data_v1_7 sky_cfg; - struct mdp_pa_mem_col_data_v1_7 fol_cfg; - uint32_t six_zone_thresh; - uint32_t six_zone_adj_p0; - uint32_t six_zone_adj_p1; - uint8_t six_zone_sat_hold; - uint8_t six_zone_val_hold; - uint32_t six_zone_len; - uint32_t * six_zone_curve_p0; - uint32_t * six_zone_curve_p1; -}; -struct mdp_pa_v2_cfg_data { - uint32_t version; - uint32_t block; - uint32_t flags; - struct mdp_pa_v2_data pa_v2_data; - void * cfg_payload; -}; -enum { - mdp_igc_rec601 = 1, - mdp_igc_rec709, - mdp_igc_srgb, - mdp_igc_custom, - mdp_igc_rec_max, -}; -struct mdp_igc_lut_data { - uint32_t block; - uint32_t version; - uint32_t len, ops; - uint32_t * c0_c1_data; - uint32_t * c2_data; - void * cfg_payload; -}; -struct mdp_igc_lut_data_v1_7 { - uint32_t table_fmt; - uint32_t len; - uint32_t * c0_c1_data; - uint32_t * c2_data; -}; -struct mdp_igc_lut_data_payload { - uint32_t table_fmt; - uint32_t len; - uint64_t c0_c1_data; - uint64_t c2_data; - uint32_t strength; -}; -struct mdp_histogram_cfg { - uint32_t ops; - uint32_t block; - uint8_t frame_cnt; - uint8_t bit_mask; - uint16_t num_bins; -}; -struct mdp_hist_lut_data_v1_7 { - uint32_t len; - uint32_t * data; -}; -struct mdp_hist_lut_data { - uint32_t block; - uint32_t version; - uint32_t hist_lut_first; - uint32_t ops; - uint32_t len; - uint32_t * data; - void * cfg_payload; -}; -struct mdp_pcc_coeff { - uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; -}; -struct mdp_pcc_coeff_v1_7 { - uint32_t c, r, g, b, rg, gb, rb, rgb; -}; -struct mdp_pcc_data_v1_7 { - struct mdp_pcc_coeff_v1_7 r, g, b; -}; -struct mdp_pcc_cfg_data { - uint32_t version; - uint32_t block; - uint32_t ops; - struct mdp_pcc_coeff r, g, b; - void * cfg_payload; -}; -enum { - mdp_lut_igc, - mdp_lut_pgc, - mdp_lut_hist, - mdp_lut_rgb, - mdp_lut_max, -}; -struct mdp_overlay_pp_params { - uint32_t config_ops; - struct mdp_csc_cfg csc_cfg; - struct mdp_qseed_cfg qseed_cfg[2]; - struct mdp_pa_cfg pa_cfg; - struct mdp_pa_v2_data pa_v2_cfg; - struct mdp_igc_lut_data igc_cfg; - struct mdp_sharp_cfg sharp_cfg; - struct mdp_histogram_cfg hist_cfg; - struct mdp_hist_lut_data hist_lut_cfg; - struct mdp_pa_v2_cfg_data pa_v2_cfg_data; - struct mdp_pcc_cfg_data pcc_cfg_data; -}; -enum mdss_mdp_blend_op { - BLEND_OP_NOT_DEFINED = 0, - BLEND_OP_OPAQUE, - BLEND_OP_PREMULTIPLIED, - BLEND_OP_COVERAGE, - BLEND_OP_MAX, -}; -#define DECIMATED_DIMENSION(dim,deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) -#define MAX_PLANES 4 -struct mdp_scale_data { - uint8_t enable_pxl_ext; - int init_phase_x[MAX_PLANES]; - int phase_step_x[MAX_PLANES]; - int init_phase_y[MAX_PLANES]; - int phase_step_y[MAX_PLANES]; - int num_ext_pxls_left[MAX_PLANES]; - int num_ext_pxls_right[MAX_PLANES]; - int num_ext_pxls_top[MAX_PLANES]; - int num_ext_pxls_btm[MAX_PLANES]; - int left_ftch[MAX_PLANES]; - int left_rpt[MAX_PLANES]; - int right_ftch[MAX_PLANES]; - int right_rpt[MAX_PLANES]; - int top_rpt[MAX_PLANES]; - int btm_rpt[MAX_PLANES]; - int top_ftch[MAX_PLANES]; - int btm_ftch[MAX_PLANES]; - uint32_t roi_w[MAX_PLANES]; -}; -enum mdp_overlay_pipe_type { - PIPE_TYPE_AUTO = 0, - PIPE_TYPE_VIG, - PIPE_TYPE_RGB, - PIPE_TYPE_DMA, - PIPE_TYPE_CURSOR, - PIPE_TYPE_MAX, -}; -struct mdp_overlay { - struct msmfb_img src; - struct mdp_rect src_rect; - struct mdp_rect dst_rect; - uint32_t z_order; - uint32_t is_fg; - uint32_t alpha; - uint32_t blend_op; - uint32_t transp_mask; - uint32_t flags; - uint32_t pipe_type; - uint32_t id; - uint8_t priority; - uint32_t user_data[6]; - uint32_t bg_color; - uint8_t horz_deci; - uint8_t vert_deci; - struct mdp_overlay_pp_params overlay_pp_cfg; - struct mdp_scale_data scale; - uint8_t color_space; - uint32_t frame_rate; -}; -struct msmfb_overlay_3d { - uint32_t is_3d; - uint32_t width; - uint32_t height; -}; -struct msmfb_overlay_blt { - uint32_t enable; - uint32_t offset; - uint32_t width; - uint32_t height; - uint32_t bpp; -}; -struct mdp_histogram { - uint32_t frame_cnt; - uint32_t bin_cnt; - uint32_t * r; - uint32_t * g; - uint32_t * b; -}; -#define MISR_CRC_BATCH_SIZE 32 -enum { - DISPLAY_MISR_EDP, - DISPLAY_MISR_DSI0, - DISPLAY_MISR_DSI1, - DISPLAY_MISR_HDMI, - DISPLAY_MISR_LCDC, - DISPLAY_MISR_MDP, - DISPLAY_MISR_ATV, - DISPLAY_MISR_DSI_CMD, - DISPLAY_MISR_MAX -}; -enum { - MISR_OP_NONE, - MISR_OP_SFM, - MISR_OP_MFM, - MISR_OP_BM, - MISR_OP_MAX -}; -struct mdp_misr { - uint32_t block_id; - uint32_t frame_count; - uint32_t crc_op_mode; - uint32_t crc_value[MISR_CRC_BATCH_SIZE]; -}; -enum { - MDP_BLOCK_RESERVED = 0, - MDP_BLOCK_OVERLAY_0, - MDP_BLOCK_OVERLAY_1, - MDP_BLOCK_VG_1, - MDP_BLOCK_VG_2, - MDP_BLOCK_RGB_1, - MDP_BLOCK_RGB_2, - MDP_BLOCK_DMA_P, - MDP_BLOCK_DMA_S, - MDP_BLOCK_DMA_E, - MDP_BLOCK_OVERLAY_2, - MDP_LOGICAL_BLOCK_DISP_0 = 0x10, - MDP_LOGICAL_BLOCK_DISP_1, - MDP_LOGICAL_BLOCK_DISP_2, - MDP_BLOCK_MAX, -}; -struct mdp_histogram_start_req { - uint32_t block; - uint8_t frame_cnt; - uint8_t bit_mask; - uint16_t num_bins; -}; -struct mdp_histogram_data { - uint32_t block; - uint32_t bin_cnt; - uint32_t * c0; - uint32_t * c1; - uint32_t * c2; - uint32_t * extra_info; -}; -#define GC_LUT_ENTRIES_V1_7 512 -struct mdp_ar_gc_lut_data { - uint32_t x_start; - uint32_t slope; - uint32_t offset; -}; -#define MDP_PP_PGC_ROUNDING_ENABLE 0x10 -struct mdp_pgc_lut_data { - uint32_t version; - uint32_t block; - uint32_t flags; - uint8_t num_r_stages; - uint8_t num_g_stages; - uint8_t num_b_stages; - struct mdp_ar_gc_lut_data * r_data; - struct mdp_ar_gc_lut_data * g_data; - struct mdp_ar_gc_lut_data * b_data; - void * cfg_payload; -}; -#define PGC_LUT_ENTRIES 1024 -struct mdp_pgc_lut_data_v1_7 { - uint32_t len; - uint32_t * c0_data; - uint32_t * c1_data; - uint32_t * c2_data; -}; -struct mdp_rgb_lut_data { - uint32_t flags; - uint32_t lut_type; - struct fb_cmap cmap; -}; -enum { - mdp_rgb_lut_gc, - mdp_rgb_lut_hist, -}; -struct mdp_lut_cfg_data { - uint32_t lut_type; - union { - struct mdp_igc_lut_data igc_lut_data; - struct mdp_pgc_lut_data pgc_lut_data; - struct mdp_hist_lut_data hist_lut_data; - struct mdp_rgb_lut_data rgb_lut_data; - } data; -}; -struct mdp_bl_scale_data { - uint32_t min_lvl; - uint32_t scale; -}; -struct mdp_pa_cfg_data { - uint32_t block; - struct mdp_pa_cfg pa_data; -}; -#define MDP_DITHER_DATA_V1_7_SZ 16 -struct mdp_dither_data_v1_7 { - uint32_t g_y_depth; - uint32_t r_cr_depth; - uint32_t b_cb_depth; - uint32_t len; - uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; - uint32_t temporal_en; -}; -struct mdp_pa_dither_data { - uint64_t data_flags; - uint32_t matrix_sz; - uint64_t matrix_data; - uint32_t strength; - uint32_t offset_en; -}; -struct mdp_dither_cfg_data { - uint32_t version; - uint32_t block; - uint32_t flags; - uint32_t mode; - uint32_t g_y_depth; - uint32_t r_cr_depth; - uint32_t b_cb_depth; - void * cfg_payload; -}; -#define MDP_GAMUT_TABLE_NUM 8 -#define MDP_GAMUT_TABLE_NUM_V1_7 4 -#define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 -#define MDP_GAMUT_TABLE_V1_7_SZ 1229 -#define MDP_GAMUT_SCALE_OFF_SZ 16 -#define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 -struct mdp_gamut_cfg_data { - uint32_t block; - uint32_t flags; - uint32_t version; - uint32_t gamut_first; - uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; - uint16_t * r_tbl[MDP_GAMUT_TABLE_NUM]; - uint16_t * g_tbl[MDP_GAMUT_TABLE_NUM]; - uint16_t * b_tbl[MDP_GAMUT_TABLE_NUM]; - void * cfg_payload; -}; -enum { - mdp_gamut_fine_mode = 0x1, - mdp_gamut_coarse_mode, -}; -struct mdp_gamut_data_v1_7 { - uint32_t mode; - uint32_t map_en; - uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; - uint32_t * c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; - uint32_t * c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; - uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; - uint32_t * scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; -}; -struct mdp_calib_config_data { - uint32_t ops; - uint32_t addr; - uint32_t data; -}; -struct mdp_calib_config_buffer { - uint32_t ops; - uint32_t size; - uint32_t * buffer; -}; -struct mdp_calib_dcm_state { - uint32_t ops; - uint32_t dcm_state; -}; -enum { - DCM_UNINIT, - DCM_UNBLANK, - DCM_ENTER, - DCM_EXIT, - DCM_BLANK, - DTM_ENTER, - DTM_EXIT, -}; -#define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 -#define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 -#define MDSS_PP_SPLIT_MASK 0x30000000 -#define MDSS_MAX_BL_BRIGHTNESS 255 -#define AD_BL_LIN_LEN 256 -#define AD_BL_ATT_LUT_LEN 33 -#define MDSS_AD_MODE_AUTO_BL 0x0 -#define MDSS_AD_MODE_AUTO_STR 0x1 -#define MDSS_AD_MODE_TARG_STR 0x3 -#define MDSS_AD_MODE_MAN_STR 0x7 -#define MDSS_AD_MODE_CALIB 0xF -#define MDP_PP_AD_INIT 0x10 -#define MDP_PP_AD_CFG 0x20 -struct mdss_ad_init { - uint32_t asym_lut[33]; - uint32_t color_corr_lut[33]; - uint8_t i_control[2]; - uint16_t black_lvl; - uint16_t white_lvl; - uint8_t var; - uint8_t limit_ampl; - uint8_t i_dither; - uint8_t slope_max; - uint8_t slope_min; - uint8_t dither_ctl; - uint8_t format; - uint8_t auto_size; - uint16_t frame_w; - uint16_t frame_h; - uint8_t logo_v; - uint8_t logo_h; - uint32_t alpha; - uint32_t alpha_base; - uint32_t al_thresh; - uint32_t bl_lin_len; - uint32_t bl_att_len; - uint32_t * bl_lin; - uint32_t * bl_lin_inv; - uint32_t * bl_att_lut; -}; -#define MDSS_AD_BL_CTRL_MODE_EN 1 -#define MDSS_AD_BL_CTRL_MODE_DIS 0 -struct mdss_ad_cfg { - uint32_t mode; - uint32_t al_calib_lut[33]; - uint16_t backlight_min; - uint16_t backlight_max; - uint16_t backlight_scale; - uint16_t amb_light_min; - uint16_t filter[2]; - uint16_t calib[4]; - uint8_t strength_limit; - uint8_t t_filter_recursion; - uint16_t stab_itr; - uint32_t bl_ctrl_mode; -}; -struct mdss_ad_bl_cfg { - uint32_t bl_min_delta; - uint32_t bl_low_limit; -}; -struct mdss_ad_init_cfg { - uint32_t ops; - union { - struct mdss_ad_init init; - struct mdss_ad_cfg cfg; - } params; -}; -struct mdss_ad_input { - uint32_t mode; - union { - uint32_t amb_light; - uint32_t strength; - uint32_t calib_bl; - } in; - uint32_t output; -}; -#define MDSS_CALIB_MODE_BL 0x1 -struct mdss_calib_cfg { - uint32_t ops; - uint32_t calib_mask; -}; -enum { - mdp_op_pcc_cfg, - mdp_op_csc_cfg, - mdp_op_lut_cfg, - mdp_op_qseed_cfg, - mdp_bl_scale_cfg, - mdp_op_pa_cfg, - mdp_op_pa_v2_cfg, - mdp_op_dither_cfg, - mdp_op_gamut_cfg, - mdp_op_calib_cfg, - mdp_op_ad_cfg, - mdp_op_ad_input, - mdp_op_calib_mode, - mdp_op_calib_buffer, - mdp_op_calib_dcm_state, - mdp_op_max, - mdp_op_pa_dither_cfg, - mdp_op_ad_bl_cfg, - mdp_op_pp_max = 255, -}; -#define mdp_op_pa_dither_cfg mdp_op_pa_dither_cfg -#define mdp_op_pp_max mdp_op_pp_max -#define mdp_op_ad_bl_cfg mdp_op_ad_bl_cfg -enum { - WB_FORMAT_NV12, - WB_FORMAT_RGB_565, - WB_FORMAT_RGB_888, - WB_FORMAT_xRGB_8888, - WB_FORMAT_ARGB_8888, - WB_FORMAT_BGRA_8888, - WB_FORMAT_BGRX_8888, - WB_FORMAT_ARGB_8888_INPUT_ALPHA -}; -struct msmfb_mdp_pp { - uint32_t op; - union { - struct mdp_pcc_cfg_data pcc_cfg_data; - struct mdp_csc_cfg_data csc_cfg_data; - struct mdp_lut_cfg_data lut_cfg_data; - struct mdp_qseed_cfg_data qseed_cfg_data; - struct mdp_bl_scale_data bl_scale_data; - struct mdp_pa_cfg_data pa_cfg_data; - struct mdp_pa_v2_cfg_data pa_v2_cfg_data; - struct mdp_dither_cfg_data dither_cfg_data; - struct mdp_gamut_cfg_data gamut_cfg_data; - struct mdp_calib_config_data calib_cfg; - struct mdss_ad_init_cfg ad_init_cfg; - struct mdss_calib_cfg mdss_calib_cfg; - struct mdss_ad_input ad_input; - struct mdp_calib_config_buffer calib_buffer; - struct mdp_calib_dcm_state calib_dcm; - struct mdss_ad_bl_cfg ad_bl_cfg; - } data; -}; -#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 -enum { - metadata_op_none, - metadata_op_base_blend, - metadata_op_frame_rate, - metadata_op_vic, - metadata_op_wb_format, - metadata_op_wb_secure, - metadata_op_get_caps, - metadata_op_crc, - metadata_op_get_ion_fd, - metadata_op_max -}; -struct mdp_blend_cfg { - uint32_t is_premultiplied; -}; -struct mdp_mixer_cfg { - uint32_t writeback_format; - uint32_t alpha; -}; -struct mdss_hw_caps { - uint32_t mdp_rev; - uint8_t rgb_pipes; - uint8_t vig_pipes; - uint8_t dma_pipes; - uint8_t max_smp_cnt; - uint8_t smp_per_pipe; - uint32_t features; -}; -struct msmfb_metadata { - uint32_t op; - uint32_t flags; - union { - struct mdp_misr misr_request; - struct mdp_blend_cfg blend_cfg; - struct mdp_mixer_cfg mixer_cfg; - uint32_t panel_frame_rate; - uint32_t video_info_code; - struct mdss_hw_caps caps; - uint8_t secure_en; - int fbmem_ionfd; - } data; -}; -#define MDP_MAX_FENCE_FD 32 -#define MDP_BUF_SYNC_FLAG_WAIT 1 -#define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 -struct mdp_buf_sync { - uint32_t flags; - uint32_t acq_fen_fd_cnt; - uint32_t session_id; - int * acq_fen_fd; - int * rel_fen_fd; - int * retire_fen_fd; -}; -struct mdp_async_blit_req_list { - struct mdp_buf_sync sync; - uint32_t count; - struct mdp_blit_req req[]; -}; -#define MDP_DISPLAY_COMMIT_OVERLAY 1 -struct mdp_display_commit { - uint32_t flags; - uint32_t wait_for_finish; - struct fb_var_screeninfo var; - struct mdp_rect l_roi; - struct mdp_rect r_roi; -}; -struct mdp_overlay_list { - uint32_t num_overlays; - struct mdp_overlay * * overlay_list; - uint32_t flags; - uint32_t processed_overlays; -}; -struct mdp_page_protection { - uint32_t page_protection; -}; -struct mdp_mixer_info { - int pndx; - int pnum; - int ptype; - int mixer_num; - int z_order; -}; -#define MAX_PIPE_PER_MIXER 7 -struct msmfb_mixer_info_req { - int mixer_num; - int cnt; - struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; -}; -enum { - DISPLAY_SUBSYSTEM_ID, - ROTATOR_SUBSYSTEM_ID, -}; -enum { - MDP_IOMMU_DOMAIN_CP, - MDP_IOMMU_DOMAIN_NS, -}; -enum { - MDP_WRITEBACK_MIRROR_OFF, - MDP_WRITEBACK_MIRROR_ON, - MDP_WRITEBACK_MIRROR_PAUSE, - MDP_WRITEBACK_MIRROR_RESUME, -}; -enum mdp_color_space { - MDP_CSC_ITU_R_601, - MDP_CSC_ITU_R_601_FR, - MDP_CSC_ITU_R_709, -}; -#define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) -#define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) -enum { - mdp_igc_v1_7 = 1, - mdp_igc_vmax, - mdp_hist_lut_v1_7, - mdp_hist_lut_vmax, - mdp_pgc_v1_7, - mdp_pgc_vmax, - mdp_dither_v1_7, - mdp_dither_vmax, - mdp_gamut_v1_7, - mdp_gamut_vmax, - mdp_pa_v1_7, - mdp_pa_vmax, - mdp_pcc_v1_7, - mdp_pcc_vmax, - mdp_pp_legacy, - mdp_dither_pa_v1_7, - mdp_igc_v3, - mdp_pp_unknown = 255 -}; -#define mdp_dither_pa_v1_7 mdp_dither_pa_v1_7 -#define mdp_pp_unknown mdp_pp_unknown -#define mdp_igc_v3 mdp_igc_v3 -enum { - IGC = 1, - PCC, - GC, - PA, - GAMUT, - DITHER, - QSEED, - HIST_LUT, - HIST, - PP_FEATURE_MAX, - PA_DITHER, - PP_MAX_FEATURES = 25, -}; -#define PA_DITHER PA_DITHER -#define PP_MAX_FEATURES PP_MAX_FEATURES -struct mdp_pp_feature_version { - uint32_t pp_feature; - uint32_t version_info; -}; -#endif - diff --git a/sdm710/kernel-headers/linux/msm_mdp_ext.h b/sdm710/kernel-headers/linux/msm_mdp_ext.h deleted file mode 100644 index c17045e1..00000000 --- a/sdm710/kernel-headers/linux/msm_mdp_ext.h +++ /dev/null @@ -1,230 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _MSM_MDP_EXT_H_ -#define _MSM_MDP_EXT_H_ -#include <linux/msm_mdp.h> -#define MDP_IOCTL_MAGIC 'S' -#define MSMFB_ATOMIC_COMMIT _IOWR(MDP_IOCTL_MAGIC, 128, void *) -#define MSMFB_ASYNC_POSITION_UPDATE _IOWR(MDP_IOCTL_MAGIC, 129, struct mdp_position_update) -#define MSMFB_MDP_SET_CFG _IOW(MDP_IOCTL_MAGIC, 130, struct mdp_set_cfg) -#ifdef __LP64 -#define MDP_LAYER_COMMIT_V1_PAD 2 -#else -#define MDP_LAYER_COMMIT_V1_PAD 3 -#endif -#define MDP_LAYER_FLIP_LR 0x1 -#define MDP_LAYER_FLIP_UD 0x2 -#define MDP_LAYER_ENABLE_PIXEL_EXT 0x4 -#define MDP_LAYER_FORGROUND 0x8 -#define MDP_LAYER_SECURE_SESSION 0x10 -#define MDP_LAYER_SOLID_FILL 0x20 -#define MDP_LAYER_DEINTERLACE 0x40 -#define MDP_LAYER_BWC 0x80 -#define MDP_LAYER_ASYNC 0x100 -#define MDP_LAYER_PP 0x200 -#define MDP_LAYER_SECURE_DISPLAY_SESSION 0x400 -#define MDP_LAYER_ENABLE_QSEED3_SCALE 0x800 -#define MDP_LAYER_MULTIRECT_ENABLE 0x1000 -#define MDP_LAYER_MULTIRECT_PARALLEL_MODE 0x2000 -#define MDP_DESTSCALER_ENABLE 0x1 -#define MDP_DESTSCALER_SCALE_UPDATE 0x2 -#define MDP_DESTSCALER_ENHANCER_UPDATE 0x4 -#define MDP_VALIDATE_LAYER 0x01 -#define MDP_COMMIT_WAIT_FOR_FINISH 0x02 -#define MDP_COMMIT_SYNC_FENCE_WAIT 0x04 -#define MDP_COMMIT_AVR_EN 0x08 -#define MDP_COMMIT_AVR_ONE_SHOT_MODE 0x10 -#define MDP_COMMIT_CWB_EN 0x800 -#define MDP_COMMIT_CWB_DSPP 0x1000 -#define MDP_COMMIT_VERSION_1_0 0x00010000 -struct mdp_layer_plane { - int fd; - uint32_t offset; - uint32_t stride; -}; -struct mdp_layer_buffer { - uint32_t width; - uint32_t height; - uint32_t format; - struct mdp_layer_plane planes[MAX_PLANES]; - uint32_t plane_count; - struct mult_factor comp_ratio; - int fence; - uint32_t reserved; -}; -struct mdp_input_layer { - uint32_t flags; - uint32_t pipe_ndx; - uint8_t horz_deci; - uint8_t vert_deci; - uint8_t alpha; - uint16_t z_order; - uint32_t transp_mask; - uint32_t bg_color; - enum mdss_mdp_blend_op blend_op; - enum mdp_color_space color_space; - struct mdp_rect src_rect; - struct mdp_rect dst_rect; - void * scale; - struct mdp_layer_buffer buffer; - void * pp_info; - int error_code; - uint32_t reserved[6]; -}; -struct mdp_output_layer { - uint32_t flags; - uint32_t writeback_ndx; - struct mdp_layer_buffer buffer; - enum mdp_color_space color_space; - uint32_t reserved[5]; -}; -struct mdp_destination_scaler_data { - uint32_t flags; - uint32_t dest_scaler_ndx; - uint32_t lm_width; - uint32_t lm_height; - uint64_t scale; -}; -#define MDP_VIDEO_FRC_ENABLE (1 << 0) -struct mdp_frc_info { - uint32_t flags; - uint32_t frame_cnt; - int64_t timestamp; -}; -struct mdp_layer_commit_v1 { - uint32_t flags; - int release_fence; - struct mdp_rect left_roi; - struct mdp_rect right_roi; - struct mdp_input_layer * input_layers; - uint32_t input_layer_cnt; - struct mdp_output_layer * output_layer; - int retire_fence; - void * dest_scaler; - uint32_t dest_scaler_cnt; - struct mdp_frc_info * frc_info; - uint32_t reserved[MDP_LAYER_COMMIT_V1_PAD]; -}; -struct mdp_layer_commit { - uint32_t version; - union { - struct mdp_layer_commit_v1 commit_v1; - }; -}; -struct mdp_point { - uint32_t x; - uint32_t y; -}; -struct mdp_async_layer { - uint32_t flags; - uint32_t pipe_ndx; - struct mdp_point src; - struct mdp_point dst; - int error_code; - uint32_t reserved[3]; -}; -struct mdp_position_update { - struct mdp_async_layer * input_layers; - uint32_t input_layer_cnt; -}; -#define MAX_DET_CURVES 3 -struct mdp_det_enhance_data { - uint32_t enable; - int16_t sharpen_level1; - int16_t sharpen_level2; - uint16_t clip; - uint16_t limit; - uint16_t thr_quiet; - uint16_t thr_dieout; - uint16_t thr_low; - uint16_t thr_high; - uint16_t prec_shift; - int16_t adjust_a[MAX_DET_CURVES]; - int16_t adjust_b[MAX_DET_CURVES]; - int16_t adjust_c[MAX_DET_CURVES]; -}; -#define ENABLE_SCALE 0x1 -#define ENABLE_DETAIL_ENHANCE 0x2 -#define ENABLE_DIRECTION_DETECTION 0x4 -#define SCALER_LUT_SWAP 0x1 -#define SCALER_LUT_DIR_WR 0x2 -#define SCALER_LUT_Y_CIR_WR 0x4 -#define SCALER_LUT_UV_CIR_WR 0x8 -#define SCALER_LUT_Y_SEP_WR 0x10 -#define SCALER_LUT_UV_SEP_WR 0x20 -#define FILTER_EDGE_DIRECTED_2D 0x0 -#define FILTER_CIRCULAR_2D 0x1 -#define FILTER_SEPARABLE_1D 0x2 -#define FILTER_BILINEAR 0x3 -#define FILTER_ALPHA_DROP_REPEAT 0x0 -#define FILTER_ALPHA_BILINEAR 0x1 -struct mdp_scale_data_v2 { - uint32_t enable; - int32_t init_phase_x[MAX_PLANES]; - int32_t phase_step_x[MAX_PLANES]; - int32_t init_phase_y[MAX_PLANES]; - int32_t phase_step_y[MAX_PLANES]; - uint32_t num_ext_pxls_left[MAX_PLANES]; - uint32_t num_ext_pxls_right[MAX_PLANES]; - uint32_t num_ext_pxls_top[MAX_PLANES]; - uint32_t num_ext_pxls_btm[MAX_PLANES]; - int32_t left_ftch[MAX_PLANES]; - int32_t left_rpt[MAX_PLANES]; - int32_t right_ftch[MAX_PLANES]; - int32_t right_rpt[MAX_PLANES]; - uint32_t top_rpt[MAX_PLANES]; - uint32_t btm_rpt[MAX_PLANES]; - uint32_t top_ftch[MAX_PLANES]; - uint32_t btm_ftch[MAX_PLANES]; - uint32_t roi_w[MAX_PLANES]; - uint32_t preload_x[MAX_PLANES]; - uint32_t preload_y[MAX_PLANES]; - uint32_t src_width[MAX_PLANES]; - uint32_t src_height[MAX_PLANES]; - uint32_t dst_width; - uint32_t dst_height; - uint32_t y_rgb_filter_cfg; - uint32_t uv_filter_cfg; - uint32_t alpha_filter_cfg; - uint32_t blend_cfg; - uint32_t lut_flag; - uint32_t dir_lut_idx; - uint32_t y_rgb_cir_lut_idx; - uint32_t uv_cir_lut_idx; - uint32_t y_rgb_sep_lut_idx; - uint32_t uv_sep_lut_idx; - struct mdp_det_enhance_data detail_enhance; - uint64_t reserved[8]; -}; -struct mdp_scale_luts_info { - uint64_t dir_lut; - uint64_t cir_lut; - uint64_t sep_lut; - uint32_t dir_lut_size; - uint32_t cir_lut_size; - uint32_t sep_lut_size; -}; -#define MDP_QSEED3_LUT_CFG 0x1 -struct mdp_set_cfg { - uint64_t flags; - uint32_t len; - uint64_t payload; -}; -#endif - diff --git a/sdm710/kernel-headers/linux/msm_pft.h b/sdm710/kernel-headers/linux/msm_pft.h deleted file mode 100644 index 73071103..00000000 --- a/sdm710/kernel-headers/linux/msm_pft.h +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef MSM_PFT_H_ -#define MSM_PFT_H_ -#include <linux/types.h> -enum pft_command_opcode { - PFT_CMD_OPCODE_SET_STATE, - PFT_CMD_OPCODE_UPDATE_REG_APP_UID, - PFT_CMD_OPCODE_PERFORM_IN_PLACE_FILE_ENC, - PFT_CMD_OPCODE_MAX_COMMAND_INDEX -}; -enum pft_state { - PFT_STATE_DEACTIVATED, - PFT_STATE_DEACTIVATING, - PFT_STATE_KEY_REMOVED, - PFT_STATE_REMOVING_KEY, - PFT_STATE_KEY_LOADED, - PFT_STATE_MAX_INDEX -}; -enum pft_command_response_code { - PFT_CMD_RESP_SUCCESS, - PFT_CMD_RESP_GENERAL_ERROR, - PFT_CMD_RESP_INVALID_COMMAND, - PFT_CMD_RESP_INVALID_CMD_PARAMS, - PFT_CMD_RESP_INVALID_STATE, - PFT_CMD_RESP_ALREADY_IN_STATE, - PFT_CMD_RESP_INPLACE_FILE_IS_OPEN, - PFT_CMD_RESP_ENT_FILES_CLOSING_FAILURE, - PFT_CMD_RESP_MAX_INDEX -}; -struct pft_command_response { - __u32 command_id; - __u32 error_code; -}; -struct pft_command { - __u32 opcode; - union { - struct { - __u32 state; - } set_state; - struct { - __u32 items_count; - uid_t table[0]; - } update_app_list; - struct { - __u32 file_descriptor; - } preform_in_place_file_enc; - }; -}; -#endif - diff --git a/sdm710/kernel-headers/linux/msm_rmnet.h b/sdm710/kernel-headers/linux/msm_rmnet.h deleted file mode 100644 index 10071dfc..00000000 --- a/sdm710/kernel-headers/linux/msm_rmnet.h +++ /dev/null @@ -1,129 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _MSM_RMNET_H_ -#define _MSM_RMNET_H_ -#define RMNET_MODE_NONE (0x00) -#define RMNET_MODE_LLP_ETH (0x01) -#define RMNET_MODE_LLP_IP (0x02) -#define RMNET_MODE_QOS (0x04) -#define RMNET_MODE_MASK (RMNET_MODE_LLP_ETH | RMNET_MODE_LLP_IP | RMNET_MODE_QOS) -#define RMNET_IS_MODE_QOS(mode) ((mode & RMNET_MODE_QOS) == RMNET_MODE_QOS) -#define RMNET_IS_MODE_IP(mode) ((mode & RMNET_MODE_LLP_IP) == RMNET_MODE_LLP_IP) -#define RMNET_IOCTL_SET_LLP_ETHERNET 0x000089F1 -#define RMNET_IOCTL_SET_LLP_IP 0x000089F2 -#define RMNET_IOCTL_GET_LLP 0x000089F3 -#define RMNET_IOCTL_SET_QOS_ENABLE 0x000089F4 -#define RMNET_IOCTL_SET_QOS_DISABLE 0x000089F5 -#define RMNET_IOCTL_GET_QOS 0x000089F6 -#define RMNET_IOCTL_GET_OPMODE 0x000089F7 -#define RMNET_IOCTL_OPEN 0x000089F8 -#define RMNET_IOCTL_CLOSE 0x000089F9 -#define RMNET_IOCTL_FLOW_ENABLE 0x000089FA -#define RMNET_IOCTL_FLOW_DISABLE 0x000089FB -#define RMNET_IOCTL_FLOW_SET_HNDL 0x000089FC -#define RMNET_IOCTL_EXTENDED 0x000089FD -#define RMNET_IOCTL_GET_SUPPORTED_FEATURES 0x0000 -#define RMNET_IOCTL_SET_MRU 0x0001 -#define RMNET_IOCTL_GET_MRU 0x0002 -#define RMNET_IOCTL_GET_EPID 0x0003 -#define RMNET_IOCTL_GET_DRIVER_NAME 0x0004 -#define RMNET_IOCTL_ADD_MUX_CHANNEL 0x0005 -#define RMNET_IOCTL_SET_EGRESS_DATA_FORMAT 0x0006 -#define RMNET_IOCTL_SET_INGRESS_DATA_FORMAT 0x0007 -#define RMNET_IOCTL_SET_AGGREGATION_COUNT 0x0008 -#define RMNET_IOCTL_GET_AGGREGATION_COUNT 0x0009 -#define RMNET_IOCTL_SET_AGGREGATION_SIZE 0x000A -#define RMNET_IOCTL_GET_AGGREGATION_SIZE 0x000B -#define RMNET_IOCTL_FLOW_CONTROL 0x000C -#define RMNET_IOCTL_GET_DFLT_CONTROL_CHANNEL 0x000D -#define RMNET_IOCTL_GET_HWSW_MAP 0x000E -#define RMNET_IOCTL_SET_RX_HEADROOM 0x000F -#define RMNET_IOCTL_GET_EP_PAIR 0x0010 -#define RMNET_IOCTL_SET_QOS_VERSION 0x0011 -#define RMNET_IOCTL_GET_QOS_VERSION 0x0012 -#define RMNET_IOCTL_GET_SUPPORTED_QOS_MODES 0x0013 -#define RMNET_IOCTL_SET_SLEEP_STATE 0x0014 -#define RMNET_IOCTL_SET_XLAT_DEV_INFO 0x0015 -#define RMNET_IOCTL_DEREGISTER_DEV 0x0016 -#define RMNET_IOCTL_GET_SG_SUPPORT 0x0017 -#define RMNET_IOCTL_FEAT_NOTIFY_MUX_CHANNEL (1 << 0) -#define RMNET_IOCTL_FEAT_SET_EGRESS_DATA_FORMAT (1 << 1) -#define RMNET_IOCTL_FEAT_SET_INGRESS_DATA_FORMAT (1 << 2) -#define RMNET_IOCTL_FEAT_SET_AGGREGATION_COUNT (1 << 3) -#define RMNET_IOCTL_FEAT_GET_AGGREGATION_COUNT (1 << 4) -#define RMNET_IOCTL_FEAT_SET_AGGREGATION_SIZE (1 << 5) -#define RMNET_IOCTL_FEAT_GET_AGGREGATION_SIZE (1 << 6) -#define RMNET_IOCTL_FEAT_FLOW_CONTROL (1 << 7) -#define RMNET_IOCTL_FEAT_GET_DFLT_CONTROL_CHANNEL (1 << 8) -#define RMNET_IOCTL_FEAT_GET_HWSW_MAP (1 << 9) -#define RMNET_IOCTL_EGRESS_FORMAT_MAP (1 << 1) -#define RMNET_IOCTL_EGRESS_FORMAT_AGGREGATION (1 << 2) -#define RMNET_IOCTL_EGRESS_FORMAT_MUXING (1 << 3) -#define RMNET_IOCTL_EGRESS_FORMAT_CHECKSUM (1 << 4) -#define RMNET_IOCTL_INGRESS_FORMAT_MAP (1 << 1) -#define RMNET_IOCTL_INGRESS_FORMAT_DEAGGREGATION (1 << 2) -#define RMNET_IOCTL_INGRESS_FORMAT_DEMUXING (1 << 3) -#define RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM (1 << 4) -#define RMNET_IOCTL_INGRESS_FORMAT_AGG_DATA (1 << 5) -#ifndef IFNAMSIZ -#define IFNAMSIZ 16 -#endif -struct rmnet_ioctl_extended_s { - uint32_t extended_ioctl; - union { - uint32_t data; - int8_t if_name[IFNAMSIZ]; - struct { - uint32_t mux_id; - int8_t vchannel_name[IFNAMSIZ]; - } rmnet_mux_val; - struct { - uint8_t flow_mode; - uint8_t mux_id; - } flow_control_prop; - struct { - uint32_t consumer_pipe_num; - uint32_t producer_pipe_num; - } ipa_ep_pair; - struct { - uint32_t __data; - uint32_t agg_size; - uint32_t agg_count; - } ingress_format; - } u; -}; -struct rmnet_ioctl_data_s { - union { - uint32_t operation_mode; - uint32_t tcm_handle; - } u; -}; -#define RMNET_IOCTL_QOS_MODE_6 (1 << 0) -#define RMNET_IOCTL_QOS_MODE_8 (1 << 1) -struct QMI_QOS_HDR_S { - unsigned char version; - unsigned char flags; - uint32_t flow_id; -} __attribute((__packed__)); -struct qmi_qos_hdr8_s { - struct QMI_QOS_HDR_S hdr; - uint8_t reserved[2]; -} __attribute((__packed__)); -#endif - diff --git a/sdm710/kernel-headers/linux/msm_rotator.h b/sdm710/kernel-headers/linux/msm_rotator.h deleted file mode 100644 index 283459a6..00000000 --- a/sdm710/kernel-headers/linux/msm_rotator.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __MSM_ROTATOR_H__ -#define __MSM_ROTATOR_H__ -#include <linux/types.h> -#include <linux/msm_mdp.h> -#define MSM_ROTATOR_IOCTL_MAGIC 'R' -#define MSM_ROTATOR_IOCTL_START _IOWR(MSM_ROTATOR_IOCTL_MAGIC, 1, struct msm_rotator_img_info) -#define MSM_ROTATOR_IOCTL_ROTATE _IOW(MSM_ROTATOR_IOCTL_MAGIC, 2, struct msm_rotator_data_info) -#define MSM_ROTATOR_IOCTL_FINISH _IOW(MSM_ROTATOR_IOCTL_MAGIC, 3, int) -#define ROTATOR_VERSION_01 0xA5B4C301 -enum rotator_clk_type { - ROTATOR_CORE_CLK, - ROTATOR_PCLK, - ROTATOR_IMEM_CLK -}; -struct msm_rotator_img_info { - unsigned int session_id; - struct msmfb_img src; - struct msmfb_img dst; - struct mdp_rect src_rect; - unsigned int dst_x; - unsigned int dst_y; - unsigned char rotations; - int enable; - unsigned int downscale_ratio; - unsigned int secure; -}; -struct msm_rotator_data_info { - int session_id; - struct msmfb_data src; - struct msmfb_data dst; - unsigned int version_key; - struct msmfb_data src_chroma; - struct msmfb_data dst_chroma; -}; -struct msm_rot_clocks { - const char * clk_name; - enum rotator_clk_type clk_type; - unsigned int clk_rate; -}; -struct msm_rotator_platform_data { - unsigned int number_of_clocks; - unsigned int hardware_version_number; - struct msm_rot_clocks * rotator_clks; - struct msm_bus_scale_pdata * bus_scale_table; - char rot_iommu_split_domain; -}; -#endif - diff --git a/sdm710/kernel-headers/linux/msm_thermal_ioctl.h b/sdm710/kernel-headers/linux/msm_thermal_ioctl.h deleted file mode 100644 index 1dcf2882..00000000 --- a/sdm710/kernel-headers/linux/msm_thermal_ioctl.h +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _MSM_THERMAL_IOCTL_H -#define _MSM_THERMAL_IOCTL_H -#include <linux/ioctl.h> -#define MSM_THERMAL_IOCTL_NAME "msm_thermal_query" -#define MSM_IOCTL_FREQ_SIZE 16 -struct __attribute__((__packed__)) cpu_freq_arg { - uint32_t cpu_num; - uint32_t freq_req; -}; -struct __attribute__((__packed__)) clock_plan_arg { - uint32_t cluster_num; - uint32_t freq_table_len; - uint32_t set_idx; - unsigned int freq_table[MSM_IOCTL_FREQ_SIZE]; -}; -struct __attribute__((__packed__)) voltage_plan_arg { - uint32_t cluster_num; - uint32_t voltage_table_len; - uint32_t set_idx; - uint32_t voltage_table[MSM_IOCTL_FREQ_SIZE]; -}; -struct __attribute__((__packed__)) msm_thermal_ioctl { - uint32_t size; - union { - struct cpu_freq_arg cpu_freq; - struct clock_plan_arg clock_freq; - struct voltage_plan_arg voltage; - }; -}; -enum { - MSM_SET_CPU_MAX_FREQ = 0x00, - MSM_SET_CPU_MIN_FREQ = 0x01, - MSM_SET_CLUSTER_MAX_FREQ = 0x02, - MSM_SET_CLUSTER_MIN_FREQ = 0x03, - MSM_GET_CLUSTER_FREQ_PLAN = 0x04, - MSM_GET_CLUSTER_VOLTAGE_PLAN = 0x05, - MSM_CMD_MAX_NR, -}; -#define MSM_THERMAL_MAGIC_NUM 0xCA -#define MSM_THERMAL_SET_CPU_MAX_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM, MSM_SET_CPU_MAX_FREQ, struct msm_thermal_ioctl) -#define MSM_THERMAL_SET_CPU_MIN_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM, MSM_SET_CPU_MIN_FREQ, struct msm_thermal_ioctl) -#define MSM_THERMAL_SET_CLUSTER_MAX_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM, MSM_SET_CLUSTER_MAX_FREQ, struct msm_thermal_ioctl) -#define MSM_THERMAL_SET_CLUSTER_MIN_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM, MSM_SET_CLUSTER_MIN_FREQ, struct msm_thermal_ioctl) -#define MSM_THERMAL_GET_CLUSTER_FREQUENCY_PLAN _IOR(MSM_THERMAL_MAGIC_NUM, MSM_GET_CLUSTER_FREQ_PLAN, struct msm_thermal_ioctl) -#define MSM_THERMAL_GET_CLUSTER_VOLTAGE_PLAN _IOR(MSM_THERMAL_MAGIC_NUM, MSM_GET_CLUSTER_VOLTAGE_PLAN, struct msm_thermal_ioctl) -#endif - diff --git a/sdm710/kernel-headers/linux/msm_vidc_dec.h b/sdm710/kernel-headers/linux/msm_vidc_dec.h deleted file mode 100644 index 6daf270a..00000000 --- a/sdm710/kernel-headers/linux/msm_vidc_dec.h +++ /dev/null @@ -1,469 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _MSM_VIDC_DEC_H_ -#define _MSM_VIDC_DEC_H_ -#include <linux/types.h> -#include <linux/ioctl.h> -#define VDEC_S_BASE 0x40000000 -#define VDEC_S_SUCCESS (VDEC_S_BASE) -#define VDEC_S_EFAIL (VDEC_S_BASE + 1) -#define VDEC_S_EFATAL (VDEC_S_BASE + 2) -#define VDEC_S_EBADPARAM (VDEC_S_BASE + 3) -#define VDEC_S_EINVALSTATE (VDEC_S_BASE + 4) -#define VDEC_S_ENOSWRES (VDEC_S_BASE + 5) -#define VDEC_S_ENOHWRES (VDEC_S_BASE + 6) -#define VDEC_S_EINVALCMD (VDEC_S_BASE + 7) -#define VDEC_S_ETIMEOUT (VDEC_S_BASE + 8) -#define VDEC_S_ENOPREREQ (VDEC_S_BASE + 9) -#define VDEC_S_ECMDQFULL (VDEC_S_BASE + 10) -#define VDEC_S_ENOTSUPP (VDEC_S_BASE + 11) -#define VDEC_S_ENOTIMPL (VDEC_S_BASE + 12) -#define VDEC_S_BUSY (VDEC_S_BASE + 13) -#define VDEC_S_INPUT_BITSTREAM_ERR (VDEC_S_BASE + 14) -#define VDEC_INTF_VER 1 -#define VDEC_MSG_BASE 0x0000000 -#define VDEC_MSG_INVALID (VDEC_MSG_BASE + 0) -#define VDEC_MSG_RESP_INPUT_BUFFER_DONE (VDEC_MSG_BASE + 1) -#define VDEC_MSG_RESP_OUTPUT_BUFFER_DONE (VDEC_MSG_BASE + 2) -#define VDEC_MSG_RESP_INPUT_FLUSHED (VDEC_MSG_BASE + 3) -#define VDEC_MSG_RESP_OUTPUT_FLUSHED (VDEC_MSG_BASE + 4) -#define VDEC_MSG_RESP_FLUSH_INPUT_DONE (VDEC_MSG_BASE + 5) -#define VDEC_MSG_RESP_FLUSH_OUTPUT_DONE (VDEC_MSG_BASE + 6) -#define VDEC_MSG_RESP_START_DONE (VDEC_MSG_BASE + 7) -#define VDEC_MSG_RESP_STOP_DONE (VDEC_MSG_BASE + 8) -#define VDEC_MSG_RESP_PAUSE_DONE (VDEC_MSG_BASE + 9) -#define VDEC_MSG_RESP_RESUME_DONE (VDEC_MSG_BASE + 10) -#define VDEC_MSG_RESP_RESOURCE_LOADED (VDEC_MSG_BASE + 11) -#define VDEC_EVT_RESOURCES_LOST (VDEC_MSG_BASE + 12) -#define VDEC_MSG_EVT_CONFIG_CHANGED (VDEC_MSG_BASE + 13) -#define VDEC_MSG_EVT_HW_ERROR (VDEC_MSG_BASE + 14) -#define VDEC_MSG_EVT_INFO_CONFIG_CHANGED (VDEC_MSG_BASE + 15) -#define VDEC_MSG_EVT_INFO_FIELD_DROPPED (VDEC_MSG_BASE + 16) -#define VDEC_MSG_EVT_HW_OVERLOAD (VDEC_MSG_BASE + 17) -#define VDEC_MSG_EVT_MAX_CLIENTS (VDEC_MSG_BASE + 18) -#define VDEC_MSG_EVT_HW_UNSUPPORTED (VDEC_MSG_BASE + 19) -#define VDEC_BUFFERFLAG_EOS 0x00000001 -#define VDEC_BUFFERFLAG_DECODEONLY 0x00000004 -#define VDEC_BUFFERFLAG_DATACORRUPT 0x00000008 -#define VDEC_BUFFERFLAG_ENDOFFRAME 0x00000010 -#define VDEC_BUFFERFLAG_SYNCFRAME 0x00000020 -#define VDEC_BUFFERFLAG_EXTRADATA 0x00000040 -#define VDEC_BUFFERFLAG_CODECCONFIG 0x00000080 -#define VDEC_EXTRADATA_NONE 0x001 -#define VDEC_EXTRADATA_QP 0x004 -#define VDEC_EXTRADATA_MB_ERROR_MAP 0x008 -#define VDEC_EXTRADATA_SEI 0x010 -#define VDEC_EXTRADATA_VUI 0x020 -#define VDEC_EXTRADATA_VC1 0x040 -#define VDEC_EXTRADATA_EXT_DATA 0x0800 -#define VDEC_EXTRADATA_USER_DATA 0x1000 -#define VDEC_EXTRADATA_EXT_BUFFER 0x2000 -#define VDEC_CMDBASE 0x800 -#define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE) -#define VDEC_IOCTL_MAGIC 'v' -struct vdec_ioctl_msg { - void * in; - void * out; -}; -#define VDEC_IOCTL_GET_PROFILE_LEVEL_SUPPORTED _IOWR(VDEC_IOCTL_MAGIC, 0, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_INTERLACE_FORMAT _IOR(VDEC_IOCTL_MAGIC, 1, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_CURRENT_PROFILE_LEVEL _IOWR(VDEC_IOCTL_MAGIC, 2, struct vdec_ioctl_msg) -#define VDEC_IOCTL_SET_OUTPUT_FORMAT _IOWR(VDEC_IOCTL_MAGIC, 3, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_OUTPUT_FORMAT _IOWR(VDEC_IOCTL_MAGIC, 4, struct vdec_ioctl_msg) -#define VDEC_IOCTL_SET_CODEC _IOW(VDEC_IOCTL_MAGIC, 5, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_CODEC _IOR(VDEC_IOCTL_MAGIC, 6, struct vdec_ioctl_msg) -#define VDEC_IOCTL_SET_PICRES _IOW(VDEC_IOCTL_MAGIC, 7, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_PICRES _IOR(VDEC_IOCTL_MAGIC, 8, struct vdec_ioctl_msg) -#define VDEC_IOCTL_SET_EXTRADATA _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_EXTRADATA _IOR(VDEC_IOCTL_MAGIC, 10, struct vdec_ioctl_msg) -#define VDEC_IOCTL_SET_SEQUENCE_HEADER _IOW(VDEC_IOCTL_MAGIC, 11, struct vdec_ioctl_msg) -#define VDEC_IOCTL_SET_BUFFER_REQ _IOW(VDEC_IOCTL_MAGIC, 12, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_BUFFER_REQ _IOR(VDEC_IOCTL_MAGIC, 13, struct vdec_ioctl_msg) -#define VDEC_IOCTL_ALLOCATE_BUFFER _IOWR(VDEC_IOCTL_MAGIC, 14, struct vdec_ioctl_msg) -#define VDEC_IOCTL_FREE_BUFFER _IOW(VDEC_IOCTL_MAGIC, 15, struct vdec_ioctl_msg) -#define VDEC_IOCTL_SET_BUFFER _IOW(VDEC_IOCTL_MAGIC, 16, struct vdec_ioctl_msg) -#define VDEC_IOCTL_FILL_OUTPUT_BUFFER _IOW(VDEC_IOCTL_MAGIC, 17, struct vdec_ioctl_msg) -#define VDEC_IOCTL_DECODE_FRAME _IOW(VDEC_IOCTL_MAGIC, 18, struct vdec_ioctl_msg) -#define VDEC_IOCTL_LOAD_RESOURCES _IO(VDEC_IOCTL_MAGIC, 19) -#define VDEC_IOCTL_CMD_START _IO(VDEC_IOCTL_MAGIC, 20) -#define VDEC_IOCTL_CMD_STOP _IO(VDEC_IOCTL_MAGIC, 21) -#define VDEC_IOCTL_CMD_PAUSE _IO(VDEC_IOCTL_MAGIC, 22) -#define VDEC_IOCTL_CMD_RESUME _IO(VDEC_IOCTL_MAGIC, 23) -#define VDEC_IOCTL_CMD_FLUSH _IOW(VDEC_IOCTL_MAGIC, 24, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_NEXT_MSG _IOR(VDEC_IOCTL_MAGIC, 25, struct vdec_ioctl_msg) -#define VDEC_IOCTL_STOP_NEXT_MSG _IO(VDEC_IOCTL_MAGIC, 26) -#define VDEC_IOCTL_GET_NUMBER_INSTANCES _IOR(VDEC_IOCTL_MAGIC, 27, struct vdec_ioctl_msg) -#define VDEC_IOCTL_SET_PICTURE_ORDER _IOW(VDEC_IOCTL_MAGIC, 28, struct vdec_ioctl_msg) -#define VDEC_IOCTL_SET_FRAME_RATE _IOW(VDEC_IOCTL_MAGIC, 29, struct vdec_ioctl_msg) -#define VDEC_IOCTL_SET_H264_MV_BUFFER _IOW(VDEC_IOCTL_MAGIC, 30, struct vdec_ioctl_msg) -#define VDEC_IOCTL_FREE_H264_MV_BUFFER _IOW(VDEC_IOCTL_MAGIC, 31, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_MV_BUFFER_SIZE _IOR(VDEC_IOCTL_MAGIC, 32, struct vdec_ioctl_msg) -#define VDEC_IOCTL_SET_IDR_ONLY_DECODING _IO(VDEC_IOCTL_MAGIC, 33) -#define VDEC_IOCTL_SET_CONT_ON_RECONFIG _IO(VDEC_IOCTL_MAGIC, 34) -#define VDEC_IOCTL_SET_DISABLE_DMX _IOW(VDEC_IOCTL_MAGIC, 35, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_DISABLE_DMX _IOR(VDEC_IOCTL_MAGIC, 36, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_DISABLE_DMX_SUPPORT _IOR(VDEC_IOCTL_MAGIC, 37, struct vdec_ioctl_msg) -#define VDEC_IOCTL_SET_PERF_CLK _IOR(VDEC_IOCTL_MAGIC, 38, struct vdec_ioctl_msg) -#define VDEC_IOCTL_SET_META_BUFFERS _IOW(VDEC_IOCTL_MAGIC, 39, struct vdec_ioctl_msg) -#define VDEC_IOCTL_FREE_META_BUFFERS _IO(VDEC_IOCTL_MAGIC, 40) -enum vdec_picture { - PICTURE_TYPE_I, - PICTURE_TYPE_P, - PICTURE_TYPE_B, - PICTURE_TYPE_BI, - PICTURE_TYPE_SKIP, - PICTURE_TYPE_IDR, - PICTURE_TYPE_UNKNOWN -}; -enum vdec_buffer { - VDEC_BUFFER_TYPE_INPUT, - VDEC_BUFFER_TYPE_OUTPUT -}; -struct vdec_allocatorproperty { - enum vdec_buffer buffer_type; - uint32_t mincount; - uint32_t maxcount; - uint32_t actualcount; - size_t buffer_size; - uint32_t alignment; - uint32_t buf_poolid; - size_t meta_buffer_size; -}; -struct vdec_bufferpayload { - void * bufferaddr; - size_t buffer_len; - int pmem_fd; - size_t offset; - size_t mmaped_size; -}; -struct vdec_setbuffer_cmd { - enum vdec_buffer buffer_type; - struct vdec_bufferpayload buffer; -}; -struct vdec_fillbuffer_cmd { - struct vdec_bufferpayload buffer; - void * client_data; -}; -enum vdec_bufferflush { - VDEC_FLUSH_TYPE_INPUT, - VDEC_FLUSH_TYPE_OUTPUT, - VDEC_FLUSH_TYPE_ALL -}; -enum vdec_codec { - VDEC_CODECTYPE_H264 = 0x1, - VDEC_CODECTYPE_H263 = 0x2, - VDEC_CODECTYPE_MPEG4 = 0x3, - VDEC_CODECTYPE_DIVX_3 = 0x4, - VDEC_CODECTYPE_DIVX_4 = 0x5, - VDEC_CODECTYPE_DIVX_5 = 0x6, - VDEC_CODECTYPE_DIVX_6 = 0x7, - VDEC_CODECTYPE_XVID = 0x8, - VDEC_CODECTYPE_MPEG1 = 0x9, - VDEC_CODECTYPE_MPEG2 = 0xa, - VDEC_CODECTYPE_VC1 = 0xb, - VDEC_CODECTYPE_VC1_RCV = 0xc, - VDEC_CODECTYPE_HEVC = 0xd, - VDEC_CODECTYPE_MVC = 0xe, - VDEC_CODECTYPE_VP8 = 0xf, - VDEC_CODECTYPE_VP9 = 0x10, -}; -enum vdec_mpeg2_profile { - VDEC_MPEG2ProfileSimple = 0x1, - VDEC_MPEG2ProfileMain = 0x2, - VDEC_MPEG2Profile422 = 0x4, - VDEC_MPEG2ProfileSNR = 0x8, - VDEC_MPEG2ProfileSpatial = 0x10, - VDEC_MPEG2ProfileHigh = 0x20, - VDEC_MPEG2ProfileKhronosExtensions = 0x6F000000, - VDEC_MPEG2ProfileVendorStartUnused = 0x7F000000, - VDEC_MPEG2ProfileMax = 0x7FFFFFFF -}; -enum vdec_mpeg2_level { - VDEC_MPEG2LevelLL = 0x1, - VDEC_MPEG2LevelML = 0x2, - VDEC_MPEG2LevelH14 = 0x4, - VDEC_MPEG2LevelHL = 0x8, - VDEC_MPEG2LevelKhronosExtensions = 0x6F000000, - VDEC_MPEG2LevelVendorStartUnused = 0x7F000000, - VDEC_MPEG2LevelMax = 0x7FFFFFFF -}; -enum vdec_mpeg4_profile { - VDEC_MPEG4ProfileSimple = 0x01, - VDEC_MPEG4ProfileSimpleScalable = 0x02, - VDEC_MPEG4ProfileCore = 0x04, - VDEC_MPEG4ProfileMain = 0x08, - VDEC_MPEG4ProfileNbit = 0x10, - VDEC_MPEG4ProfileScalableTexture = 0x20, - VDEC_MPEG4ProfileSimpleFace = 0x40, - VDEC_MPEG4ProfileSimpleFBA = 0x80, - VDEC_MPEG4ProfileBasicAnimated = 0x100, - VDEC_MPEG4ProfileHybrid = 0x200, - VDEC_MPEG4ProfileAdvancedRealTime = 0x400, - VDEC_MPEG4ProfileCoreScalable = 0x800, - VDEC_MPEG4ProfileAdvancedCoding = 0x1000, - VDEC_MPEG4ProfileAdvancedCore = 0x2000, - VDEC_MPEG4ProfileAdvancedScalable = 0x4000, - VDEC_MPEG4ProfileAdvancedSimple = 0x8000, - VDEC_MPEG4ProfileKhronosExtensions = 0x6F000000, - VDEC_MPEG4ProfileVendorStartUnused = 0x7F000000, - VDEC_MPEG4ProfileMax = 0x7FFFFFFF -}; -enum vdec_mpeg4_level { - VDEC_MPEG4Level0 = 0x01, - VDEC_MPEG4Level0b = 0x02, - VDEC_MPEG4Level1 = 0x04, - VDEC_MPEG4Level2 = 0x08, - VDEC_MPEG4Level3 = 0x10, - VDEC_MPEG4Level4 = 0x20, - VDEC_MPEG4Level4a = 0x40, - VDEC_MPEG4Level5 = 0x80, - VDEC_MPEG4LevelKhronosExtensions = 0x6F000000, - VDEC_MPEG4LevelVendorStartUnused = 0x7F000000, - VDEC_MPEG4LevelMax = 0x7FFFFFFF -}; -enum vdec_avc_profile { - VDEC_AVCProfileBaseline = 0x01, - VDEC_AVCProfileMain = 0x02, - VDEC_AVCProfileExtended = 0x04, - VDEC_AVCProfileHigh = 0x08, - VDEC_AVCProfileHigh10 = 0x10, - VDEC_AVCProfileHigh422 = 0x20, - VDEC_AVCProfileHigh444 = 0x40, - VDEC_AVCProfileKhronosExtensions = 0x6F000000, - VDEC_AVCProfileVendorStartUnused = 0x7F000000, - VDEC_AVCProfileMax = 0x7FFFFFFF -}; -enum vdec_avc_level { - VDEC_AVCLevel1 = 0x01, - VDEC_AVCLevel1b = 0x02, - VDEC_AVCLevel11 = 0x04, - VDEC_AVCLevel12 = 0x08, - VDEC_AVCLevel13 = 0x10, - VDEC_AVCLevel2 = 0x20, - VDEC_AVCLevel21 = 0x40, - VDEC_AVCLevel22 = 0x80, - VDEC_AVCLevel3 = 0x100, - VDEC_AVCLevel31 = 0x200, - VDEC_AVCLevel32 = 0x400, - VDEC_AVCLevel4 = 0x800, - VDEC_AVCLevel41 = 0x1000, - VDEC_AVCLevel42 = 0x2000, - VDEC_AVCLevel5 = 0x4000, - VDEC_AVCLevel51 = 0x8000, - VDEC_AVCLevelKhronosExtensions = 0x6F000000, - VDEC_AVCLevelVendorStartUnused = 0x7F000000, - VDEC_AVCLevelMax = 0x7FFFFFFF -}; -enum vdec_divx_profile { - VDEC_DIVXProfile_qMobile = 0x01, - VDEC_DIVXProfile_Mobile = 0x02, - VDEC_DIVXProfile_HD = 0x04, - VDEC_DIVXProfile_Handheld = 0x08, - VDEC_DIVXProfile_Portable = 0x10, - VDEC_DIVXProfile_HomeTheater = 0x20 -}; -enum vdec_xvid_profile { - VDEC_XVIDProfile_Simple = 0x1, - VDEC_XVIDProfile_Advanced_Realtime_Simple = 0x2, - VDEC_XVIDProfile_Advanced_Simple = 0x4 -}; -enum vdec_xvid_level { - VDEC_XVID_LEVEL_S_L0 = 0x1, - VDEC_XVID_LEVEL_S_L1 = 0x2, - VDEC_XVID_LEVEL_S_L2 = 0x4, - VDEC_XVID_LEVEL_S_L3 = 0x8, - VDEC_XVID_LEVEL_ARTS_L1 = 0x10, - VDEC_XVID_LEVEL_ARTS_L2 = 0x20, - VDEC_XVID_LEVEL_ARTS_L3 = 0x40, - VDEC_XVID_LEVEL_ARTS_L4 = 0x80, - VDEC_XVID_LEVEL_AS_L0 = 0x100, - VDEC_XVID_LEVEL_AS_L1 = 0x200, - VDEC_XVID_LEVEL_AS_L2 = 0x400, - VDEC_XVID_LEVEL_AS_L3 = 0x800, - VDEC_XVID_LEVEL_AS_L4 = 0x1000 -}; -enum vdec_h263profile { - VDEC_H263ProfileBaseline = 0x01, - VDEC_H263ProfileH320Coding = 0x02, - VDEC_H263ProfileBackwardCompatible = 0x04, - VDEC_H263ProfileISWV2 = 0x08, - VDEC_H263ProfileISWV3 = 0x10, - VDEC_H263ProfileHighCompression = 0x20, - VDEC_H263ProfileInternet = 0x40, - VDEC_H263ProfileInterlace = 0x80, - VDEC_H263ProfileHighLatency = 0x100, - VDEC_H263ProfileKhronosExtensions = 0x6F000000, - VDEC_H263ProfileVendorStartUnused = 0x7F000000, - VDEC_H263ProfileMax = 0x7FFFFFFF -}; -enum vdec_h263level { - VDEC_H263Level10 = 0x01, - VDEC_H263Level20 = 0x02, - VDEC_H263Level30 = 0x04, - VDEC_H263Level40 = 0x08, - VDEC_H263Level45 = 0x10, - VDEC_H263Level50 = 0x20, - VDEC_H263Level60 = 0x40, - VDEC_H263Level70 = 0x80, - VDEC_H263LevelKhronosExtensions = 0x6F000000, - VDEC_H263LevelVendorStartUnused = 0x7F000000, - VDEC_H263LevelMax = 0x7FFFFFFF -}; -enum vdec_wmv_format { - VDEC_WMVFormatUnused = 0x01, - VDEC_WMVFormat7 = 0x02, - VDEC_WMVFormat8 = 0x04, - VDEC_WMVFormat9 = 0x08, - VDEC_WMFFormatKhronosExtensions = 0x6F000000, - VDEC_WMFFormatVendorStartUnused = 0x7F000000, - VDEC_WMVFormatMax = 0x7FFFFFFF -}; -enum vdec_vc1_profile { - VDEC_VC1ProfileSimple = 0x1, - VDEC_VC1ProfileMain = 0x2, - VDEC_VC1ProfileAdvanced = 0x4 -}; -enum vdec_vc1_level { - VDEC_VC1_LEVEL_S_Low = 0x1, - VDEC_VC1_LEVEL_S_Medium = 0x2, - VDEC_VC1_LEVEL_M_Low = 0x4, - VDEC_VC1_LEVEL_M_Medium = 0x8, - VDEC_VC1_LEVEL_M_High = 0x10, - VDEC_VC1_LEVEL_A_L0 = 0x20, - VDEC_VC1_LEVEL_A_L1 = 0x40, - VDEC_VC1_LEVEL_A_L2 = 0x80, - VDEC_VC1_LEVEL_A_L3 = 0x100, - VDEC_VC1_LEVEL_A_L4 = 0x200 -}; -struct vdec_profile_level { - uint32_t profiles; - uint32_t levels; -}; -enum vdec_interlaced_format { - VDEC_InterlaceFrameProgressive = 0x1, - VDEC_InterlaceInterleaveFrameTopFieldFirst = 0x2, - VDEC_InterlaceInterleaveFrameBottomFieldFirst = 0x4 -}; -#define VDEC_YUV_FORMAT_NV12_TP10_UBWC VDEC_YUV_FORMAT_NV12_TP10_UBWC -enum vdec_output_fromat { - VDEC_YUV_FORMAT_NV12 = 0x1, - VDEC_YUV_FORMAT_TILE_4x2 = 0x2, - VDEC_YUV_FORMAT_NV12_UBWC = 0x3, - VDEC_YUV_FORMAT_NV12_TP10_UBWC = 0x4 -}; -enum vdec_output_order { - VDEC_ORDER_DISPLAY = 0x1, - VDEC_ORDER_DECODE = 0x2 -}; -struct vdec_picsize { - uint32_t frame_width; - uint32_t frame_height; - uint32_t stride; - uint32_t scan_lines; -}; -struct vdec_seqheader { - void * ptr_seqheader; - size_t seq_header_len; - int pmem_fd; - size_t pmem_offset; -}; -struct vdec_mberror { - void * ptr_errormap; - size_t err_mapsize; -}; -struct vdec_input_frameinfo { - void * bufferaddr; - size_t offset; - size_t datalen; - uint32_t flags; - int64_t timestamp; - void * client_data; - int pmem_fd; - size_t pmem_offset; - void * desc_addr; - uint32_t desc_size; -}; -struct vdec_framesize { - uint32_t left; - uint32_t top; - uint32_t right; - uint32_t bottom; -}; -struct vdec_aspectratioinfo { - uint32_t aspect_ratio; - uint32_t par_width; - uint32_t par_height; -}; -struct vdec_sep_metadatainfo { - void * metabufaddr; - uint32_t size; - int fd; - int offset; - uint32_t buffer_size; -}; -struct vdec_output_frameinfo { - void * bufferaddr; - size_t offset; - size_t len; - uint32_t flags; - int64_t time_stamp; - enum vdec_picture pic_type; - void * client_data; - void * input_frame_clientdata; - struct vdec_picsize picsize; - struct vdec_framesize framesize; - enum vdec_interlaced_format interlaced_format; - struct vdec_aspectratioinfo aspect_ratio_info; - struct vdec_sep_metadatainfo metadata_info; -}; -union vdec_msgdata { - struct vdec_output_frameinfo output_frame; - void * input_frame_clientdata; -}; -struct vdec_msginfo { - uint32_t status_code; - uint32_t msgcode; - union vdec_msgdata msgdata; - size_t msgdatasize; -}; -struct vdec_framerate { - unsigned long fps_denominator; - unsigned long fps_numerator; -}; -struct vdec_h264_mv { - size_t size; - int count; - int pmem_fd; - int offset; -}; -struct vdec_mv_buff_size { - int width; - int height; - int size; - int alignment; -}; -struct vdec_meta_buffers { - size_t size; - int count; - int pmem_fd; - int pmem_fd_iommu; - int offset; -}; -#endif - diff --git a/sdm710/kernel-headers/linux/msm_vidc_enc.h b/sdm710/kernel-headers/linux/msm_vidc_enc.h deleted file mode 100644 index baa2854d..00000000 --- a/sdm710/kernel-headers/linux/msm_vidc_enc.h +++ /dev/null @@ -1,387 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _MSM_VIDC_ENC_H_ -#define _MSM_VIDC_ENC_H_ -#include <linux/types.h> -#include <linux/ioctl.h> -#define VEN_S_BASE 0x00000000 -#define VEN_S_SUCCESS (VEN_S_BASE) -#define VEN_S_EFAIL (VEN_S_BASE + 1) -#define VEN_S_EFATAL (VEN_S_BASE + 2) -#define VEN_S_EBADPARAM (VEN_S_BASE + 3) -#define VEN_S_EINVALSTATE (VEN_S_BASE + 4) -#define VEN_S_ENOSWRES (VEN_S_BASE + 5) -#define VEN_S_ENOHWRES (VEN_S_BASE + 6) -#define VEN_S_EBUFFREQ (VEN_S_BASE + 7) -#define VEN_S_EINVALCMD (VEN_S_BASE + 8) -#define VEN_S_ETIMEOUT (VEN_S_BASE + 9) -#define VEN_S_ENOREATMPT (VEN_S_BASE + 10) -#define VEN_S_ENOPREREQ (VEN_S_BASE + 11) -#define VEN_S_ECMDQFULL (VEN_S_BASE + 12) -#define VEN_S_ENOTSUPP (VEN_S_BASE + 13) -#define VEN_S_ENOTIMPL (VEN_S_BASE + 14) -#define VEN_S_ENOTPMEM (VEN_S_BASE + 15) -#define VEN_S_EFLUSHED (VEN_S_BASE + 16) -#define VEN_S_EINSUFBUF (VEN_S_BASE + 17) -#define VEN_S_ESAMESTATE (VEN_S_BASE + 18) -#define VEN_S_EINVALTRANS (VEN_S_BASE + 19) -#define VEN_INTF_VER 1 -#define VEN_MSG_INDICATION 0 -#define VEN_MSG_INPUT_BUFFER_DONE 1 -#define VEN_MSG_OUTPUT_BUFFER_DONE 2 -#define VEN_MSG_NEED_OUTPUT_BUFFER 3 -#define VEN_MSG_FLUSH_INPUT_DONE 4 -#define VEN_MSG_FLUSH_OUTPUT_DONE 5 -#define VEN_MSG_START 6 -#define VEN_MSG_STOP 7 -#define VEN_MSG_PAUSE 8 -#define VEN_MSG_RESUME 9 -#define VEN_MSG_STOP_READING_MSG 10 -#define VEN_MSG_LTRUSE_FAILED 11 -#define VEN_MSG_HW_OVERLOAD 12 -#define VEN_MSG_MAX_CLIENTS 13 -#define VEN_BUFFLAG_EOS 0x00000001 -#define VEN_BUFFLAG_ENDOFFRAME 0x00000010 -#define VEN_BUFFLAG_SYNCFRAME 0x00000020 -#define VEN_BUFFLAG_EXTRADATA 0x00000040 -#define VEN_BUFFLAG_CODECCONFIG 0x00000080 -#define VEN_EXTRADATA_NONE 0x001 -#define VEN_EXTRADATA_QCOMFILLER 0x002 -#define VEN_EXTRADATA_SLICEINFO 0x100 -#define VEN_EXTRADATA_LTRINFO 0x200 -#define VEN_EXTRADATA_MBINFO 0x400 -#define VEN_FRAME_TYPE_I 1 -#define VEN_FRAME_TYPE_P 2 -#define VEN_FRAME_TYPE_B 3 -#define VEN_CODEC_MPEG4 1 -#define VEN_CODEC_H264 2 -#define VEN_CODEC_H263 3 -#define VEN_PROFILE_MPEG4_SP 1 -#define VEN_PROFILE_MPEG4_ASP 2 -#define VEN_PROFILE_H264_BASELINE 3 -#define VEN_PROFILE_H264_MAIN 4 -#define VEN_PROFILE_H264_HIGH 5 -#define VEN_PROFILE_H263_BASELINE 6 -#define VEN_LEVEL_MPEG4_0 0x1 -#define VEN_LEVEL_MPEG4_1 0x2 -#define VEN_LEVEL_MPEG4_2 0x3 -#define VEN_LEVEL_MPEG4_3 0x4 -#define VEN_LEVEL_MPEG4_4 0x5 -#define VEN_LEVEL_MPEG4_5 0x6 -#define VEN_LEVEL_MPEG4_3b 0x7 -#define VEN_LEVEL_MPEG4_6 0x8 -#define VEN_LEVEL_H264_1 0x9 -#define VEN_LEVEL_H264_1b 0xA -#define VEN_LEVEL_H264_1p1 0xB -#define VEN_LEVEL_H264_1p2 0xC -#define VEN_LEVEL_H264_1p3 0xD -#define VEN_LEVEL_H264_2 0xE -#define VEN_LEVEL_H264_2p1 0xF -#define VEN_LEVEL_H264_2p2 0x10 -#define VEN_LEVEL_H264_3 0x11 -#define VEN_LEVEL_H264_3p1 0x12 -#define VEN_LEVEL_H264_3p2 0x13 -#define VEN_LEVEL_H264_4 0x14 -#define VEN_LEVEL_H263_10 0x15 -#define VEN_LEVEL_H263_20 0x16 -#define VEN_LEVEL_H263_30 0x17 -#define VEN_LEVEL_H263_40 0x18 -#define VEN_LEVEL_H263_45 0x19 -#define VEN_LEVEL_H263_50 0x1A -#define VEN_LEVEL_H263_60 0x1B -#define VEN_LEVEL_H263_70 0x1C -#define VEN_ENTROPY_MODEL_CAVLC 1 -#define VEN_ENTROPY_MODEL_CABAC 2 -#define VEN_CABAC_MODEL_0 1 -#define VEN_CABAC_MODEL_1 2 -#define VEN_CABAC_MODEL_2 3 -#define VEN_DB_DISABLE 1 -#define VEN_DB_ALL_BLKG_BNDRY 2 -#define VEN_DB_SKIP_SLICE_BNDRY 3 -#define VEN_MSLICE_OFF 1 -#define VEN_MSLICE_CNT_MB 2 -#define VEN_MSLICE_CNT_BYTE 3 -#define VEN_MSLICE_GOB 4 -#define VEN_RC_OFF 1 -#define VEN_RC_VBR_VFR 2 -#define VEN_RC_VBR_CFR 3 -#define VEN_RC_CBR_VFR 4 -#define VEN_RC_CBR_CFR 5 -#define VEN_FLUSH_INPUT 1 -#define VEN_FLUSH_OUTPUT 2 -#define VEN_FLUSH_ALL 3 -#define VEN_INPUTFMT_NV12 1 -#define VEN_INPUTFMT_NV21 2 -#define VEN_INPUTFMT_NV12_16M2KA 3 -#define VEN_ROTATION_0 1 -#define VEN_ROTATION_90 2 -#define VEN_ROTATION_180 3 -#define VEN_ROTATION_270 4 -#define VEN_TIMEOUT_INFINITE 0xffffffff -#define VEN_IR_OFF 1 -#define VEN_IR_CYCLIC 2 -#define VEN_IR_RANDOM 3 -#define VEN_IOCTLBASE_NENC 0x800 -#define VEN_IOCTLBASE_ENC 0x850 -struct venc_ioctl_msg { - void * in; - void * out; -}; -#define VEN_IOCTL_SET_INTF_VERSION _IOW(VEN_IOCTLBASE_NENC, 0, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_READ_NEXT_MSG _IOWR(VEN_IOCTLBASE_NENC, 1, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_STOP_READ_MSG _IO(VEN_IOCTLBASE_NENC, 2) -#define VEN_IOCTL_SET_INPUT_BUFFER_REQ _IOW(VEN_IOCTLBASE_NENC, 3, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_INPUT_BUFFER_REQ _IOR(VEN_IOCTLBASE_NENC, 4, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_ALLOC_INPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 5, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_INPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 6, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_FREE_INPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 7, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_OUTPUT_BUFFER_REQ _IOW(VEN_IOCTLBASE_NENC, 8, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_OUTPUT_BUFFER_REQ _IOR(VEN_IOCTLBASE_NENC, 9, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_ALLOC_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 10, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 11, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_FREE_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 12, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_START _IO(VEN_IOCTLBASE_NENC, 13) -#define VEN_IOCTL_CMD_ENCODE_FRAME _IOW(VEN_IOCTLBASE_NENC, 14, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_FILL_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 15, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_FLUSH _IOW(VEN_IOCTLBASE_NENC, 16, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_PAUSE _IO(VEN_IOCTLBASE_NENC, 17) -#define VEN_IOCTL_CMD_RESUME _IO(VEN_IOCTLBASE_NENC, 18) -#define VEN_IOCTL_CMD_STOP _IO(VEN_IOCTLBASE_NENC, 19) -#define VEN_IOCTL_SET_RECON_BUFFER _IOW(VEN_IOCTLBASE_NENC, 20, struct venc_ioctl_msg) -#define VEN_IOCTL_FREE_RECON_BUFFER _IOW(VEN_IOCTLBASE_NENC, 21, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_RECON_BUFFER_SIZE _IOW(VEN_IOCTLBASE_NENC, 22, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_BASE_CFG _IOW(VEN_IOCTLBASE_ENC, 1, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_BASE_CFG _IOR(VEN_IOCTLBASE_ENC, 2, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_LIVE_MODE _IOW(VEN_IOCTLBASE_ENC, 3, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_LIVE_MODE _IOR(VEN_IOCTLBASE_ENC, 4, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_CODEC_PROFILE _IOW(VEN_IOCTLBASE_ENC, 5, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_CODEC_PROFILE _IOR(VEN_IOCTLBASE_ENC, 6, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_PROFILE_LEVEL _IOW(VEN_IOCTLBASE_ENC, 7, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_PROFILE_LEVEL _IOR(VEN_IOCTLBASE_ENC, 8, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_SHORT_HDR _IOW(VEN_IOCTLBASE_ENC, 9, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_SHORT_HDR _IOR(VEN_IOCTLBASE_ENC, 10, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_SESSION_QP _IOW(VEN_IOCTLBASE_ENC, 11, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_SESSION_QP _IOR(VEN_IOCTLBASE_ENC, 12, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_INTRA_PERIOD _IOW(VEN_IOCTLBASE_ENC, 13, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_INTRA_PERIOD _IOR(VEN_IOCTLBASE_ENC, 14, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_REQUEST_IFRAME _IO(VEN_IOCTLBASE_ENC, 15) -#define VEN_IOCTL_GET_CAPABILITY _IOR(VEN_IOCTLBASE_ENC, 16, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_SEQUENCE_HDR _IOR(VEN_IOCTLBASE_ENC, 17, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_ENTROPY_CFG _IOW(VEN_IOCTLBASE_ENC, 18, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_ENTROPY_CFG _IOR(VEN_IOCTLBASE_ENC, 19, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_DEBLOCKING_CFG _IOW(VEN_IOCTLBASE_ENC, 20, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_DEBLOCKING_CFG _IOR(VEN_IOCTLBASE_ENC, 21, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_INTRA_REFRESH _IOW(VEN_IOCTLBASE_ENC, 22, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_INTRA_REFRESH _IOR(VEN_IOCTLBASE_ENC, 23, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_MULTI_SLICE_CFG _IOW(VEN_IOCTLBASE_ENC, 24, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_MULTI_SLICE_CFG _IOR(VEN_IOCTLBASE_ENC, 25, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_RATE_CTRL_CFG _IOW(VEN_IOCTLBASE_ENC, 26, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_RATE_CTRL_CFG _IOR(VEN_IOCTLBASE_ENC, 27, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_VOP_TIMING_CFG _IOW(VEN_IOCTLBASE_ENC, 28, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_VOP_TIMING_CFG _IOR(VEN_IOCTLBASE_ENC, 29, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_FRAME_RATE _IOW(VEN_IOCTLBASE_ENC, 30, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_FRAME_RATE _IOR(VEN_IOCTLBASE_ENC, 31, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_TARGET_BITRATE _IOW(VEN_IOCTLBASE_ENC, 32, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_TARGET_BITRATE _IOR(VEN_IOCTLBASE_ENC, 33, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_ROTATION _IOW(VEN_IOCTLBASE_ENC, 34, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_ROTATION _IOR(VEN_IOCTLBASE_ENC, 35, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_HEC _IOW(VEN_IOCTLBASE_ENC, 36, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_HEC _IOR(VEN_IOCTLBASE_ENC, 37, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_DATA_PARTITION _IOW(VEN_IOCTLBASE_ENC, 38, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_DATA_PARTITION _IOR(VEN_IOCTLBASE_ENC, 39, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_RVLC _IOW(VEN_IOCTLBASE_ENC, 40, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_RVLC _IOR(VEN_IOCTLBASE_ENC, 41, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_AC_PREDICTION _IOW(VEN_IOCTLBASE_ENC, 42, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_AC_PREDICTION _IOR(VEN_IOCTLBASE_ENC, 43, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_QP_RANGE _IOW(VEN_IOCTLBASE_ENC, 44, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_QP_RANGE _IOR(VEN_IOCTLBASE_ENC, 45, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_NUMBER_INSTANCES _IOR(VEN_IOCTLBASE_ENC, 46, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_METABUFFER_MODE _IOW(VEN_IOCTLBASE_ENC, 47, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_EXTRADATA _IOW(VEN_IOCTLBASE_ENC, 48, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_EXTRADATA _IOR(VEN_IOCTLBASE_ENC, 49, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_SLICE_DELIVERY_MODE _IO(VEN_IOCTLBASE_ENC, 50) -#define VEN_IOCTL_SET_H263_PLUSPTYPE _IOW(VEN_IOCTLBASE_ENC, 51, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_CAPABILITY_LTRCOUNT _IOW(VEN_IOCTLBASE_ENC, 52, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_CAPABILITY_LTRCOUNT _IOR(VEN_IOCTLBASE_ENC, 53, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_LTRMODE _IOW(VEN_IOCTLBASE_ENC, 54, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_LTRMODE _IOR(VEN_IOCTLBASE_ENC, 55, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_LTRCOUNT _IOW(VEN_IOCTLBASE_ENC, 56, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_LTRCOUNT _IOR(VEN_IOCTLBASE_ENC, 57, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_LTRPERIOD _IOW(VEN_IOCTLBASE_ENC, 58, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_LTRPERIOD _IOR(VEN_IOCTLBASE_ENC, 59, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_LTRUSE _IOW(VEN_IOCTLBASE_ENC, 60, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_LTRUSE _IOR(VEN_IOCTLBASE_ENC, 61, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_LTRMARK _IOW(VEN_IOCTLBASE_ENC, 62, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_LTRMARK _IOR(VEN_IOCTLBASE_ENC, 63, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_SPS_PPS_FOR_IDR _IOW(VEN_IOCTLBASE_ENC, 64, struct venc_ioctl_msg) -struct venc_range { - unsigned long max; - unsigned long min; - unsigned long step_size; -}; -struct venc_switch { - unsigned char status; -}; -struct venc_allocatorproperty { - unsigned long mincount; - unsigned long maxcount; - unsigned long actualcount; - unsigned long datasize; - unsigned long suffixsize; - unsigned long alignment; - unsigned long bufpoolid; -}; -struct venc_bufferpayload { - unsigned char * pbuffer; - size_t sz; - int fd; - unsigned int offset; - unsigned int maped_size; - unsigned long filled_len; -}; -struct venc_buffer { - unsigned char * ptrbuffer; - unsigned long sz; - unsigned long len; - unsigned long offset; - long long timestamp; - unsigned long flags; - void * clientdata; -}; -struct venc_basecfg { - unsigned long input_width; - unsigned long input_height; - unsigned long dvs_width; - unsigned long dvs_height; - unsigned long codectype; - unsigned long fps_num; - unsigned long fps_den; - unsigned long targetbitrate; - unsigned long inputformat; -}; -struct venc_profile { - unsigned long profile; -}; -struct ven_profilelevel { - unsigned long level; -}; -struct venc_sessionqp { - unsigned long iframeqp; - unsigned long pframqp; -}; -struct venc_qprange { - unsigned long maxqp; - unsigned long minqp; -}; -struct venc_plusptype { - unsigned long plusptype_enable; -}; -struct venc_intraperiod { - unsigned long num_pframes; - unsigned long num_bframes; -}; -struct venc_seqheader { - unsigned char * hdrbufptr; - unsigned long bufsize; - unsigned long hdrlen; -}; -struct venc_capability { - unsigned long codec_types; - unsigned long maxframe_width; - unsigned long maxframe_height; - unsigned long maxtarget_bitrate; - unsigned long maxframe_rate; - unsigned long input_formats; - unsigned char dvs; -}; -struct venc_entropycfg { - unsigned int longentropysel; - unsigned long cabacmodel; -}; -struct venc_dbcfg { - unsigned long db_mode; - unsigned long slicealpha_offset; - unsigned long slicebeta_offset; -}; -struct venc_intrarefresh { - unsigned long irmode; - unsigned long mbcount; -}; -struct venc_multiclicecfg { - unsigned long mslice_mode; - unsigned long mslice_size; -}; -struct venc_bufferflush { - unsigned long flush_mode; -}; -struct venc_ratectrlcfg { - unsigned long rcmode; -}; -struct venc_voptimingcfg { - unsigned long voptime_resolution; -}; -struct venc_framerate { - unsigned long fps_denominator; - unsigned long fps_numerator; -}; -struct venc_targetbitrate { - unsigned long target_bitrate; -}; -struct venc_rotation { - unsigned long rotation; -}; -struct venc_timeout { - unsigned long millisec; -}; -struct venc_headerextension { - unsigned long header_extension; -}; -struct venc_msg { - unsigned long statuscode; - unsigned long msgcode; - struct venc_buffer buf; - unsigned long msgdata_size; -}; -struct venc_recon_addr { - unsigned char * pbuffer; - unsigned long buffer_size; - unsigned long pmem_fd; - unsigned long offset; -}; -struct venc_recon_buff_size { - int width; - int height; - int size; - int alignment; -}; -struct venc_ltrmode { - unsigned long ltr_mode; -}; -struct venc_ltrcount { - unsigned long ltr_count; -}; -struct venc_ltrperiod { - unsigned long ltr_period; -}; -struct venc_ltruse { - unsigned long ltr_id; - unsigned long ltr_frames; -}; -#endif - diff --git a/sdm710/kernel-headers/linux/qseecom.h b/sdm710/kernel-headers/linux/qseecom.h deleted file mode 100644 index de4bc398..00000000 --- a/sdm710/kernel-headers/linux/qseecom.h +++ /dev/null @@ -1,214 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _QSEECOM_H_ -#define _QSEECOM_H_ -#include <linux/types.h> -#include <linux/ioctl.h> -#define MAX_ION_FD 4 -#define MAX_APP_NAME_SIZE 64 -#define QSEECOM_HASH_SIZE 32 -#define QSEECOM_TA_ION_ALLOCATE_DELAY 50 -#define QSEECOM_TA_ION_ALLOCATE_MAX_ATTEMP 20 -struct qseecom_register_listener_req { - uint32_t listener_id; - int32_t ifd_data_fd; - void * virt_sb_base; - uint32_t sb_size; -}; -struct qseecom_send_cmd_req { - void * cmd_req_buf; - unsigned int cmd_req_len; - void * resp_buf; - unsigned int resp_len; -}; -struct qseecom_ion_fd_info { - int32_t fd; - uint32_t cmd_buf_offset; -}; -struct qseecom_send_modfd_cmd_req { - void * cmd_req_buf; - unsigned int cmd_req_len; - void * resp_buf; - unsigned int resp_len; - struct qseecom_ion_fd_info ifd_data[MAX_ION_FD]; -}; -struct qseecom_send_resp_req { - void * resp_buf; - unsigned int resp_len; -}; -struct qseecom_load_img_req { - uint32_t mdt_len; - uint32_t img_len; - int32_t ifd_data_fd; - char img_name[MAX_APP_NAME_SIZE]; - uint32_t app_arch; - uint32_t app_id; -}; -struct qseecom_set_sb_mem_param_req { - int32_t ifd_data_fd; - void * virt_sb_base; - uint32_t sb_len; -}; -struct qseecom_qseos_version_req { - unsigned int qseos_version; -}; -struct qseecom_qseos_app_load_query { - char app_name[MAX_APP_NAME_SIZE]; - uint32_t app_id; - uint32_t app_arch; -}; -struct qseecom_send_svc_cmd_req { - uint32_t cmd_id; - void * cmd_req_buf; - unsigned int cmd_req_len; - void * resp_buf; - unsigned int resp_len; -}; -enum qseecom_key_management_usage_type { - QSEOS_KM_USAGE_DISK_ENCRYPTION = 0x01, - QSEOS_KM_USAGE_FILE_ENCRYPTION = 0x02, - QSEOS_KM_USAGE_UFS_ICE_DISK_ENCRYPTION = 0x03, - QSEOS_KM_USAGE_SDCC_ICE_DISK_ENCRYPTION = 0x04, - QSEOS_KM_USAGE_MAX -}; -struct qseecom_create_key_req { - unsigned char hash32[QSEECOM_HASH_SIZE]; - enum qseecom_key_management_usage_type usage; -}; -struct qseecom_wipe_key_req { - enum qseecom_key_management_usage_type usage; - int wipe_key_flag; -}; -struct qseecom_update_key_userinfo_req { - unsigned char current_hash32[QSEECOM_HASH_SIZE]; - unsigned char new_hash32[QSEECOM_HASH_SIZE]; - enum qseecom_key_management_usage_type usage; -}; -#define SHA256_DIGEST_LENGTH (256 / 8) -struct qseecom_save_partition_hash_req { - int partition_id; - char digest[SHA256_DIGEST_LENGTH]; -}; -struct qseecom_is_es_activated_req { - int is_activated; -}; -struct qseecom_mdtp_cipher_dip_req { - uint8_t * in_buf; - uint32_t in_buf_size; - uint8_t * out_buf; - uint32_t out_buf_size; - uint32_t direction; -}; -enum qseecom_bandwidth_request_mode { - INACTIVE = 0, - LOW, - MEDIUM, - HIGH, -}; -struct qseecom_send_modfd_listener_resp { - void * resp_buf_ptr; - unsigned int resp_len; - struct qseecom_ion_fd_info ifd_data[MAX_ION_FD]; -}; -struct qseecom_qteec_req { - void * req_ptr; - uint32_t req_len; - void * resp_ptr; - uint32_t resp_len; -}; -struct qseecom_qteec_modfd_req { - void * req_ptr; - uint32_t req_len; - void * resp_ptr; - uint32_t resp_len; - struct qseecom_ion_fd_info ifd_data[MAX_ION_FD]; -}; -struct qseecom_sg_entry { - uint32_t phys_addr; - uint32_t len; -}; -struct qseecom_sg_entry_64bit { - uint64_t phys_addr; - uint32_t len; -} __attribute__((packed)); -#define QSEECOM_SG_LIST_BUF_FORMAT_VERSION_1 1 -#define QSEECOM_SG_LIST_BUF_FORMAT_VERSION_2 2 -struct qseecom_sg_list_buf_hdr_64bit { - struct qseecom_sg_entry_64bit blank_entry; - uint32_t version; - uint64_t new_buf_phys_addr; - uint32_t nents_total; -} __attribute__((packed)); -#define QSEECOM_SG_LIST_BUF_HDR_SZ_64BIT sizeof(struct qseecom_sg_list_buf_hdr_64bit) -#define MAX_CE_PIPE_PAIR_PER_UNIT 3 -#define INVALID_CE_INFO_UNIT_NUM 0xffffffff -#define CE_PIPE_PAIR_USE_TYPE_FDE 0 -#define CE_PIPE_PAIR_USE_TYPE_PFE 1 -struct qseecom_ce_pipe_entry { - int valid; - unsigned int ce_num; - unsigned int ce_pipe_pair; -}; -#define MAX_CE_INFO_HANDLE_SIZE 32 -struct qseecom_ce_info_req { - unsigned char handle[MAX_CE_INFO_HANDLE_SIZE]; - unsigned int usage; - unsigned int unit_num; - unsigned int num_ce_pipe_entries; - struct qseecom_ce_pipe_entry ce_pipe_entry[MAX_CE_PIPE_PAIR_PER_UNIT]; -}; -#define SG_ENTRY_SZ sizeof(struct qseecom_sg_entry) -#define SG_ENTRY_SZ_64BIT sizeof(struct qseecom_sg_entry_64bit) -struct file; -#define QSEECOM_IOC_MAGIC 0x97 -#define QSEECOM_IOCTL_REGISTER_LISTENER_REQ _IOWR(QSEECOM_IOC_MAGIC, 1, struct qseecom_register_listener_req) -#define QSEECOM_IOCTL_UNREGISTER_LISTENER_REQ _IO(QSEECOM_IOC_MAGIC, 2) -#define QSEECOM_IOCTL_SEND_CMD_REQ _IOWR(QSEECOM_IOC_MAGIC, 3, struct qseecom_send_cmd_req) -#define QSEECOM_IOCTL_SEND_MODFD_CMD_REQ _IOWR(QSEECOM_IOC_MAGIC, 4, struct qseecom_send_modfd_cmd_req) -#define QSEECOM_IOCTL_RECEIVE_REQ _IO(QSEECOM_IOC_MAGIC, 5) -#define QSEECOM_IOCTL_SEND_RESP_REQ _IO(QSEECOM_IOC_MAGIC, 6) -#define QSEECOM_IOCTL_LOAD_APP_REQ _IOWR(QSEECOM_IOC_MAGIC, 7, struct qseecom_load_img_req) -#define QSEECOM_IOCTL_SET_MEM_PARAM_REQ _IOWR(QSEECOM_IOC_MAGIC, 8, struct qseecom_set_sb_mem_param_req) -#define QSEECOM_IOCTL_UNLOAD_APP_REQ _IO(QSEECOM_IOC_MAGIC, 9) -#define QSEECOM_IOCTL_GET_QSEOS_VERSION_REQ _IOWR(QSEECOM_IOC_MAGIC, 10, struct qseecom_qseos_version_req) -#define QSEECOM_IOCTL_PERF_ENABLE_REQ _IO(QSEECOM_IOC_MAGIC, 11) -#define QSEECOM_IOCTL_PERF_DISABLE_REQ _IO(QSEECOM_IOC_MAGIC, 12) -#define QSEECOM_IOCTL_LOAD_EXTERNAL_ELF_REQ _IOWR(QSEECOM_IOC_MAGIC, 13, struct qseecom_load_img_req) -#define QSEECOM_IOCTL_UNLOAD_EXTERNAL_ELF_REQ _IO(QSEECOM_IOC_MAGIC, 14) -#define QSEECOM_IOCTL_APP_LOADED_QUERY_REQ _IOWR(QSEECOM_IOC_MAGIC, 15, struct qseecom_qseos_app_load_query) -#define QSEECOM_IOCTL_SEND_CMD_SERVICE_REQ _IOWR(QSEECOM_IOC_MAGIC, 16, struct qseecom_send_svc_cmd_req) -#define QSEECOM_IOCTL_CREATE_KEY_REQ _IOWR(QSEECOM_IOC_MAGIC, 17, struct qseecom_create_key_req) -#define QSEECOM_IOCTL_WIPE_KEY_REQ _IOWR(QSEECOM_IOC_MAGIC, 18, struct qseecom_wipe_key_req) -#define QSEECOM_IOCTL_SAVE_PARTITION_HASH_REQ _IOWR(QSEECOM_IOC_MAGIC, 19, struct qseecom_save_partition_hash_req) -#define QSEECOM_IOCTL_IS_ES_ACTIVATED_REQ _IOWR(QSEECOM_IOC_MAGIC, 20, struct qseecom_is_es_activated_req) -#define QSEECOM_IOCTL_SEND_MODFD_RESP _IOWR(QSEECOM_IOC_MAGIC, 21, struct qseecom_send_modfd_listener_resp) -#define QSEECOM_IOCTL_SET_BUS_SCALING_REQ _IOWR(QSEECOM_IOC_MAGIC, 23, int) -#define QSEECOM_IOCTL_UPDATE_KEY_USER_INFO_REQ _IOWR(QSEECOM_IOC_MAGIC, 24, struct qseecom_update_key_userinfo_req) -#define QSEECOM_QTEEC_IOCTL_OPEN_SESSION_REQ _IOWR(QSEECOM_IOC_MAGIC, 30, struct qseecom_qteec_modfd_req) -#define QSEECOM_QTEEC_IOCTL_CLOSE_SESSION_REQ _IOWR(QSEECOM_IOC_MAGIC, 31, struct qseecom_qteec_req) -#define QSEECOM_QTEEC_IOCTL_INVOKE_MODFD_CMD_REQ _IOWR(QSEECOM_IOC_MAGIC, 32, struct qseecom_qteec_modfd_req) -#define QSEECOM_QTEEC_IOCTL_REQUEST_CANCELLATION_REQ _IOWR(QSEECOM_IOC_MAGIC, 33, struct qseecom_qteec_modfd_req) -#define QSEECOM_IOCTL_MDTP_CIPHER_DIP_REQ _IOWR(QSEECOM_IOC_MAGIC, 34, struct qseecom_mdtp_cipher_dip_req) -#define QSEECOM_IOCTL_SEND_MODFD_CMD_64_REQ _IOWR(QSEECOM_IOC_MAGIC, 35, struct qseecom_send_modfd_cmd_req) -#define QSEECOM_IOCTL_SEND_MODFD_RESP_64 _IOWR(QSEECOM_IOC_MAGIC, 36, struct qseecom_send_modfd_listener_resp) -#define QSEECOM_IOCTL_GET_CE_PIPE_INFO _IOWR(QSEECOM_IOC_MAGIC, 40, struct qseecom_ce_info_req) -#define QSEECOM_IOCTL_FREE_CE_PIPE_INFO _IOWR(QSEECOM_IOC_MAGIC, 41, struct qseecom_ce_info_req) -#define QSEECOM_IOCTL_QUERY_CE_PIPE_INFO _IOWR(QSEECOM_IOC_MAGIC, 42, struct qseecom_ce_info_req) -#endif - diff --git a/sdm710/kernel-headers/linux/rmnet_data.h b/sdm710/kernel-headers/linux/rmnet_data.h deleted file mode 100644 index 71df613f..00000000 --- a/sdm710/kernel-headers/linux/rmnet_data.h +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _RMNET_DATA_H_ -#define _RMNET_DATA_H_ -#define RMNET_LOCAL_LOGICAL_ENDPOINT - 1 -#define RMNET_EGRESS_FORMAT__RESERVED__ (1 << 0) -#define RMNET_EGRESS_FORMAT_MAP (1 << 1) -#define RMNET_EGRESS_FORMAT_AGGREGATION (1 << 2) -#define RMNET_EGRESS_FORMAT_MUXING (1 << 3) -#define RMNET_EGRESS_FORMAT_MAP_CKSUMV3 (1 << 4) -#define RMNET_EGRESS_FORMAT_MAP_CKSUMV4 (1 << 5) -#define RMNET_INGRESS_FIX_ETHERNET (1 << 0) -#define RMNET_INGRESS_FORMAT_MAP (1 << 1) -#define RMNET_INGRESS_FORMAT_DEAGGREGATION (1 << 2) -#define RMNET_INGRESS_FORMAT_DEMUXING (1 << 3) -#define RMNET_INGRESS_FORMAT_MAP_COMMANDS (1 << 4) -#define RMNET_INGRESS_FORMAT_MAP_CKSUMV3 (1 << 5) -#define RMNET_INGRESS_FORMAT_MAP_CKSUMV4 (1 << 6) -#define RMNET_NETLINK_PROTO 31 -#define RMNET_MAX_STR_LEN 16 -#define RMNET_NL_DATA_MAX_LEN 64 -#define RMNET_NETLINK_MSG_COMMAND 0 -#define RMNET_NETLINK_MSG_RETURNCODE 1 -#define RMNET_NETLINK_MSG_RETURNDATA 2 -struct rmnet_nl_msg_s { - uint16_t reserved; - uint16_t message_type; - uint16_t reserved2 : 14; - uint16_t crd : 2; - union { - uint16_t arg_length; - uint16_t return_code; - }; - union { - uint8_t data[RMNET_NL_DATA_MAX_LEN]; - struct { - uint8_t dev[RMNET_MAX_STR_LEN]; - uint32_t flags; - uint16_t agg_size; - uint16_t agg_count; - uint8_t tail_spacing; - } data_format; - struct { - uint8_t dev[RMNET_MAX_STR_LEN]; - int32_t ep_id; - uint8_t operating_mode; - uint8_t next_dev[RMNET_MAX_STR_LEN]; - } local_ep_config; - struct { - uint32_t id; - uint8_t vnd_name[RMNET_MAX_STR_LEN]; - } vnd; - struct { - uint32_t id; - uint32_t map_flow_id; - uint32_t tc_flow_id; - } flow_control; - }; -}; -enum rmnet_netlink_message_types_e { - RMNET_NETLINK_ASSOCIATE_NETWORK_DEVICE, - RMNET_NETLINK_UNASSOCIATE_NETWORK_DEVICE, - RMNET_NETLINK_GET_NETWORK_DEVICE_ASSOCIATED, - RMNET_NETLINK_SET_LINK_EGRESS_DATA_FORMAT, - RMNET_NETLINK_GET_LINK_EGRESS_DATA_FORMAT, - RMNET_NETLINK_SET_LINK_INGRESS_DATA_FORMAT, - RMNET_NETLINK_GET_LINK_INGRESS_DATA_FORMAT, - RMNET_NETLINK_SET_LOGICAL_EP_CONFIG, - RMNET_NETLINK_UNSET_LOGICAL_EP_CONFIG, - RMNET_NETLINK_GET_LOGICAL_EP_CONFIG, - RMNET_NETLINK_NEW_VND, - RMNET_NETLINK_NEW_VND_WITH_PREFIX, - RMNET_NETLINK_GET_VND_NAME, - RMNET_NETLINK_FREE_VND, - RMNET_NETLINK_ADD_VND_TC_FLOW, - RMNET_NETLINK_DEL_VND_TC_FLOW, - RMNET_NETLINK_NEW_VND_WITH_NAME -}; -#define RMNET_NETLINK_NEW_VND_WITH_NAME RMNET_NETLINK_NEW_VND_WITH_NAME -enum rmnet_config_endpoint_modes_e { - RMNET_EPMODE_NONE, - RMNET_EPMODE_VND, - RMNET_EPMODE_BRIDGE, - RMNET_EPMODE_LENGTH -}; -enum rmnet_config_return_codes_e { - RMNET_CONFIG_OK, - RMNET_CONFIG_UNKNOWN_MESSAGE, - RMNET_CONFIG_UNKNOWN_ERROR, - RMNET_CONFIG_NOMEM, - RMNET_CONFIG_DEVICE_IN_USE, - RMNET_CONFIG_INVALID_REQUEST, - RMNET_CONFIG_NO_SUCH_DEVICE, - RMNET_CONFIG_BAD_ARGUMENTS, - RMNET_CONFIG_BAD_EGRESS_DEVICE, - RMNET_CONFIG_TC_HANDLE_FULL -}; -#endif - diff --git a/sdm710/kernel-headers/linux/rmnet_ipa_fd_ioctl.h b/sdm710/kernel-headers/linux/rmnet_ipa_fd_ioctl.h deleted file mode 100644 index c903b554..00000000 --- a/sdm710/kernel-headers/linux/rmnet_ipa_fd_ioctl.h +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _RMNET_IPA_FD_IOCTL_H -#define _RMNET_IPA_FD_IOCTL_H -#include <linux/ioctl.h> -#include <linux/ipa_qmi_service_v01.h> -#include <linux/msm_ipa.h> -#define WAN_IOC_MAGIC 0x69 -#define WAN_IOCTL_ADD_FLT_RULE 0 -#define WAN_IOCTL_ADD_FLT_INDEX 1 -#define WAN_IOCTL_VOTE_FOR_BW_MBPS 2 -#define WAN_IOCTL_POLL_TETHERING_STATS 3 -#define WAN_IOCTL_SET_DATA_QUOTA 4 -#define WAN_IOCTL_SET_TETHER_CLIENT_PIPE 5 -#define WAN_IOCTL_QUERY_TETHER_STATS 6 -#define WAN_IOCTL_RESET_TETHER_STATS 7 -#define WAN_IOCTL_QUERY_DL_FILTER_STATS 8 -#define WAN_IOCTL_ADD_FLT_RULE_EX 9 -#define WAN_IOCTL_QUERY_TETHER_STATS_ALL 10 -#define WAN_IOCTL_NOTIFY_WAN_STATE 11 -#define WAN_IOCTL_ADD_UL_FLT_RULE 12 -#define WAN_IOCTL_ENABLE_PER_CLIENT_STATS 13 -#define WAN_IOCTL_QUERY_PER_CLIENT_STATS 14 -#define WAN_IOCTL_SET_LAN_CLIENT_INFO 15 -#define WAN_IOCTL_CLEAR_LAN_CLIENT_INFO 16 -#define WAN_IOCTL_SEND_LAN_CLIENT_MSG 17 -#ifndef IFNAMSIZ -#define IFNAMSIZ 16 -#endif -struct wan_ioctl_poll_tethering_stats { - uint64_t polling_interval_secs; - uint8_t reset_stats; -}; -struct wan_ioctl_set_data_quota { - char interface_name[IFNAMSIZ]; - uint64_t quota_mbytes; - uint8_t set_quota; -}; -struct wan_ioctl_set_tether_client_pipe { - enum ipacm_client_enum ipa_client; - uint8_t reset_client; - uint32_t ul_src_pipe_len; - uint32_t ul_src_pipe_list[QMI_IPA_MAX_PIPES_V01]; - uint32_t dl_dst_pipe_len; - uint32_t dl_dst_pipe_list[QMI_IPA_MAX_PIPES_V01]; -}; -struct wan_ioctl_query_tether_stats { - char upstreamIface[IFNAMSIZ]; - char tetherIface[IFNAMSIZ]; - enum ipacm_client_enum ipa_client; - uint64_t ipv4_tx_packets; - uint64_t ipv4_tx_bytes; - uint64_t ipv4_rx_packets; - uint64_t ipv4_rx_bytes; - uint64_t ipv6_tx_packets; - uint64_t ipv6_tx_bytes; - uint64_t ipv6_rx_packets; - uint64_t ipv6_rx_bytes; -}; -struct wan_ioctl_query_tether_stats_all { - char upstreamIface[IFNAMSIZ]; - enum ipacm_client_enum ipa_client; - uint8_t reset_stats; - uint64_t tx_bytes; - uint64_t rx_bytes; -}; -struct wan_ioctl_reset_tether_stats { - char upstreamIface[IFNAMSIZ]; - uint8_t reset_stats; -}; -struct wan_ioctl_query_dl_filter_stats { - uint8_t reset_stats; - struct ipa_get_data_stats_resp_msg_v01 stats_resp; - uint32_t index; -}; -struct wan_ioctl_notify_wan_state { - uint8_t up; -}; -struct wan_ioctl_send_lan_client_msg { - struct ipa_lan_client_msg lan_client; - enum ipa_per_client_stats_event client_event; -}; -struct wan_ioctl_lan_client_info { - enum ipacm_per_client_device_type device_type; - uint8_t mac[IPA_MAC_ADDR_SIZE]; - uint8_t client_init; - int8_t client_idx; - uint8_t hdr_len; - enum ipa_client_type ul_src_pipe; -}; -struct wan_ioctl_per_client_info { - uint8_t mac[IPA_MAC_ADDR_SIZE]; - uint64_t ipv4_tx_bytes; - uint64_t ipv4_rx_bytes; - uint64_t ipv6_tx_bytes; - uint64_t ipv6_rx_bytes; -}; -struct wan_ioctl_query_per_client_stats { - enum ipacm_per_client_device_type device_type; - uint8_t reset_stats; - uint8_t disconnect_clnt; - uint8_t num_clients; - struct wan_ioctl_per_client_info client_info[IPA_MAX_NUM_HW_PATH_CLIENTS]; -}; -#define WAN_IOC_ADD_FLT_RULE _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_ADD_FLT_RULE, struct ipa_install_fltr_rule_req_msg_v01 *) -#define WAN_IOC_ADD_FLT_RULE_INDEX _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_ADD_FLT_INDEX, struct ipa_fltr_installed_notif_req_msg_v01 *) -#define WAN_IOC_VOTE_FOR_BW_MBPS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_VOTE_FOR_BW_MBPS, uint32_t *) -#define WAN_IOC_POLL_TETHERING_STATS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_POLL_TETHERING_STATS, struct wan_ioctl_poll_tethering_stats *) -#define WAN_IOC_SET_DATA_QUOTA _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_SET_DATA_QUOTA, struct wan_ioctl_set_data_quota *) -#define WAN_IOC_SET_TETHER_CLIENT_PIPE _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_SET_TETHER_CLIENT_PIPE, struct wan_ioctl_set_tether_client_pipe *) -#define WAN_IOC_QUERY_TETHER_STATS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_QUERY_TETHER_STATS, struct wan_ioctl_query_tether_stats *) -#define WAN_IOC_RESET_TETHER_STATS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_RESET_TETHER_STATS, struct wan_ioctl_reset_tether_stats *) -#define WAN_IOC_QUERY_DL_FILTER_STATS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_QUERY_DL_FILTER_STATS, struct wan_ioctl_query_dl_filter_stats *) -#define WAN_IOC_ADD_FLT_RULE_EX _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_ADD_FLT_RULE_EX, struct ipa_install_fltr_rule_req_ex_msg_v01 *) -#define WAN_IOC_QUERY_TETHER_STATS_ALL _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_QUERY_TETHER_STATS_ALL, struct wan_ioctl_query_tether_stats_all *) -#define WAN_IOC_NOTIFY_WAN_STATE _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_NOTIFY_WAN_STATE, struct wan_ioctl_notify_wan_state *) -#define WAN_IOC_ADD_UL_FLT_RULE _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_ADD_UL_FLT_RULE, struct ipa_configure_ul_firewall_rules_req_msg_v01 *) -#define WAN_IOC_ENABLE_PER_CLIENT_STATS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_ENABLE_PER_CLIENT_STATS, bool *) -#define WAN_IOC_QUERY_PER_CLIENT_STATS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_QUERY_PER_CLIENT_STATS, struct wan_ioctl_query_per_client_stats *) -#define WAN_IOC_SET_LAN_CLIENT_INFO _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_SET_LAN_CLIENT_INFO, struct wan_ioctl_lan_client_info *) -#define WAN_IOC_SEND_LAN_CLIENT_MSG _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_SEND_LAN_CLIENT_MSG, struct wan_ioctl_send_lan_client_msg *) -#define WAN_IOC_CLEAR_LAN_CLIENT_INFO _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_CLEAR_LAN_CLIENT_INFO, struct wan_ioctl_lan_client_info *) -#endif - diff --git a/sdm710/kernel-headers/linux/sockios.h b/sdm710/kernel-headers/linux/sockios.h deleted file mode 100644 index b9a2ac4f..00000000 --- a/sdm710/kernel-headers/linux/sockios.h +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _LINUX_SOCKIOS_H -#define _LINUX_SOCKIOS_H -#include <asm/sockios.h> -#define SIOCINQ FIONREAD -#define SIOCOUTQ TIOCOUTQ -#define SIOCADDRT 0x890B -#define SIOCDELRT 0x890C -#define SIOCRTMSG 0x890D -#define SIOCGIFNAME 0x8910 -#define SIOCSIFLINK 0x8911 -#define SIOCGIFCONF 0x8912 -#define SIOCGIFFLAGS 0x8913 -#define SIOCSIFFLAGS 0x8914 -#define SIOCGIFADDR 0x8915 -#define SIOCSIFADDR 0x8916 -#define SIOCGIFDSTADDR 0x8917 -#define SIOCSIFDSTADDR 0x8918 -#define SIOCGIFBRDADDR 0x8919 -#define SIOCSIFBRDADDR 0x891a -#define SIOCGIFNETMASK 0x891b -#define SIOCSIFNETMASK 0x891c -#define SIOCGIFMETRIC 0x891d -#define SIOCSIFMETRIC 0x891e -#define SIOCGIFMEM 0x891f -#define SIOCSIFMEM 0x8920 -#define SIOCGIFMTU 0x8921 -#define SIOCSIFMTU 0x8922 -#define SIOCSIFNAME 0x8923 -#define SIOCSIFHWADDR 0x8924 -#define SIOCGIFENCAP 0x8925 -#define SIOCSIFENCAP 0x8926 -#define SIOCGIFHWADDR 0x8927 -#define SIOCGIFSLAVE 0x8929 -#define SIOCSIFSLAVE 0x8930 -#define SIOCADDMULTI 0x8931 -#define SIOCDELMULTI 0x8932 -#define SIOCGIFINDEX 0x8933 -#define SIOGIFINDEX SIOCGIFINDEX -#define SIOCSIFPFLAGS 0x8934 -#define SIOCGIFPFLAGS 0x8935 -#define SIOCDIFADDR 0x8936 -#define SIOCSIFHWBROADCAST 0x8937 -#define SIOCGIFCOUNT 0x8938 -#define SIOCGIFBR 0x8940 -#define SIOCSIFBR 0x8941 -#define SIOCGIFTXQLEN 0x8942 -#define SIOCSIFTXQLEN 0x8943 -#define SIOCETHTOOL 0x8946 -#define SIOCGMIIPHY 0x8947 -#define SIOCGMIIREG 0x8948 -#define SIOCSMIIREG 0x8949 -#define SIOCWANDEV 0x894A -#define SIOCOUTQNSD 0x894B -#define SIOCDARP 0x8953 -#define SIOCGARP 0x8954 -#define SIOCSARP 0x8955 -#define SIOCDRARP 0x8960 -#define SIOCGRARP 0x8961 -#define SIOCSRARP 0x8962 -#define SIOCGIFMAP 0x8970 -#define SIOCSIFMAP 0x8971 -#define SIOCADDDLCI 0x8980 -#define SIOCDELDLCI 0x8981 -#define SIOCGIFVLAN 0x8982 -#define SIOCSIFVLAN 0x8983 -#define SIOCBONDENSLAVE 0x8990 -#define SIOCBONDRELEASE 0x8991 -#define SIOCBONDSETHWADDR 0x8992 -#define SIOCBONDSLAVEINFOQUERY 0x8993 -#define SIOCBONDINFOQUERY 0x8994 -#define SIOCBONDCHANGEACTIVE 0x8995 -#define SIOCBRADDBR 0x89a0 -#define SIOCBRDELBR 0x89a1 -#define SIOCBRADDIF 0x89a2 -#define SIOCBRDELIF 0x89a3 -#define SIOCSHWTSTAMP 0x89b0 -#define SIOCGHWTSTAMP 0x89b1 -#define SIOCDEVPRIVATE 0x89F0 -#define SIOCPROTOPRIVATE 0x89E0 -#endif - diff --git a/sdm710/kernel-headers/linux/spcom.h b/sdm710/kernel-headers/linux/spcom.h deleted file mode 100644 index b468f622..00000000 --- a/sdm710/kernel-headers/linux/spcom.h +++ /dev/null @@ -1,78 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _SPCOM_H_ -#define _SPCOM_H_ -#include <linux/types.h> -#ifndef BIT -#define BIT(x) (1 << x) -#endif -#ifndef PAGE_SIZE -#define PAGE_SIZE 4096 -#endif -#define SPCOM_MAX_CHANNELS 0x20 -#define SPCOM_CHANNEL_NAME_SIZE 32 -#define SPCOM_GET_NEXT_REQUEST_SIZE (PAGE_SIZE - 1) -enum spcom_cmd_id { - SPCOM_CMD_LOAD_APP = 0x4C4F4144, - SPCOM_CMD_RESET_SP = 0x52455354, - SPCOM_CMD_SEND = 0x53454E44, - SPCOM_CMD_SEND_MODIFIED = 0x534E444D, - SPCOM_CMD_LOCK_ION_BUF = 0x4C4F434B, - SPCOM_CMD_UNLOCK_ION_BUF = 0x554C434B, - SPCOM_CMD_FSSR = 0x46535352, - SPCOM_CMD_CREATE_CHANNEL = 0x43524554, -}; -enum spcom_poll_events { - SPCOM_POLL_LINK_STATE = BIT(1), - SPCOM_POLL_CH_CONNECT = BIT(2), - SPCOM_POLL_READY_FLAG = BIT(14), - SPCOM_POLL_WAIT_FLAG = BIT(15), -}; -struct spcom_user_command { - enum spcom_cmd_id cmd_id; - uint32_t arg; -} __attribute__((packed)); -struct spcom_send_command { - enum spcom_cmd_id cmd_id; - uint32_t timeout_msec; - uint32_t buf_size; - char buf[0]; -} __attribute__((packed)); -struct spcom_user_create_channel_command { - enum spcom_cmd_id cmd_id; - char ch_name[SPCOM_CHANNEL_NAME_SIZE]; -} __attribute__((packed)); -#define SPCOM_MAX_ION_BUF 4 -struct spcom_ion_info { - int32_t fd; - uint32_t buf_offset; -}; -#define SPCOM_ION_FD_UNLOCK_ALL 0xFFFF -struct spcom_ion_handle { - int32_t fd; -}; -struct spcom_user_send_modified_command { - enum spcom_cmd_id cmd_id; - struct spcom_ion_info ion_info[SPCOM_MAX_ION_BUF]; - uint32_t timeout_msec; - uint32_t buf_size; - char buf[0]; -} __attribute__((packed)); -#endif - diff --git a/sdm710/kernel-headers/linux/v4l2-controls.h b/sdm710/kernel-headers/linux/v4l2-controls.h deleted file mode 100644 index e1046c68..00000000 --- a/sdm710/kernel-headers/linux/v4l2-controls.h +++ /dev/null @@ -1,1286 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __LINUX_V4L2_CONTROLS_H -#define __LINUX_V4L2_CONTROLS_H -#define V4L2_CTRL_CLASS_USER 0x00980000 -#define V4L2_CTRL_CLASS_MPEG 0x00990000 -#define V4L2_CTRL_CLASS_CAMERA 0x009a0000 -#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 -#define V4L2_CTRL_CLASS_FLASH 0x009c0000 -#define V4L2_CTRL_CLASS_JPEG 0x009d0000 -#define V4L2_CTRL_CLASS_IMAGE_SOURCE 0x009e0000 -#define V4L2_CTRL_CLASS_IMAGE_PROC 0x009f0000 -#define V4L2_CTRL_CLASS_DV 0x00a00000 -#define V4L2_CTRL_CLASS_FM_RX 0x00a10000 -#define V4L2_CTRL_CLASS_RF_TUNER 0x00a20000 -#define V4L2_CTRL_CLASS_DETECT 0x00a30000 -#define V4L2_CID_BASE (V4L2_CTRL_CLASS_USER | 0x900) -#define V4L2_CID_USER_BASE V4L2_CID_BASE -#define V4L2_CID_USER_CLASS (V4L2_CTRL_CLASS_USER | 1) -#define V4L2_CID_BRIGHTNESS (V4L2_CID_BASE + 0) -#define V4L2_CID_CONTRAST (V4L2_CID_BASE + 1) -#define V4L2_CID_SATURATION (V4L2_CID_BASE + 2) -#define V4L2_CID_HUE (V4L2_CID_BASE + 3) -#define V4L2_CID_AUDIO_VOLUME (V4L2_CID_BASE + 5) -#define V4L2_CID_AUDIO_BALANCE (V4L2_CID_BASE + 6) -#define V4L2_CID_AUDIO_BASS (V4L2_CID_BASE + 7) -#define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE + 8) -#define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE + 9) -#define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE + 10) -#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE + 11) -#define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE + 12) -#define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE + 13) -#define V4L2_CID_RED_BALANCE (V4L2_CID_BASE + 14) -#define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE + 15) -#define V4L2_CID_GAMMA (V4L2_CID_BASE + 16) -#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) -#define V4L2_CID_EXPOSURE (V4L2_CID_BASE + 17) -#define V4L2_CID_AUTOGAIN (V4L2_CID_BASE + 18) -#define V4L2_CID_GAIN (V4L2_CID_BASE + 19) -#define V4L2_CID_HFLIP (V4L2_CID_BASE + 20) -#define V4L2_CID_VFLIP (V4L2_CID_BASE + 21) -#define V4L2_CID_POWER_LINE_FREQUENCY (V4L2_CID_BASE + 24) -enum v4l2_power_line_frequency { - V4L2_CID_POWER_LINE_FREQUENCY_DISABLED = 0, - V4L2_CID_POWER_LINE_FREQUENCY_50HZ = 1, - V4L2_CID_POWER_LINE_FREQUENCY_60HZ = 2, - V4L2_CID_POWER_LINE_FREQUENCY_AUTO = 3, -}; -#define V4L2_CID_HUE_AUTO (V4L2_CID_BASE + 25) -#define V4L2_CID_WHITE_BALANCE_TEMPERATURE (V4L2_CID_BASE + 26) -#define V4L2_CID_SHARPNESS (V4L2_CID_BASE + 27) -#define V4L2_CID_BACKLIGHT_COMPENSATION (V4L2_CID_BASE + 28) -#define V4L2_CID_CHROMA_AGC (V4L2_CID_BASE + 29) -#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE + 30) -#define V4L2_CID_COLORFX (V4L2_CID_BASE + 31) -enum v4l2_colorfx { - V4L2_COLORFX_NONE = 0, - V4L2_COLORFX_BW = 1, - V4L2_COLORFX_SEPIA = 2, - V4L2_COLORFX_NEGATIVE = 3, - V4L2_COLORFX_EMBOSS = 4, - V4L2_COLORFX_SKETCH = 5, - V4L2_COLORFX_SKY_BLUE = 6, - V4L2_COLORFX_GRASS_GREEN = 7, - V4L2_COLORFX_SKIN_WHITEN = 8, - V4L2_COLORFX_VIVID = 9, - V4L2_COLORFX_AQUA = 10, - V4L2_COLORFX_ART_FREEZE = 11, - V4L2_COLORFX_SILHOUETTE = 12, - V4L2_COLORFX_SOLARIZATION = 13, - V4L2_COLORFX_ANTIQUE = 14, - V4L2_COLORFX_SET_CBCR = 15, -}; -#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE + 32) -#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE + 33) -#define V4L2_CID_ROTATE (V4L2_CID_BASE + 34) -#define V4L2_CID_BG_COLOR (V4L2_CID_BASE + 35) -#define V4L2_CID_CHROMA_GAIN (V4L2_CID_BASE + 36) -#define V4L2_CID_ILLUMINATORS_1 (V4L2_CID_BASE + 37) -#define V4L2_CID_ILLUMINATORS_2 (V4L2_CID_BASE + 38) -#define V4L2_CID_MIN_BUFFERS_FOR_CAPTURE (V4L2_CID_BASE + 39) -#define V4L2_CID_MIN_BUFFERS_FOR_OUTPUT (V4L2_CID_BASE + 40) -#define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE + 41) -#define V4L2_CID_COLORFX_CBCR (V4L2_CID_BASE + 42) -#define V4L2_CID_LASTP1 (V4L2_CID_BASE + 43) -#define V4L2_CID_USER_MEYE_BASE (V4L2_CID_USER_BASE + 0x1000) -#define V4L2_CID_USER_BTTV_BASE (V4L2_CID_USER_BASE + 0x1010) -#define V4L2_CID_USER_S2255_BASE (V4L2_CID_USER_BASE + 0x1030) -#define V4L2_CID_USER_SI476X_BASE (V4L2_CID_USER_BASE + 0x1040) -#define V4L2_CID_USER_TI_VPE_BASE (V4L2_CID_USER_BASE + 0x1050) -#define V4L2_CID_USER_SAA7134_BASE (V4L2_CID_USER_BASE + 0x1060) -#define V4L2_CID_USER_ADV7180_BASE (V4L2_CID_USER_BASE + 0x1070) -#define V4L2_CID_USER_TC358743_BASE (V4L2_CID_USER_BASE + 0x1080) -#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900) -#define V4L2_CID_MPEG_CLASS (V4L2_CTRL_CLASS_MPEG | 1) -#define V4L2_CID_MPEG_STREAM_TYPE (V4L2_CID_MPEG_BASE + 0) -enum v4l2_mpeg_stream_type { - V4L2_MPEG_STREAM_TYPE_MPEG2_PS = 0, - V4L2_MPEG_STREAM_TYPE_MPEG2_TS = 1, - V4L2_MPEG_STREAM_TYPE_MPEG1_SS = 2, - V4L2_MPEG_STREAM_TYPE_MPEG2_DVD = 3, - V4L2_MPEG_STREAM_TYPE_MPEG1_VCD = 4, - V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD = 5, -}; -#define V4L2_CID_MPEG_STREAM_PID_PMT (V4L2_CID_MPEG_BASE + 1) -#define V4L2_CID_MPEG_STREAM_PID_AUDIO (V4L2_CID_MPEG_BASE + 2) -#define V4L2_CID_MPEG_STREAM_PID_VIDEO (V4L2_CID_MPEG_BASE + 3) -#define V4L2_CID_MPEG_STREAM_PID_PCR (V4L2_CID_MPEG_BASE + 4) -#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO (V4L2_CID_MPEG_BASE + 5) -#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO (V4L2_CID_MPEG_BASE + 6) -#define V4L2_CID_MPEG_STREAM_VBI_FMT (V4L2_CID_MPEG_BASE + 7) -enum v4l2_mpeg_stream_vbi_fmt { - V4L2_MPEG_STREAM_VBI_FMT_NONE = 0, - V4L2_MPEG_STREAM_VBI_FMT_IVTV = 1, -}; -#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ (V4L2_CID_MPEG_BASE + 100) -enum v4l2_mpeg_audio_sampling_freq { - V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100 = 0, - V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000 = 1, - V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000 = 2, -}; -#define V4L2_CID_MPEG_AUDIO_ENCODING (V4L2_CID_MPEG_BASE + 101) -enum v4l2_mpeg_audio_encoding { - V4L2_MPEG_AUDIO_ENCODING_LAYER_1 = 0, - V4L2_MPEG_AUDIO_ENCODING_LAYER_2 = 1, - V4L2_MPEG_AUDIO_ENCODING_LAYER_3 = 2, - V4L2_MPEG_AUDIO_ENCODING_AAC = 3, - V4L2_MPEG_AUDIO_ENCODING_AC3 = 4, -}; -#define V4L2_CID_MPEG_AUDIO_L1_BITRATE (V4L2_CID_MPEG_BASE + 102) -enum v4l2_mpeg_audio_l1_bitrate { - V4L2_MPEG_AUDIO_L1_BITRATE_32K = 0, - V4L2_MPEG_AUDIO_L1_BITRATE_64K = 1, - V4L2_MPEG_AUDIO_L1_BITRATE_96K = 2, - V4L2_MPEG_AUDIO_L1_BITRATE_128K = 3, - V4L2_MPEG_AUDIO_L1_BITRATE_160K = 4, - V4L2_MPEG_AUDIO_L1_BITRATE_192K = 5, - V4L2_MPEG_AUDIO_L1_BITRATE_224K = 6, - V4L2_MPEG_AUDIO_L1_BITRATE_256K = 7, - V4L2_MPEG_AUDIO_L1_BITRATE_288K = 8, - V4L2_MPEG_AUDIO_L1_BITRATE_320K = 9, - V4L2_MPEG_AUDIO_L1_BITRATE_352K = 10, - V4L2_MPEG_AUDIO_L1_BITRATE_384K = 11, - V4L2_MPEG_AUDIO_L1_BITRATE_416K = 12, - V4L2_MPEG_AUDIO_L1_BITRATE_448K = 13, -}; -#define V4L2_CID_MPEG_AUDIO_L2_BITRATE (V4L2_CID_MPEG_BASE + 103) -enum v4l2_mpeg_audio_l2_bitrate { - V4L2_MPEG_AUDIO_L2_BITRATE_32K = 0, - V4L2_MPEG_AUDIO_L2_BITRATE_48K = 1, - V4L2_MPEG_AUDIO_L2_BITRATE_56K = 2, - V4L2_MPEG_AUDIO_L2_BITRATE_64K = 3, - V4L2_MPEG_AUDIO_L2_BITRATE_80K = 4, - V4L2_MPEG_AUDIO_L2_BITRATE_96K = 5, - V4L2_MPEG_AUDIO_L2_BITRATE_112K = 6, - V4L2_MPEG_AUDIO_L2_BITRATE_128K = 7, - V4L2_MPEG_AUDIO_L2_BITRATE_160K = 8, - V4L2_MPEG_AUDIO_L2_BITRATE_192K = 9, - V4L2_MPEG_AUDIO_L2_BITRATE_224K = 10, - V4L2_MPEG_AUDIO_L2_BITRATE_256K = 11, - V4L2_MPEG_AUDIO_L2_BITRATE_320K = 12, - V4L2_MPEG_AUDIO_L2_BITRATE_384K = 13, -}; -#define V4L2_CID_MPEG_AUDIO_L3_BITRATE (V4L2_CID_MPEG_BASE + 104) -enum v4l2_mpeg_audio_l3_bitrate { - V4L2_MPEG_AUDIO_L3_BITRATE_32K = 0, - V4L2_MPEG_AUDIO_L3_BITRATE_40K = 1, - V4L2_MPEG_AUDIO_L3_BITRATE_48K = 2, - V4L2_MPEG_AUDIO_L3_BITRATE_56K = 3, - V4L2_MPEG_AUDIO_L3_BITRATE_64K = 4, - V4L2_MPEG_AUDIO_L3_BITRATE_80K = 5, - V4L2_MPEG_AUDIO_L3_BITRATE_96K = 6, - V4L2_MPEG_AUDIO_L3_BITRATE_112K = 7, - V4L2_MPEG_AUDIO_L3_BITRATE_128K = 8, - V4L2_MPEG_AUDIO_L3_BITRATE_160K = 9, - V4L2_MPEG_AUDIO_L3_BITRATE_192K = 10, - V4L2_MPEG_AUDIO_L3_BITRATE_224K = 11, - V4L2_MPEG_AUDIO_L3_BITRATE_256K = 12, - V4L2_MPEG_AUDIO_L3_BITRATE_320K = 13, -}; -#define V4L2_CID_MPEG_AUDIO_MODE (V4L2_CID_MPEG_BASE + 105) -enum v4l2_mpeg_audio_mode { - V4L2_MPEG_AUDIO_MODE_STEREO = 0, - V4L2_MPEG_AUDIO_MODE_JOINT_STEREO = 1, - V4L2_MPEG_AUDIO_MODE_DUAL = 2, - V4L2_MPEG_AUDIO_MODE_MONO = 3, -}; -#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION (V4L2_CID_MPEG_BASE + 106) -enum v4l2_mpeg_audio_mode_extension { - V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4 = 0, - V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8 = 1, - V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12 = 2, - V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16 = 3, -}; -#define V4L2_CID_MPEG_AUDIO_EMPHASIS (V4L2_CID_MPEG_BASE + 107) -enum v4l2_mpeg_audio_emphasis { - V4L2_MPEG_AUDIO_EMPHASIS_NONE = 0, - V4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS = 1, - V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17 = 2, -}; -#define V4L2_CID_MPEG_AUDIO_CRC (V4L2_CID_MPEG_BASE + 108) -enum v4l2_mpeg_audio_crc { - V4L2_MPEG_AUDIO_CRC_NONE = 0, - V4L2_MPEG_AUDIO_CRC_CRC16 = 1, -}; -#define V4L2_CID_MPEG_AUDIO_MUTE (V4L2_CID_MPEG_BASE + 109) -#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE (V4L2_CID_MPEG_BASE + 110) -#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE (V4L2_CID_MPEG_BASE + 111) -enum v4l2_mpeg_audio_ac3_bitrate { - V4L2_MPEG_AUDIO_AC3_BITRATE_32K = 0, - V4L2_MPEG_AUDIO_AC3_BITRATE_40K = 1, - V4L2_MPEG_AUDIO_AC3_BITRATE_48K = 2, - V4L2_MPEG_AUDIO_AC3_BITRATE_56K = 3, - V4L2_MPEG_AUDIO_AC3_BITRATE_64K = 4, - V4L2_MPEG_AUDIO_AC3_BITRATE_80K = 5, - V4L2_MPEG_AUDIO_AC3_BITRATE_96K = 6, - V4L2_MPEG_AUDIO_AC3_BITRATE_112K = 7, - V4L2_MPEG_AUDIO_AC3_BITRATE_128K = 8, - V4L2_MPEG_AUDIO_AC3_BITRATE_160K = 9, - V4L2_MPEG_AUDIO_AC3_BITRATE_192K = 10, - V4L2_MPEG_AUDIO_AC3_BITRATE_224K = 11, - V4L2_MPEG_AUDIO_AC3_BITRATE_256K = 12, - V4L2_MPEG_AUDIO_AC3_BITRATE_320K = 13, - V4L2_MPEG_AUDIO_AC3_BITRATE_384K = 14, - V4L2_MPEG_AUDIO_AC3_BITRATE_448K = 15, - V4L2_MPEG_AUDIO_AC3_BITRATE_512K = 16, - V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17, - V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18, -}; -#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK (V4L2_CID_MPEG_BASE + 112) -enum v4l2_mpeg_audio_dec_playback { - V4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO = 0, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO = 1, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_LEFT = 2, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_RIGHT = 3, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO = 4, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO = 5, -}; -#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_MPEG_BASE + 113) -#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE + 200) -enum v4l2_mpeg_video_encoding { - V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0, - V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1, - V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2, -}; -#define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_MPEG_BASE + 201) -enum v4l2_mpeg_video_aspect { - V4L2_MPEG_VIDEO_ASPECT_1x1 = 0, - V4L2_MPEG_VIDEO_ASPECT_4x3 = 1, - V4L2_MPEG_VIDEO_ASPECT_16x9 = 2, - V4L2_MPEG_VIDEO_ASPECT_221x100 = 3, -}; -#define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_MPEG_BASE + 202) -#define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_MPEG_BASE + 203) -#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_MPEG_BASE + 204) -#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_MPEG_BASE + 205) -#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_MPEG_BASE + 206) -enum v4l2_mpeg_video_bitrate_mode { - V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0, - V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1, -}; -#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_MPEG_BASE + 207) -#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_MPEG_BASE + 208) -#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_MPEG_BASE + 209) -#define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_MPEG_BASE + 210) -#define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_MPEG_BASE + 211) -#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (V4L2_CID_MPEG_BASE + 212) -#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER (V4L2_CID_MPEG_BASE + 213) -#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (V4L2_CID_MPEG_BASE + 214) -#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE (V4L2_CID_MPEG_BASE + 215) -#define V4L2_CID_MPEG_VIDEO_HEADER_MODE (V4L2_CID_MPEG_BASE + 216) -enum v4l2_mpeg_video_header_mode { - V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0, - V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1, - V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_I_FRAME = 2, -}; -#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_MPEG_BASE + 217) -#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_MPEG_BASE + 218) -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES (V4L2_CID_MPEG_BASE + 219) -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB (V4L2_CID_MPEG_BASE + 220) -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE (V4L2_CID_MPEG_BASE + 221) -enum v4l2_mpeg_video_multi_slice_mode { - V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE = 0, - V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB = 1, - V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2, - V4L2_MPEG_VIDEO_MULTI_SLICE_GOB = 3, -}; -#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE + 222) -#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_MPEG_BASE + 223) -#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE + 224) -#define V4L2_CID_MPEG_VIDEO_VBV_DELAY (V4L2_CID_MPEG_BASE + 225) -#define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER (V4L2_CID_MPEG_BASE + 226) -#define V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE (V4L2_CID_MPEG_BASE + 227) -#define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE (V4L2_CID_MPEG_BASE + 228) -#define V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME (V4L2_CID_MPEG_BASE + 229) -#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE + 300) -#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE + 301) -#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_MPEG_BASE + 302) -#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP (V4L2_CID_MPEG_BASE + 303) -#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP (V4L2_CID_MPEG_BASE + 304) -#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_MPEG_BASE + 350) -#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP (V4L2_CID_MPEG_BASE + 351) -#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP (V4L2_CID_MPEG_BASE + 352) -#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP (V4L2_CID_MPEG_BASE + 353) -#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_MPEG_BASE + 354) -#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (V4L2_CID_MPEG_BASE + 355) -#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE (V4L2_CID_MPEG_BASE + 356) -#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE (V4L2_CID_MPEG_BASE + 357) -enum v4l2_mpeg_video_h264_entropy_mode { - V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC = 0, - V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC = 1, -}; -#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_MPEG_BASE + 358) -#define V4L2_CID_MPEG_VIDEO_H264_LEVEL (V4L2_CID_MPEG_BASE + 359) -enum v4l2_mpeg_video_h264_level { - V4L2_MPEG_VIDEO_H264_LEVEL_1_0 = 0, - V4L2_MPEG_VIDEO_H264_LEVEL_1B = 1, - V4L2_MPEG_VIDEO_H264_LEVEL_1_1 = 2, - V4L2_MPEG_VIDEO_H264_LEVEL_1_2 = 3, - V4L2_MPEG_VIDEO_H264_LEVEL_1_3 = 4, - V4L2_MPEG_VIDEO_H264_LEVEL_2_0 = 5, - V4L2_MPEG_VIDEO_H264_LEVEL_2_1 = 6, - V4L2_MPEG_VIDEO_H264_LEVEL_2_2 = 7, - V4L2_MPEG_VIDEO_H264_LEVEL_3_0 = 8, - V4L2_MPEG_VIDEO_H264_LEVEL_3_1 = 9, - V4L2_MPEG_VIDEO_H264_LEVEL_3_2 = 10, - V4L2_MPEG_VIDEO_H264_LEVEL_4_0 = 11, - V4L2_MPEG_VIDEO_H264_LEVEL_4_1 = 12, - V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13, - V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14, - V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15, - V4L2_MPEG_VIDEO_H264_LEVEL_5_2 = 16, -#define V4L2_MPEG_VIDEO_H264_LEVEL_UNKNOWN V4L2_MPEG_VIDEO_H264_LEVEL_UNKNOWN - V4L2_MPEG_VIDEO_H264_LEVEL_UNKNOWN = 17, -}; -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE + 360) -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_MPEG_BASE + 361) -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE (V4L2_CID_MPEG_BASE + 362) -enum v4l2_mpeg_video_h264_loop_filter_mode { - V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED = 0, - V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED = 1, - V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY = 2, -}; -#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_MPEG_BASE + 363) -enum v4l2_mpeg_video_h264_profile { - V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE = 0, - V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE = 1, - V4L2_MPEG_VIDEO_H264_PROFILE_MAIN = 2, - V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED = 3, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH = 4, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10 = 5, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422 = 6, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE = 7, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10_INTRA = 8, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422_INTRA = 9, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_INTRA = 10, - V4L2_MPEG_VIDEO_H264_PROFILE_CAVLC_444_INTRA = 11, - V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_BASELINE = 12, - V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH = 13, - V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14, - V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15, - V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16, - V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH = 17, -}; -#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE + 364) -#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE + 365) -#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (V4L2_CID_MPEG_BASE + 366) -#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC (V4L2_CID_MPEG_BASE + 367) -enum v4l2_mpeg_video_h264_vui_sar_idc { - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED = 0, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 = 1, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 = 2, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 = 3, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 = 4, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 = 5, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 = 6, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 = 7, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 = 8, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 = 9, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 = 10, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 = 11, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 = 12, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 = 13, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 = 14, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 = 15, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 = 16, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED = 17, -}; -#define V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING (V4L2_CID_MPEG_BASE + 368) -#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0 (V4L2_CID_MPEG_BASE + 369) -#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE (V4L2_CID_MPEG_BASE + 370) -enum v4l2_mpeg_video_h264_sei_fp_arrangement_type { - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_CHECKERBOARD = 0, - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_COLUMN = 1, - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_ROW = 2, - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE = 3, - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TOP_BOTTOM = 4, - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TEMPORAL = 5, -}; -#define V4L2_CID_MPEG_VIDEO_H264_FMO (V4L2_CID_MPEG_BASE + 371) -#define V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE (V4L2_CID_MPEG_BASE + 372) -enum v4l2_mpeg_video_h264_fmo_map_type { - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES = 0, - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES = 1, - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_FOREGROUND_WITH_LEFT_OVER = 2, - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_BOX_OUT = 3, - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN = 4, - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN = 5, - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_EXPLICIT = 6, -}; -#define V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP (V4L2_CID_MPEG_BASE + 373) -#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION (V4L2_CID_MPEG_BASE + 374) -enum v4l2_mpeg_video_h264_fmo_change_dir { - V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT = 0, - V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_LEFT = 1, -}; -#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE (V4L2_CID_MPEG_BASE + 375) -#define V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH (V4L2_CID_MPEG_BASE + 376) -#define V4L2_CID_MPEG_VIDEO_H264_ASO (V4L2_CID_MPEG_BASE + 377) -#define V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER (V4L2_CID_MPEG_BASE + 378) -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING (V4L2_CID_MPEG_BASE + 379) -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE (V4L2_CID_MPEG_BASE + 380) -enum v4l2_mpeg_video_h264_hierarchical_coding_type { - V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B = 0, - V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P = 1, -}; -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER (V4L2_CID_MPEG_BASE + 381) -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_MPEG_BASE + 382) -#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE + 400) -#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE + 401) -#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE + 402) -#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_MPEG_BASE + 403) -#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_MPEG_BASE + 404) -#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_MPEG_BASE + 405) -enum v4l2_mpeg_video_mpeg4_level { - V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 = 0, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 = 2, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 = 3, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 = 4, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B = 5, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 = 6, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 = 7, -}; -#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_MPEG_BASE + 406) -enum v4l2_mpeg_video_mpeg4_profile { - V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE = 0, - V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE = 1, - V4L2_MPEG_VIDEO_MPEG4_PROFILE_CORE = 2, - V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE = 3, - V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY = 4, -}; -#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_MPEG_BASE + 407) -#define V4L2_CID_MPEG_VIDEO_VPX_NUM_PARTITIONS (V4L2_CID_MPEG_BASE + 500) -enum v4l2_vp8_num_partitions { - V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION = 0, - V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS = 1, - V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS = 2, - V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS = 3, -}; -#define V4L2_CID_MPEG_VIDEO_VPX_IMD_DISABLE_4X4 (V4L2_CID_MPEG_BASE + 501) -#define V4L2_CID_MPEG_VIDEO_VPX_NUM_REF_FRAMES (V4L2_CID_MPEG_BASE + 502) -enum v4l2_vp8_num_ref_frames { - V4L2_CID_MPEG_VIDEO_VPX_1_REF_FRAME = 0, - V4L2_CID_MPEG_VIDEO_VPX_2_REF_FRAME = 1, - V4L2_CID_MPEG_VIDEO_VPX_3_REF_FRAME = 2, -}; -#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_LEVEL (V4L2_CID_MPEG_BASE + 503) -#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_SHARPNESS (V4L2_CID_MPEG_BASE + 504) -#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_REF_PERIOD (V4L2_CID_MPEG_BASE + 505) -#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_SEL (V4L2_CID_MPEG_BASE + 506) -enum v4l2_vp8_golden_frame_sel { - V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_PREV = 0, - V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_REF_PERIOD = 1, -}; -#define V4L2_CID_MPEG_VIDEO_VPX_MIN_QP (V4L2_CID_MPEG_BASE + 507) -#define V4L2_CID_MPEG_VIDEO_VPX_MAX_QP (V4L2_CID_MPEG_BASE + 508) -#define V4L2_CID_MPEG_VIDEO_VPX_I_FRAME_QP (V4L2_CID_MPEG_BASE + 509) -#define V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP (V4L2_CID_MPEG_BASE + 510) -#define V4L2_CID_MPEG_VIDEO_VPX_PROFILE (V4L2_CID_MPEG_BASE + 511) -#define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000) -#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE + 0) -enum v4l2_mpeg_cx2341x_video_spatial_filter_mode { - V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0, - V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO = 1, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE + 1) -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE + 2) -enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type { - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF = 0, - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT = 2, - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE = 3, - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE = 4, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE + 3) -enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type { - V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF = 0, - V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE + 4) -enum v4l2_mpeg_cx2341x_video_temporal_filter_mode { - V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL = 0, - V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE + 5) -#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE + 6) -enum v4l2_mpeg_cx2341x_video_median_filter_type { - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF = 0, - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR = 1, - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_VERT = 2, - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3, - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG = 4, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE + 7) -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE + 8) -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE + 9) -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE + 10) -#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_MPEG_CX2341X_BASE + 11) -#define V4L2_CID_MPEG_MFC51_BASE (V4L2_CTRL_CLASS_MPEG | 0x1100) -#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (V4L2_CID_MPEG_MFC51_BASE + 0) -#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE (V4L2_CID_MPEG_MFC51_BASE + 1) -#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE (V4L2_CID_MPEG_MFC51_BASE + 2) -enum v4l2_mpeg_mfc51_video_frame_skip_mode { - V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED = 0, - V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT = 1, - V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT = 2, -}; -#define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE (V4L2_CID_MPEG_MFC51_BASE + 3) -enum v4l2_mpeg_mfc51_video_force_frame_type { - V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED = 0, - V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_I_FRAME = 1, - V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED = 2, -}; -#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING (V4L2_CID_MPEG_MFC51_BASE + 4) -#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV (V4L2_CID_MPEG_MFC51_BASE + 5) -#define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT (V4L2_CID_MPEG_MFC51_BASE + 6) -#define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF (V4L2_CID_MPEG_MFC51_BASE + 7) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY (V4L2_CID_MPEG_MFC51_BASE + 50) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK (V4L2_CID_MPEG_MFC51_BASE + 51) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH (V4L2_CID_MPEG_MFC51_BASE + 52) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE + 53) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE + 54) -#define V4L2_CID_MPEG_MSM_VIDC_BASE (V4L2_CTRL_CLASS_MPEG | 0x2000) -#define V4L2_CID_MPEG_VIDC_VIDEO_PICTYPE_DEC_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 0) -enum v4l2_mpeg_vidc_video_pictype_dec_mode { - V4L2_MPEG_VIDC_VIDEO_PICTYPE_DECODE_OFF = 0, - V4L2_MPEG_VIDC_VIDEO_PICTYPE_DECODE_ON = 1, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_KEEP_ASPECT_RATIO (V4L2_CID_MPEG_MSM_VIDC_BASE + 1) -#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE + 2) -enum v4l2_mpeg_vidc_video_stream_format { - V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_STARTCODES = 0, - V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_NAL_PER_BUFFER = 1, - V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_BYTE_LENGTH = 2, - V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_TWO_BYTE_LENGTH = 3, - V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_FOUR_BYTE_LENGTH = 4, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_OUTPUT_ORDER (V4L2_CID_MPEG_MSM_VIDC_BASE + 3) -enum v4l2_mpeg_vidc_video_output_order { - V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DISPLAY = 0, - V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DECODE = 1, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_RATE (V4L2_CID_MPEG_MSM_VIDC_BASE + 4) -#define V4L2_CID_MPEG_VIDC_VIDEO_IDR_PERIOD (V4L2_CID_MPEG_MSM_VIDC_BASE + 5) -#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE + 6) -#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE + 7) -#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_IFRAME (V4L2_CID_MPEG_MSM_VIDC_BASE + 8) -#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL (V4L2_CID_MPEG_MSM_VIDC_BASE + 9) -enum v4l2_mpeg_vidc_video_rate_control { - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_OFF = 0, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_VFR = 1, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR = 2, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_VFR = 3, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_CFR = 4, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_CFR = 5, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_VFR = 6, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CQ = 7, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_CFR V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_CFR -#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_VFR V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_VFR -#define V4L2_CID_MPEG_VIDC_VIDEO_ROTATION (V4L2_CID_MPEG_MSM_VIDC_BASE + 10) -enum v4l2_mpeg_vidc_video_rotation { - V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_NONE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_90 = 1, - V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_180 = 2, - V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_270 = 3, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 11) -enum v4l2_mpeg_vidc_h264_cabac_model { - V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_0 = 0, - V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_1 = 1, - V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_2 = 2, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 12) -enum v4l2_mpeg_vidc_video_intra_refresh_mode { - V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_NONE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC = 1, - V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_RANDOM = 2, - V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_ADAPTIVE = 3, - V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC_ADAPTIVE = 4, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_IR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE + 13) -#define V4L2_CID_MPEG_VIDC_VIDEO_AU_DELIMITER (V4L2_CID_MPEG_MSM_VIDC_BASE + 14) -enum v4l2_mpeg_vidc_video_au_delimiter { - V4L2_MPEG_VIDC_VIDEO_AU_DELIMITER_DISABLED = 0, - V4L2_MPEG_VIDC_VIDEO_AU_DELIMITER_ENABLED = 1 -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 15) -enum v4l2_mpeg_vidc_video_sync_frame_decode { - V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_DISABLE = 0, - V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_ENABLE = 1 -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE (V4L2_CID_MPEG_MSM_VIDC_BASE + 16) -#define V4L2_CID_MPEG_VIDC_VIDEO_EXTRADATA (V4L2_CID_MPEG_MSM_VIDC_BASE + 17) -enum v4l2_mpeg_vidc_extradata { - V4L2_MPEG_VIDC_EXTRADATA_NONE = 0, - V4L2_MPEG_VIDC_EXTRADATA_MB_QUANTIZATION = 1, - V4L2_MPEG_VIDC_EXTRADATA_INTERLACE_VIDEO = 2, - V4L2_MPEG_VIDC_EXTRADATA_VC1_FRAMEDISP = 3, - V4L2_MPEG_VIDC_EXTRADATA_VC1_SEQDISP = 4, - V4L2_MPEG_VIDC_EXTRADATA_TIMESTAMP = 5, - V4L2_MPEG_VIDC_EXTRADATA_S3D_FRAME_PACKING = 6, - V4L2_MPEG_VIDC_EXTRADATA_FRAME_RATE = 7, - V4L2_MPEG_VIDC_EXTRADATA_PANSCAN_WINDOW = 8, - V4L2_MPEG_VIDC_EXTRADATA_RECOVERY_POINT_SEI = 9, - V4L2_MPEG_VIDC_EXTRADATA_MULTISLICE_INFO = 10, - V4L2_MPEG_VIDC_EXTRADATA_NUM_CONCEALED_MB = 11, - V4L2_MPEG_VIDC_EXTRADATA_METADATA_FILLER = 12, - V4L2_MPEG_VIDC_EXTRADATA_INPUT_CROP = 13, - V4L2_MPEG_VIDC_EXTRADATA_DIGITAL_ZOOM = 14, - V4L2_MPEG_VIDC_EXTRADATA_ASPECT_RATIO = 15, - V4L2_MPEG_VIDC_EXTRADATA_MPEG2_SEQDISP = 16, - V4L2_MPEG_VIDC_EXTRADATA_STREAM_USERDATA = 17, - V4L2_MPEG_VIDC_EXTRADATA_FRAME_QP = 18, - V4L2_MPEG_VIDC_EXTRADATA_FRAME_BITS_INFO = 19, - V4L2_MPEG_VIDC_EXTRADATA_LTR = 20, - V4L2_MPEG_VIDC_EXTRADATA_METADATA_MBI = 21, - V4L2_MPEG_VIDC_EXTRADATA_VQZIP_SEI = 22, - V4L2_MPEG_VIDC_EXTRADATA_YUV_STATS = 23, - V4L2_MPEG_VIDC_EXTRADATA_ROI_QP = 24, -#define V4L2_MPEG_VIDC_EXTRADATA_OUTPUT_CROP V4L2_MPEG_VIDC_EXTRADATA_OUTPUT_CROP - V4L2_MPEG_VIDC_EXTRADATA_OUTPUT_CROP = 25, -#define V4L2_MPEG_VIDC_EXTRADATA_DISPLAY_COLOUR_SEI V4L2_MPEG_VIDC_EXTRADATA_DISPLAY_COLOUR_SEI - V4L2_MPEG_VIDC_EXTRADATA_DISPLAY_COLOUR_SEI = 26, -#define V4L2_MPEG_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI V4L2_MPEG_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI - V4L2_MPEG_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI = 27, -#define V4L2_MPEG_VIDC_EXTRADATA_PQ_INFO V4L2_MPEG_VIDC_EXTRADATA_PQ_INFO - V4L2_MPEG_VIDC_EXTRADATA_PQ_INFO = 28, -#define V4L2_MPEG_VIDC_EXTRADATA_VUI_DISPLAY V4L2_MPEG_VIDC_EXTRADATA_VUI_DISPLAY - V4L2_MPEG_VIDC_EXTRADATA_VUI_DISPLAY = 29, -#define V4L2_MPEG_VIDC_EXTRADATA_VPX_COLORSPACE V4L2_MPEG_VIDC_EXTRADATA_VPX_COLORSPACE - V4L2_MPEG_VIDC_EXTRADATA_VPX_COLORSPACE = 30, -#define V4L2_MPEG_VIDC_EXTRADATA_UBWC_CR_STATS_INFO V4L2_MPEG_VIDC_EXTRADATA_UBWC_CR_STATS_INFO - V4L2_MPEG_VIDC_EXTRADATA_UBWC_CR_STATS_INFO = 31, -#define V4L2_MPEG_VIDC_EXTRADATA_ENC_FRAME_QP V4L2_MPEG_VIDC_EXTRADATA_ENC_FRAME_QP - V4L2_MPEG_VIDC_EXTRADATA_ENC_FRAME_QP = 32, -}; -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_DELIVERY_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 18) -#define V4L2_CID_MPEG_VIDC_VIDEO_VUI_TIMING_INFO (V4L2_CID_MPEG_MSM_VIDC_BASE + 19) -enum v4l2_mpeg_vidc_video_vui_timing_info { - V4L2_MPEG_VIDC_VIDEO_VUI_TIMING_INFO_DISABLED = 0, - V4L2_MPEG_VIDC_VIDEO_VUI_TIMING_INFO_ENABLED = 1 -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_PROFILE_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 20) -enum v4l2_mpeg_vidc_video_vp8_profile_level { - V4L2_MPEG_VIDC_VIDEO_VP8_UNUSED, - V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_0, - V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_1, - V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_2, - V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_3, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY (V4L2_CID_MPEG_MSM_VIDC_BASE + 21) -enum v4l2_mpeg_vidc_video_preserve_text_quality { - V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_DISABLED = 0, - V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_ENABLED = 1 -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 22) -enum v4l2_mpeg_vidc_video_decoder_multi_stream { - V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_PRIMARY = 0, - V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_SECONDARY = 1, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 23) -enum v4l2_mpeg_vidc_video_mpeg2_level { - V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_0 = 0, - V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_1 = 1, - V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_2 = 2, - V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_3 = 3, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE + 24) -enum v4l2_mpeg_vidc_video_mpeg2_profile { - V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SIMPLE = 0, - V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_MAIN = 1, - V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_422 = 2, - V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SNR_SCALABLE = 3, - V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SPATIAL_SCALABLE = 4, - V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_HIGH = 5, -}; -enum v4l2_mpeg_vidc_video_mvc_layout { - V4L2_MPEG_VIDC_VIDEO_MVC_SEQUENTIAL = 0, - V4L2_MPEG_VIDC_VIDEO_MVC_TOP_BOTTOM = 1 -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_CONCEAL_COLOR (V4L2_CID_MPEG_MSM_VIDC_BASE + 25) -#define V4L2_CID_MPEG_VIDC_VIDEO_LTRMODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 26) -enum v4l2_mpeg_vidc_video_ltrmode { - V4L2_MPEG_VIDC_VIDEO_LTR_MODE_DISABLE = 0, - V4L2_MPEG_VIDC_VIDEO_LTR_MODE_MANUAL = 1, - V4L2_MPEG_VIDC_VIDEO_LTR_MODE_PERIODIC = 2 -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_LTRCOUNT (V4L2_CID_MPEG_MSM_VIDC_BASE + 27) -#define V4L2_CID_MPEG_VIDC_VIDEO_USELTRFRAME (V4L2_CID_MPEG_MSM_VIDC_BASE + 28) -#define V4L2_CID_MPEG_VIDC_VIDEO_MARKLTRFRAME (V4L2_CID_MPEG_MSM_VIDC_BASE + 29) -#define V4L2_CID_MPEG_VIDC_VIDEO_HIER_P_NUM_LAYERS (V4L2_CID_MPEG_MSM_VIDC_BASE + 30) -#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_OUTPUT (V4L2_CID_MPEG_MSM_VIDC_BASE + 31) -enum v4l2_mpeg_vidc_video_alloc_mode_type { - V4L2_MPEG_VIDC_VIDEO_STATIC = 0, - V4L2_MPEG_VIDC_VIDEO_RING = 1, - V4L2_MPEG_VIDC_VIDEO_DYNAMIC = 2, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_X_RANGE (V4L2_CID_MPEG_MSM_VIDC_BASE + 32) -#define V4L2_CID_MPEG_VIDC_VIDEO_PFRAME_X_RANGE (V4L2_CID_MPEG_MSM_VIDC_BASE + 33) -#define V4L2_CID_MPEG_VIDC_VIDEO_BFRAME_X_RANGE (V4L2_CID_MPEG_MSM_VIDC_BASE + 34) -#define V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_Y_RANGE (V4L2_CID_MPEG_MSM_VIDC_BASE + 35) -#define V4L2_CID_MPEG_VIDC_VIDEO_PFRAME_Y_RANGE (V4L2_CID_MPEG_MSM_VIDC_BASE + 36) -#define V4L2_CID_MPEG_VIDC_VIDEO_BFRAME_Y_RANGE (V4L2_CID_MPEG_MSM_VIDC_BASE + 37) -#define V4L2_CID_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE (V4L2_CID_MPEG_MSM_VIDC_BASE + 38) -#define V4L2_CID_MPEG_VIDC_VIDEO_BUFFER_SIZE_LIMIT (V4L2_CID_MPEG_MSM_VIDC_BASE + 39) -enum vl42_mpeg_vidc_video_vpx_error_resilience { - V4L2_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE_DISABLED = 0, - V4L2_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE_ENABLED = 1, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE + 40) -enum v4l2_mpeg_video_hevc_profile { - V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN = 0, - V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN10 = 1, - V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN_STILL_PIC = 2, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_TIER_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 41) -enum v4l2_mpeg_video_hevc_level { - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_1 = 0, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_1 = 1, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_2 = 2, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_2 = 3, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_2_1 = 4, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_2_1 = 5, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_3 = 6, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_3 = 7, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_3_1 = 8, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_3_1 = 9, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_4 = 10, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_4 = 11, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_4_1 = 12, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_4_1 = 13, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5 = 14, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5 = 15, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5_1 = 16, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5_1 = 17, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5_2 = 18, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5_2 = 19, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6 = 20, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6 = 21, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6_1 = 22, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6_1 = 23, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6_2 = 24, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6_2 = 25, -#define V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_UNKNOWN V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_UNKNOWN - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_UNKNOWN = 26, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_HIER_B_NUM_LAYERS (V4L2_CID_MPEG_MSM_VIDC_BASE + 42) -#define V4L2_CID_MPEG_VIDC_VIDEO_HYBRID_HIERP_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 43) -#define V4L2_CID_MPEG_VIDC_VIDEO_DPB_COLOR_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE + 44) -enum v4l2_mpeg_vidc_video_dpb_color_format { - V4L2_MPEG_VIDC_VIDEO_DPB_COLOR_FMT_NONE = 0, - V4L2_MPEG_VIDC_VIDEO_DPB_COLOR_FMT_UBWC = 1, - V4L2_MPEG_VIDC_VIDEO_DPB_COLOR_FMT_TP10_UBWC = 2 -}; -#define V4L2_CID_VIDC_QBUF_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 45) -enum v4l2_vidc_qbuf_mode { - V4L2_VIDC_QBUF_STANDARD = 0, - V4L2_VIDC_QBUF_BATCHED = 1, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_MAX_HIERP_LAYERS (V4L2_CID_MPEG_MSM_VIDC_BASE + 46) -#define V4L2_CID_MPEG_VIDC_VIDEO_BASELAYER_ID (V4L2_CID_MPEG_MSM_VIDC_BASE + 47) -#define V4L2_CID_MPEG_VIDC_VENC_PARAM_SAR_WIDTH (V4L2_CID_MPEG_MSM_VIDC_BASE + 48) -#define V4L2_CID_MPEG_VIDC_VENC_PARAM_SAR_HEIGHT (V4L2_CID_MPEG_MSM_VIDC_BASE + 49) -#define V4L2_CID_MPEG_VIDC_VIDEO_VQZIP_SEI (V4L2_CID_MPEG_MSM_VIDC_BASE + 50) -enum v4l2_mpeg_vidc_video_vqzip_sei_enable { - V4L2_CID_MPEG_VIDC_VIDEO_VQZIP_SEI_DISABLE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_VQZIP_SEI_ENABLE = 1 -}; -#define V4L2_CID_MPEG_VIDC_VENC_PARAM_LAYER_BITRATE (V4L2_CID_MPEG_MSM_VIDC_BASE + 51) -#define V4L2_CID_MPEG_VIDC_VIDEO_PRIORITY (V4L2_CID_MPEG_MSM_VIDC_BASE + 52) -enum v4l2_mpeg_vidc_video_priority { - V4L2_MPEG_VIDC_VIDEO_PRIORITY_REALTIME_ENABLE = 0, - V4L2_MPEG_VIDC_VIDEO_PRIORITY_REALTIME_DISABLE = 1, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_OPERATING_RATE (V4L2_CID_MPEG_MSM_VIDC_BASE + 53) -#define V4L2_CID_MPEG_VIDC_VIDEO_VENC_BITRATE_TYPE (V4L2_CID_MPEG_MSM_VIDC_BASE + 54) -enum v4l2_mpeg_vidc_video_venc_bitrate_type_enable { - V4L2_CID_MPEG_VIDC_VIDEO_VENC_BITRATE_DISABLE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_VENC_BITRATE_ENABLE = 1 -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_VPE_CSC (V4L2_CID_MPEG_MSM_VIDC_BASE + 55) -enum v4l2_cid_mpeg_vidc_video_vpe_csc_type_enable { - V4L2_CID_MPEG_VIDC_VIDEO_VPE_CSC_DISABLE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_VPE_CSC_ENABLE = 1 -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_LOWLATENCY_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 56) -enum v4l2_mpeg_vidc_video_lowlatency_mode { - V4L2_CID_MPEG_VIDC_VIDEO_LOWLATENCY_DISABLE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_LOWLATENCY_ENABLE = 1, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_BLUR_WIDTH (V4L2_CID_MPEG_MSM_VIDC_BASE + 57) -#define V4L2_CID_MPEG_VIDC_VIDEO_BLUR_HEIGHT (V4L2_CID_MPEG_MSM_VIDC_BASE + 58) -#define V4L2_CID_MPEG_VIDC_VIDEO_H264_TRANSFORM_8x8 (V4L2_CID_MPEG_MSM_VIDC_BASE + 59) -enum v4l2_mpeg_vidc_video_h264_transform_8x8 { - V4L2_MPEG_VIDC_VIDEO_H264_TRANSFORM_8x8_DISABLE = 0, - V4L2_MPEG_VIDC_VIDEO_H264_TRANSFORM_8x8_ENABLE = 1, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_COLOR_SPACE (V4L2_CID_MPEG_MSM_VIDC_BASE + 60) -#define V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE (V4L2_CID_MPEG_MSM_VIDC_BASE + 61) -enum v4l2_cid_mpeg_vidc_video_full_range { - V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE_DISABLE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE_ENABLE = 1, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_TRANSFER_CHARS (V4L2_CID_MPEG_MSM_VIDC_BASE + 62) -#define V4L2_CID_MPEG_VIDC_VIDEO_MATRIX_COEFFS (V4L2_CID_MPEG_MSM_VIDC_BASE + 63) -#define V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_TYPE (V4L2_CID_MPEG_MSM_VIDC_BASE + 64) -#define V4L2_CID_MPEG_VIDC_VIDEO_LAYER_ID (V4L2_CID_MPEG_MSM_VIDC_BASE + 65) -#define V4L2_CID_MPEG_VIDC_VIDEO_VP9_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE + 66) -enum v4l2_mpeg_vidc_video_vp9_profile { - V4L2_MPEG_VIDC_VIDEO_VP9_PROFILE_UNUSED = 0, - V4L2_MPEG_VIDC_VIDEO_VP9_PROFILE_P0 = 1, - V4L2_MPEG_VIDC_VIDEO_VP9_PROFILE_P2_10 = 2, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_VP9_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 67) -enum v4l2_mpeg_vidc_video_vp9_level { - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_UNUSED = 0, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_1 = 1, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_11 = 2, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_2 = 3, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_21 = 4, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_3 = 5, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_31 = 6, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_4 = 7, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_41 = 8, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_5 = 9, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_51 = 10, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_MB_ERROR_MAP_REPORTING (V4L2_CID_MPEG_MSM_VIDC_BASE + 68) -#define V4L2_CID_MPEG_VIDC_VIDEO_CONTINUE_DATA_TRANSFER (V4L2_CID_MPEG_MSM_VIDC_BASE + 69) -#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_INPUT (V4L2_CID_MPEG_MSM_VIDC_BASE + 70) -#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_ASSEMBLY (V4L2_CID_MPEG_MSM_VIDC_BASE + 71) -enum v4l2_mpeg_vidc_video_assembly { - V4L2_MPEG_VIDC_FRAME_ASSEMBLY_DISABLE = 0, - V4L2_MPEG_VIDC_FRAME_ASSEMBLY_ENABLE = 1, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_H263_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE + 72) -enum v4l2_mpeg_vidc_video_h263_profile { - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BASELINE = 0, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_H320CODING = 1, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BACKWARDCOMPATIBLE = 2, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV2 = 3, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV3 = 4, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHCOMPRESSION = 5, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERNET = 6, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERLACE = 7, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHLATENCY = 8, -}; -#define V4L2_CID_MPEG_VIDEO_MIN_QP_PACKED (V4L2_CID_MPEG_MSM_VIDC_BASE + 97) -#define V4L2_CID_MPEG_VIDEO_MAX_QP_PACKED (V4L2_CID_MPEG_MSM_VIDC_BASE + 98) -#define V4L2_CID_MPEG_VIDC_VIDEO_I_FRAME_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 99) -#define V4L2_CID_MPEG_VIDC_VIDEO_P_FRAME_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 100) -#define V4L2_CID_MPEG_VIDC_VIDEO_B_FRAME_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 101) -#define V4L2_CID_MPEG_VIDC_VIDEO_I_FRAME_QP_MIN (V4L2_CID_MPEG_MSM_VIDC_BASE + 102) -#define V4L2_CID_MPEG_VIDC_VIDEO_P_FRAME_QP_MIN (V4L2_CID_MPEG_MSM_VIDC_BASE + 103) -#define V4L2_CID_MPEG_VIDC_VIDEO_B_FRAME_QP_MIN (V4L2_CID_MPEG_MSM_VIDC_BASE + 104) -#define V4L2_CID_MPEG_VIDC_VIDEO_I_FRAME_QP_MAX (V4L2_CID_MPEG_MSM_VIDC_BASE + 105) -#define V4L2_CID_MPEG_VIDC_VIDEO_P_FRAME_QP_MAX (V4L2_CID_MPEG_MSM_VIDC_BASE + 106) -#define V4L2_CID_MPEG_VIDC_VIDEO_B_FRAME_QP_MAX (V4L2_CID_MPEG_MSM_VIDC_BASE + 107) -#define V4L2_CID_MPEG_VIDC_VIDEO_QP_MASK (V4L2_CID_MPEG_MSM_VIDC_BASE + 108) -enum v4l2_mpeg_vidc_video_venc_iframesize_type { - V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_DEFAULT, - V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_MEDIUM, - V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_HUGE, - V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_UNLIMITED, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_CONCEAL_COLOR_8BIT (V4L2_CID_MPEG_MSM_VIDC_BASE + 109) -#define V4L2_CID_MPEG_VIDC_VIDEO_CONCEAL_COLOR_10BIT (V4L2_CID_MPEG_MSM_VIDC_BASE + 110) -#define V4L2_CID_MPEG_VIDC_VIDEO_TME_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE + 111) -enum v4l2_mpeg_vidc_video_tme_profile { - V4L2_MPEG_VIDC_VIDEO_TME_PROFILE_0 = 0, - V4L2_MPEG_VIDC_VIDEO_TME_PROFILE_1 = 1, - V4L2_MPEG_VIDC_VIDEO_TME_PROFILE_2 = 2, - V4L2_MPEG_VIDC_VIDEO_TME_PROFILE_3 = 3, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_TME_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 112) -enum v4l2_mpeg_vidc_video_tme_level { - V4L2_MPEG_VIDC_VIDEO_TME_LEVEL_INTEGER = 0, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_TME_PAYLOAD_VERSION (V4L2_CID_MPEG_MSM_VIDC_BASE + 113) -#define V4L2_CID_MPEG_VIDC_VIDEO_VPE_CSC_CUSTOM_MATRIX (V4L2_CID_MPEG_MSM_VIDC_BASE + 114) -#define V4L2_CID_MPEG_VIDC_VIDEO_FLIP (V4L2_CID_MPEG_MSM_VIDC_BASE + 115) -enum v4l2_mpeg_vidc_video_flip { - V4L2_CID_MPEG_VIDC_VIDEO_FLIP_NONE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_FLIP_HORI = 1, - V4L2_CID_MPEG_VIDC_VIDEO_FLIP_VERT = 2, - V4L2_CID_MPEG_VIDC_VIDEO_FLIP_BOTH = 3, -}; -#define V4L2_MPEG_VIDC_VENC_HDR_INFO_ENABLED 1 -#define V4L2_MPEG_VIDC_VENC_HDR_INFO_DISABLED 0 -#define V4L2_CID_MPEG_VIDC_VENC_HDR_INFO (V4L2_CID_MPEG_MSM_VIDC_BASE + 116) -#define V4L2_CID_MPEG_VIDC_VENC_RGB_PRIMARY_00 (V4L2_CID_MPEG_MSM_VIDC_BASE + 117) -#define V4L2_CID_MPEG_VIDC_VENC_RGB_PRIMARY_01 (V4L2_CID_MPEG_MSM_VIDC_BASE + 118) -#define V4L2_CID_MPEG_VIDC_VENC_RGB_PRIMARY_10 (V4L2_CID_MPEG_MSM_VIDC_BASE + 119) -#define V4L2_CID_MPEG_VIDC_VENC_RGB_PRIMARY_11 (V4L2_CID_MPEG_MSM_VIDC_BASE + 120) -#define V4L2_CID_MPEG_VIDC_VENC_RGB_PRIMARY_20 (V4L2_CID_MPEG_MSM_VIDC_BASE + 121) -#define V4L2_CID_MPEG_VIDC_VENC_RGB_PRIMARY_21 (V4L2_CID_MPEG_MSM_VIDC_BASE + 122) -#define V4L2_CID_MPEG_VIDC_VENC_WHITEPOINT_X (V4L2_CID_MPEG_MSM_VIDC_BASE + 123) -#define V4L2_CID_MPEG_VIDC_VENC_WHITEPOINT_Y (V4L2_CID_MPEG_MSM_VIDC_BASE + 124) -#define V4L2_CID_MPEG_VIDC_VENC_MAX_DISP_LUM (V4L2_CID_MPEG_MSM_VIDC_BASE + 125) -#define V4L2_CID_MPEG_VIDC_VENC_MIN_DISP_LUM (V4L2_CID_MPEG_MSM_VIDC_BASE + 126) -#define V4L2_CID_MPEG_VIDC_VENC_MAX_CLL (V4L2_CID_MPEG_MSM_VIDC_BASE + 127) -#define V4L2_CID_MPEG_VIDC_VENC_MAX_FLL (V4L2_CID_MPEG_MSM_VIDC_BASE + 128) -#define V4L2_CID_MPEG_VIDC_SET_PERF_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 129) -enum v4l2_mpeg_vidc_perf_level { - V4L2_CID_MPEG_VIDC_PERF_LEVEL_NOMINAL = 0, - V4L2_CID_MPEG_VIDC_PERF_LEVEL_PERFORMANCE = 1, - V4L2_CID_MPEG_VIDC_PERF_LEVEL_TURBO = 2, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE + 130) -#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_REF (V4L2_CID_MPEG_MSM_VIDC_BASE + 131) -#define V4L2_CID_MPEG_VIDC_VIDEO_CIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE + 132) -#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO (V4L2_CID_MPEG_MSM_VIDC_BASE + 135) -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_GOB (V4L2_CID_MPEG_MSM_VIDC_BASE + 136) -#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT (V4L2_CID_MPEG_MSM_VIDC_BASE + 137) -enum v4l2_mpeg_vidc_video_h264_vui_bitstream_restrict { - V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_DISABLED = 0, - V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_ENABLED = 1 -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE (V4L2_CID_MPEG_MSM_VIDC_BASE + 138) -enum v4l2_mpeg_vidc_video_deinterlace { - V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE_DISABLED = 0, - V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE_ENABLED = 1 -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG4_TIME_RESOLUTION (V4L2_CID_MPEG_MSM_VIDC_BASE + 139) -#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_SEQ_HEADER (V4L2_CID_MPEG_MSM_VIDC_BASE + 140) -#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 141) -enum v4l2_mpeg_vidc_video_rate_control_timestamp_mode { - V4L2_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE_HONOR = 0, - V4L2_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE_IGNORE = 1, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 142) -enum vl42_mpeg_vidc_video_enable_initial_qp { - V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_IFRAME = 0x1, - V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_PFRAME = 0x2, - V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_BFRAME = 0x4, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_INITIAL_I_FRAME_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 143) -#define V4L2_CID_MPEG_VIDC_VIDEO_INITIAL_P_FRAME_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 144) -#define V4L2_CID_MPEG_VIDC_VIDEO_INITIAL_B_FRAME_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 145) -#define V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC (V4L2_CID_MPEG_MSM_VIDC_BASE + 146) -#define V4L2_CID_MPEG_VIDC_VIDEO_PERF_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 147) -enum v4l2_mpeg_vidc_video_perf_mode { - V4L2_MPEG_VIDC_VIDEO_PERF_MAX_QUALITY = 1, - V4L2_MPEG_VIDC_VIDEO_PERF_POWER_SAVE = 2 -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_MBI_STATISTICS_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 148) -#define V4L2_CID_MPEG_VIDC_VIDEO_CONFIG_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 149) -#define V4L2_CID_MPEG_VIDC_VIDEO_H264_PIC_ORDER_CNT (V4L2_CID_MPEG_MSM_VIDC_BASE + 150) -#define V4L2_CID_MPEG_VIDC_VIDEO_SCS_THRESHOLD (V4L2_CID_MPEG_MSM_VIDC_BASE + 151) -#define V4L2_CID_MPEG_VIDC_VIDEO_MVC_BUFFER_LAYOUT (V4L2_CID_MPEG_MSM_VIDC_BASE + 152) -#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE_SCALING_THRESHOLD (V4L2_CID_MPEG_MSM_VIDC_BASE + 153) -#define V4L2_CID_MPEG_VIDC_VIDEO_NON_SECURE_OUTPUT2 (V4L2_CID_MPEG_MSM_VIDC_BASE + 154) -#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_MIN_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 155) -#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_MAX_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 156) -#define V4L2_CID_MPEG_VIDC_VIDEO_H263_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 157) -enum v4l2_mpeg_vidc_video_h263_level { - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_1_0 = 0, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_2_0 = 1, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_3_0 = 2, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_0 = 3, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_5 = 4, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_5_0 = 5, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_6_0 = 6, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_7_0 = 7, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_POST_LOOP_DEBLOCKER_MODE (V4L2_CID_MPEG_MSM_VIDC_BASE + 158) -#define V4L2_CID_MPEG_VIDC_VIDEO_DIVX_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE + 159) -enum v4l2_mpeg_vidc_video_divx_format_type { - V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_4 = 0, - V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_5 = 1, - V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_6 = 2, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_QUALITY (V4L2_CID_MPEG_MSM_VIDC_BASE + 160) -#define V4L2_CID_MPEG_VIDC_IMG_GRID_DIMENSION (V4L2_CID_MPEG_MSM_VIDC_BASE + 161) -enum v4l2_mpeg_vidc_video_mbi_statistics_mode { - V4L2_CID_MPEG_VIDC_VIDEO_MBI_MODE_DEFAULT = 0, - V4L2_CID_MPEG_VIDC_VIDEO_MBI_MODE_1 = 1, - V4L2_CID_MPEG_VIDC_VIDEO_MBI_MODE_2 = 2, - V4L2_CID_MPEG_VIDC_VIDEO_MBI_MODE_3 = 3, -}; -enum vl42_mpeg_vidc_video_h264_svc_nal { - V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_DISABLED = 0, - V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_ENABLED = 1, -}; -enum v4l2_mpeg_vidc_video_h264_vui_timing_info { - V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_DISABLED = 0, - V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_ENABLED = 1 -}; -#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900) -#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1) -#define V4L2_CID_EXPOSURE_AUTO (V4L2_CID_CAMERA_CLASS_BASE + 1) -enum v4l2_exposure_auto_type { - V4L2_EXPOSURE_AUTO = 0, - V4L2_EXPOSURE_MANUAL = 1, - V4L2_EXPOSURE_SHUTTER_PRIORITY = 2, - V4L2_EXPOSURE_APERTURE_PRIORITY = 3 -}; -#define V4L2_CID_EXPOSURE_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE + 2) -#define V4L2_CID_EXPOSURE_AUTO_PRIORITY (V4L2_CID_CAMERA_CLASS_BASE + 3) -#define V4L2_CID_PAN_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE + 4) -#define V4L2_CID_TILT_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE + 5) -#define V4L2_CID_PAN_RESET (V4L2_CID_CAMERA_CLASS_BASE + 6) -#define V4L2_CID_TILT_RESET (V4L2_CID_CAMERA_CLASS_BASE + 7) -#define V4L2_CID_PAN_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE + 8) -#define V4L2_CID_TILT_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE + 9) -#define V4L2_CID_FOCUS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE + 10) -#define V4L2_CID_FOCUS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE + 11) -#define V4L2_CID_FOCUS_AUTO (V4L2_CID_CAMERA_CLASS_BASE + 12) -#define V4L2_CID_ZOOM_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE + 13) -#define V4L2_CID_ZOOM_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE + 14) -#define V4L2_CID_ZOOM_CONTINUOUS (V4L2_CID_CAMERA_CLASS_BASE + 15) -#define V4L2_CID_PRIVACY (V4L2_CID_CAMERA_CLASS_BASE + 16) -#define V4L2_CID_IRIS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE + 17) -#define V4L2_CID_IRIS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE + 18) -#define V4L2_CID_AUTO_EXPOSURE_BIAS (V4L2_CID_CAMERA_CLASS_BASE + 19) -#define V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE (V4L2_CID_CAMERA_CLASS_BASE + 20) -enum v4l2_auto_n_preset_white_balance { - V4L2_WHITE_BALANCE_MANUAL = 0, - V4L2_WHITE_BALANCE_AUTO = 1, - V4L2_WHITE_BALANCE_INCANDESCENT = 2, - V4L2_WHITE_BALANCE_FLUORESCENT = 3, - V4L2_WHITE_BALANCE_FLUORESCENT_H = 4, - V4L2_WHITE_BALANCE_HORIZON = 5, - V4L2_WHITE_BALANCE_DAYLIGHT = 6, - V4L2_WHITE_BALANCE_FLASH = 7, - V4L2_WHITE_BALANCE_CLOUDY = 8, - V4L2_WHITE_BALANCE_SHADE = 9, -}; -#define V4L2_CID_WIDE_DYNAMIC_RANGE (V4L2_CID_CAMERA_CLASS_BASE + 21) -#define V4L2_CID_IMAGE_STABILIZATION (V4L2_CID_CAMERA_CLASS_BASE + 22) -#define V4L2_CID_ISO_SENSITIVITY (V4L2_CID_CAMERA_CLASS_BASE + 23) -#define V4L2_CID_ISO_SENSITIVITY_AUTO (V4L2_CID_CAMERA_CLASS_BASE + 24) -enum v4l2_iso_sensitivity_auto_type { - V4L2_ISO_SENSITIVITY_MANUAL = 0, - V4L2_ISO_SENSITIVITY_AUTO = 1, -}; -#define V4L2_CID_EXPOSURE_METERING (V4L2_CID_CAMERA_CLASS_BASE + 25) -enum v4l2_exposure_metering { - V4L2_EXPOSURE_METERING_AVERAGE = 0, - V4L2_EXPOSURE_METERING_CENTER_WEIGHTED = 1, - V4L2_EXPOSURE_METERING_SPOT = 2, - V4L2_EXPOSURE_METERING_MATRIX = 3, -}; -#define V4L2_CID_SCENE_MODE (V4L2_CID_CAMERA_CLASS_BASE + 26) -enum v4l2_scene_mode { - V4L2_SCENE_MODE_NONE = 0, - V4L2_SCENE_MODE_BACKLIGHT = 1, - V4L2_SCENE_MODE_BEACH_SNOW = 2, - V4L2_SCENE_MODE_CANDLE_LIGHT = 3, - V4L2_SCENE_MODE_DAWN_DUSK = 4, - V4L2_SCENE_MODE_FALL_COLORS = 5, - V4L2_SCENE_MODE_FIREWORKS = 6, - V4L2_SCENE_MODE_LANDSCAPE = 7, - V4L2_SCENE_MODE_NIGHT = 8, - V4L2_SCENE_MODE_PARTY_INDOOR = 9, - V4L2_SCENE_MODE_PORTRAIT = 10, - V4L2_SCENE_MODE_SPORTS = 11, - V4L2_SCENE_MODE_SUNSET = 12, - V4L2_SCENE_MODE_TEXT = 13, -}; -#define V4L2_CID_3A_LOCK (V4L2_CID_CAMERA_CLASS_BASE + 27) -#define V4L2_LOCK_EXPOSURE (1 << 0) -#define V4L2_LOCK_WHITE_BALANCE (1 << 1) -#define V4L2_LOCK_FOCUS (1 << 2) -#define V4L2_CID_AUTO_FOCUS_START (V4L2_CID_CAMERA_CLASS_BASE + 28) -#define V4L2_CID_AUTO_FOCUS_STOP (V4L2_CID_CAMERA_CLASS_BASE + 29) -#define V4L2_CID_AUTO_FOCUS_STATUS (V4L2_CID_CAMERA_CLASS_BASE + 30) -#define V4L2_AUTO_FOCUS_STATUS_IDLE (0 << 0) -#define V4L2_AUTO_FOCUS_STATUS_BUSY (1 << 0) -#define V4L2_AUTO_FOCUS_STATUS_REACHED (1 << 1) -#define V4L2_AUTO_FOCUS_STATUS_FAILED (1 << 2) -#define V4L2_CID_AUTO_FOCUS_RANGE (V4L2_CID_CAMERA_CLASS_BASE + 31) -enum v4l2_auto_focus_range { - V4L2_AUTO_FOCUS_RANGE_AUTO = 0, - V4L2_AUTO_FOCUS_RANGE_NORMAL = 1, - V4L2_AUTO_FOCUS_RANGE_MACRO = 2, - V4L2_AUTO_FOCUS_RANGE_INFINITY = 3, -}; -#define V4L2_CID_PAN_SPEED (V4L2_CID_CAMERA_CLASS_BASE + 32) -#define V4L2_CID_TILT_SPEED (V4L2_CID_CAMERA_CLASS_BASE + 33) -#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900) -#define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1) -#define V4L2_CID_RDS_TX_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 1) -#define V4L2_CID_RDS_TX_PI (V4L2_CID_FM_TX_CLASS_BASE + 2) -#define V4L2_CID_RDS_TX_PTY (V4L2_CID_FM_TX_CLASS_BASE + 3) -#define V4L2_CID_RDS_TX_PS_NAME (V4L2_CID_FM_TX_CLASS_BASE + 5) -#define V4L2_CID_RDS_TX_RADIO_TEXT (V4L2_CID_FM_TX_CLASS_BASE + 6) -#define V4L2_CID_RDS_TX_MONO_STEREO (V4L2_CID_FM_TX_CLASS_BASE + 7) -#define V4L2_CID_RDS_TX_ARTIFICIAL_HEAD (V4L2_CID_FM_TX_CLASS_BASE + 8) -#define V4L2_CID_RDS_TX_COMPRESSED (V4L2_CID_FM_TX_CLASS_BASE + 9) -#define V4L2_CID_RDS_TX_DYNAMIC_PTY (V4L2_CID_FM_TX_CLASS_BASE + 10) -#define V4L2_CID_RDS_TX_TRAFFIC_ANNOUNCEMENT (V4L2_CID_FM_TX_CLASS_BASE + 11) -#define V4L2_CID_RDS_TX_TRAFFIC_PROGRAM (V4L2_CID_FM_TX_CLASS_BASE + 12) -#define V4L2_CID_RDS_TX_MUSIC_SPEECH (V4L2_CID_FM_TX_CLASS_BASE + 13) -#define V4L2_CID_RDS_TX_ALT_FREQS_ENABLE (V4L2_CID_FM_TX_CLASS_BASE + 14) -#define V4L2_CID_RDS_TX_ALT_FREQS (V4L2_CID_FM_TX_CLASS_BASE + 15) -#define V4L2_CID_AUDIO_LIMITER_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 64) -#define V4L2_CID_AUDIO_LIMITER_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 65) -#define V4L2_CID_AUDIO_LIMITER_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 66) -#define V4L2_CID_AUDIO_COMPRESSION_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 80) -#define V4L2_CID_AUDIO_COMPRESSION_GAIN (V4L2_CID_FM_TX_CLASS_BASE + 81) -#define V4L2_CID_AUDIO_COMPRESSION_THRESHOLD (V4L2_CID_FM_TX_CLASS_BASE + 82) -#define V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME (V4L2_CID_FM_TX_CLASS_BASE + 83) -#define V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 84) -#define V4L2_CID_PILOT_TONE_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 96) -#define V4L2_CID_PILOT_TONE_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 97) -#define V4L2_CID_PILOT_TONE_FREQUENCY (V4L2_CID_FM_TX_CLASS_BASE + 98) -#define V4L2_CID_TUNE_PREEMPHASIS (V4L2_CID_FM_TX_CLASS_BASE + 112) -enum v4l2_preemphasis { - V4L2_PREEMPHASIS_DISABLED = 0, - V4L2_PREEMPHASIS_50_uS = 1, - V4L2_PREEMPHASIS_75_uS = 2, -}; -#define V4L2_CID_TUNE_POWER_LEVEL (V4L2_CID_FM_TX_CLASS_BASE + 113) -#define V4L2_CID_TUNE_ANTENNA_CAPACITOR (V4L2_CID_FM_TX_CLASS_BASE + 114) -#define V4L2_CID_FLASH_CLASS_BASE (V4L2_CTRL_CLASS_FLASH | 0x900) -#define V4L2_CID_FLASH_CLASS (V4L2_CTRL_CLASS_FLASH | 1) -#define V4L2_CID_FLASH_LED_MODE (V4L2_CID_FLASH_CLASS_BASE + 1) -enum v4l2_flash_led_mode { - V4L2_FLASH_LED_MODE_NONE, - V4L2_FLASH_LED_MODE_FLASH, - V4L2_FLASH_LED_MODE_TORCH, -}; -#define V4L2_CID_FLASH_STROBE_SOURCE (V4L2_CID_FLASH_CLASS_BASE + 2) -enum v4l2_flash_strobe_source { - V4L2_FLASH_STROBE_SOURCE_SOFTWARE, - V4L2_FLASH_STROBE_SOURCE_EXTERNAL, -}; -#define V4L2_CID_FLASH_STROBE (V4L2_CID_FLASH_CLASS_BASE + 3) -#define V4L2_CID_FLASH_STROBE_STOP (V4L2_CID_FLASH_CLASS_BASE + 4) -#define V4L2_CID_FLASH_STROBE_STATUS (V4L2_CID_FLASH_CLASS_BASE + 5) -#define V4L2_CID_FLASH_TIMEOUT (V4L2_CID_FLASH_CLASS_BASE + 6) -#define V4L2_CID_FLASH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 7) -#define V4L2_CID_FLASH_TORCH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 8) -#define V4L2_CID_FLASH_INDICATOR_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 9) -#define V4L2_CID_FLASH_FAULT (V4L2_CID_FLASH_CLASS_BASE + 10) -#define V4L2_FLASH_FAULT_OVER_VOLTAGE (1 << 0) -#define V4L2_FLASH_FAULT_TIMEOUT (1 << 1) -#define V4L2_FLASH_FAULT_OVER_TEMPERATURE (1 << 2) -#define V4L2_FLASH_FAULT_SHORT_CIRCUIT (1 << 3) -#define V4L2_FLASH_FAULT_OVER_CURRENT (1 << 4) -#define V4L2_FLASH_FAULT_INDICATOR (1 << 5) -#define V4L2_FLASH_FAULT_UNDER_VOLTAGE (1 << 6) -#define V4L2_FLASH_FAULT_INPUT_VOLTAGE (1 << 7) -#define V4L2_FLASH_FAULT_LED_OVER_TEMPERATURE (1 << 8) -#define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11) -#define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12) -#define V4L2_CID_JPEG_CLASS_BASE (V4L2_CTRL_CLASS_JPEG | 0x900) -#define V4L2_CID_JPEG_CLASS (V4L2_CTRL_CLASS_JPEG | 1) -#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1) -enum v4l2_jpeg_chroma_subsampling { - V4L2_JPEG_CHROMA_SUBSAMPLING_444 = 0, - V4L2_JPEG_CHROMA_SUBSAMPLING_422 = 1, - V4L2_JPEG_CHROMA_SUBSAMPLING_420 = 2, - V4L2_JPEG_CHROMA_SUBSAMPLING_411 = 3, - V4L2_JPEG_CHROMA_SUBSAMPLING_410 = 4, - V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY = 5, -}; -#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2) -#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3) -#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4) -#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0) -#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1) -#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16) -#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) -#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) -#define V4L2_CID_IMAGE_SOURCE_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_SOURCE | 0x900) -#define V4L2_CID_IMAGE_SOURCE_CLASS (V4L2_CTRL_CLASS_IMAGE_SOURCE | 1) -#define V4L2_CID_VBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 1) -#define V4L2_CID_HBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 2) -#define V4L2_CID_ANALOGUE_GAIN (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 3) -#define V4L2_CID_TEST_PATTERN_RED (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 4) -#define V4L2_CID_TEST_PATTERN_GREENR (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 5) -#define V4L2_CID_TEST_PATTERN_BLUE (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 6) -#define V4L2_CID_TEST_PATTERN_GREENB (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 7) -#define V4L2_CID_IMAGE_PROC_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_PROC | 0x900) -#define V4L2_CID_IMAGE_PROC_CLASS (V4L2_CTRL_CLASS_IMAGE_PROC | 1) -#define V4L2_CID_LINK_FREQ (V4L2_CID_IMAGE_PROC_CLASS_BASE + 1) -#define V4L2_CID_PIXEL_RATE (V4L2_CID_IMAGE_PROC_CLASS_BASE + 2) -#define V4L2_CID_TEST_PATTERN (V4L2_CID_IMAGE_PROC_CLASS_BASE + 3) -#define V4L2_CID_DV_CLASS_BASE (V4L2_CTRL_CLASS_DV | 0x900) -#define V4L2_CID_DV_CLASS (V4L2_CTRL_CLASS_DV | 1) -#define V4L2_CID_DV_TX_HOTPLUG (V4L2_CID_DV_CLASS_BASE + 1) -#define V4L2_CID_DV_TX_RXSENSE (V4L2_CID_DV_CLASS_BASE + 2) -#define V4L2_CID_DV_TX_EDID_PRESENT (V4L2_CID_DV_CLASS_BASE + 3) -#define V4L2_CID_DV_TX_MODE (V4L2_CID_DV_CLASS_BASE + 4) -enum v4l2_dv_tx_mode { - V4L2_DV_TX_MODE_DVI_D = 0, - V4L2_DV_TX_MODE_HDMI = 1, -}; -#define V4L2_CID_DV_TX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 5) -enum v4l2_dv_rgb_range { - V4L2_DV_RGB_RANGE_AUTO = 0, - V4L2_DV_RGB_RANGE_LIMITED = 1, - V4L2_DV_RGB_RANGE_FULL = 2, -}; -#define V4L2_CID_DV_TX_IT_CONTENT_TYPE (V4L2_CID_DV_CLASS_BASE + 6) -enum v4l2_dv_it_content_type { - V4L2_DV_IT_CONTENT_TYPE_GRAPHICS = 0, - V4L2_DV_IT_CONTENT_TYPE_PHOTO = 1, - V4L2_DV_IT_CONTENT_TYPE_CINEMA = 2, - V4L2_DV_IT_CONTENT_TYPE_GAME = 3, - V4L2_DV_IT_CONTENT_TYPE_NO_ITC = 4, -}; -#define V4L2_CID_DV_RX_POWER_PRESENT (V4L2_CID_DV_CLASS_BASE + 100) -#define V4L2_CID_DV_RX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 101) -#define V4L2_CID_DV_RX_IT_CONTENT_TYPE (V4L2_CID_DV_CLASS_BASE + 102) -#define V4L2_CID_FM_RX_CLASS_BASE (V4L2_CTRL_CLASS_FM_RX | 0x900) -#define V4L2_CID_FM_RX_CLASS (V4L2_CTRL_CLASS_FM_RX | 1) -#define V4L2_CID_TUNE_DEEMPHASIS (V4L2_CID_FM_RX_CLASS_BASE + 1) -enum v4l2_deemphasis { - V4L2_DEEMPHASIS_DISABLED = V4L2_PREEMPHASIS_DISABLED, - V4L2_DEEMPHASIS_50_uS = V4L2_PREEMPHASIS_50_uS, - V4L2_DEEMPHASIS_75_uS = V4L2_PREEMPHASIS_75_uS, -}; -#define V4L2_CID_RDS_RECEPTION (V4L2_CID_FM_RX_CLASS_BASE + 2) -#define V4L2_CID_RDS_RX_PTY (V4L2_CID_FM_RX_CLASS_BASE + 3) -#define V4L2_CID_RDS_RX_PS_NAME (V4L2_CID_FM_RX_CLASS_BASE + 4) -#define V4L2_CID_RDS_RX_RADIO_TEXT (V4L2_CID_FM_RX_CLASS_BASE + 5) -#define V4L2_CID_RDS_RX_TRAFFIC_ANNOUNCEMENT (V4L2_CID_FM_RX_CLASS_BASE + 6) -#define V4L2_CID_RDS_RX_TRAFFIC_PROGRAM (V4L2_CID_FM_RX_CLASS_BASE + 7) -#define V4L2_CID_RDS_RX_MUSIC_SPEECH (V4L2_CID_FM_RX_CLASS_BASE + 8) -#define V4L2_CID_RF_TUNER_CLASS_BASE (V4L2_CTRL_CLASS_RF_TUNER | 0x900) -#define V4L2_CID_RF_TUNER_CLASS (V4L2_CTRL_CLASS_RF_TUNER | 1) -#define V4L2_CID_RF_TUNER_BANDWIDTH_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 11) -#define V4L2_CID_RF_TUNER_BANDWIDTH (V4L2_CID_RF_TUNER_CLASS_BASE + 12) -#define V4L2_CID_RF_TUNER_RF_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 32) -#define V4L2_CID_RF_TUNER_LNA_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 41) -#define V4L2_CID_RF_TUNER_LNA_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 42) -#define V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 51) -#define V4L2_CID_RF_TUNER_MIXER_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 52) -#define V4L2_CID_RF_TUNER_IF_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 61) -#define V4L2_CID_RF_TUNER_IF_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 62) -#define V4L2_CID_RF_TUNER_PLL_LOCK (V4L2_CID_RF_TUNER_CLASS_BASE + 91) -#define V4L2_CID_DETECT_CLASS_BASE (V4L2_CTRL_CLASS_DETECT | 0x900) -#define V4L2_CID_DETECT_CLASS (V4L2_CTRL_CLASS_DETECT | 1) -#define V4L2_CID_DETECT_MD_MODE (V4L2_CID_DETECT_CLASS_BASE + 1) -enum v4l2_detect_md_mode { - V4L2_DETECT_MD_MODE_DISABLED = 0, - V4L2_DETECT_MD_MODE_GLOBAL = 1, - V4L2_DETECT_MD_MODE_THRESHOLD_GRID = 2, - V4L2_DETECT_MD_MODE_REGION_GRID = 3, -}; -#define V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD (V4L2_CID_DETECT_CLASS_BASE + 2) -#define V4L2_CID_DETECT_MD_THRESHOLD_GRID (V4L2_CID_DETECT_CLASS_BASE + 3) -#define V4L2_CID_DETECT_MD_REGION_GRID (V4L2_CID_DETECT_CLASS_BASE + 4) -#endif - diff --git a/sdm710/kernel-headers/linux/videodev2.h b/sdm710/kernel-headers/linux/videodev2.h deleted file mode 100644 index 6784b287..00000000 --- a/sdm710/kernel-headers/linux/videodev2.h +++ /dev/null @@ -1,1400 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __LINUX_VIDEODEV2_H -#define __LINUX_VIDEODEV2_H -#include <sys/time.h> -#include <linux/ioctl.h> -#include <linux/types.h> -#include <linux/v4l2-common.h> -#include <linux/v4l2-controls.h> -#define VIDEO_MAX_FRAME 64 -#define VIDEO_MAX_PLANES 8 -#define v4l2_fourcc(a,b,c,d) ((__u32) (a) | ((__u32) (b) << 8) | ((__u32) (c) << 16) | ((__u32) (d) << 24)) -#define v4l2_fourcc_be(a,b,c,d) (v4l2_fourcc(a, b, c, d) | (1 << 31)) -enum v4l2_field { - V4L2_FIELD_ANY = 0, - V4L2_FIELD_NONE = 1, - V4L2_FIELD_TOP = 2, - V4L2_FIELD_BOTTOM = 3, - V4L2_FIELD_INTERLACED = 4, - V4L2_FIELD_SEQ_TB = 5, - V4L2_FIELD_SEQ_BT = 6, - V4L2_FIELD_ALTERNATE = 7, - V4L2_FIELD_INTERLACED_TB = 8, - V4L2_FIELD_INTERLACED_BT = 9, -}; -#define V4L2_FIELD_HAS_TOP(field) ((field) == V4L2_FIELD_TOP || (field) == V4L2_FIELD_INTERLACED || (field) == V4L2_FIELD_INTERLACED_TB || (field) == V4L2_FIELD_INTERLACED_BT || (field) == V4L2_FIELD_SEQ_TB || (field) == V4L2_FIELD_SEQ_BT) -#define V4L2_FIELD_HAS_BOTTOM(field) ((field) == V4L2_FIELD_BOTTOM || (field) == V4L2_FIELD_INTERLACED || (field) == V4L2_FIELD_INTERLACED_TB || (field) == V4L2_FIELD_INTERLACED_BT || (field) == V4L2_FIELD_SEQ_TB || (field) == V4L2_FIELD_SEQ_BT) -#define V4L2_FIELD_HAS_BOTH(field) ((field) == V4L2_FIELD_INTERLACED || (field) == V4L2_FIELD_INTERLACED_TB || (field) == V4L2_FIELD_INTERLACED_BT || (field) == V4L2_FIELD_SEQ_TB || (field) == V4L2_FIELD_SEQ_BT) -#define V4L2_FIELD_HAS_T_OR_B(field) ((field) == V4L2_FIELD_BOTTOM || (field) == V4L2_FIELD_TOP || (field) == V4L2_FIELD_ALTERNATE) -enum v4l2_buf_type { - V4L2_BUF_TYPE_VIDEO_CAPTURE = 1, - V4L2_BUF_TYPE_VIDEO_OUTPUT = 2, - V4L2_BUF_TYPE_VIDEO_OVERLAY = 3, - V4L2_BUF_TYPE_VBI_CAPTURE = 4, - V4L2_BUF_TYPE_VBI_OUTPUT = 5, - V4L2_BUF_TYPE_SLICED_VBI_CAPTURE = 6, - V4L2_BUF_TYPE_SLICED_VBI_OUTPUT = 7, - V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY = 8, - V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE = 9, - V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE = 10, - V4L2_BUF_TYPE_SDR_CAPTURE = 11, - V4L2_BUF_TYPE_SDR_OUTPUT = 12, - V4L2_BUF_TYPE_PRIVATE = 0x80, -}; -#define V4L2_TYPE_IS_MULTIPLANAR(type) ((type) == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) -#define V4L2_TYPE_IS_OUTPUT(type) ((type) == V4L2_BUF_TYPE_VIDEO_OUTPUT || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || (type) == V4L2_BUF_TYPE_VIDEO_OVERLAY || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY || (type) == V4L2_BUF_TYPE_VBI_OUTPUT || (type) == V4L2_BUF_TYPE_SLICED_VBI_OUTPUT || (type) == V4L2_BUF_TYPE_SDR_OUTPUT) -enum v4l2_tuner_type { - V4L2_TUNER_RADIO = 1, - V4L2_TUNER_ANALOG_TV = 2, - V4L2_TUNER_DIGITAL_TV = 3, - V4L2_TUNER_SDR = 4, - V4L2_TUNER_RF = 5, -}; -#define V4L2_TUNER_ADC V4L2_TUNER_SDR -enum v4l2_memory { - V4L2_MEMORY_MMAP = 1, - V4L2_MEMORY_USERPTR = 2, - V4L2_MEMORY_OVERLAY = 3, - V4L2_MEMORY_DMABUF = 4, -}; -enum v4l2_colorspace { - V4L2_COLORSPACE_DEFAULT = 0, - V4L2_COLORSPACE_SMPTE170M = 1, - V4L2_COLORSPACE_SMPTE240M = 2, - V4L2_COLORSPACE_REC709 = 3, - V4L2_COLORSPACE_BT878 = 4, - V4L2_COLORSPACE_470_SYSTEM_M = 5, - V4L2_COLORSPACE_470_SYSTEM_BG = 6, - V4L2_COLORSPACE_JPEG = 7, - V4L2_COLORSPACE_SRGB = 8, - V4L2_COLORSPACE_ADOBERGB = 9, - V4L2_COLORSPACE_BT2020 = 10, - V4L2_COLORSPACE_RAW = 11, - V4L2_COLORSPACE_DCI_P3 = 12, -}; -#define V4L2_MAP_COLORSPACE_DEFAULT(is_sdtv,is_hdtv) ((is_sdtv) ? V4L2_COLORSPACE_SMPTE170M : ((is_hdtv) ? V4L2_COLORSPACE_REC709 : V4L2_COLORSPACE_SRGB)) -enum v4l2_xfer_func { - V4L2_XFER_FUNC_DEFAULT = 0, - V4L2_XFER_FUNC_709 = 1, - V4L2_XFER_FUNC_SRGB = 2, - V4L2_XFER_FUNC_ADOBERGB = 3, - V4L2_XFER_FUNC_SMPTE240M = 4, - V4L2_XFER_FUNC_NONE = 5, - V4L2_XFER_FUNC_DCI_P3 = 6, - V4L2_XFER_FUNC_SMPTE2084 = 7, -}; -#define V4L2_MAP_XFER_FUNC_DEFAULT(colsp) ((colsp) == V4L2_COLORSPACE_ADOBERGB ? V4L2_XFER_FUNC_ADOBERGB : ((colsp) == V4L2_COLORSPACE_SMPTE240M ? V4L2_XFER_FUNC_SMPTE240M : ((colsp) == V4L2_COLORSPACE_DCI_P3 ? V4L2_XFER_FUNC_DCI_P3 : ((colsp) == V4L2_COLORSPACE_RAW ? V4L2_XFER_FUNC_NONE : ((colsp) == V4L2_COLORSPACE_SRGB || (colsp) == V4L2_COLORSPACE_JPEG ? V4L2_XFER_FUNC_SRGB : V4L2_XFER_FUNC_709))))) -enum v4l2_ycbcr_encoding { - V4L2_YCBCR_ENC_DEFAULT = 0, - V4L2_YCBCR_ENC_601 = 1, - V4L2_YCBCR_ENC_709 = 2, - V4L2_YCBCR_ENC_XV601 = 3, - V4L2_YCBCR_ENC_XV709 = 4, - V4L2_YCBCR_ENC_SYCC = 5, - V4L2_YCBCR_ENC_BT2020 = 6, - V4L2_YCBCR_ENC_BT2020_CONST_LUM = 7, - V4L2_YCBCR_ENC_SMPTE240M = 8, -}; -#define V4L2_MAP_YCBCR_ENC_DEFAULT(colsp) (((colsp) == V4L2_COLORSPACE_REC709 || (colsp) == V4L2_COLORSPACE_DCI_P3) ? V4L2_YCBCR_ENC_709 : ((colsp) == V4L2_COLORSPACE_BT2020 ? V4L2_YCBCR_ENC_BT2020 : ((colsp) == V4L2_COLORSPACE_SMPTE240M ? V4L2_YCBCR_ENC_SMPTE240M : V4L2_YCBCR_ENC_601))) -enum v4l2_quantization { - V4L2_QUANTIZATION_DEFAULT = 0, - V4L2_QUANTIZATION_FULL_RANGE = 1, - V4L2_QUANTIZATION_LIM_RANGE = 2, -}; -#define V4L2_MAP_QUANTIZATION_DEFAULT(is_rgb,colsp,ycbcr_enc) (((is_rgb) && (colsp) == V4L2_COLORSPACE_BT2020) ? V4L2_QUANTIZATION_LIM_RANGE : (((is_rgb) || (ycbcr_enc) == V4L2_YCBCR_ENC_XV601 || (ycbcr_enc) == V4L2_YCBCR_ENC_XV709 || (colsp) == V4L2_COLORSPACE_JPEG) ? V4L2_QUANTIZATION_FULL_RANGE : V4L2_QUANTIZATION_LIM_RANGE)) -enum v4l2_priority { - V4L2_PRIORITY_UNSET = 0, - V4L2_PRIORITY_BACKGROUND = 1, - V4L2_PRIORITY_INTERACTIVE = 2, - V4L2_PRIORITY_RECORD = 3, - V4L2_PRIORITY_DEFAULT = V4L2_PRIORITY_INTERACTIVE, -}; -struct v4l2_rect { - __s32 left; - __s32 top; - __u32 width; - __u32 height; -}; -struct v4l2_fract { - __u32 numerator; - __u32 denominator; -}; -struct v4l2_capability { - __u8 driver[16]; - __u8 card[32]; - __u8 bus_info[32]; - __u32 version; - __u32 capabilities; - __u32 device_caps; - __u32 reserved[3]; -}; -#define V4L2_CAP_VIDEO_CAPTURE 0x00000001 -#define V4L2_CAP_VIDEO_OUTPUT 0x00000002 -#define V4L2_CAP_VIDEO_OVERLAY 0x00000004 -#define V4L2_CAP_VBI_CAPTURE 0x00000010 -#define V4L2_CAP_VBI_OUTPUT 0x00000020 -#define V4L2_CAP_SLICED_VBI_CAPTURE 0x00000040 -#define V4L2_CAP_SLICED_VBI_OUTPUT 0x00000080 -#define V4L2_CAP_RDS_CAPTURE 0x00000100 -#define V4L2_CAP_VIDEO_OUTPUT_OVERLAY 0x00000200 -#define V4L2_CAP_HW_FREQ_SEEK 0x00000400 -#define V4L2_CAP_RDS_OUTPUT 0x00000800 -#define V4L2_CAP_VIDEO_CAPTURE_MPLANE 0x00001000 -#define V4L2_CAP_VIDEO_OUTPUT_MPLANE 0x00002000 -#define V4L2_CAP_VIDEO_M2M_MPLANE 0x00004000 -#define V4L2_CAP_VIDEO_M2M 0x00008000 -#define V4L2_CAP_TUNER 0x00010000 -#define V4L2_CAP_AUDIO 0x00020000 -#define V4L2_CAP_RADIO 0x00040000 -#define V4L2_CAP_MODULATOR 0x00080000 -#define V4L2_CAP_SDR_CAPTURE 0x00100000 -#define V4L2_CAP_EXT_PIX_FORMAT 0x00200000 -#define V4L2_CAP_SDR_OUTPUT 0x00400000 -#define V4L2_CAP_READWRITE 0x01000000 -#define V4L2_CAP_ASYNCIO 0x02000000 -#define V4L2_CAP_STREAMING 0x04000000 -#define V4L2_CAP_TOUCH 0x10000000 -#define V4L2_CAP_DEVICE_CAPS 0x80000000 -struct v4l2_pix_format { - __u32 width; - __u32 height; - __u32 pixelformat; - __u32 field; - __u32 bytesperline; - __u32 sizeimage; - __u32 colorspace; - __u32 priv; - __u32 flags; - __u32 ycbcr_enc; - __u32 quantization; - __u32 xfer_func; -}; -#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1') -#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4') -#define V4L2_PIX_FMT_ARGB444 v4l2_fourcc('A', 'R', '1', '2') -#define V4L2_PIX_FMT_XRGB444 v4l2_fourcc('X', 'R', '1', '2') -#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O') -#define V4L2_PIX_FMT_ARGB555 v4l2_fourcc('A', 'R', '1', '5') -#define V4L2_PIX_FMT_XRGB555 v4l2_fourcc('X', 'R', '1', '5') -#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R', 'G', 'B', 'P') -#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') -#define V4L2_PIX_FMT_ARGB555X v4l2_fourcc_be('A', 'R', '1', '5') -#define V4L2_PIX_FMT_XRGB555X v4l2_fourcc_be('X', 'R', '1', '5') -#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') -#define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H') -#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') -#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') -#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') -#define V4L2_PIX_FMT_ABGR32 v4l2_fourcc('A', 'R', '2', '4') -#define V4L2_PIX_FMT_XBGR32 v4l2_fourcc('X', 'R', '2', '4') -#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') -#define V4L2_PIX_FMT_ARGB32 v4l2_fourcc('B', 'A', '2', '4') -#define V4L2_PIX_FMT_XRGB32 v4l2_fourcc('B', 'X', '2', '4') -#define V4L2_PIX_FMT_RGBA8888_UBWC v4l2_fourcc('Q', 'R', 'G', 'B') -#define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') -#define V4L2_PIX_FMT_Y4 v4l2_fourcc('Y', '0', '4', ' ') -#define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ') -#define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ') -#define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') -#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') -#define V4L2_PIX_FMT_Y16_BE v4l2_fourcc_be('Y', '1', '6', ' ') -#define V4L2_PIX_FMT_Y10BPACK v4l2_fourcc('Y', '1', '0', 'B') -#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') -#define V4L2_PIX_FMT_UV8 v4l2_fourcc('U', 'V', '8', ' ') -#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y', 'U', 'Y', 'V') -#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y', 'Y', 'U', 'V') -#define V4L2_PIX_FMT_YVYU v4l2_fourcc('Y', 'V', 'Y', 'U') -#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U', 'Y', 'V', 'Y') -#define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y') -#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P') -#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') -#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') -#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') -#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') -#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') -#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') -#define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') -#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') -#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') -#define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') -#define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') -#define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') -#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') -#define V4L2_PIX_FMT_NV12_UBWC v4l2_fourcc('Q', '1', '2', '8') -#define V4L2_PIX_FMT_NV12_TP10_UBWC v4l2_fourcc('Q', '1', '2', 'A') -#define V4L2_PIX_FMT_NV12_P010_UBWC v4l2_fourcc('Q', '1', '2', 'B') -#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') -#define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') -#define V4L2_PIX_FMT_NV16M v4l2_fourcc('N', 'M', '1', '6') -#define V4L2_PIX_FMT_NV61M v4l2_fourcc('N', 'M', '6', '1') -#define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') -#define V4L2_PIX_FMT_NV12MT_16X16 v4l2_fourcc('V', 'M', '1', '2') -#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y', 'U', 'V', '9') -#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y', 'V', 'U', '9') -#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P') -#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y', 'U', '1', '2') -#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y', 'V', '1', '2') -#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P') -#define V4L2_PIX_FMT_YUV420M v4l2_fourcc('Y', 'M', '1', '2') -#define V4L2_PIX_FMT_YVU420M v4l2_fourcc('Y', 'M', '2', '1') -#define V4L2_PIX_FMT_YUV422M v4l2_fourcc('Y', 'M', '1', '6') -#define V4L2_PIX_FMT_YVU422M v4l2_fourcc('Y', 'M', '6', '1') -#define V4L2_PIX_FMT_YUV444M v4l2_fourcc('Y', 'M', '2', '4') -#define V4L2_PIX_FMT_YVU444M v4l2_fourcc('Y', 'M', '4', '2') -#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') -#define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G', 'B', 'R', 'G') -#define V4L2_PIX_FMT_SGRBG8 v4l2_fourcc('G', 'R', 'B', 'G') -#define V4L2_PIX_FMT_SRGGB8 v4l2_fourcc('R', 'G', 'G', 'B') -#define V4L2_PIX_FMT_SBGGR10 v4l2_fourcc('B', 'G', '1', '0') -#define V4L2_PIX_FMT_SGBRG10 v4l2_fourcc('G', 'B', '1', '0') -#define V4L2_PIX_FMT_SGRBG10 v4l2_fourcc('B', 'A', '1', '0') -#define V4L2_PIX_FMT_SRGGB10 v4l2_fourcc('R', 'G', '1', '0') -#define V4L2_PIX_FMT_SBGGR10P v4l2_fourcc('p', 'B', 'A', 'A') -#define V4L2_PIX_FMT_SGBRG10P v4l2_fourcc('p', 'G', 'A', 'A') -#define V4L2_PIX_FMT_SGRBG10P v4l2_fourcc('p', 'g', 'A', 'A') -#define V4L2_PIX_FMT_SRGGB10P v4l2_fourcc('p', 'R', 'A', 'A') -#define V4L2_PIX_FMT_SBGGR10ALAW8 v4l2_fourcc('a', 'B', 'A', '8') -#define V4L2_PIX_FMT_SGBRG10ALAW8 v4l2_fourcc('a', 'G', 'A', '8') -#define V4L2_PIX_FMT_SGRBG10ALAW8 v4l2_fourcc('a', 'g', 'A', '8') -#define V4L2_PIX_FMT_SRGGB10ALAW8 v4l2_fourcc('a', 'R', 'A', '8') -#define V4L2_PIX_FMT_SBGGR10DPCM8 v4l2_fourcc('b', 'B', 'A', '8') -#define V4L2_PIX_FMT_SGBRG10DPCM8 v4l2_fourcc('b', 'G', 'A', '8') -#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0') -#define V4L2_PIX_FMT_SRGGB10DPCM8 v4l2_fourcc('b', 'R', 'A', '8') -#define V4L2_PIX_FMT_SBGGR12 v4l2_fourcc('B', 'G', '1', '2') -#define V4L2_PIX_FMT_SGBRG12 v4l2_fourcc('G', 'B', '1', '2') -#define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') -#define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') -#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') -#define V4L2_PIX_FMT_SBGGR10DPCM6 v4l2_fourcc('b', 'B', 'A', '6') -#define V4L2_PIX_FMT_SGBRG10DPCM6 v4l2_fourcc('b', 'G', 'A', '6') -#define V4L2_PIX_FMT_SGRBG10DPCM6 v4l2_fourcc('B', 'D', '1', '6') -#define V4L2_PIX_FMT_SRGGB10DPCM6 v4l2_fourcc('b', 'R', 'A', '6') -#define V4L2_PIX_FMT_SBGGRPLAIN16 v4l2_fourcc('B', 'G', '1', '6') -#define V4L2_PIX_FMT_SGBRGPLAIN16 v4l2_fourcc('G', 'B', '1', '6') -#define V4L2_PIX_FMT_SGRBGPLAIN16 v4l2_fourcc('G', 'R', '1', '6') -#define V4L2_PIX_FMT_SRGGBPLAIN16 v4l2_fourcc('R', 'G', '1', '6') -#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') -#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G') -#define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd') -#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G') -#define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') -#define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') -#define V4L2_PIX_FMT_H264_MVC v4l2_fourcc('M', '2', '6', '4') -#define V4L2_PIX_FMT_H263 v4l2_fourcc('H', '2', '6', '3') -#define V4L2_PIX_FMT_MPEG1 v4l2_fourcc('M', 'P', 'G', '1') -#define V4L2_PIX_FMT_MPEG2 v4l2_fourcc('M', 'P', 'G', '2') -#define V4L2_PIX_FMT_MPEG4 v4l2_fourcc('M', 'P', 'G', '4') -#define V4L2_PIX_FMT_XVID v4l2_fourcc('X', 'V', 'I', 'D') -#define V4L2_PIX_FMT_VC1_ANNEX_G v4l2_fourcc('V', 'C', '1', 'G') -#define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') -#define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') -#define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0') -#define V4L2_PIX_FMT_DIVX_311 v4l2_fourcc('D', 'I', 'V', '3') -#define V4L2_PIX_FMT_DIVX v4l2_fourcc('D', 'I', 'V', 'X') -#define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') -#define V4L2_PIX_FMT_HEVC_HYBRID v4l2_fourcc('H', 'V', 'C', 'H') -#define V4L2_PIX_FMT_TME v4l2_fourcc('T', 'M', 'E', '0') -#define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') -#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W', 'N', 'V', 'A') -#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S', '9', '1', '0') -#define V4L2_PIX_FMT_SN9C20X_I420 v4l2_fourcc('S', '9', '2', '0') -#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P', 'W', 'C', '1') -#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P', 'W', 'C', '2') -#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E', '6', '2', '5') -#define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S', '5', '0', '1') -#define V4L2_PIX_FMT_SPCA505 v4l2_fourcc('S', '5', '0', '5') -#define V4L2_PIX_FMT_SPCA508 v4l2_fourcc('S', '5', '0', '8') -#define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S', '5', '6', '1') -#define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P', '2', '0', '7') -#define V4L2_PIX_FMT_MR97310A v4l2_fourcc('M', '3', '1', '0') -#define V4L2_PIX_FMT_JL2005BCD v4l2_fourcc('J', 'L', '2', '0') -#define V4L2_PIX_FMT_SN9C2028 v4l2_fourcc('S', 'O', 'N', 'X') -#define V4L2_PIX_FMT_SQ905C v4l2_fourcc('9', '0', '5', 'C') -#define V4L2_PIX_FMT_PJPG v4l2_fourcc('P', 'J', 'P', 'G') -#define V4L2_PIX_FMT_OV511 v4l2_fourcc('O', '5', '1', '1') -#define V4L2_PIX_FMT_OV518 v4l2_fourcc('O', '5', '1', '8') -#define V4L2_PIX_FMT_STV0680 v4l2_fourcc('S', '6', '8', '0') -#define V4L2_PIX_FMT_TM6000 v4l2_fourcc('T', 'M', '6', '0') -#define V4L2_PIX_FMT_CIT_YYVYUY v4l2_fourcc('C', 'I', 'T', 'V') -#define V4L2_PIX_FMT_KONICA420 v4l2_fourcc('K', 'O', 'N', 'I') -#define V4L2_PIX_FMT_JPGL v4l2_fourcc('J', 'P', 'G', 'L') -#define V4L2_PIX_FMT_SE401 v4l2_fourcc('S', '4', '0', '1') -#define V4L2_PIX_FMT_S5C_UYVY_JPG v4l2_fourcc('S', '5', 'C', 'I') -#define V4L2_PIX_FMT_Y8I v4l2_fourcc('Y', '8', 'I', ' ') -#define V4L2_PIX_FMT_Y12I v4l2_fourcc('Y', '1', '2', 'I') -#define V4L2_PIX_FMT_Z16 v4l2_fourcc('Z', '1', '6', ' ') -#define V4L2_PIX_FMT_SDE_ABGR_8888 v4l2_fourcc('R', 'A', '2', '4') -#define V4L2_PIX_FMT_SDE_RGBA_8888 v4l2_fourcc('A', 'B', '2', '4') -#define V4L2_PIX_FMT_SDE_RGBX_8888 v4l2_fourcc('X', 'B', '2', '4') -#define V4L2_PIX_FMT_SDE_XBGR_8888 v4l2_fourcc('R', 'X', '2', '4') -#define V4L2_PIX_FMT_SDE_RGBA_5551 v4l2_fourcc('R', 'A', '1', '5') -#define V4L2_PIX_FMT_SDE_ABGR_1555 v4l2_fourcc('A', 'B', '1', '5') -#define V4L2_PIX_FMT_SDE_BGRA_5551 v4l2_fourcc('B', 'A', '1', '5') -#define V4L2_PIX_FMT_SDE_BGRX_5551 v4l2_fourcc('B', 'X', '1', '5') -#define V4L2_PIX_FMT_SDE_RGBX_5551 v4l2_fourcc('R', 'X', '1', '5') -#define V4L2_PIX_FMT_SDE_XBGR_1555 v4l2_fourcc('X', 'B', '1', '5') -#define V4L2_PIX_FMT_SDE_RGBA_4444 v4l2_fourcc('R', 'A', '1', '2') -#define V4L2_PIX_FMT_SDE_BGRA_4444 v4l2_fourcc('b', 'A', '1', '2') -#define V4L2_PIX_FMT_SDE_ABGR_4444 v4l2_fourcc('A', 'B', '1', '2') -#define V4L2_PIX_FMT_SDE_RGBX_4444 v4l2_fourcc('R', 'X', '1', '2') -#define V4L2_PIX_FMT_SDE_BGRX_4444 v4l2_fourcc('B', 'X', '1', '2') -#define V4L2_PIX_FMT_SDE_XBGR_4444 v4l2_fourcc('X', 'B', '1', '2') -#define V4L2_PIX_FMT_SDE_BGR_565 v4l2_fourcc('B', 'G', '1', '6') -#define V4L2_PIX_FMT_SDE_Y_CR_CB_GH2V2 v4l2_fourcc('Y', 'U', '4', '2') -#define V4L2_PIX_FMT_SDE_Y_CBCR_H1V2 v4l2_fourcc('N', 'H', '1', '6') -#define V4L2_PIX_FMT_SDE_Y_CRCB_H1V2 v4l2_fourcc('N', 'H', '6', '1') -#define V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_VENUS v4l2_fourcc('Q', 'N', 'V', '2') -#define V4L2_PIX_FMT_SDE_Y_CRCB_H2V2_VENUS v4l2_fourcc('Q', 'N', 'V', '1') -#define V4L2_PIX_FMT_SDE_RGBX_8888_UBWC v4l2_fourcc('Q', 'X', 'B', '4') -#define V4L2_PIX_FMT_SDE_RGB_565_UBWC v4l2_fourcc('Q', 'R', 'G', '6') -#define V4L2_PIX_FMT_SDE_RGBA_1010102 v4l2_fourcc('A', 'B', '3', '0') -#define V4L2_PIX_FMT_SDE_RGBX_1010102 v4l2_fourcc('X', 'B', '3', '0') -#define V4L2_PIX_FMT_SDE_ARGB_2101010 v4l2_fourcc('A', 'R', '3', '0') -#define V4L2_PIX_FMT_SDE_XRGB_2101010 v4l2_fourcc('X', 'R', '3', '0') -#define V4L2_PIX_FMT_SDE_BGRA_1010102 v4l2_fourcc('B', 'A', '3', '0') -#define V4L2_PIX_FMT_SDE_BGRX_1010102 v4l2_fourcc('B', 'X', '3', '0') -#define V4L2_PIX_FMT_SDE_ABGR_2101010 v4l2_fourcc('R', 'A', '3', '0') -#define V4L2_PIX_FMT_SDE_XBGR_2101010 v4l2_fourcc('R', 'X', '3', '0') -#define V4L2_PIX_FMT_SDE_RGBA_1010102_UBWC v4l2_fourcc('Q', 'R', 'B', 'A') -#define V4L2_PIX_FMT_SDE_RGBX_1010102_UBWC v4l2_fourcc('Q', 'X', 'B', 'A') -#define V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_TP10 v4l2_fourcc('T', 'P', '1', '0') -#define V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010 v4l2_fourcc('P', '0', '1', '0') -#define V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010_VENUS v4l2_fourcc('Q', 'P', '1', '0') -#define V4L2_SDR_FMT_CU8 v4l2_fourcc('C', 'U', '0', '8') -#define V4L2_SDR_FMT_CU16LE v4l2_fourcc('C', 'U', '1', '6') -#define V4L2_SDR_FMT_CS8 v4l2_fourcc('C', 'S', '0', '8') -#define V4L2_SDR_FMT_CS14LE v4l2_fourcc('C', 'S', '1', '4') -#define V4L2_SDR_FMT_RU12LE v4l2_fourcc('R', 'U', '1', '2') -#define V4L2_TCH_FMT_DELTA_TD16 v4l2_fourcc('T', 'D', '1', '6') -#define V4L2_TCH_FMT_DELTA_TD08 v4l2_fourcc('T', 'D', '0', '8') -#define V4L2_TCH_FMT_TU16 v4l2_fourcc('T', 'U', '1', '6') -#define V4L2_TCH_FMT_TU08 v4l2_fourcc('T', 'U', '0', '8') -#define V4L2_PIX_FMT_PRIV_MAGIC 0xfeedcafe -#define V4L2_PIX_FMT_FLAG_PREMUL_ALPHA 0x00000001 -struct v4l2_fmtdesc { - __u32 index; - __u32 type; - __u32 flags; - __u8 description[32]; - __u32 pixelformat; - __u32 reserved[4]; -}; -#define V4L2_FMT_FLAG_COMPRESSED 0x0001 -#define V4L2_FMT_FLAG_EMULATED 0x0002 -enum v4l2_frmsizetypes { - V4L2_FRMSIZE_TYPE_DISCRETE = 1, - V4L2_FRMSIZE_TYPE_CONTINUOUS = 2, - V4L2_FRMSIZE_TYPE_STEPWISE = 3, -}; -struct v4l2_frmsize_discrete { - __u32 width; - __u32 height; -}; -struct v4l2_frmsize_stepwise { - __u32 min_width; - __u32 max_width; - __u32 step_width; - __u32 min_height; - __u32 max_height; - __u32 step_height; -}; -struct v4l2_frmsizeenum { - __u32 index; - __u32 pixel_format; - __u32 type; - union { - struct v4l2_frmsize_discrete discrete; - struct v4l2_frmsize_stepwise stepwise; - }; - __u32 reserved[2]; -}; -enum v4l2_frmivaltypes { - V4L2_FRMIVAL_TYPE_DISCRETE = 1, - V4L2_FRMIVAL_TYPE_CONTINUOUS = 2, - V4L2_FRMIVAL_TYPE_STEPWISE = 3, -}; -struct v4l2_frmival_stepwise { - struct v4l2_fract min; - struct v4l2_fract max; - struct v4l2_fract step; -}; -struct v4l2_frmivalenum { - __u32 index; - __u32 pixel_format; - __u32 width; - __u32 height; - __u32 type; - union { - struct v4l2_fract discrete; - struct v4l2_frmival_stepwise stepwise; - }; - __u32 reserved[2]; -}; -struct v4l2_timecode { - __u32 type; - __u32 flags; - __u8 frames; - __u8 seconds; - __u8 minutes; - __u8 hours; - __u8 userbits[4]; -}; -#define V4L2_TC_TYPE_24FPS 1 -#define V4L2_TC_TYPE_25FPS 2 -#define V4L2_TC_TYPE_30FPS 3 -#define V4L2_TC_TYPE_50FPS 4 -#define V4L2_TC_TYPE_60FPS 5 -#define V4L2_TC_FLAG_DROPFRAME 0x0001 -#define V4L2_TC_FLAG_COLORFRAME 0x0002 -#define V4L2_TC_USERBITS_field 0x000C -#define V4L2_TC_USERBITS_USERDEFINED 0x0000 -#define V4L2_TC_USERBITS_8BITCHARS 0x0008 -struct v4l2_jpegcompression { - int quality; - int APPn; - int APP_len; - char APP_data[60]; - int COM_len; - char COM_data[60]; - __u32 jpeg_markers; -#define V4L2_JPEG_MARKER_DHT (1 << 3) -#define V4L2_JPEG_MARKER_DQT (1 << 4) -#define V4L2_JPEG_MARKER_DRI (1 << 5) -#define V4L2_JPEG_MARKER_COM (1 << 6) -#define V4L2_JPEG_MARKER_APP (1 << 7) -}; -struct v4l2_requestbuffers { - __u32 count; - __u32 type; - __u32 memory; - __u32 reserved[2]; -}; -struct v4l2_plane { - __u32 bytesused; - __u32 length; - union { - __u32 mem_offset; - unsigned long userptr; - __s32 fd; - } m; - __u32 data_offset; - __u32 reserved[11]; -}; -struct v4l2_buffer { - __u32 index; - __u32 type; - __u32 bytesused; - __u32 flags; - __u32 field; - struct timeval timestamp; - struct v4l2_timecode timecode; - __u32 sequence; - __u32 memory; - union { - __u32 offset; - unsigned long userptr; - struct v4l2_plane * planes; - __s32 fd; - } m; - __u32 length; - __u32 reserved2; - __u32 reserved; -}; -#define V4L2_BUF_FLAG_MAPPED 0x00000001 -#define V4L2_BUF_FLAG_QUEUED 0x00000002 -#define V4L2_BUF_FLAG_DONE 0x00000004 -#define V4L2_BUF_FLAG_KEYFRAME 0x00000008 -#define V4L2_BUF_FLAG_PFRAME 0x00000010 -#define V4L2_BUF_FLAG_BFRAME 0x00000020 -#define V4L2_BUF_FLAG_ERROR 0x00000040 -#define V4L2_BUF_FLAG_TIMECODE 0x00000100 -#define V4L2_BUF_FLAG_PREPARED 0x00000400 -#define V4L2_BUF_FLAG_NO_CACHE_INVALIDATE 0x00000800 -#define V4L2_BUF_FLAG_NO_CACHE_CLEAN 0x00001000 -#define V4L2_BUF_FLAG_TIMESTAMP_MASK 0x0000e000 -#define V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN 0x00000000 -#define V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC 0x00002000 -#define V4L2_BUF_FLAG_TIMESTAMP_COPY 0x00004000 -#define V4L2_BUF_FLAG_TSTAMP_SRC_MASK 0x00070000 -#define V4L2_BUF_FLAG_TSTAMP_SRC_EOF 0x00000000 -#define V4L2_BUF_FLAG_TSTAMP_SRC_SOE 0x00010000 -#define V4L2_BUF_FLAG_LAST 0x00100000 -#define V4L2_QCOM_BUF_END_OF_SUBFRAME 0x00000080 -#define V4L2_QCOM_BUF_FLAG_CODECCONFIG 0x00020000 -#define V4L2_QCOM_BUF_FLAG_EOSEQ 0x00040000 -#define V4L2_QCOM_BUF_TIMESTAMP_INVALID 0x00080000 -#define V4L2_MSM_BUF_FLAG_MBAFF 0x00000200 -#define V4L2_QCOM_BUF_FLAG_DECODEONLY 0x00200000 -#define V4L2_QCOM_BUF_DATA_CORRUPT 0x00400000 -#define V4L2_QCOM_BUF_DROP_FRAME 0x00800000 -#define V4L2_QCOM_BUF_INPUT_UNSUPPORTED 0x01000000 -#define V4L2_QCOM_BUF_FLAG_EOS 0x02000000 -#define V4L2_QCOM_BUF_FLAG_READONLY 0x04000000 -#define V4L2_MSM_VIDC_BUF_START_CODE_NOT_FOUND 0x08000000 -#define V4L2_MSM_BUF_FLAG_YUV_601_709_CLAMP 0x10000000 -#define V4L2_QCOM_BUF_FLAG_PERF_MODE 0x20000000 -#define V4L2_MSM_BUF_FLAG_DEFER 0x40000000 -#define V4L2_QCOM_BUF_FLAG_IDRFRAME 0x80000000 -struct v4l2_exportbuffer { - __u32 type; - __u32 index; - __u32 plane; - __u32 flags; - __s32 fd; - __u32 reserved[11]; -}; -struct v4l2_framebuffer { - __u32 capability; - __u32 flags; - void * base; - struct { - __u32 width; - __u32 height; - __u32 pixelformat; - __u32 field; - __u32 bytesperline; - __u32 sizeimage; - __u32 colorspace; - __u32 priv; - } fmt; -}; -#define V4L2_FBUF_CAP_EXTERNOVERLAY 0x0001 -#define V4L2_FBUF_CAP_CHROMAKEY 0x0002 -#define V4L2_FBUF_CAP_LIST_CLIPPING 0x0004 -#define V4L2_FBUF_CAP_BITMAP_CLIPPING 0x0008 -#define V4L2_FBUF_CAP_LOCAL_ALPHA 0x0010 -#define V4L2_FBUF_CAP_GLOBAL_ALPHA 0x0020 -#define V4L2_FBUF_CAP_LOCAL_INV_ALPHA 0x0040 -#define V4L2_FBUF_CAP_SRC_CHROMAKEY 0x0080 -#define V4L2_FBUF_FLAG_PRIMARY 0x0001 -#define V4L2_FBUF_FLAG_OVERLAY 0x0002 -#define V4L2_FBUF_FLAG_CHROMAKEY 0x0004 -#define V4L2_FBUF_FLAG_LOCAL_ALPHA 0x0008 -#define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010 -#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020 -#define V4L2_FBUF_FLAG_SRC_CHROMAKEY 0x0040 -struct v4l2_clip { - struct v4l2_rect c; - struct v4l2_clip * next; -}; -struct v4l2_window { - struct v4l2_rect w; - __u32 field; - __u32 chromakey; - struct v4l2_clip * clips; - __u32 clipcount; - void * bitmap; - __u8 global_alpha; -}; -struct v4l2_captureparm { - __u32 capability; - __u32 capturemode; - struct v4l2_fract timeperframe; - __u32 extendedmode; - __u32 readbuffers; - __u32 reserved[4]; -}; -#define V4L2_MODE_HIGHQUALITY 0x0001 -#define V4L2_CAP_TIMEPERFRAME 0x1000 -struct v4l2_outputparm { - __u32 capability; - __u32 outputmode; - struct v4l2_fract timeperframe; - __u32 extendedmode; - __u32 writebuffers; - __u32 reserved[4]; -}; -struct v4l2_cropcap { - __u32 type; - struct v4l2_rect bounds; - struct v4l2_rect defrect; - struct v4l2_fract pixelaspect; -}; -struct v4l2_crop { - __u32 type; - struct v4l2_rect c; -}; -struct v4l2_selection { - __u32 type; - __u32 target; - __u32 flags; - struct v4l2_rect r; - __u32 reserved[9]; -}; -typedef __u64 v4l2_std_id; -#define V4L2_STD_PAL_B ((v4l2_std_id) 0x00000001) -#define V4L2_STD_PAL_B1 ((v4l2_std_id) 0x00000002) -#define V4L2_STD_PAL_G ((v4l2_std_id) 0x00000004) -#define V4L2_STD_PAL_H ((v4l2_std_id) 0x00000008) -#define V4L2_STD_PAL_I ((v4l2_std_id) 0x00000010) -#define V4L2_STD_PAL_D ((v4l2_std_id) 0x00000020) -#define V4L2_STD_PAL_D1 ((v4l2_std_id) 0x00000040) -#define V4L2_STD_PAL_K ((v4l2_std_id) 0x00000080) -#define V4L2_STD_PAL_M ((v4l2_std_id) 0x00000100) -#define V4L2_STD_PAL_N ((v4l2_std_id) 0x00000200) -#define V4L2_STD_PAL_Nc ((v4l2_std_id) 0x00000400) -#define V4L2_STD_PAL_60 ((v4l2_std_id) 0x00000800) -#define V4L2_STD_NTSC_M ((v4l2_std_id) 0x00001000) -#define V4L2_STD_NTSC_M_JP ((v4l2_std_id) 0x00002000) -#define V4L2_STD_NTSC_443 ((v4l2_std_id) 0x00004000) -#define V4L2_STD_NTSC_M_KR ((v4l2_std_id) 0x00008000) -#define V4L2_STD_SECAM_B ((v4l2_std_id) 0x00010000) -#define V4L2_STD_SECAM_D ((v4l2_std_id) 0x00020000) -#define V4L2_STD_SECAM_G ((v4l2_std_id) 0x00040000) -#define V4L2_STD_SECAM_H ((v4l2_std_id) 0x00080000) -#define V4L2_STD_SECAM_K ((v4l2_std_id) 0x00100000) -#define V4L2_STD_SECAM_K1 ((v4l2_std_id) 0x00200000) -#define V4L2_STD_SECAM_L ((v4l2_std_id) 0x00400000) -#define V4L2_STD_SECAM_LC ((v4l2_std_id) 0x00800000) -#define V4L2_STD_ATSC_8_VSB ((v4l2_std_id) 0x01000000) -#define V4L2_STD_ATSC_16_VSB ((v4l2_std_id) 0x02000000) -#define V4L2_STD_NTSC (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_M_KR) -#define V4L2_STD_SECAM_DK (V4L2_STD_SECAM_D | V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1) -#define V4L2_STD_SECAM (V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H | V4L2_STD_SECAM_DK | V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC) -#define V4L2_STD_PAL_BG (V4L2_STD_PAL_B | V4L2_STD_PAL_B1 | V4L2_STD_PAL_G) -#define V4L2_STD_PAL_DK (V4L2_STD_PAL_D | V4L2_STD_PAL_D1 | V4L2_STD_PAL_K) -#define V4L2_STD_PAL (V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_H | V4L2_STD_PAL_I) -#define V4L2_STD_B (V4L2_STD_PAL_B | V4L2_STD_PAL_B1 | V4L2_STD_SECAM_B) -#define V4L2_STD_G (V4L2_STD_PAL_G | V4L2_STD_SECAM_G) -#define V4L2_STD_H (V4L2_STD_PAL_H | V4L2_STD_SECAM_H) -#define V4L2_STD_L (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC) -#define V4L2_STD_GH (V4L2_STD_G | V4L2_STD_H) -#define V4L2_STD_DK (V4L2_STD_PAL_DK | V4L2_STD_SECAM_DK) -#define V4L2_STD_BG (V4L2_STD_B | V4L2_STD_G) -#define V4L2_STD_MN (V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | V4L2_STD_NTSC) -#define V4L2_STD_MTS (V4L2_STD_NTSC_M | V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc) -#define V4L2_STD_525_60 (V4L2_STD_PAL_M | V4L2_STD_PAL_60 | V4L2_STD_NTSC | V4L2_STD_NTSC_443) -#define V4L2_STD_625_50 (V4L2_STD_PAL | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | V4L2_STD_SECAM) -#define V4L2_STD_ATSC (V4L2_STD_ATSC_8_VSB | V4L2_STD_ATSC_16_VSB) -#define V4L2_STD_UNKNOWN 0 -#define V4L2_STD_ALL (V4L2_STD_525_60 | V4L2_STD_625_50) -struct v4l2_standard { - __u32 index; - v4l2_std_id id; - __u8 name[24]; - struct v4l2_fract frameperiod; - __u32 framelines; - __u32 reserved[4]; -}; -struct v4l2_bt_timings { - __u32 width; - __u32 height; - __u32 interlaced; - __u32 polarities; - __u64 pixelclock; - __u32 hfrontporch; - __u32 hsync; - __u32 hbackporch; - __u32 vfrontporch; - __u32 vsync; - __u32 vbackporch; - __u32 il_vfrontporch; - __u32 il_vsync; - __u32 il_vbackporch; - __u32 standards; - __u32 flags; - __u32 reserved[14]; -} __attribute__((packed)); -#define V4L2_DV_PROGRESSIVE 0 -#define V4L2_DV_INTERLACED 1 -#define V4L2_DV_VSYNC_POS_POL 0x00000001 -#define V4L2_DV_HSYNC_POS_POL 0x00000002 -#define V4L2_DV_BT_STD_CEA861 (1 << 0) -#define V4L2_DV_BT_STD_DMT (1 << 1) -#define V4L2_DV_BT_STD_CVT (1 << 2) -#define V4L2_DV_BT_STD_GTF (1 << 3) -#define V4L2_DV_BT_STD_SDI (1 << 4) -#define V4L2_DV_FL_REDUCED_BLANKING (1 << 0) -#define V4L2_DV_FL_CAN_REDUCE_FPS (1 << 1) -#define V4L2_DV_FL_REDUCED_FPS (1 << 2) -#define V4L2_DV_FL_HALF_LINE (1 << 3) -#define V4L2_DV_FL_IS_CE_VIDEO (1 << 4) -#define V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE (1 << 5) -#define V4L2_DV_BT_BLANKING_WIDTH(bt) ((bt)->hfrontporch + (bt)->hsync + (bt)->hbackporch) -#define V4L2_DV_BT_FRAME_WIDTH(bt) ((bt)->width + V4L2_DV_BT_BLANKING_WIDTH(bt)) -#define V4L2_DV_BT_BLANKING_HEIGHT(bt) ((bt)->vfrontporch + (bt)->vsync + (bt)->vbackporch + (bt)->il_vfrontporch + (bt)->il_vsync + (bt)->il_vbackporch) -#define V4L2_DV_BT_FRAME_HEIGHT(bt) ((bt)->height + V4L2_DV_BT_BLANKING_HEIGHT(bt)) -struct v4l2_dv_timings { - __u32 type; - union { - struct v4l2_bt_timings bt; - __u32 reserved[32]; - }; -} __attribute__((packed)); -#define V4L2_DV_BT_656_1120 0 -struct v4l2_enum_dv_timings { - __u32 index; - __u32 pad; - __u32 reserved[2]; - struct v4l2_dv_timings timings; -}; -struct v4l2_bt_timings_cap { - __u32 min_width; - __u32 max_width; - __u32 min_height; - __u32 max_height; - __u64 min_pixelclock; - __u64 max_pixelclock; - __u32 standards; - __u32 capabilities; - __u32 reserved[16]; -} __attribute__((packed)); -#define V4L2_DV_BT_CAP_INTERLACED (1 << 0) -#define V4L2_DV_BT_CAP_PROGRESSIVE (1 << 1) -#define V4L2_DV_BT_CAP_REDUCED_BLANKING (1 << 2) -#define V4L2_DV_BT_CAP_CUSTOM (1 << 3) -struct v4l2_dv_timings_cap { - __u32 type; - __u32 pad; - __u32 reserved[2]; - union { - struct v4l2_bt_timings_cap bt; - __u32 raw_data[32]; - }; -}; -struct v4l2_input { - __u32 index; - __u8 name[32]; - __u32 type; - __u32 audioset; - __u32 tuner; - v4l2_std_id std; - __u32 status; - __u32 capabilities; - __u32 reserved[3]; -}; -#define V4L2_INPUT_TYPE_TUNER 1 -#define V4L2_INPUT_TYPE_CAMERA 2 -#define V4L2_INPUT_TYPE_TOUCH 3 -#define V4L2_IN_ST_NO_POWER 0x00000001 -#define V4L2_IN_ST_NO_SIGNAL 0x00000002 -#define V4L2_IN_ST_NO_COLOR 0x00000004 -#define V4L2_IN_ST_HFLIP 0x00000010 -#define V4L2_IN_ST_VFLIP 0x00000020 -#define V4L2_IN_ST_NO_H_LOCK 0x00000100 -#define V4L2_IN_ST_COLOR_KILL 0x00000200 -#define V4L2_IN_ST_NO_V_LOCK 0x00000400 -#define V4L2_IN_ST_NO_STD_LOCK 0x00000800 -#define V4L2_IN_ST_NO_SYNC 0x00010000 -#define V4L2_IN_ST_NO_EQU 0x00020000 -#define V4L2_IN_ST_NO_CARRIER 0x00040000 -#define V4L2_IN_ST_MACROVISION 0x01000000 -#define V4L2_IN_ST_NO_ACCESS 0x02000000 -#define V4L2_IN_ST_VTR 0x04000000 -#define V4L2_IN_CAP_DV_TIMINGS 0x00000002 -#define V4L2_IN_CAP_CUSTOM_TIMINGS V4L2_IN_CAP_DV_TIMINGS -#define V4L2_IN_CAP_STD 0x00000004 -#define V4L2_IN_CAP_NATIVE_SIZE 0x00000008 -struct v4l2_output { - __u32 index; - __u8 name[32]; - __u32 type; - __u32 audioset; - __u32 modulator; - v4l2_std_id std; - __u32 capabilities; - __u32 reserved[3]; -}; -#define V4L2_OUTPUT_TYPE_MODULATOR 1 -#define V4L2_OUTPUT_TYPE_ANALOG 2 -#define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY 3 -#define V4L2_OUT_CAP_DV_TIMINGS 0x00000002 -#define V4L2_OUT_CAP_CUSTOM_TIMINGS V4L2_OUT_CAP_DV_TIMINGS -#define V4L2_OUT_CAP_STD 0x00000004 -#define V4L2_OUT_CAP_NATIVE_SIZE 0x00000008 -struct v4l2_control { - __u32 id; - __s32 value; -}; -struct v4l2_ext_control { - __u32 id; - __u32 size; - __u32 reserved2[1]; - union { - __s32 value; - __s64 value64; - char * string; - __u8 * p_u8; - __u16 * p_u16; - __u32 * p_u32; - void * ptr; - }; -} __attribute__((packed)); -struct v4l2_ext_controls { - union { - __u32 ctrl_class; - __u32 which; - }; - __u32 count; - __u32 error_idx; - __u32 reserved[2]; - struct v4l2_ext_control * controls; -}; -#define V4L2_CTRL_ID_MASK (0x0fffffff) -#define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL) -#define V4L2_CTRL_ID2WHICH(id) ((id) & 0x0fff0000UL) -#define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000) -#define V4L2_CTRL_MAX_DIMS (4) -#define V4L2_CTRL_WHICH_CUR_VAL 0 -#define V4L2_CTRL_WHICH_DEF_VAL 0x0f000000 -enum v4l2_ctrl_type { - V4L2_CTRL_TYPE_INTEGER = 1, - V4L2_CTRL_TYPE_BOOLEAN = 2, - V4L2_CTRL_TYPE_MENU = 3, - V4L2_CTRL_TYPE_BUTTON = 4, - V4L2_CTRL_TYPE_INTEGER64 = 5, - V4L2_CTRL_TYPE_CTRL_CLASS = 6, - V4L2_CTRL_TYPE_STRING = 7, - V4L2_CTRL_TYPE_BITMASK = 8, - V4L2_CTRL_TYPE_INTEGER_MENU = 9, - V4L2_CTRL_COMPOUND_TYPES = 0x0100, - V4L2_CTRL_TYPE_U8 = 0x0100, - V4L2_CTRL_TYPE_U16 = 0x0101, - V4L2_CTRL_TYPE_U32 = 0x0102, -}; -struct v4l2_queryctrl { - __u32 id; - __u32 type; - __u8 name[32]; - __s32 minimum; - __s32 maximum; - __s32 step; - __s32 default_value; - __u32 flags; - __u32 reserved[2]; -}; -struct v4l2_query_ext_ctrl { - __u32 id; - __u32 type; - char name[32]; - __s64 minimum; - __s64 maximum; - __u64 step; - __s64 default_value; - __u32 flags; - __u32 elem_size; - __u32 elems; - __u32 nr_of_dims; - __u32 dims[V4L2_CTRL_MAX_DIMS]; - __u32 reserved[32]; -}; -struct v4l2_querymenu { - __u32 id; - __u32 index; - union { - __u8 name[32]; - __s64 value; - }; - __u32 reserved; -} __attribute__((packed)); -#define V4L2_CTRL_FLAG_DISABLED 0x0001 -#define V4L2_CTRL_FLAG_GRABBED 0x0002 -#define V4L2_CTRL_FLAG_READ_ONLY 0x0004 -#define V4L2_CTRL_FLAG_UPDATE 0x0008 -#define V4L2_CTRL_FLAG_INACTIVE 0x0010 -#define V4L2_CTRL_FLAG_SLIDER 0x0020 -#define V4L2_CTRL_FLAG_WRITE_ONLY 0x0040 -#define V4L2_CTRL_FLAG_VOLATILE 0x0080 -#define V4L2_CTRL_FLAG_HAS_PAYLOAD 0x0100 -#define V4L2_CTRL_FLAG_EXECUTE_ON_WRITE 0x0200 -#define V4L2_CTRL_FLAG_NEXT_CTRL 0x80000000 -#define V4L2_CTRL_FLAG_NEXT_COMPOUND 0x40000000 -#define V4L2_CID_MAX_CTRLS 1024 -#define V4L2_CID_PRIVATE_BASE 0x08000000 -struct v4l2_tuner { - __u32 index; - __u8 name[32]; - __u32 type; - __u32 capability; - __u32 rangelow; - __u32 rangehigh; - __u32 rxsubchans; - __u32 audmode; - __s32 signal; - __s32 afc; - __u32 reserved[4]; -}; -struct v4l2_modulator { - __u32 index; - __u8 name[32]; - __u32 capability; - __u32 rangelow; - __u32 rangehigh; - __u32 txsubchans; - __u32 type; - __u32 reserved[3]; -}; -#define V4L2_TUNER_CAP_LOW 0x0001 -#define V4L2_TUNER_CAP_NORM 0x0002 -#define V4L2_TUNER_CAP_HWSEEK_BOUNDED 0x0004 -#define V4L2_TUNER_CAP_HWSEEK_WRAP 0x0008 -#define V4L2_TUNER_CAP_STEREO 0x0010 -#define V4L2_TUNER_CAP_LANG2 0x0020 -#define V4L2_TUNER_CAP_SAP 0x0020 -#define V4L2_TUNER_CAP_LANG1 0x0040 -#define V4L2_TUNER_CAP_RDS 0x0080 -#define V4L2_TUNER_CAP_RDS_BLOCK_IO 0x0100 -#define V4L2_TUNER_CAP_RDS_CONTROLS 0x0200 -#define V4L2_TUNER_CAP_FREQ_BANDS 0x0400 -#define V4L2_TUNER_CAP_HWSEEK_PROG_LIM 0x0800 -#define V4L2_TUNER_CAP_1HZ 0x1000 -#define V4L2_TUNER_SUB_MONO 0x0001 -#define V4L2_TUNER_SUB_STEREO 0x0002 -#define V4L2_TUNER_SUB_LANG2 0x0004 -#define V4L2_TUNER_SUB_SAP 0x0004 -#define V4L2_TUNER_SUB_LANG1 0x0008 -#define V4L2_TUNER_SUB_RDS 0x0010 -#define V4L2_TUNER_MODE_MONO 0x0000 -#define V4L2_TUNER_MODE_STEREO 0x0001 -#define V4L2_TUNER_MODE_LANG2 0x0002 -#define V4L2_TUNER_MODE_SAP 0x0002 -#define V4L2_TUNER_MODE_LANG1 0x0003 -#define V4L2_TUNER_MODE_LANG1_LANG2 0x0004 -struct v4l2_frequency { - __u32 tuner; - __u32 type; - __u32 frequency; - __u32 reserved[8]; -}; -#define V4L2_BAND_MODULATION_VSB (1 << 1) -#define V4L2_BAND_MODULATION_FM (1 << 2) -#define V4L2_BAND_MODULATION_AM (1 << 3) -struct v4l2_frequency_band { - __u32 tuner; - __u32 type; - __u32 index; - __u32 capability; - __u32 rangelow; - __u32 rangehigh; - __u32 modulation; - __u32 reserved[9]; -}; -struct v4l2_hw_freq_seek { - __u32 tuner; - __u32 type; - __u32 seek_upward; - __u32 wrap_around; - __u32 spacing; - __u32 rangelow; - __u32 rangehigh; - __u32 reserved[5]; -}; -struct v4l2_rds_data { - __u8 lsb; - __u8 msb; - __u8 block; -} __attribute__((packed)); -#define V4L2_RDS_BLOCK_MSK 0x7 -#define V4L2_RDS_BLOCK_A 0 -#define V4L2_RDS_BLOCK_B 1 -#define V4L2_RDS_BLOCK_C 2 -#define V4L2_RDS_BLOCK_D 3 -#define V4L2_RDS_BLOCK_C_ALT 4 -#define V4L2_RDS_BLOCK_INVALID 7 -#define V4L2_RDS_BLOCK_CORRECTED 0x40 -#define V4L2_RDS_BLOCK_ERROR 0x80 -struct v4l2_audio { - __u32 index; - __u8 name[32]; - __u32 capability; - __u32 mode; - __u32 reserved[2]; -}; -#define V4L2_AUDCAP_STEREO 0x00001 -#define V4L2_AUDCAP_AVL 0x00002 -#define V4L2_AUDMODE_AVL 0x00001 -struct v4l2_audioout { - __u32 index; - __u8 name[32]; - __u32 capability; - __u32 mode; - __u32 reserved[2]; -}; -#define V4L2_ENC_IDX_FRAME_I (0) -#define V4L2_ENC_IDX_FRAME_P (1) -#define V4L2_ENC_IDX_FRAME_B (2) -#define V4L2_ENC_IDX_FRAME_MASK (0xf) -struct v4l2_enc_idx_entry { - __u64 offset; - __u64 pts; - __u32 length; - __u32 flags; - __u32 reserved[2]; -}; -#define V4L2_ENC_IDX_ENTRIES (64) -struct v4l2_enc_idx { - __u32 entries; - __u32 entries_cap; - __u32 reserved[4]; - struct v4l2_enc_idx_entry entry[V4L2_ENC_IDX_ENTRIES]; -}; -#define V4L2_ENC_CMD_START (0) -#define V4L2_ENC_CMD_STOP (1) -#define V4L2_ENC_CMD_PAUSE (2) -#define V4L2_ENC_CMD_RESUME (3) -#define V4L2_ENC_CMD_STOP_AT_GOP_END (1 << 0) -struct v4l2_encoder_cmd { - __u32 cmd; - __u32 flags; - union { - struct { - __u32 data[8]; - } raw; - }; -}; -#define V4L2_DEC_CMD_START (0) -#define V4L2_DEC_CMD_STOP (1) -#define V4L2_DEC_CMD_PAUSE (2) -#define V4L2_DEC_CMD_RESUME (3) -#define V4L2_QCOM_CMD_FLUSH (4) -#define V4L2_DEC_QCOM_CMD_RECONFIG_HINT (5) -#define V4L2_QCOM_CMD_SESSION_CONTINUE (6) -#define V4L2_DEC_CMD_START_MUTE_AUDIO (1 << 0) -#define V4L2_DEC_CMD_PAUSE_TO_BLACK (1 << 0) -#define V4L2_DEC_CMD_STOP_TO_BLACK (1 << 0) -#define V4L2_DEC_CMD_STOP_IMMEDIATELY (1 << 1) -#define V4L2_QCOM_CMD_FLUSH_OUTPUT (1 << 0) -#define V4L2_QCOM_CMD_FLUSH_CAPTURE (1 << 1) -#define V4L2_DEC_START_FMT_NONE (0) -#define V4L2_DEC_START_FMT_GOP (1) -struct v4l2_decoder_cmd { - __u32 cmd; - __u32 flags; - union { - struct { - __u64 pts; - } stop; - struct { - __s32 speed; - __u32 format; - } start; - struct { - __u32 data[16]; - } raw; - }; -}; -struct v4l2_vbi_format { - __u32 sampling_rate; - __u32 offset; - __u32 samples_per_line; - __u32 sample_format; - __s32 start[2]; - __u32 count[2]; - __u32 flags; - __u32 reserved[2]; -}; -#define V4L2_VBI_UNSYNC (1 << 0) -#define V4L2_VBI_INTERLACED (1 << 1) -#define V4L2_VBI_ITU_525_F1_START (1) -#define V4L2_VBI_ITU_525_F2_START (264) -#define V4L2_VBI_ITU_625_F1_START (1) -#define V4L2_VBI_ITU_625_F2_START (314) -struct v4l2_sliced_vbi_format { - __u16 service_set; - __u16 service_lines[2][24]; - __u32 io_size; - __u32 reserved[2]; -}; -#define V4L2_SLICED_TELETEXT_B (0x0001) -#define V4L2_SLICED_VPS (0x0400) -#define V4L2_SLICED_CAPTION_525 (0x1000) -#define V4L2_SLICED_WSS_625 (0x4000) -#define V4L2_SLICED_VBI_525 (V4L2_SLICED_CAPTION_525) -#define V4L2_SLICED_VBI_625 (V4L2_SLICED_TELETEXT_B | V4L2_SLICED_VPS | V4L2_SLICED_WSS_625) -struct v4l2_sliced_vbi_cap { - __u16 service_set; - __u16 service_lines[2][24]; - __u32 type; - __u32 reserved[3]; -}; -struct v4l2_sliced_vbi_data { - __u32 id; - __u32 field; - __u32 line; - __u32 reserved; - __u8 data[48]; -}; -#define V4L2_MPEG_VBI_IVTV_TELETEXT_B (1) -#define V4L2_MPEG_VBI_IVTV_CAPTION_525 (4) -#define V4L2_MPEG_VBI_IVTV_WSS_625 (5) -#define V4L2_MPEG_VBI_IVTV_VPS (7) -struct v4l2_mpeg_vbi_itv0_line { - __u8 id; - __u8 data[42]; -} __attribute__((packed)); -struct v4l2_mpeg_vbi_itv0 { - __le32 linemask[2]; - struct v4l2_mpeg_vbi_itv0_line line[35]; -} __attribute__((packed)); -struct v4l2_mpeg_vbi_ITV0 { - struct v4l2_mpeg_vbi_itv0_line line[36]; -} __attribute__((packed)); -#define V4L2_MPEG_VBI_IVTV_MAGIC0 "itv0" -#define V4L2_MPEG_VBI_IVTV_MAGIC1 "ITV0" -struct v4l2_mpeg_vbi_fmt_ivtv { - __u8 magic[4]; - union { - struct v4l2_mpeg_vbi_itv0 itv0; - struct v4l2_mpeg_vbi_ITV0 ITV0; - }; -} __attribute__((packed)); -struct v4l2_plane_pix_format { - __u32 sizeimage; - __u32 bytesperline; - __u16 reserved[6]; -} __attribute__((packed)); -struct v4l2_pix_format_mplane { - __u32 width; - __u32 height; - __u32 pixelformat; - __u32 field; - __u32 colorspace; - struct v4l2_plane_pix_format plane_fmt[VIDEO_MAX_PLANES]; - __u8 num_planes; - __u8 flags; - __u8 ycbcr_enc; - __u8 quantization; - __u8 xfer_func; - __u8 reserved[7]; -} __attribute__((packed)); -struct v4l2_sdr_format { - __u32 pixelformat; - __u32 buffersize; - __u8 reserved[24]; -} __attribute__((packed)); -struct v4l2_format { - __u32 type; - union { - struct v4l2_pix_format pix; - struct v4l2_pix_format_mplane pix_mp; - struct v4l2_window win; - struct v4l2_vbi_format vbi; - struct v4l2_sliced_vbi_format sliced; - struct v4l2_sdr_format sdr; - __u8 raw_data[200]; - } fmt; -}; -struct v4l2_streamparm { - __u32 type; - union { - struct v4l2_captureparm capture; - struct v4l2_outputparm output; - __u8 raw_data[200]; - } parm; -}; -#define V4L2_EVENT_ALL 0 -#define V4L2_EVENT_VSYNC 1 -#define V4L2_EVENT_EOS 2 -#define V4L2_EVENT_CTRL 3 -#define V4L2_EVENT_FRAME_SYNC 4 -#define V4L2_EVENT_SOURCE_CHANGE 5 -#define V4L2_EVENT_MOTION_DET 6 -#define V4L2_EVENT_PRIVATE_START 0x08000000 -#define V4L2_EVENT_BITDEPTH_FLAG 0x1 -#define V4L2_EVENT_PICSTRUCT_FLAG 0x2 -#define V4L2_EVENT_COLOUR_SPACE_FLAG 0x4 -#define V4L2_EVENT_MSM_VIDC_START (V4L2_EVENT_PRIVATE_START + 0x00001000) -#define V4L2_EVENT_MSM_VIDC_FLUSH_DONE (V4L2_EVENT_MSM_VIDC_START + 1) -#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_SUFFICIENT (V4L2_EVENT_MSM_VIDC_START + 2) -#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_INSUFFICIENT (V4L2_EVENT_MSM_VIDC_START + 3) -#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_BITDEPTH_CHANGED_INSUFFICIENT (V4L2_EVENT_MSM_VIDC_START + 4) -#define V4L2_EVENT_MSM_VIDC_SYS_ERROR (V4L2_EVENT_MSM_VIDC_START + 5) -#define V4L2_EVENT_MSM_VIDC_RELEASE_BUFFER_REFERENCE (V4L2_EVENT_MSM_VIDC_START + 6) -#define V4L2_EVENT_MSM_VIDC_RELEASE_UNQUEUED_BUFFER (V4L2_EVENT_MSM_VIDC_START + 7) -#define V4L2_EVENT_MSM_VIDC_HW_OVERLOAD (V4L2_EVENT_MSM_VIDC_START + 8) -#define V4L2_EVENT_MSM_VIDC_MAX_CLIENTS (V4L2_EVENT_MSM_VIDC_START + 9) -#define V4L2_EVENT_MSM_VIDC_HW_UNSUPPORTED (V4L2_EVENT_MSM_VIDC_START + 10) -struct v4l2_event_vsync { - __u8 field; -} __attribute__((packed)); -#define V4L2_EVENT_CTRL_CH_VALUE (1 << 0) -#define V4L2_EVENT_CTRL_CH_FLAGS (1 << 1) -#define V4L2_EVENT_CTRL_CH_RANGE (1 << 2) -struct v4l2_event_ctrl { - __u32 changes; - __u32 type; - union { - __s32 value; - __s64 value64; - }; - __u32 flags; - __s32 minimum; - __s32 maximum; - __s32 step; - __s32 default_value; -}; -struct v4l2_event_frame_sync { - __u32 frame_sequence; -}; -#define V4L2_EVENT_SRC_CH_RESOLUTION (1 << 0) -struct v4l2_event_src_change { - __u32 changes; -}; -#define V4L2_EVENT_MD_FL_HAVE_FRAME_SEQ (1 << 0) -struct v4l2_event_motion_det { - __u32 flags; - __u32 frame_sequence; - __u32 region_mask; -}; -struct v4l2_event { - __u32 type; - union { - struct v4l2_event_vsync vsync; - struct v4l2_event_ctrl ctrl; - struct v4l2_event_frame_sync frame_sync; - struct v4l2_event_src_change src_change; - struct v4l2_event_motion_det motion_det; - __u8 data[64]; - } u; - __u32 pending; - __u32 sequence; - struct timespec timestamp; - __u32 id; - __u32 reserved[8]; -}; -#define V4L2_EVENT_SUB_FL_SEND_INITIAL (1 << 0) -#define V4L2_EVENT_SUB_FL_ALLOW_FEEDBACK (1 << 1) -struct v4l2_event_subscription { - __u32 type; - __u32 id; - __u32 flags; - __u32 reserved[5]; -}; -#define V4L2_CHIP_MATCH_BRIDGE 0 -#define V4L2_CHIP_MATCH_SUBDEV 4 -#define V4L2_CHIP_MATCH_HOST V4L2_CHIP_MATCH_BRIDGE -#define V4L2_CHIP_MATCH_I2C_DRIVER 1 -#define V4L2_CHIP_MATCH_I2C_ADDR 2 -#define V4L2_CHIP_MATCH_AC97 3 -struct v4l2_dbg_match { - __u32 type; - union { - __u32 addr; - char name[32]; - }; -} __attribute__((packed)); -struct v4l2_dbg_register { - struct v4l2_dbg_match match; - __u32 size; - __u64 reg; - __u64 val; -} __attribute__((packed)); -#define V4L2_CHIP_FL_READABLE (1 << 0) -#define V4L2_CHIP_FL_WRITABLE (1 << 1) -struct v4l2_dbg_chip_info { - struct v4l2_dbg_match match; - char name[32]; - __u32 flags; - __u32 reserved[32]; -} __attribute__((packed)); -struct v4l2_create_buffers { - __u32 index; - __u32 count; - __u32 memory; - struct v4l2_format format; - __u32 reserved[8]; -}; -#define VIDIOC_QUERYCAP _IOR('V', 0, struct v4l2_capability) -#define VIDIOC_RESERVED _IO('V', 1) -#define VIDIOC_ENUM_FMT _IOWR('V', 2, struct v4l2_fmtdesc) -#define VIDIOC_G_FMT _IOWR('V', 4, struct v4l2_format) -#define VIDIOC_S_FMT _IOWR('V', 5, struct v4l2_format) -#define VIDIOC_REQBUFS _IOWR('V', 8, struct v4l2_requestbuffers) -#define VIDIOC_QUERYBUF _IOWR('V', 9, struct v4l2_buffer) -#define VIDIOC_G_FBUF _IOR('V', 10, struct v4l2_framebuffer) -#define VIDIOC_S_FBUF _IOW('V', 11, struct v4l2_framebuffer) -#define VIDIOC_OVERLAY _IOW('V', 14, int) -#define VIDIOC_QBUF _IOWR('V', 15, struct v4l2_buffer) -#define VIDIOC_EXPBUF _IOWR('V', 16, struct v4l2_exportbuffer) -#define VIDIOC_DQBUF _IOWR('V', 17, struct v4l2_buffer) -#define VIDIOC_STREAMON _IOW('V', 18, int) -#define VIDIOC_STREAMOFF _IOW('V', 19, int) -#define VIDIOC_G_PARM _IOWR('V', 21, struct v4l2_streamparm) -#define VIDIOC_S_PARM _IOWR('V', 22, struct v4l2_streamparm) -#define VIDIOC_G_STD _IOR('V', 23, v4l2_std_id) -#define VIDIOC_S_STD _IOW('V', 24, v4l2_std_id) -#define VIDIOC_ENUMSTD _IOWR('V', 25, struct v4l2_standard) -#define VIDIOC_ENUMINPUT _IOWR('V', 26, struct v4l2_input) -#define VIDIOC_G_CTRL _IOWR('V', 27, struct v4l2_control) -#define VIDIOC_S_CTRL _IOWR('V', 28, struct v4l2_control) -#define VIDIOC_G_TUNER _IOWR('V', 29, struct v4l2_tuner) -#define VIDIOC_S_TUNER _IOW('V', 30, struct v4l2_tuner) -#define VIDIOC_G_AUDIO _IOR('V', 33, struct v4l2_audio) -#define VIDIOC_S_AUDIO _IOW('V', 34, struct v4l2_audio) -#define VIDIOC_QUERYCTRL _IOWR('V', 36, struct v4l2_queryctrl) -#define VIDIOC_QUERYMENU _IOWR('V', 37, struct v4l2_querymenu) -#define VIDIOC_G_INPUT _IOR('V', 38, int) -#define VIDIOC_S_INPUT _IOWR('V', 39, int) -#define VIDIOC_G_EDID _IOWR('V', 40, struct v4l2_edid) -#define VIDIOC_S_EDID _IOWR('V', 41, struct v4l2_edid) -#define VIDIOC_G_OUTPUT _IOR('V', 46, int) -#define VIDIOC_S_OUTPUT _IOWR('V', 47, int) -#define VIDIOC_ENUMOUTPUT _IOWR('V', 48, struct v4l2_output) -#define VIDIOC_G_AUDOUT _IOR('V', 49, struct v4l2_audioout) -#define VIDIOC_S_AUDOUT _IOW('V', 50, struct v4l2_audioout) -#define VIDIOC_G_MODULATOR _IOWR('V', 54, struct v4l2_modulator) -#define VIDIOC_S_MODULATOR _IOW('V', 55, struct v4l2_modulator) -#define VIDIOC_G_FREQUENCY _IOWR('V', 56, struct v4l2_frequency) -#define VIDIOC_S_FREQUENCY _IOW('V', 57, struct v4l2_frequency) -#define VIDIOC_CROPCAP _IOWR('V', 58, struct v4l2_cropcap) -#define VIDIOC_G_CROP _IOWR('V', 59, struct v4l2_crop) -#define VIDIOC_S_CROP _IOW('V', 60, struct v4l2_crop) -#define VIDIOC_G_JPEGCOMP _IOR('V', 61, struct v4l2_jpegcompression) -#define VIDIOC_S_JPEGCOMP _IOW('V', 62, struct v4l2_jpegcompression) -#define VIDIOC_QUERYSTD _IOR('V', 63, v4l2_std_id) -#define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format) -#define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio) -#define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout) -#define VIDIOC_G_PRIORITY _IOR('V', 67, __u32) -#define VIDIOC_S_PRIORITY _IOW('V', 68, __u32) -#define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap) -#define VIDIOC_LOG_STATUS _IO('V', 70) -#define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls) -#define VIDIOC_S_EXT_CTRLS _IOWR('V', 72, struct v4l2_ext_controls) -#define VIDIOC_TRY_EXT_CTRLS _IOWR('V', 73, struct v4l2_ext_controls) -#define VIDIOC_ENUM_FRAMESIZES _IOWR('V', 74, struct v4l2_frmsizeenum) -#define VIDIOC_ENUM_FRAMEINTERVALS _IOWR('V', 75, struct v4l2_frmivalenum) -#define VIDIOC_G_ENC_INDEX _IOR('V', 76, struct v4l2_enc_idx) -#define VIDIOC_ENCODER_CMD _IOWR('V', 77, struct v4l2_encoder_cmd) -#define VIDIOC_TRY_ENCODER_CMD _IOWR('V', 78, struct v4l2_encoder_cmd) -#define VIDIOC_DBG_S_REGISTER _IOW('V', 79, struct v4l2_dbg_register) -#define VIDIOC_DBG_G_REGISTER _IOWR('V', 80, struct v4l2_dbg_register) -#define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek) -#define VIDIOC_S_DV_TIMINGS _IOWR('V', 87, struct v4l2_dv_timings) -#define VIDIOC_G_DV_TIMINGS _IOWR('V', 88, struct v4l2_dv_timings) -#define VIDIOC_DQEVENT _IOR('V', 89, struct v4l2_event) -#define VIDIOC_SUBSCRIBE_EVENT _IOW('V', 90, struct v4l2_event_subscription) -#define VIDIOC_UNSUBSCRIBE_EVENT _IOW('V', 91, struct v4l2_event_subscription) -#define VIDIOC_CREATE_BUFS _IOWR('V', 92, struct v4l2_create_buffers) -#define VIDIOC_PREPARE_BUF _IOWR('V', 93, struct v4l2_buffer) -#define VIDIOC_G_SELECTION _IOWR('V', 94, struct v4l2_selection) -#define VIDIOC_S_SELECTION _IOWR('V', 95, struct v4l2_selection) -#define VIDIOC_DECODER_CMD _IOWR('V', 96, struct v4l2_decoder_cmd) -#define VIDIOC_TRY_DECODER_CMD _IOWR('V', 97, struct v4l2_decoder_cmd) -#define VIDIOC_ENUM_DV_TIMINGS _IOWR('V', 98, struct v4l2_enum_dv_timings) -#define VIDIOC_QUERY_DV_TIMINGS _IOR('V', 99, struct v4l2_dv_timings) -#define VIDIOC_DV_TIMINGS_CAP _IOWR('V', 100, struct v4l2_dv_timings_cap) -#define VIDIOC_ENUM_FREQ_BANDS _IOWR('V', 101, struct v4l2_frequency_band) -#define VIDIOC_DBG_G_CHIP_INFO _IOWR('V', 102, struct v4l2_dbg_chip_info) -#define VIDIOC_QUERY_EXT_CTRL _IOWR('V', 103, struct v4l2_query_ext_ctrl) -#define BASE_VIDIOC_PRIVATE 192 -#endif - diff --git a/sdm710/kernel-headers/linux/wcd-spi-ac-params.h b/sdm710/kernel-headers/linux/wcd-spi-ac-params.h deleted file mode 100644 index 764b891b..00000000 --- a/sdm710/kernel-headers/linux/wcd-spi-ac-params.h +++ /dev/null @@ -1,38 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_WCD_SPI_AC_PARAMS_H__ -#define __UAPI_WCD_SPI_AC_PARAMS_H__ -#include <linux/types.h> -#define WCD_SPI_AC_CMD_CONC_BEGIN 0x01 -#define WCD_SPI_AC_CMD_CONC_END 0x02 -#define WCD_SPI_AC_CMD_BUF_DATA 0x03 -#define WCD_SPI_AC_MAX_BUFFERS 2 -#define WCD_SPI_AC_MAX_CH_PER_BUF 8 -#define WCD_SPI_AC_CLIENT_CDEV_NAME "wcd-spi-ac-client" -#define WCD_SPI_AC_PROCFS_DIR_NAME "wcd-spi-ac" -#define WCD_SPI_AC_PROCFS_STATE_NAME "svc-state" -struct wcd_spi_ac_buf_data { - __u32 addr[WCD_SPI_AC_MAX_CH_PER_BUF]; -} __attribute__((packed)); -struct wcd_spi_ac_write_cmd { - __u32 cmd_type; - __u8 payload[0]; -} __attribute__((packed)); -#endif - diff --git a/sdm710/kernel-headers/media/cam_cpas.h b/sdm710/kernel-headers/media/cam_cpas.h deleted file mode 100644 index aff8754b..00000000 --- a/sdm710/kernel-headers/media/cam_cpas.h +++ /dev/null @@ -1,31 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_CAM_CPAS_H__ -#define __UAPI_CAM_CPAS_H__ -#include "cam_defs.h" -#define CAM_FAMILY_CAMERA_SS 1 -#define CAM_FAMILY_CPAS_SS 2 -struct cam_cpas_query_cap { - uint32_t camera_family; - uint32_t reserved; - struct cam_hw_version camera_version; - struct cam_hw_version cpas_version; -}; -#endif - diff --git a/sdm710/kernel-headers/media/cam_defs.h b/sdm710/kernel-headers/media/cam_defs.h deleted file mode 100644 index 11f34e67..00000000 --- a/sdm710/kernel-headers/media/cam_defs.h +++ /dev/null @@ -1,262 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_CAM_DEFS_H__ -#define __UAPI_CAM_DEFS_H__ -#include <linux/videodev2.h> -#include <linux/types.h> -#include <linux/ioctl.h> -#define CAM_COMMON_OPCODE_BASE 0x100 -#define CAM_QUERY_CAP (CAM_COMMON_OPCODE_BASE + 0x1) -#define CAM_ACQUIRE_DEV (CAM_COMMON_OPCODE_BASE + 0x2) -#define CAM_START_DEV (CAM_COMMON_OPCODE_BASE + 0x3) -#define CAM_STOP_DEV (CAM_COMMON_OPCODE_BASE + 0x4) -#define CAM_CONFIG_DEV (CAM_COMMON_OPCODE_BASE + 0x5) -#define CAM_RELEASE_DEV (CAM_COMMON_OPCODE_BASE + 0x6) -#define CAM_SD_SHUTDOWN (CAM_COMMON_OPCODE_BASE + 0x7) -#define CAM_FLUSH_REQ (CAM_COMMON_OPCODE_BASE + 0x8) -#define CAM_COMMON_OPCODE_MAX (CAM_COMMON_OPCODE_BASE + 0x9) -#define CAM_EXT_OPCODE_BASE 0x200 -#define CAM_CONFIG_DEV_EXTERNAL (CAM_EXT_OPCODE_BASE + 0x1) -#define CAM_HANDLE_USER_POINTER 1 -#define CAM_HANDLE_MEM_HANDLE 2 -#define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_MASK 0xFFFFFF00 -#define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_SHIFT 8 -#define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_MASK 0xFF -#define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_SHIFT 0 -#define CAM_CMD_BUF_DMI 0x1 -#define CAM_CMD_BUF_DMI16 0x2 -#define CAM_CMD_BUF_DMI32 0x3 -#define CAM_CMD_BUF_DMI64 0x4 -#define CAM_CMD_BUF_DIRECT 0x5 -#define CAM_CMD_BUF_INDIRECT 0x6 -#define CAM_CMD_BUF_I2C 0x7 -#define CAM_CMD_BUF_FW 0x8 -#define CAM_CMD_BUF_GENERIC 0x9 -#define CAM_CMD_BUF_LEGACY 0xA -enum flush_type_t { - CAM_FLUSH_TYPE_REQ, - CAM_FLUSH_TYPE_ALL, - CAM_FLUSH_TYPE_MAX -}; -struct cam_control { - uint32_t op_code; - uint32_t size; - uint32_t handle_type; - uint32_t reserved; - uint64_t handle; -}; -#define VIDIOC_CAM_CONTROL _IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_control) -struct cam_hw_version { - uint32_t major; - uint32_t minor; - uint32_t incr; - uint32_t reserved; -}; -struct cam_iommu_handle { - int32_t non_secure; - int32_t secure; -}; -#define CAM_SECURE_MODE_NON_SECURE 0 -#define CAM_SECURE_MODE_SECURE 1 -#define CAM_FORMAT_BASE 0 -#define CAM_FORMAT_MIPI_RAW_6 1 -#define CAM_FORMAT_MIPI_RAW_8 2 -#define CAM_FORMAT_MIPI_RAW_10 3 -#define CAM_FORMAT_MIPI_RAW_12 4 -#define CAM_FORMAT_MIPI_RAW_14 5 -#define CAM_FORMAT_MIPI_RAW_16 6 -#define CAM_FORMAT_MIPI_RAW_20 7 -#define CAM_FORMAT_QTI_RAW_8 8 -#define CAM_FORMAT_QTI_RAW_10 9 -#define CAM_FORMAT_QTI_RAW_12 10 -#define CAM_FORMAT_QTI_RAW_14 11 -#define CAM_FORMAT_PLAIN8 12 -#define CAM_FORMAT_PLAIN16_8 13 -#define CAM_FORMAT_PLAIN16_10 14 -#define CAM_FORMAT_PLAIN16_12 15 -#define CAM_FORMAT_PLAIN16_14 16 -#define CAM_FORMAT_PLAIN16_16 17 -#define CAM_FORMAT_PLAIN32_20 18 -#define CAM_FORMAT_PLAIN64 19 -#define CAM_FORMAT_PLAIN128 20 -#define CAM_FORMAT_ARGB 21 -#define CAM_FORMAT_ARGB_10 22 -#define CAM_FORMAT_ARGB_12 23 -#define CAM_FORMAT_ARGB_14 24 -#define CAM_FORMAT_DPCM_10_6_10 25 -#define CAM_FORMAT_DPCM_10_8_10 26 -#define CAM_FORMAT_DPCM_12_6_12 27 -#define CAM_FORMAT_DPCM_12_8_12 28 -#define CAM_FORMAT_DPCM_14_8_14 29 -#define CAM_FORMAT_DPCM_14_10_14 30 -#define CAM_FORMAT_NV21 31 -#define CAM_FORMAT_NV12 32 -#define CAM_FORMAT_TP10 33 -#define CAM_FORMAT_YUV422 34 -#define CAM_FORMAT_PD8 35 -#define CAM_FORMAT_PD10 36 -#define CAM_FORMAT_UBWC_NV12 37 -#define CAM_FORMAT_UBWC_NV12_4R 38 -#define CAM_FORMAT_UBWC_TP10 39 -#define CAM_FORMAT_UBWC_P010 40 -#define CAM_FORMAT_PLAIN8_SWAP 41 -#define CAM_FORMAT_PLAIN8_10 42 -#define CAM_FORMAT_PLAIN8_10_SWAP 43 -#define CAM_FORMAT_YV12 44 -#define CAM_FORMAT_Y_ONLY 45 -#define CAM_FORMAT_MAX 46 -#define CAM_ROTATE_CW_0_DEGREE 0 -#define CAM_ROTATE_CW_90_DEGREE 1 -#define CAM_RORATE_CW_180_DEGREE 2 -#define CAM_ROTATE_CW_270_DEGREE 3 -#define CAM_COLOR_SPACE_BASE 0 -#define CAM_COLOR_SPACE_BT601_FULL 1 -#define CAM_COLOR_SPACE_BT601625 2 -#define CAM_COLOR_SPACE_BT601525 3 -#define CAM_COLOR_SPACE_BT709 4 -#define CAM_COLOR_SPACE_DEPTH 5 -#define CAM_COLOR_SPACE_MAX 6 -#define CAM_BUF_INPUT 1 -#define CAM_BUF_OUTPUT 2 -#define CAM_BUF_IN_OUT 3 -#define CAM_PACKET_DEV_BASE 0 -#define CAM_PACKET_DEV_IMG_SENSOR 1 -#define CAM_PACKET_DEV_ACTUATOR 2 -#define CAM_PACKET_DEV_COMPANION 3 -#define CAM_PACKET_DEV_EEPOM 4 -#define CAM_PACKET_DEV_CSIPHY 5 -#define CAM_PACKET_DEV_OIS 6 -#define CAM_PACKET_DEV_FLASH 7 -#define CAM_PACKET_DEV_FD 8 -#define CAM_PACKET_DEV_JPEG_ENC 9 -#define CAM_PACKET_DEV_JPEG_DEC 10 -#define CAM_PACKET_DEV_VFE 11 -#define CAM_PACKET_DEV_CPP 12 -#define CAM_PACKET_DEV_CSID 13 -#define CAM_PACKET_DEV_ISPIF 14 -#define CAM_PACKET_DEV_IFE 15 -#define CAM_PACKET_DEV_ICP 16 -#define CAM_PACKET_DEV_LRME 17 -#define CAM_PACKET_DEV_MAX 18 -#define CAM_PACKET_MAX_PLANES 3 -struct cam_plane_cfg { - uint32_t width; - uint32_t height; - uint32_t plane_stride; - uint32_t slice_height; - uint32_t meta_stride; - uint32_t meta_size; - uint32_t meta_offset; - uint32_t packer_config; - uint32_t mode_config; - uint32_t tile_config; - uint32_t h_init; - uint32_t v_init; -}; -struct cam_cmd_buf_desc { - int32_t mem_handle; - uint32_t offset; - uint32_t size; - uint32_t length; - uint32_t type; - uint32_t meta_data; -}; -struct cam_buf_io_cfg { - int32_t mem_handle[CAM_PACKET_MAX_PLANES]; - uint32_t offsets[CAM_PACKET_MAX_PLANES]; - struct cam_plane_cfg planes[CAM_PACKET_MAX_PLANES]; - uint32_t format; - uint32_t color_space; - uint32_t color_pattern; - uint32_t bpp; - uint32_t rotation; - uint32_t resource_type; - int32_t fence; - int32_t early_fence; - struct cam_cmd_buf_desc aux_cmd_buf; - uint32_t direction; - uint32_t batch_size; - uint32_t subsample_pattern; - uint32_t subsample_period; - uint32_t framedrop_pattern; - uint32_t framedrop_period; - uint32_t flag; - uint32_t padding; -}; -struct cam_packet_header { - uint32_t op_code; - uint32_t size; - uint64_t request_id; - uint32_t flags; - uint32_t padding; -}; -struct cam_patch_desc { - int32_t dst_buf_hdl; - uint32_t dst_offset; - int32_t src_buf_hdl; - uint32_t src_offset; -}; -struct cam_packet { - struct cam_packet_header header; - uint32_t cmd_buf_offset; - uint32_t num_cmd_buf; - uint32_t io_configs_offset; - uint32_t num_io_configs; - uint32_t patch_offset; - uint32_t num_patches; - uint32_t kmd_cmd_buf_index; - uint32_t kmd_cmd_buf_offset; - uint64_t payload[1]; -}; -struct cam_release_dev_cmd { - int32_t session_handle; - int32_t dev_handle; -}; -struct cam_start_stop_dev_cmd { - int32_t session_handle; - int32_t dev_handle; -}; -struct cam_config_dev_cmd { - int32_t session_handle; - int32_t dev_handle; - uint64_t offset; - uint64_t packet_handle; -}; -struct cam_query_cap_cmd { - uint32_t size; - uint32_t handle_type; - uint64_t caps_handle; -}; -struct cam_acquire_dev_cmd { - int32_t session_handle; - int32_t dev_handle; - uint32_t handle_type; - uint32_t num_resources; - uint64_t resource_hdl; -}; -struct cam_flush_dev_cmd { - uint64_t version; - int32_t session_handle; - int32_t dev_handle; - uint32_t flush_type; - uint32_t reserved; - int64_t req_id; -}; -#endif - diff --git a/sdm710/kernel-headers/media/cam_fd.h b/sdm710/kernel-headers/media/cam_fd.h deleted file mode 100644 index 74cda55c..00000000 --- a/sdm710/kernel-headers/media/cam_fd.h +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_CAM_FD_H__ -#define __UAPI_CAM_FD_H__ -#include "cam_defs.h" -#define CAM_FD_MAX_FACES 35 -#define CAM_FD_RAW_RESULT_ENTRIES 512 -#define CAM_PACKET_OPCODES_FD_FRAME_UPDATE 0x0 -#define CAM_FD_CMD_BUFFER_ID_GENERIC 0x0 -#define CAM_FD_CMD_BUFFER_ID_CDM 0x1 -#define CAM_FD_CMD_BUFFER_ID_MAX 0x2 -#define CAM_FD_BLOB_TYPE_SOC_CLOCK_BW_REQUEST 0x0 -#define CAM_FD_BLOB_TYPE_RAW_RESULTS_REQUIRED 0x1 -#define CAM_FD_INPUT_PORT_ID_IMAGE 0x0 -#define CAM_FD_INPUT_PORT_ID_MAX 0x1 -#define CAM_FD_OUTPUT_PORT_ID_RESULTS 0x0 -#define CAM_FD_OUTPUT_PORT_ID_RAW_RESULTS 0x1 -#define CAM_FD_OUTPUT_PORT_ID_WORK_BUFFER 0x2 -#define CAM_FD_OUTPUT_PORT_ID_MAX 0x3 -struct cam_fd_soc_clock_bw_request { - uint64_t clock_rate; - uint64_t bandwidth; - uint64_t reserved[4]; -}; -struct cam_fd_face { - uint32_t prop1; - uint32_t prop2; - uint32_t prop3; - uint32_t prop4; -}; -struct cam_fd_results { - struct cam_fd_face faces[CAM_FD_MAX_FACES]; - uint32_t face_count; - uint32_t reserved[3]; -}; -struct cam_fd_hw_caps { - struct cam_hw_version core_version; - struct cam_hw_version wrapper_version; - uint32_t raw_results_available; - uint32_t supported_modes; - uint64_t reserved; -}; -struct cam_fd_query_cap_cmd { - struct cam_iommu_handle device_iommu; - struct cam_iommu_handle cdm_iommu; - struct cam_fd_hw_caps hw_caps; - uint64_t reserved; -}; -struct cam_fd_acquire_dev_info { - struct cam_fd_soc_clock_bw_request clk_bw_request; - uint32_t priority; - uint32_t mode; - uint32_t get_raw_results; - uint32_t reserved[13]; -}; -#endif - diff --git a/sdm710/kernel-headers/media/cam_icp.h b/sdm710/kernel-headers/media/cam_icp.h deleted file mode 100644 index c237196c..00000000 --- a/sdm710/kernel-headers/media/cam_icp.h +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_CAM_ICP_H__ -#define __UAPI_CAM_ICP_H__ -#include "cam_defs.h" -#define CAM_ICP_DEV_TYPE_A5 1 -#define CAM_ICP_DEV_TYPE_IPE 2 -#define CAM_ICP_DEV_TYPE_BPS 3 -#define CAM_ICP_DEV_TYPE_IPE_CDM 4 -#define CAM_ICP_DEV_TYPE_BPS_CDM 5 -#define CAM_ICP_DEV_TYPE_MAX 5 -#define CAM_ICP_RES_TYPE_BPS 1 -#define CAM_ICP_RES_TYPE_IPE_RT 2 -#define CAM_ICP_RES_TYPE_IPE 3 -#define CAM_ICP_RES_TYPE_MAX 4 -#define CAM_ICP_OPCODE_IPE_UPDATE 0 -#define CAM_ICP_OPCODE_BPS_UPDATE 1 -#define CAM_ICP_IPE_INPUT_IMAGE_FULL 0x0 -#define CAM_ICP_IPE_INPUT_IMAGE_DS4 0x1 -#define CAM_ICP_IPE_INPUT_IMAGE_DS16 0x2 -#define CAM_ICP_IPE_INPUT_IMAGE_DS64 0x3 -#define CAM_ICP_IPE_INPUT_IMAGE_FULL_REF 0x4 -#define CAM_ICP_IPE_INPUT_IMAGE_DS4_REF 0x5 -#define CAM_ICP_IPE_INPUT_IMAGE_DS16_REF 0x6 -#define CAM_ICP_IPE_INPUT_IMAGE_DS64_REF 0x7 -#define CAM_ICP_IPE_OUTPUT_IMAGE_DISPLAY 0x8 -#define CAM_ICP_IPE_OUTPUT_IMAGE_VIDEO 0x9 -#define CAM_ICP_IPE_OUTPUT_IMAGE_FULL_REF 0xA -#define CAM_ICP_IPE_OUTPUT_IMAGE_DS4_REF 0xB -#define CAM_ICP_IPE_OUTPUT_IMAGE_DS16_REF 0xC -#define CAM_ICP_IPE_OUTPUT_IMAGE_DS64_REF 0xD -#define CAM_ICP_IPE_IMAGE_MAX 0xE -#define CAM_ICP_BPS_INPUT_IMAGE 0x0 -#define CAM_ICP_BPS_OUTPUT_IMAGE_FULL 0x1 -#define CAM_ICP_BPS_OUTPUT_IMAGE_DS4 0x2 -#define CAM_ICP_BPS_OUTPUT_IMAGE_DS16 0x3 -#define CAM_ICP_BPS_OUTPUT_IMAGE_DS64 0x4 -#define CAM_ICP_BPS_OUTPUT_IMAGE_STATS_BG 0x5 -#define CAM_ICP_BPS_OUTPUT_IMAGE_STATS_BHIST 0x6 -#define CAM_ICP_BPS_OUTPUT_IMAGE_REG1 0x7 -#define CAM_ICP_BPS_OUTPUT_IMAGE_REG2 0x8 -#define CAM_ICP_BPS_IO_IMAGES_MAX 0x9 -#define CAM_ICP_CMD_META_GENERIC_BLOB 0x1 -#define CAM_ICP_CMD_GENERIC_BLOB_CLK 0x1 -struct cam_icp_clk_bw_request { - uint64_t budget_ns; - uint32_t frame_cycles; - uint32_t rt_flag; - uint64_t uncompressed_bw; - uint64_t compressed_bw; -}; -struct cam_icp_dev_ver { - uint32_t dev_type; - uint32_t reserved; - struct cam_hw_version hw_ver; -}; -struct cam_icp_ver { - uint32_t major; - uint32_t minor; - uint32_t revision; - uint32_t reserved; -}; -struct cam_icp_query_cap_cmd { - struct cam_iommu_handle dev_iommu_handle; - struct cam_iommu_handle cdm_iommu_handle; - struct cam_icp_ver fw_version; - struct cam_icp_ver api_version; - uint32_t num_ipe; - uint32_t num_bps; - struct cam_icp_dev_ver dev_ver[CAM_ICP_DEV_TYPE_MAX]; -}; -struct cam_icp_res_info { - uint32_t format; - uint32_t width; - uint32_t height; - uint32_t fps; -}; -struct cam_icp_acquire_dev_info { - uint32_t scratch_mem_size; - uint32_t dev_type; - uint32_t io_config_cmd_size; - int32_t io_config_cmd_handle; - uint32_t secure_mode; - int32_t chain_info; - struct cam_icp_res_info in_res; - uint32_t num_out_res; - struct cam_icp_res_info out_res[1]; -} __attribute__((__packed__)); -#endif - diff --git a/sdm710/kernel-headers/media/cam_isp.h b/sdm710/kernel-headers/media/cam_isp.h deleted file mode 100644 index bbda6709..00000000 --- a/sdm710/kernel-headers/media/cam_isp.h +++ /dev/null @@ -1,188 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_CAM_ISP_H__ -#define __UAPI_CAM_ISP_H__ -#include "cam_defs.h" -#include "cam_isp_vfe.h" -#include "cam_isp_ife.h" -#define CAM_ISP_DEV_NAME "cam-isp" -#define CAM_ISP_HW_BASE 0 -#define CAM_ISP_HW_CSID 1 -#define CAM_ISP_HW_VFE 2 -#define CAM_ISP_HW_IFE 3 -#define CAM_ISP_HW_ISPIF 4 -#define CAM_ISP_HW_MAX 5 -#define CAM_ISP_PATTERN_BAYER_RGRGRG 0 -#define CAM_ISP_PATTERN_BAYER_GRGRGR 1 -#define CAM_ISP_PATTERN_BAYER_BGBGBG 2 -#define CAM_ISP_PATTERN_BAYER_GBGBGB 3 -#define CAM_ISP_PATTERN_YUV_YCBYCR 4 -#define CAM_ISP_PATTERN_YUV_YCRYCB 5 -#define CAM_ISP_PATTERN_YUV_CBYCRY 6 -#define CAM_ISP_PATTERN_YUV_CRYCBY 7 -#define CAM_ISP_PATTERN_MAX 8 -#define CAM_ISP_RES_USAGE_SINGLE 0 -#define CAM_ISP_RES_USAGE_DUAL 1 -#define CAM_ISP_RES_USAGE_MAX 2 -#define CAM_ISP_RES_ID_PORT 0 -#define CAM_ISP_RES_ID_CLK 1 -#define CAM_ISP_RES_ID_MAX 2 -#define CAM_ISP_LANE_TYPE_DPHY 0 -#define CAM_ISP_LANE_TYPE_CPHY 1 -#define CAM_ISP_LANE_TYPE_MAX 2 -#define CAM_ISP_RES_COMP_GROUP_NONE 0 -#define CAM_ISP_RES_COMP_GROUP_ID_0 1 -#define CAM_ISP_RES_COMP_GROUP_ID_1 2 -#define CAM_ISP_RES_COMP_GROUP_ID_2 3 -#define CAM_ISP_RES_COMP_GROUP_ID_3 4 -#define CAM_ISP_RES_COMP_GROUP_ID_4 5 -#define CAM_ISP_RES_COMP_GROUP_ID_5 6 -#define CAM_ISP_RES_COMP_GROUP_ID_MAX 6 -#define CAM_ISP_PACKET_OP_BASE 0 -#define CAM_ISP_PACKET_INIT_DEV 1 -#define CAM_ISP_PACKET_UPDATE_DEV 2 -#define CAM_ISP_PACKET_OP_MAX 3 -#define CAM_ISP_PACKET_META_BASE 0 -#define CAM_ISP_PACKET_META_LEFT 1 -#define CAM_ISP_PACKET_META_RIGHT 2 -#define CAM_ISP_PACKET_META_COMMON 3 -#define CAM_ISP_PACKET_META_DMI_LEFT 4 -#define CAM_ISP_PACKET_META_DMI_RIGHT 5 -#define CAM_ISP_PACKET_META_DMI_COMMON 6 -#define CAM_ISP_PACKET_META_CLOCK 7 -#define CAM_ISP_PACKET_META_CSID 8 -#define CAM_ISP_PACKET_META_DUAL_CONFIG 9 -#define CAM_ISP_PACKET_META_GENERIC_BLOB_LEFT 10 -#define CAM_ISP_PACKET_META_GENERIC_BLOB_RIGHT 11 -#define CAM_ISP_PACKET_META_GENERIC_BLOB_COMMON 12 -#define CAM_ISP_DSP_MODE_NONE 0 -#define CAM_ISP_DSP_MODE_ONE_WAY 1 -#define CAM_ISP_DSP_MODE_ROUND 2 -#define CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG 0 -#define CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1 -#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG 2 -struct cam_isp_dev_cap_info { - uint32_t hw_type; - uint32_t reserved; - struct cam_hw_version hw_version; -}; -struct cam_isp_query_cap_cmd { - struct cam_iommu_handle device_iommu; - struct cam_iommu_handle cdm_iommu; - int32_t num_dev; - uint32_t reserved; - struct cam_isp_dev_cap_info dev_caps[CAM_ISP_HW_MAX]; -}; -struct cam_isp_out_port_info { - uint32_t res_type; - uint32_t format; - uint32_t width; - uint32_t height; - uint32_t comp_grp_id; - uint32_t split_point; - uint32_t secure_mode; - uint32_t reserved; -}; -struct cam_isp_in_port_info { - uint32_t res_type; - uint32_t lane_type; - uint32_t lane_num; - uint32_t lane_cfg; - uint32_t vc; - uint32_t dt; - uint32_t format; - uint32_t test_pattern; - uint32_t usage_type; - uint32_t left_start; - uint32_t left_stop; - uint32_t left_width; - uint32_t right_start; - uint32_t right_stop; - uint32_t right_width; - uint32_t line_start; - uint32_t line_stop; - uint32_t height; - uint32_t pixel_clk; - uint32_t batch_size; - uint32_t dsp_mode; - uint32_t hbi_cnt; - uint32_t reserved; - uint32_t num_out_res; - struct cam_isp_out_port_info data[1]; -}; -struct cam_isp_resource { - uint32_t resource_id; - uint32_t length; - uint32_t handle_type; - uint32_t reserved; - uint64_t res_hdl; -}; -struct cam_isp_port_hfr_config { - uint32_t resource_type; - uint32_t subsample_pattern; - uint32_t subsample_period; - uint32_t framedrop_pattern; - uint32_t framedrop_period; - uint32_t reserved; -} __attribute__((packed)); -struct cam_isp_resource_hfr_config { - uint32_t num_ports; - uint32_t reserved; - struct cam_isp_port_hfr_config port_hfr_config[1]; -} __attribute__((packed)); -struct cam_isp_dual_split_params { - uint32_t split_point; - uint32_t right_padding; - uint32_t left_padding; - uint32_t reserved; -}; -struct cam_isp_dual_stripe_config { - uint32_t offset; - uint32_t width; - uint32_t tileconfig; - uint32_t port_id; -}; -struct cam_isp_dual_config { - uint32_t num_ports; - uint32_t reserved; - struct cam_isp_dual_split_params split_params; - struct cam_isp_dual_stripe_config stripes[1]; -} __attribute__((packed)); -struct cam_isp_clock_config { - uint32_t usage_type; - uint32_t num_rdi; - uint64_t left_pix_hz; - uint64_t right_pix_hz; - uint64_t rdi_hz[1]; -} __attribute__((packed)); -struct cam_isp_bw_vote { - uint32_t resource_id; - uint32_t reserved; - uint64_t cam_bw_bps; - uint64_t ext_bw_bps; -} __attribute__((packed)); -struct cam_isp_bw_config { - uint32_t usage_type; - uint32_t num_rdi; - struct cam_isp_bw_vote left_pix_vote; - struct cam_isp_bw_vote right_pix_vote; - struct cam_isp_bw_vote rdi_vote[1]; -} __attribute__((packed)); -#endif - diff --git a/sdm710/kernel-headers/media/cam_isp_ife.h b/sdm710/kernel-headers/media/cam_isp_ife.h deleted file mode 100644 index 79fdace2..00000000 --- a/sdm710/kernel-headers/media/cam_isp_ife.h +++ /dev/null @@ -1,50 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_CAM_ISP_IFE_H__ -#define __UAPI_CAM_ISP_IFE_H__ -#define CAM_ISP_IFE_OUT_RES_BASE 0x3000 -#define CAM_ISP_IFE_OUT_RES_FULL (CAM_ISP_IFE_OUT_RES_BASE + 0) -#define CAM_ISP_IFE_OUT_RES_DS4 (CAM_ISP_IFE_OUT_RES_BASE + 1) -#define CAM_ISP_IFE_OUT_RES_DS16 (CAM_ISP_IFE_OUT_RES_BASE + 2) -#define CAM_ISP_IFE_OUT_RES_RAW_DUMP (CAM_ISP_IFE_OUT_RES_BASE + 3) -#define CAM_ISP_IFE_OUT_RES_FD (CAM_ISP_IFE_OUT_RES_BASE + 4) -#define CAM_ISP_IFE_OUT_RES_PDAF (CAM_ISP_IFE_OUT_RES_BASE + 5) -#define CAM_ISP_IFE_OUT_RES_RDI_0 (CAM_ISP_IFE_OUT_RES_BASE + 6) -#define CAM_ISP_IFE_OUT_RES_RDI_1 (CAM_ISP_IFE_OUT_RES_BASE + 7) -#define CAM_ISP_IFE_OUT_RES_RDI_2 (CAM_ISP_IFE_OUT_RES_BASE + 8) -#define CAM_ISP_IFE_OUT_RES_RDI_3 (CAM_ISP_IFE_OUT_RES_BASE + 9) -#define CAM_ISP_IFE_OUT_RES_STATS_HDR_BE (CAM_ISP_IFE_OUT_RES_BASE + 10) -#define CAM_ISP_IFE_OUT_RES_STATS_HDR_BHIST (CAM_ISP_IFE_OUT_RES_BASE + 11) -#define CAM_ISP_IFE_OUT_RES_STATS_TL_BG (CAM_ISP_IFE_OUT_RES_BASE + 12) -#define CAM_ISP_IFE_OUT_RES_STATS_BF (CAM_ISP_IFE_OUT_RES_BASE + 13) -#define CAM_ISP_IFE_OUT_RES_STATS_AWB_BG (CAM_ISP_IFE_OUT_RES_BASE + 14) -#define CAM_ISP_IFE_OUT_RES_STATS_BHIST (CAM_ISP_IFE_OUT_RES_BASE + 15) -#define CAM_ISP_IFE_OUT_RES_STATS_RS (CAM_ISP_IFE_OUT_RES_BASE + 16) -#define CAM_ISP_IFE_OUT_RES_STATS_CS (CAM_ISP_IFE_OUT_RES_BASE + 17) -#define CAM_ISP_IFE_OUT_RES_STATS_IHIST (CAM_ISP_IFE_OUT_RES_BASE + 18) -#define CAM_ISP_IFE_OUT_RES_MAX (CAM_ISP_IFE_OUT_RES_BASE + 19) -#define CAM_ISP_IFE_IN_RES_BASE 0x4000 -#define CAM_ISP_IFE_IN_RES_TPG (CAM_ISP_IFE_IN_RES_BASE + 0) -#define CAM_ISP_IFE_IN_RES_PHY_0 (CAM_ISP_IFE_IN_RES_BASE + 1) -#define CAM_ISP_IFE_IN_RES_PHY_1 (CAM_ISP_IFE_IN_RES_BASE + 2) -#define CAM_ISP_IFE_IN_RES_PHY_2 (CAM_ISP_IFE_IN_RES_BASE + 3) -#define CAM_ISP_IFE_IN_RES_PHY_3 (CAM_ISP_IFE_IN_RES_BASE + 4) -#define CAM_ISP_IFE_IN_RES_MAX (CAM_ISP_IFE_IN_RES_BASE + 5) -#endif - diff --git a/sdm710/kernel-headers/media/cam_isp_vfe.h b/sdm710/kernel-headers/media/cam_isp_vfe.h deleted file mode 100644 index cc64ab49..00000000 --- a/sdm710/kernel-headers/media/cam_isp_vfe.h +++ /dev/null @@ -1,56 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_CAM_ISP_VFE_H__ -#define __UAPI_CAM_ISP_VFE_H__ -#define CAM_ISP_VFE_OUT_RES_BASE 0x1000 -#define CAM_ISP_VFE_OUT_RES_ENC (CAM_ISP_VFE_OUT_RES_BASE + 0) -#define CAM_ISP_VFE_OUT_RES_VIEW (CAM_ISP_VFE_OUT_RES_BASE + 1) -#define CAM_ISP_VFE_OUT_RES_VID (CAM_ISP_VFE_OUT_RES_BASE + 2) -#define CAM_ISP_VFE_OUT_RES_RDI_0 (CAM_ISP_VFE_OUT_RES_BASE + 3) -#define CAM_ISP_VFE_OUT_RES_RDI_1 (CAM_ISP_VFE_OUT_RES_BASE + 4) -#define CAM_ISP_VFE_OUT_RES_RDI_2 (CAM_ISP_VFE_OUT_RES_BASE + 5) -#define CAM_ISP_VFE_OUT_RES_RDI_3 (CAM_ISP_VFE_OUT_RES_BASE + 6) -#define CAM_ISP_VFE_OUT_RES_STATS_AEC (CAM_ISP_VFE_OUT_RES_BASE + 7) -#define CAM_ISP_VFE_OUT_RES_STATS_AF (CAM_ISP_VFE_OUT_RES_BASE + 8) -#define CAM_ISP_VFE_OUT_RES_STATS_AWB (CAM_ISP_VFE_OUT_RES_BASE + 9) -#define CAM_ISP_VFE_OUT_RES_STATS_RS (CAM_ISP_VFE_OUT_RES_BASE + 10) -#define CAM_ISP_VFE_OUT_RES_STATS_CS (CAM_ISP_VFE_OUT_RES_BASE + 11) -#define CAM_ISP_VFE_OUT_RES_STATS_IHIST (CAM_ISP_VFE_OUT_RES_BASE + 12) -#define CAM_ISP_VFE_OUT_RES_STATS_SKIN (CAM_ISP_VFE_OUT_RES_BASE + 13) -#define CAM_ISP_VFE_OUT_RES_STATS_BG (CAM_ISP_VFE_OUT_RES_BASE + 14) -#define CAM_ISP_VFE_OUT_RES_STATS_BF (CAM_ISP_VFE_OUT_RES_BASE + 15) -#define CAM_ISP_VFE_OUT_RES_STATS_BE (CAM_ISP_VFE_OUT_RES_BASE + 16) -#define CAM_ISP_VFE_OUT_RES_STATS_BHIST (CAM_ISP_VFE_OUT_RES_BASE + 17) -#define CAM_ISP_VFE_OUT_RES_STATS_BF_SCALE (CAM_ISP_VFE_OUT_RES_BASE + 18) -#define CAM_ISP_VFE_OUT_RES_STATS_HDR_BE (CAM_ISP_VFE_OUT_RES_BASE + 19) -#define CAM_ISP_VFE_OUT_RES_STATS_HDR_BHIST (CAM_ISP_VFE_OUT_RES_BASE + 20) -#define CAM_ISP_VFE_OUT_RES_STATS_AEC_BG (CAM_ISP_VFE_OUT_RES_BASE + 21) -#define CAM_ISP_VFE_OUT_RES_CAMIF_RAW (CAM_ISP_VFE_OUT_RES_BASE + 22) -#define CAM_ISP_VFE_OUT_RES_IDEAL_RAW (CAM_ISP_VFE_OUT_RES_BASE + 23) -#define CAM_ISP_VFE_OUT_RES_MAX (CAM_ISP_VFE_OUT_RES_BASE + 24) -#define CAM_ISP_VFE_IN_RES_BASE 0x2000 -#define CAM_ISP_VFE_IN_RES_TPG (CAM_ISP_VFE_IN_RES_BASE + 0) -#define CAM_ISP_VFE_IN_RES_PHY_0 (CAM_ISP_VFE_IN_RES_BASE + 1) -#define CAM_ISP_VFE_IN_RES_PHY_1 (CAM_ISP_VFE_IN_RES_BASE + 2) -#define CAM_ISP_VFE_IN_RES_PHY_2 (CAM_ISP_VFE_IN_RES_BASE + 3) -#define CAM_ISP_VFE_IN_RES_PHY_3 (CAM_ISP_VFE_IN_RES_BASE + 4) -#define CAM_ISP_VFE_IN_RES_FE (CAM_ISP_VFE_IN_RES_BASE + 5) -#define CAM_ISP_VFE_IN_RES_MAX (CAM_ISP_VFE_IN_RES_BASE + 6) -#endif - diff --git a/sdm710/kernel-headers/media/cam_jpeg.h b/sdm710/kernel-headers/media/cam_jpeg.h deleted file mode 100644 index ac874117..00000000 --- a/sdm710/kernel-headers/media/cam_jpeg.h +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_CAM_JPEG_H__ -#define __UAPI_CAM_JPEG_H__ -#include "cam_defs.h" -#define CAM_JPEG_DEV_TYPE_ENC 0 -#define CAM_JPEG_DEV_TYPE_DMA 1 -#define CAM_JPEG_DEV_TYPE_MAX 2 -#define CAM_JPEG_NUM_DEV_PER_RES_MAX 1 -#define CAM_JPEG_RES_TYPE_ENC 0 -#define CAM_JPEG_RES_TYPE_DMA 1 -#define CAM_JPEG_RES_TYPE_MAX 2 -#define CAM_JPEG_OPCODE_ENC_UPDATE 0 -#define CAM_JPEG_OPCODE_DMA_UPDATE 1 -#define CAM_JPEG_ENC_INPUT_IMAGE 0x0 -#define CAM_JPEG_ENC_OUTPUT_IMAGE 0x1 -#define CAM_JPEG_ENC_IO_IMAGES_MAX 0x2 -#define CAM_JPEG_DMA_INPUT_IMAGE 0x0 -#define CAM_JPEG_DMA_OUTPUT_IMAGE 0x1 -#define CAM_JPEG_DMA_IO_IMAGES_MAX 0x2 -#define CAM_JPEG_IMAGE_MAX 0x2 -struct cam_jpeg_dev_ver { - uint32_t size; - uint32_t dev_type; - struct cam_hw_version hw_ver; -}; -struct cam_jpeg_query_cap_cmd { - struct cam_iommu_handle dev_iommu_handle; - struct cam_iommu_handle cdm_iommu_handle; - uint32_t num_enc; - uint32_t num_dma; - struct cam_jpeg_dev_ver dev_ver[CAM_JPEG_DEV_TYPE_MAX]; -}; -struct cam_jpeg_res_info { - uint32_t format; - uint32_t width; - uint32_t height; - uint32_t fps; -}; -struct cam_jpeg_acquire_dev_info { - uint32_t dev_type; - uint32_t reserved; - struct cam_jpeg_res_info in_res; - struct cam_jpeg_res_info out_res; -}; -struct cam_jpeg_config_inout_param_info { - int32_t clk_index; - int32_t output_size; -}; -#endif - diff --git a/sdm710/kernel-headers/media/cam_lrme.h b/sdm710/kernel-headers/media/cam_lrme.h deleted file mode 100644 index 8d1b52a6..00000000 --- a/sdm710/kernel-headers/media/cam_lrme.h +++ /dev/null @@ -1,60 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_CAM_LRME_H__ -#define __UAPI_CAM_LRME_H__ -#include "cam_defs.h" -enum CAM_LRME_IO_TYPE { - CAM_LRME_IO_TYPE_TAR, - CAM_LRME_IO_TYPE_REF, - CAM_LRME_IO_TYPE_RES, - CAM_LRME_IO_TYPE_DS2, -}; -#define CAM_LRME_INPUT_PORT_TYPE_TAR (1 << 0) -#define CAM_LRME_INPUT_PORT_TYPE_REF (1 << 1) -#define CAM_LRME_OUTPUT_PORT_TYPE_DS2 (1 << 0) -#define CAM_LRME_OUTPUT_PORT_TYPE_RES (1 << 1) -#define CAM_LRME_DEV_MAX 1 -struct cam_lrme_hw_version { - uint32_t gen; - uint32_t rev; - uint32_t step; -}; -struct cam_lrme_dev_cap { - struct cam_lrme_hw_version clc_hw_version; - struct cam_lrme_hw_version bus_rd_hw_version; - struct cam_lrme_hw_version bus_wr_hw_version; - struct cam_lrme_hw_version top_hw_version; - struct cam_lrme_hw_version top_titan_version; -}; -struct cam_lrme_query_cap_cmd { - struct cam_iommu_handle device_iommu; - struct cam_iommu_handle cdm_iommu; - uint32_t num_devices; - struct cam_lrme_dev_cap dev_caps[CAM_LRME_DEV_MAX]; -}; -struct cam_lrme_soc_info { - uint64_t clock_rate; - uint64_t bandwidth; - uint64_t reserved[4]; -}; -struct cam_lrme_acquire_args { - struct cam_lrme_soc_info lrme_soc_info; -}; -#endif - diff --git a/sdm710/kernel-headers/media/cam_req_mgr.h b/sdm710/kernel-headers/media/cam_req_mgr.h deleted file mode 100644 index d0698eac..00000000 --- a/sdm710/kernel-headers/media/cam_req_mgr.h +++ /dev/null @@ -1,217 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_LINUX_CAM_REQ_MGR_H -#define __UAPI_LINUX_CAM_REQ_MGR_H -#include <linux/videodev2.h> -#include <linux/types.h> -#include <linux/ioctl.h> -#include <linux/media.h> -#include <media/cam_defs.h> -#define CAM_REQ_MGR_VNODE_NAME "cam-req-mgr-devnode" -#define CAM_DEVICE_TYPE_BASE (MEDIA_ENT_F_OLD_BASE) -#define CAM_VNODE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE) -#define CAM_SENSOR_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 1) -#define CAM_IFE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 2) -#define CAM_ICP_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 3) -#define CAM_LRME_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 4) -#define CAM_JPEG_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 5) -#define CAM_FD_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 6) -#define CAM_CPAS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 7) -#define CAM_CSIPHY_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 8) -#define CAM_ACTUATOR_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 9) -#define CAM_CCI_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 10) -#define CAM_FLASH_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 11) -#define CAM_EEPROM_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 12) -#define CAM_OIS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 13) -#define CAM_REQ_MGR_HDL_IDX_POS 8 -#define CAM_REQ_MGR_HDL_IDX_MASK ((1 << CAM_REQ_MGR_HDL_IDX_POS) - 1) -#define CAM_REQ_MGR_GET_HDL_IDX(hdl) (hdl & CAM_REQ_MGR_HDL_IDX_MASK) -#define CAM_REQ_MGR_MAX_HANDLES 64 -#define MAX_LINKS_PER_SESSION 2 -#define V4L_EVENT_CAM_REQ_MGR_EVENT (V4L2_EVENT_PRIVATE_START + 0) -#define V4L_EVENT_CAM_REQ_MGR_SOF 0 -#define V4L_EVENT_CAM_REQ_MGR_ERROR 1 -#define V4L_EVENT_CAM_REQ_MGR_SOF_BOOT_TS 2 -#define V4L_EVENT_CAM_REQ_MGR_MAX 3 -#define CAM_REQ_MGR_SOF_EVENT_SUCCESS 0 -#define CAM_REQ_MGR_SOF_EVENT_ERROR 1 -#define CAM_REQ_MGR_LINK_ACTIVATE 0 -#define CAM_REQ_MGR_LINK_DEACTIVATE 1 -#define CAM_REQ_MGR_FLUSH_TYPE_ALL 0 -#define CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ 1 -#define CAM_REQ_MGR_FLUSH_TYPE_MAX 2 -#define CAM_REQ_MGR_SYNC_MODE_NO_SYNC 0 -#define CAM_REQ_MGR_SYNC_MODE_SYNC 1 -struct cam_req_mgr_event_data { - int32_t session_hdl; - int32_t link_hdl; - int32_t frame_id; - int32_t reserved; - int64_t req_id; - uint64_t tv_sec; - uint64_t tv_usec; -}; -struct cam_req_mgr_session_info { - int32_t session_hdl; - int32_t reserved; -}; -struct cam_req_mgr_link_info { - int32_t session_hdl; - uint32_t num_devices; - int32_t dev_hdls[CAM_REQ_MGR_MAX_HANDLES]; - int32_t link_hdl; -}; -struct cam_req_mgr_unlink_info { - int32_t session_hdl; - int32_t link_hdl; -}; -struct cam_req_mgr_flush_info { - int32_t session_hdl; - int32_t link_hdl; - uint32_t flush_type; - uint32_t reserved; - int64_t req_id; -}; -struct cam_req_mgr_sched_request { - int32_t session_hdl; - int32_t link_hdl; - int32_t bubble_enable; - int32_t sync_mode; - int64_t req_id; -}; -struct cam_req_mgr_sync_mode { - int32_t session_hdl; - int32_t sync_mode; - int32_t num_links; - int32_t link_hdls[MAX_LINKS_PER_SESSION]; - int32_t master_link_hdl; - int32_t reserved; -}; -struct cam_req_mgr_link_control { - int32_t ops; - int32_t session_hdl; - int32_t num_links; - int32_t reserved; - int32_t link_hdls[MAX_LINKS_PER_SESSION]; -}; -#define CAM_REQ_MGR_CREATE_DEV_NODES (CAM_COMMON_OPCODE_MAX + 1) -#define CAM_REQ_MGR_CREATE_SESSION (CAM_COMMON_OPCODE_MAX + 2) -#define CAM_REQ_MGR_DESTROY_SESSION (CAM_COMMON_OPCODE_MAX + 3) -#define CAM_REQ_MGR_LINK (CAM_COMMON_OPCODE_MAX + 4) -#define CAM_REQ_MGR_UNLINK (CAM_COMMON_OPCODE_MAX + 5) -#define CAM_REQ_MGR_SCHED_REQ (CAM_COMMON_OPCODE_MAX + 6) -#define CAM_REQ_MGR_FLUSH_REQ (CAM_COMMON_OPCODE_MAX + 7) -#define CAM_REQ_MGR_SYNC_MODE (CAM_COMMON_OPCODE_MAX + 8) -#define CAM_REQ_MGR_ALLOC_BUF (CAM_COMMON_OPCODE_MAX + 9) -#define CAM_REQ_MGR_MAP_BUF (CAM_COMMON_OPCODE_MAX + 10) -#define CAM_REQ_MGR_RELEASE_BUF (CAM_COMMON_OPCODE_MAX + 11) -#define CAM_REQ_MGR_CACHE_OPS (CAM_COMMON_OPCODE_MAX + 12) -#define CAM_REQ_MGR_LINK_CONTROL (CAM_COMMON_OPCODE_MAX + 13) -#define CAM_MEM_FLAG_HW_READ_WRITE (1 << 0) -#define CAM_MEM_FLAG_HW_READ_ONLY (1 << 1) -#define CAM_MEM_FLAG_HW_WRITE_ONLY (1 << 2) -#define CAM_MEM_FLAG_KMD_ACCESS (1 << 3) -#define CAM_MEM_FLAG_UMD_ACCESS (1 << 4) -#define CAM_MEM_FLAG_PROTECTED_MODE (1 << 5) -#define CAM_MEM_FLAG_CMD_BUF_TYPE (1 << 6) -#define CAM_MEM_FLAG_PIXEL_BUF_TYPE (1 << 7) -#define CAM_MEM_FLAG_STATS_BUF_TYPE (1 << 8) -#define CAM_MEM_FLAG_PACKET_BUF_TYPE (1 << 9) -#define CAM_MEM_FLAG_CACHE (1 << 10) -#define CAM_MEM_FLAG_HW_SHARED_ACCESS (1 << 11) -#define CAM_MEM_MMU_MAX_HANDLE 16 -#define CAM_MEM_BUFQ_MAX 1024 -#define CAM_MEM_MGR_SECURE_BIT_POS 15 -#define CAM_MEM_MGR_HDL_IDX_SIZE 15 -#define CAM_MEM_MGR_HDL_FD_SIZE 16 -#define CAM_MEM_MGR_HDL_IDX_END_POS 16 -#define CAM_MEM_MGR_HDL_FD_END_POS 32 -#define CAM_MEM_MGR_HDL_IDX_MASK ((1 << CAM_MEM_MGR_HDL_IDX_SIZE) - 1) -#define GET_MEM_HANDLE(idx,fd) ((idx & CAM_MEM_MGR_HDL_IDX_MASK) | (fd << (CAM_MEM_MGR_HDL_FD_END_POS - CAM_MEM_MGR_HDL_FD_SIZE))) -#define CAM_MEM_MGR_GET_HDL_IDX(hdl) (hdl & CAM_MEM_MGR_HDL_IDX_MASK) -#define CAM_MEM_MGR_SET_SECURE_HDL(hdl,flag) ((flag) ? (hdl |= (1 << CAM_MEM_MGR_SECURE_BIT_POS)) : ((hdl) &= ~(1 << CAM_MEM_MGR_SECURE_BIT_POS))) -#define CAM_MEM_MGR_IS_SECURE_HDL(hdl) (((hdl) & (1 << CAM_MEM_MGR_SECURE_BIT_POS)) >> CAM_MEM_MGR_SECURE_BIT_POS) -#define CAM_MEM_DMA_NONE 0 -#define CAM_MEM_DMA_BIDIRECTIONAL 1 -#define CAM_MEM_DMA_TO_DEVICE 2 -#define CAM_MEM_DMA_FROM_DEVICE 3 -#define CAM_MEM_CLEAN_CACHE 1 -#define CAM_MEM_INV_CACHE 2 -#define CAM_MEM_CLEAN_INV_CACHE 3 -struct cam_mem_alloc_out_params { - uint32_t buf_handle; - int32_t fd; - uint64_t vaddr; -}; -struct cam_mem_map_out_params { - uint32_t buf_handle; - uint32_t reserved; - uint64_t vaddr; -}; -struct cam_mem_mgr_alloc_cmd { - uint64_t len; - uint64_t align; - int32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE]; - uint32_t num_hdl; - uint32_t flags; - struct cam_mem_alloc_out_params out; -}; -struct cam_mem_mgr_map_cmd { - int32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE]; - uint32_t num_hdl; - uint32_t flags; - int32_t fd; - uint32_t reserved; - struct cam_mem_map_out_params out; -}; -struct cam_mem_mgr_release_cmd { - int32_t buf_handle; - uint32_t reserved; -}; -struct cam_mem_cache_ops_cmd { - int32_t buf_handle; - uint32_t mem_cache_ops; -}; -#define CAM_REQ_MGR_ERROR_TYPE_DEVICE 0 -#define CAM_REQ_MGR_ERROR_TYPE_REQUEST 1 -#define CAM_REQ_MGR_ERROR_TYPE_BUFFER 2 -struct cam_req_mgr_error_msg { - uint32_t error_type; - uint32_t request_id; - int32_t device_hdl; - int32_t link_hdl; - uint64_t resource_size; -}; -struct cam_req_mgr_frame_msg { - uint64_t request_id; - uint64_t frame_id; - uint64_t timestamp; - int32_t link_hdl; - uint32_t sof_status; -}; -struct cam_req_mgr_message { - int32_t session_hdl; - int32_t reserved; - union { - struct cam_req_mgr_error_msg err_msg; - struct cam_req_mgr_frame_msg frame_msg; - } u; -}; -#endif - diff --git a/sdm710/kernel-headers/media/cam_sensor.h b/sdm710/kernel-headers/media/cam_sensor.h deleted file mode 100644 index 309c66ad..00000000 --- a/sdm710/kernel-headers/media/cam_sensor.h +++ /dev/null @@ -1,239 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_CAM_SENSOR_H__ -#define __UAPI_CAM_SENSOR_H__ -#include <linux/types.h> -#include <linux/ioctl.h> -#include <media/cam_defs.h> -#define CAM_SENSOR_PROBE_CMD (CAM_COMMON_OPCODE_MAX + 1) -#define CAM_FLASH_MAX_LED_TRIGGERS 3 -#define MAX_OIS_NAME_SIZE 32 -#define CAM_CSIPHY_SECURE_MODE_ENABLED 1 -#define MAX_RAINBOW_CONFIG_SIZE 32 -enum rainbow_op_type { - RAINBOW_SEQ_READ, - RAINBOW_RANDOM_READ, - RAINBOW_SEQ_WRITE, - RAINBOW_RANDOM_WRITE -}; -struct rainbow_config { - enum rainbow_op_type operation; - uint32_t size; - uint32_t reg_addr[MAX_RAINBOW_CONFIG_SIZE]; - uint32_t reg_data[MAX_RAINBOW_CONFIG_SIZE]; -} __attribute__((packed)); -#define RAINBOW_CONFIG _IOWR('R', 1, struct rainbow_config) -struct cam_sensor_query_cap { - uint32_t slot_info; - uint32_t secure_camera; - uint32_t pos_pitch; - uint32_t pos_roll; - uint32_t pos_yaw; - uint32_t actuator_slot_id; - uint32_t eeprom_slot_id; - uint32_t ois_slot_id; - uint32_t flash_slot_id; - uint32_t csiphy_slot_id; -} __attribute__((packed)); -struct cam_csiphy_query_cap { - uint32_t slot_info; - uint32_t version; - uint32_t clk_lane; - uint32_t reserved; -} __attribute__((packed)); -struct cam_actuator_query_cap { - uint32_t slot_info; - uint32_t reserved; -} __attribute__((packed)); -struct cam_eeprom_query_cap_t { - uint32_t slot_info; - uint16_t eeprom_kernel_probe; - uint16_t reserved; -} __attribute__((packed)); -struct cam_ois_query_cap_t { - uint32_t slot_info; - uint16_t reserved; -} __attribute__((packed)); -struct cam_cmd_i2c_info { - uint16_t slave_addr; - uint8_t i2c_freq_mode; - uint8_t cmd_type; -} __attribute__((packed)); -struct cam_cmd_get_ois_data { - uint32_t reg_addr; - uint32_t reg_data; - uint64_t query_size_handle; - uint64_t query_data_handle; -} __attribute__((packed)); -struct cam_ois_shift { - int16_t ois_shift_x; - int16_t ois_shift_y; - int64_t time_readout; -} __attribute__((packed)); -struct cam_ois_opcode { - uint32_t prog; - uint32_t coeff; - uint32_t pheripheral; - uint32_t memory; -} __attribute__((packed)); -struct cam_cmd_ois_info { - uint16_t slave_addr; - uint8_t i2c_freq_mode; - uint8_t cmd_type; - uint8_t ois_fw_flag; - uint8_t is_ois_calib; - char ois_name[MAX_OIS_NAME_SIZE]; - struct cam_ois_opcode opcode; -} __attribute__((packed)); -struct cam_cmd_probe { - uint8_t data_type; - uint8_t addr_type; - uint8_t op_code; - uint8_t cmd_type; - uint32_t reg_addr; - uint32_t expected_data; - uint32_t data_mask; - uint16_t camera_id; - uint8_t fw_update_flag; - uint16_t reserved; -} __attribute__((packed)); -struct cam_power_settings { - uint16_t power_seq_type; - uint16_t reserved; - uint32_t config_val_low; - uint32_t config_val_high; -} __attribute__((packed)); -struct cam_cmd_power { - uint16_t count; - uint8_t reserved; - uint8_t cmd_type; - struct cam_power_settings power_settings[1]; -} __attribute__((packed)); -struct i2c_rdwr_header { - uint16_t count; - uint8_t op_code; - uint8_t cmd_type; - uint8_t data_type; - uint8_t addr_type; - uint16_t slave_addr; -} __attribute__((packed)); -struct i2c_random_wr_payload { - uint32_t reg_addr; - uint32_t reg_data; -} __attribute__((packed)); -struct cam_cmd_i2c_random_wr { - struct i2c_rdwr_header header; - struct i2c_random_wr_payload random_wr_payload[1]; -} __attribute__((packed)); -struct cam_cmd_read { - uint32_t reg_data; - uint32_t reserved; -} __attribute__((packed)); -struct cam_cmd_i2c_continuous_wr { - struct i2c_rdwr_header header; - uint32_t reg_addr; - struct cam_cmd_read data_read[1]; -} __attribute__((packed)); -struct cam_cmd_i2c_random_rd { - struct i2c_rdwr_header header; - struct cam_cmd_read data_read[1]; -} __attribute__((packed)); -struct cam_cmd_i2c_continuous_rd { - struct i2c_rdwr_header header; - uint32_t reg_addr; -} __attribute__((packed)); -struct cam_cmd_conditional_wait { - uint8_t data_type; - uint8_t addr_type; - uint8_t op_code; - uint8_t cmd_type; - uint16_t timeout; - uint16_t reserved; - uint32_t reg_addr; - uint32_t reg_data; - uint32_t data_mask; -} __attribute__((packed)); -struct cam_cmd_unconditional_wait { - int16_t delay; - uint8_t op_code; - uint8_t cmd_type; -} __attribute__((packed)); -struct cam_csiphy_info { - uint16_t lane_mask; - uint16_t lane_assign; - uint8_t csiphy_3phase; - uint8_t combo_mode; - uint8_t lane_cnt; - uint8_t secure_mode; - uint64_t settle_time; - uint64_t data_rate; -} __attribute__((packed)); -struct cam_csiphy_acquire_dev_info { - uint32_t combo_mode; - uint32_t reserved; -} __attribute__((packed)); -struct cam_sensor_acquire_dev { - uint32_t session_handle; - uint32_t device_handle; - uint32_t handle_type; - uint32_t reserved; - uint64_t info_handle; -} __attribute__((packed)); -struct cam_sensor_streamon_dev { - uint32_t session_handle; - uint32_t device_handle; - uint32_t handle_type; - uint32_t reserved; - uint64_t info_handle; -} __attribute__((packed)); -struct cam_flash_init { - uint8_t flash_type; - uint16_t reserved; - uint8_t cmd_type; -} __attribute__((packed)); -struct cam_flash_set_rer { - uint16_t count; - uint8_t opcode; - uint8_t cmd_type; - uint16_t num_iteration; - uint16_t reserved; - uint32_t led_on_delay_ms; - uint32_t led_off_delay_ms; - uint32_t led_current_ma[CAM_FLASH_MAX_LED_TRIGGERS]; -} __attribute__((packed)); -struct cam_flash_set_on_off { - uint16_t count; - uint8_t opcode; - uint8_t cmd_type; - uint32_t led_current_ma[CAM_FLASH_MAX_LED_TRIGGERS]; -} __attribute__((packed)); -struct cam_flash_query_curr { - uint16_t reserved; - uint8_t opcode; - uint8_t cmd_type; - uint32_t query_current_ma; -} __attribute__((packed)); -struct cam_flash_query_cap_info { - uint32_t slot_info; - uint32_t max_current_flash[CAM_FLASH_MAX_LED_TRIGGERS]; - uint32_t max_duration_flash[CAM_FLASH_MAX_LED_TRIGGERS]; - uint32_t max_current_torch[CAM_FLASH_MAX_LED_TRIGGERS]; -} __attribute__((packed)); -#endif - diff --git a/sdm710/kernel-headers/media/cam_sync.h b/sdm710/kernel-headers/media/cam_sync.h deleted file mode 100644 index 365ffd7e..00000000 --- a/sdm710/kernel-headers/media/cam_sync.h +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_CAM_SYNC_H__ -#define __UAPI_CAM_SYNC_H__ -#include <linux/videodev2.h> -#include <linux/types.h> -#include <linux/ioctl.h> -#include <linux/media.h> -#define CAM_SYNC_DEVICE_NAME "cam_sync_device" -#define CAM_SYNC_V4L_EVENT (V4L2_EVENT_PRIVATE_START + 0) -#define CAM_SYNC_V4L_EVENT_ID_CB_TRIG 0 -#define CAM_SYNC_USER_PAYLOAD_SIZE 2 -#define CAM_SYNC_DEVICE_TYPE (MEDIA_ENT_F_OLD_BASE) -#define CAM_SYNC_GET_PAYLOAD_PTR(ev,type) (type *) ((char *) ev.u.data + sizeof(struct cam_sync_ev_header)) -#define CAM_SYNC_GET_HEADER_PTR(ev) ((struct cam_sync_ev_header *) ev.u.data) -#define CAM_SYNC_STATE_INVALID 0 -#define CAM_SYNC_STATE_ACTIVE 1 -#define CAM_SYNC_STATE_SIGNALED_SUCCESS 2 -#define CAM_SYNC_STATE_SIGNALED_ERROR 3 -struct cam_sync_ev_header { - int32_t sync_obj; - int32_t status; -}; -struct cam_sync_info { - char name[64]; - int32_t sync_obj; -}; -struct cam_sync_signal { - int32_t sync_obj; - uint32_t sync_state; -}; -struct cam_sync_merge { - __u64 sync_objs; - uint32_t num_objs; - int32_t merged; -}; -struct cam_sync_userpayload_info { - int32_t sync_obj; - uint32_t reserved; - __u64 payload[CAM_SYNC_USER_PAYLOAD_SIZE]; -}; -struct cam_sync_wait { - int32_t sync_obj; - uint32_t reserved; - uint64_t timeout_ms; -}; -struct cam_private_ioctl_arg { - __u32 id; - __u32 size; - __u32 result; - __u32 reserved; - __u64 ioctl_ptr; -}; -#define CAM_PRIVATE_IOCTL_CMD _IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_private_ioctl_arg) -#define CAM_SYNC_CREATE 0 -#define CAM_SYNC_DESTROY 1 -#define CAM_SYNC_SIGNAL 2 -#define CAM_SYNC_MERGE 3 -#define CAM_SYNC_REGISTER_PAYLOAD 4 -#define CAM_SYNC_DEREGISTER_PAYLOAD 5 -#define CAM_SYNC_WAIT 6 -#endif - diff --git a/sdm710/kernel-headers/media/msm_cam_sensor.h b/sdm710/kernel-headers/media/msm_cam_sensor.h deleted file mode 100644 index fbb50849..00000000 --- a/sdm710/kernel-headers/media/msm_cam_sensor.h +++ /dev/null @@ -1,540 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_LINUX_MSM_CAM_SENSOR_H -#define __UAPI_LINUX_MSM_CAM_SENSOR_H -#include <linux/v4l2-mediabus.h> -#include <media/msm_camsensor_sdk.h> -#include <linux/types.h> -#include <linux/i2c.h> -#define I2C_SEQ_REG_SETTING_MAX 5 -#define MSM_SENSOR_MCLK_8HZ 8000000 -#define MSM_SENSOR_MCLK_16HZ 16000000 -#define MSM_SENSOR_MCLK_24HZ 24000000 -#define MAX_SENSOR_NAME 32 -#define MAX_ACTUATOR_AF_TOTAL_STEPS 1024 -#define MAX_OIS_MOD_NAME_SIZE 32 -#define MAX_OIS_NAME_SIZE 32 -#define MAX_OIS_REG_SETTINGS 800 -#define MOVE_NEAR 0 -#define MOVE_FAR 1 -#define MSM_ACTUATOR_MOVE_SIGNED_FAR - 1 -#define MSM_ACTUATOR_MOVE_SIGNED_NEAR 1 -#define MAX_ACTUATOR_REGION 5 -#define MAX_EEPROM_NAME 32 -#define MAX_AF_ITERATIONS 3 -#define MAX_NUMBER_OF_STEPS 47 -#define MAX_REGULATOR 5 -#define FLASH_QUERY_CURRENT 1 -#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') -#define MSM_V4L2_PIX_FMT_META10 v4l2_fourcc('M', 'E', '1', '0') -#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') -#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') -#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') -#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') -enum flash_type { - LED_FLASH = 1, - STROBE_FLASH, - GPIO_FLASH -}; -enum msm_sensor_resolution_t { - MSM_SENSOR_RES_FULL, - MSM_SENSOR_RES_QTR, - MSM_SENSOR_RES_2, - MSM_SENSOR_RES_3, - MSM_SENSOR_RES_4, - MSM_SENSOR_RES_5, - MSM_SENSOR_RES_6, - MSM_SENSOR_RES_7, - MSM_SENSOR_INVALID_RES, -}; -enum msm_camera_stream_type_t { - MSM_CAMERA_STREAM_PREVIEW, - MSM_CAMERA_STREAM_SNAPSHOT, - MSM_CAMERA_STREAM_VIDEO, - MSM_CAMERA_STREAM_INVALID, -}; -enum sensor_sub_module_t { - SUB_MODULE_SENSOR, - SUB_MODULE_CHROMATIX, - SUB_MODULE_ACTUATOR, - SUB_MODULE_EEPROM, - SUB_MODULE_LED_FLASH, - SUB_MODULE_STROBE_FLASH, - SUB_MODULE_CSID, - SUB_MODULE_CSID_3D, - SUB_MODULE_CSIPHY, - SUB_MODULE_CSIPHY_3D, - SUB_MODULE_OIS, - SUB_MODULE_EXT, - SUB_MODULE_IR_LED, - SUB_MODULE_IR_CUT, - SUB_MODULE_LASER_LED, - SUB_MODULE_MAX, -}; -enum { - MSM_CAMERA_EFFECT_MODE_OFF, - MSM_CAMERA_EFFECT_MODE_MONO, - MSM_CAMERA_EFFECT_MODE_NEGATIVE, - MSM_CAMERA_EFFECT_MODE_SOLARIZE, - MSM_CAMERA_EFFECT_MODE_SEPIA, - MSM_CAMERA_EFFECT_MODE_POSTERIZE, - MSM_CAMERA_EFFECT_MODE_WHITEBOARD, - MSM_CAMERA_EFFECT_MODE_BLACKBOARD, - MSM_CAMERA_EFFECT_MODE_AQUA, - MSM_CAMERA_EFFECT_MODE_EMBOSS, - MSM_CAMERA_EFFECT_MODE_SKETCH, - MSM_CAMERA_EFFECT_MODE_NEON, - MSM_CAMERA_EFFECT_MODE_MAX -}; -enum { - MSM_CAMERA_WB_MODE_AUTO, - MSM_CAMERA_WB_MODE_CUSTOM, - MSM_CAMERA_WB_MODE_INCANDESCENT, - MSM_CAMERA_WB_MODE_FLUORESCENT, - MSM_CAMERA_WB_MODE_WARM_FLUORESCENT, - MSM_CAMERA_WB_MODE_DAYLIGHT, - MSM_CAMERA_WB_MODE_CLOUDY_DAYLIGHT, - MSM_CAMERA_WB_MODE_TWILIGHT, - MSM_CAMERA_WB_MODE_SHADE, - MSM_CAMERA_WB_MODE_OFF, - MSM_CAMERA_WB_MODE_MAX -}; -enum { - MSM_CAMERA_SCENE_MODE_OFF, - MSM_CAMERA_SCENE_MODE_AUTO, - MSM_CAMERA_SCENE_MODE_LANDSCAPE, - MSM_CAMERA_SCENE_MODE_SNOW, - MSM_CAMERA_SCENE_MODE_BEACH, - MSM_CAMERA_SCENE_MODE_SUNSET, - MSM_CAMERA_SCENE_MODE_NIGHT, - MSM_CAMERA_SCENE_MODE_PORTRAIT, - MSM_CAMERA_SCENE_MODE_BACKLIGHT, - MSM_CAMERA_SCENE_MODE_SPORTS, - MSM_CAMERA_SCENE_MODE_ANTISHAKE, - MSM_CAMERA_SCENE_MODE_FLOWERS, - MSM_CAMERA_SCENE_MODE_CANDLELIGHT, - MSM_CAMERA_SCENE_MODE_FIREWORKS, - MSM_CAMERA_SCENE_MODE_PARTY, - MSM_CAMERA_SCENE_MODE_NIGHT_PORTRAIT, - MSM_CAMERA_SCENE_MODE_THEATRE, - MSM_CAMERA_SCENE_MODE_ACTION, - MSM_CAMERA_SCENE_MODE_AR, - MSM_CAMERA_SCENE_MODE_FACE_PRIORITY, - MSM_CAMERA_SCENE_MODE_BARCODE, - MSM_CAMERA_SCENE_MODE_HDR, - MSM_CAMERA_SCENE_MODE_MAX -}; -enum csid_cfg_type_t { - CSID_INIT, - CSID_CFG, - CSID_TESTMODE_CFG, - CSID_RELEASE, -}; -enum csiphy_cfg_type_t { - CSIPHY_INIT, - CSIPHY_CFG, - CSIPHY_RELEASE, -}; -enum camera_vreg_type { - VREG_TYPE_DEFAULT, - VREG_TYPE_CUSTOM, -}; -enum sensor_af_t { - SENSOR_AF_FOCUSSED, - SENSOR_AF_NOT_FOCUSSED, -}; -enum cci_i2c_master_t { - MASTER_0, - MASTER_1, - MASTER_MAX, -}; -struct msm_camera_i2c_array_write_config { - struct msm_camera_i2c_reg_setting conf_array; - uint16_t slave_addr; -}; -struct msm_camera_i2c_read_config { - uint16_t slave_addr; - uint16_t reg_addr; - enum msm_camera_i2c_reg_addr_type addr_type; - enum msm_camera_i2c_data_type data_type; - uint16_t data; -}; -struct msm_camera_csi2_params { - struct msm_camera_csid_params csid_params; - struct msm_camera_csiphy_params csiphy_params; - uint8_t csi_clk_scale_enable; -}; -struct msm_camera_csi_lane_params { - uint16_t csi_lane_assign; - uint16_t csi_lane_mask; -}; -struct csi_lane_params_t { - uint16_t csi_lane_assign; - uint8_t csi_lane_mask; - uint8_t csi_if; - int8_t csid_core[2]; - uint8_t csi_phy_sel; -}; -struct msm_sensor_info_t { - char sensor_name[MAX_SENSOR_NAME]; - uint32_t session_id; - int32_t subdev_id[SUB_MODULE_MAX]; - int32_t subdev_intf[SUB_MODULE_MAX]; - uint8_t is_mount_angle_valid; - uint32_t sensor_mount_angle; - int modes_supported; - enum camb_position_t position; -}; -struct camera_vreg_t { - const char * reg_name; - int min_voltage; - int max_voltage; - int op_mode; - uint32_t delay; - const char * custom_vreg_name; - enum camera_vreg_type type; -}; -struct sensorb_cfg_data { - int cfgtype; - union { - struct msm_sensor_info_t sensor_info; - struct msm_sensor_init_params sensor_init_params; - void * setting; - struct msm_sensor_i2c_sync_params sensor_i2c_sync_params; - } cfg; -}; -struct csid_cfg_data { - enum csid_cfg_type_t cfgtype; - union { - uint32_t csid_version; - struct msm_camera_csid_params * csid_params; - struct msm_camera_csid_testmode_parms * csid_testmode_params; - } cfg; -}; -struct csiphy_cfg_data { - enum csiphy_cfg_type_t cfgtype; - union { - struct msm_camera_csiphy_params * csiphy_params; - struct msm_camera_csi_lane_params * csi_lane_params; - } cfg; -}; -enum eeprom_cfg_type_t { - CFG_EEPROM_GET_INFO, - CFG_EEPROM_GET_CAL_DATA, - CFG_EEPROM_READ_CAL_DATA, - CFG_EEPROM_WRITE_DATA, - CFG_EEPROM_GET_MM_INFO, - CFG_EEPROM_INIT, -}; -struct eeprom_get_t { - uint32_t num_bytes; -}; -struct eeprom_read_t { - uint8_t * dbuffer; - uint32_t num_bytes; -}; -struct eeprom_write_t { - uint8_t * dbuffer; - uint32_t num_bytes; -}; -struct eeprom_get_cmm_t { - uint32_t cmm_support; - uint32_t cmm_compression; - uint32_t cmm_size; -}; -struct msm_eeprom_info_t { - struct msm_sensor_power_setting_array * power_setting_array; - enum i2c_freq_mode_t i2c_freq_mode; - struct msm_eeprom_memory_map_array * mem_map_array; -}; -struct msm_ir_led_cfg_data_t { - enum msm_ir_led_cfg_type_t cfg_type; - int32_t pwm_duty_on_ns; - int32_t pwm_period_ns; -}; -struct msm_ir_cut_cfg_data_t { - enum msm_ir_cut_cfg_type_t cfg_type; -}; -struct msm_laser_led_cfg_data_t { - enum msm_laser_led_cfg_type_t cfg_type; - void * setting; - void * debug_reg; - uint32_t debug_reg_size; - uint16_t i2c_addr; - enum i2c_freq_mode_t i2c_freq_mode; -}; -struct msm_eeprom_cfg_data { - enum eeprom_cfg_type_t cfgtype; - uint8_t is_supported; - union { - char eeprom_name[MAX_EEPROM_NAME]; - struct eeprom_get_t get_data; - struct eeprom_read_t read_data; - struct eeprom_write_t write_data; - struct eeprom_get_cmm_t get_cmm_data; - struct msm_eeprom_info_t eeprom_info; - } cfg; -}; -enum msm_sensor_cfg_type_t { - CFG_SET_SLAVE_INFO, - CFG_SLAVE_READ_I2C, - CFG_WRITE_I2C_ARRAY, - CFG_SLAVE_WRITE_I2C_ARRAY, - CFG_WRITE_I2C_SEQ_ARRAY, - CFG_POWER_UP, - CFG_POWER_DOWN, - CFG_SET_STOP_STREAM_SETTING, - CFG_GET_SENSOR_INFO, - CFG_GET_SENSOR_INIT_PARAMS, - CFG_SET_INIT_SETTING, - CFG_SET_RESOLUTION, - CFG_SET_STOP_STREAM, - CFG_SET_START_STREAM, - CFG_SET_SATURATION, - CFG_SET_CONTRAST, - CFG_SET_SHARPNESS, - CFG_SET_ISO, - CFG_SET_EXPOSURE_COMPENSATION, - CFG_SET_ANTIBANDING, - CFG_SET_BESTSHOT_MODE, - CFG_SET_EFFECT, - CFG_SET_WHITE_BALANCE, - CFG_SET_AUTOFOCUS, - CFG_CANCEL_AUTOFOCUS, - CFG_SET_STREAM_TYPE, - CFG_SET_I2C_SYNC_PARAM, - CFG_WRITE_I2C_ARRAY_ASYNC, - CFG_WRITE_I2C_ARRAY_SYNC, - CFG_WRITE_I2C_ARRAY_SYNC_BLOCK, -}; -enum msm_actuator_cfg_type_t { - CFG_GET_ACTUATOR_INFO, - CFG_SET_ACTUATOR_INFO, - CFG_SET_DEFAULT_FOCUS, - CFG_MOVE_FOCUS, - CFG_SET_POSITION, - CFG_ACTUATOR_POWERDOWN, - CFG_ACTUATOR_POWERUP, - CFG_ACTUATOR_INIT, -}; -struct msm_ois_opcode { - uint32_t prog; - uint32_t coeff; - uint32_t pheripheral; - uint32_t memory; -}; -enum msm_ois_cfg_type_t { - CFG_OIS_INIT, - CFG_OIS_POWERDOWN, - CFG_OIS_POWERUP, - CFG_OIS_CONTROL, - CFG_OIS_I2C_WRITE_SEQ_TABLE, -}; -enum msm_ois_cfg_download_type_t { - CFG_OIS_DOWNLOAD, - CFG_OIS_DATA_CONFIG, -}; -enum msm_ois_i2c_operation { - MSM_OIS_WRITE = 0, - MSM_OIS_POLL, - MSM_OIS_READ, -}; -#define MSM_OIS_READ MSM_OIS_READ -struct reg_settings_ois_t { - uint16_t reg_addr; - enum msm_camera_i2c_reg_addr_type addr_type; - uint32_t reg_data; - enum msm_camera_i2c_data_type data_type; - enum msm_ois_i2c_operation i2c_operation; - uint32_t delay; -}; -struct msm_ois_params_t { - uint16_t data_size; - uint16_t setting_size; - uint32_t i2c_addr; - enum i2c_freq_mode_t i2c_freq_mode; - enum msm_camera_i2c_reg_addr_type i2c_addr_type; - enum msm_camera_i2c_data_type i2c_data_type; - struct reg_settings_ois_t * settings; -}; -struct msm_ois_set_info_t { - struct msm_ois_params_t ois_params; -}; -struct msm_actuator_move_params_t { - int8_t dir; - int8_t sign_dir; - int16_t dest_step_pos; - int32_t num_steps; - uint16_t curr_lens_pos; - struct damping_params_t * ringing_params; -}; -struct msm_actuator_tuning_params_t { - int16_t initial_code; - uint16_t pwd_step; - uint16_t region_size; - uint32_t total_steps; - struct region_params_t * region_params; -}; -struct park_lens_data_t { - uint32_t damping_step; - uint32_t damping_delay; - uint32_t hw_params; - uint32_t max_step; -}; -struct msm_actuator_params_t { - enum actuator_type act_type; - uint8_t reg_tbl_size; - uint16_t data_size; - uint16_t init_setting_size; - uint32_t i2c_addr; - enum i2c_freq_mode_t i2c_freq_mode; - enum msm_camera_i2c_reg_addr_type i2c_addr_type; - enum msm_camera_i2c_data_type i2c_data_type; - struct msm_actuator_reg_params_t * reg_tbl_params; - struct reg_settings_t * init_settings; - struct park_lens_data_t park_lens; -}; -struct msm_actuator_set_info_t { - struct msm_actuator_params_t actuator_params; - struct msm_actuator_tuning_params_t af_tuning_params; -}; -struct msm_actuator_get_info_t { - uint32_t focal_length_num; - uint32_t focal_length_den; - uint32_t f_number_num; - uint32_t f_number_den; - uint32_t f_pix_num; - uint32_t f_pix_den; - uint32_t total_f_dist_num; - uint32_t total_f_dist_den; - uint32_t hor_view_angle_num; - uint32_t hor_view_angle_den; - uint32_t ver_view_angle_num; - uint32_t ver_view_angle_den; -}; -enum af_camera_name { - ACTUATOR_MAIN_CAM_0, - ACTUATOR_MAIN_CAM_1, - ACTUATOR_MAIN_CAM_2, - ACTUATOR_MAIN_CAM_3, - ACTUATOR_MAIN_CAM_4, - ACTUATOR_MAIN_CAM_5, - ACTUATOR_WEB_CAM_0, - ACTUATOR_WEB_CAM_1, - ACTUATOR_WEB_CAM_2, -}; -struct msm_ois_slave_info { - char ois_name[MAX_OIS_NAME_SIZE]; - uint32_t i2c_addr; - struct msm_ois_opcode opcode; -}; -struct msm_ois_cfg_data { - int cfgtype; - union { - struct msm_ois_set_info_t set_info; - struct msm_camera_i2c_seq_reg_setting * settings; - } cfg; -}; -struct msm_ois_cfg_download_data { - int cfgtype; - struct msm_ois_slave_info slave_info; -}; -struct msm_actuator_set_position_t { - uint16_t number_of_steps; - uint32_t hw_params; - uint16_t pos[MAX_NUMBER_OF_STEPS]; - uint16_t delay[MAX_NUMBER_OF_STEPS]; -}; -struct msm_actuator_cfg_data { - int cfgtype; - uint8_t is_af_supported; - union { - struct msm_actuator_move_params_t move; - struct msm_actuator_set_info_t set_info; - struct msm_actuator_get_info_t get_info; - struct msm_actuator_set_position_t setpos; - enum af_camera_name cam_name; - } cfg; -}; -enum msm_camera_led_config_t { - MSM_CAMERA_LED_OFF, - MSM_CAMERA_LED_LOW, - MSM_CAMERA_LED_HIGH, - MSM_CAMERA_LED_INIT, - MSM_CAMERA_LED_RELEASE, -}; -struct msm_camera_led_cfg_t { - enum msm_camera_led_config_t cfgtype; - int32_t torch_current[MAX_LED_TRIGGERS]; - int32_t flash_current[MAX_LED_TRIGGERS]; - int32_t flash_duration[MAX_LED_TRIGGERS]; -}; -struct msm_flash_init_info_t { - enum msm_flash_driver_type flash_driver_type; - uint32_t slave_addr; - enum i2c_freq_mode_t i2c_freq_mode; - struct msm_sensor_power_setting_array * power_setting_array; - struct msm_camera_i2c_reg_setting_array * settings; -}; -struct msm_flash_cfg_data_t { - enum msm_flash_cfg_type_t cfg_type; - int32_t flash_current[MAX_LED_TRIGGERS]; - int32_t flash_duration[MAX_LED_TRIGGERS]; - union { - struct msm_flash_init_info_t * flash_init_info; - struct msm_camera_i2c_reg_setting_array * settings; - } cfg; -}; -struct msm_flash_query_data_t { - int32_t flags; - int32_t query_type; - int32_t max_avail_curr; -}; -enum msm_sensor_init_cfg_type_t { - CFG_SINIT_PROBE, - CFG_SINIT_PROBE_DONE, - CFG_SINIT_PROBE_WAIT_DONE, -}; -struct sensor_init_cfg_data { - enum msm_sensor_init_cfg_type_t cfgtype; - struct msm_sensor_info_t probed_info; - char entity_name[MAX_SENSOR_NAME]; - union { - void * setting; - } cfg; -}; -#define VIDIOC_MSM_SENSOR_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data) -#define VIDIOC_MSM_SENSOR_RELEASE _IO('V', BASE_VIDIOC_PRIVATE + 2) -#define VIDIOC_MSM_SENSOR_GET_SUBDEV_ID _IOWR('V', BASE_VIDIOC_PRIVATE + 3, uint32_t) -#define VIDIOC_MSM_CSIPHY_IO_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data) -#define VIDIOC_MSM_CSID_IO_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data) -#define VIDIOC_MSM_ACTUATOR_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data) -#define VIDIOC_MSM_FLASH_LED_DATA_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_led_cfg_t) -#define VIDIOC_MSM_EEPROM_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data) -#define VIDIOC_MSM_SENSOR_GET_AF_STATUS _IOWR('V', BASE_VIDIOC_PRIVATE + 9, uint32_t) -#define VIDIOC_MSM_SENSOR_INIT_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data) -#define VIDIOC_MSM_OIS_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data) -#define VIDIOC_MSM_FLASH_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t) -#define VIDIOC_MSM_OIS_CFG_DOWNLOAD _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_ois_cfg_download_data) -#define VIDIOC_MSM_FLASH_QUERY_DATA _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_flash_query_data_t) -#define VIDIOC_MSM_IR_LED_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_ir_led_cfg_data_t) -#define VIDIOC_MSM_IR_CUT_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_ir_cut_cfg_data_t) -#define VIDIOC_MSM_LASER_LED_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_laser_led_cfg_data_t) -#endif - diff --git a/sdm710/kernel-headers/media/msm_camera.h b/sdm710/kernel-headers/media/msm_camera.h deleted file mode 100644 index 6024d151..00000000 --- a/sdm710/kernel-headers/media/msm_camera.h +++ /dev/null @@ -1,1707 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_MSM_CAMERA_H -#define __UAPI_MSM_CAMERA_H -#define CAM_API_V1 -#include <linux/videodev2.h> -#include <linux/types.h> -#include <linux/ioctl.h> -#include <linux/media.h> -#include <linux/msm_ion.h> -#define BIT(nr) (1UL << (nr)) -#define MSM_CAM_IOCTL_MAGIC 'm' -#define MAX_SERVER_PAYLOAD_LENGTH 8192 -#define MSM_CAM_IOCTL_GET_SENSOR_INFO _IOR(MSM_CAM_IOCTL_MAGIC, 1, struct msm_camsensor_info *) -#define MSM_CAM_IOCTL_REGISTER_PMEM _IOW(MSM_CAM_IOCTL_MAGIC, 2, struct msm_pmem_info *) -#define MSM_CAM_IOCTL_UNREGISTER_PMEM _IOW(MSM_CAM_IOCTL_MAGIC, 3, unsigned int) -#define MSM_CAM_IOCTL_CTRL_COMMAND _IOW(MSM_CAM_IOCTL_MAGIC, 4, struct msm_ctrl_cmd *) -#define MSM_CAM_IOCTL_CONFIG_VFE _IOW(MSM_CAM_IOCTL_MAGIC, 5, struct msm_camera_vfe_cfg_cmd *) -#define MSM_CAM_IOCTL_GET_STATS _IOR(MSM_CAM_IOCTL_MAGIC, 6, struct msm_camera_stats_event_ctrl *) -#define MSM_CAM_IOCTL_GETFRAME _IOR(MSM_CAM_IOCTL_MAGIC, 7, struct msm_camera_get_frame *) -#define MSM_CAM_IOCTL_ENABLE_VFE _IOW(MSM_CAM_IOCTL_MAGIC, 8, struct camera_enable_cmd *) -#define MSM_CAM_IOCTL_CTRL_CMD_DONE _IOW(MSM_CAM_IOCTL_MAGIC, 9, struct camera_cmd *) -#define MSM_CAM_IOCTL_CONFIG_CMD _IOW(MSM_CAM_IOCTL_MAGIC, 10, struct camera_cmd *) -#define MSM_CAM_IOCTL_DISABLE_VFE _IOW(MSM_CAM_IOCTL_MAGIC, 11, struct camera_enable_cmd *) -#define MSM_CAM_IOCTL_PAD_REG_RESET2 _IOW(MSM_CAM_IOCTL_MAGIC, 12, struct camera_enable_cmd *) -#define MSM_CAM_IOCTL_VFE_APPS_RESET _IOW(MSM_CAM_IOCTL_MAGIC, 13, struct camera_enable_cmd *) -#define MSM_CAM_IOCTL_RELEASE_FRAME_BUFFER _IOW(MSM_CAM_IOCTL_MAGIC, 14, struct camera_enable_cmd *) -#define MSM_CAM_IOCTL_RELEASE_STATS_BUFFER _IOW(MSM_CAM_IOCTL_MAGIC, 15, struct msm_stats_buf *) -#define MSM_CAM_IOCTL_AXI_CONFIG _IOW(MSM_CAM_IOCTL_MAGIC, 16, struct msm_camera_vfe_cfg_cmd *) -#define MSM_CAM_IOCTL_GET_PICTURE _IOW(MSM_CAM_IOCTL_MAGIC, 17, struct msm_frame *) -#define MSM_CAM_IOCTL_SET_CROP _IOW(MSM_CAM_IOCTL_MAGIC, 18, struct crop_info *) -#define MSM_CAM_IOCTL_PICT_PP _IOW(MSM_CAM_IOCTL_MAGIC, 19, uint8_t *) -#define MSM_CAM_IOCTL_PICT_PP_DONE _IOW(MSM_CAM_IOCTL_MAGIC, 20, struct msm_snapshot_pp_status *) -#define MSM_CAM_IOCTL_SENSOR_IO_CFG _IOW(MSM_CAM_IOCTL_MAGIC, 21, struct sensor_cfg_data *) -#define MSM_CAM_IOCTL_FLASH_LED_CFG _IOW(MSM_CAM_IOCTL_MAGIC, 22, unsigned int *) -#define MSM_CAM_IOCTL_UNBLOCK_POLL_FRAME _IO(MSM_CAM_IOCTL_MAGIC, 23) -#define MSM_CAM_IOCTL_CTRL_COMMAND_2 _IOW(MSM_CAM_IOCTL_MAGIC, 24, struct msm_ctrl_cmd *) -#define MSM_CAM_IOCTL_AF_CTRL _IOR(MSM_CAM_IOCTL_MAGIC, 25, struct msm_ctrl_cmt_t *) -#define MSM_CAM_IOCTL_AF_CTRL_DONE _IOW(MSM_CAM_IOCTL_MAGIC, 26, struct msm_ctrl_cmt_t *) -#define MSM_CAM_IOCTL_CONFIG_VPE _IOW(MSM_CAM_IOCTL_MAGIC, 27, struct msm_camera_vpe_cfg_cmd *) -#define MSM_CAM_IOCTL_AXI_VPE_CONFIG _IOW(MSM_CAM_IOCTL_MAGIC, 28, struct msm_camera_vpe_cfg_cmd *) -#define MSM_CAM_IOCTL_STROBE_FLASH_CFG _IOW(MSM_CAM_IOCTL_MAGIC, 29, uint32_t *) -#define MSM_CAM_IOCTL_STROBE_FLASH_CHARGE _IOW(MSM_CAM_IOCTL_MAGIC, 30, uint32_t *) -#define MSM_CAM_IOCTL_STROBE_FLASH_RELEASE _IO(MSM_CAM_IOCTL_MAGIC, 31) -#define MSM_CAM_IOCTL_FLASH_CTRL _IOW(MSM_CAM_IOCTL_MAGIC, 32, struct flash_ctrl_data *) -#define MSM_CAM_IOCTL_ERROR_CONFIG _IOW(MSM_CAM_IOCTL_MAGIC, 33, uint32_t *) -#define MSM_CAM_IOCTL_ABORT_CAPTURE _IO(MSM_CAM_IOCTL_MAGIC, 34) -#define MSM_CAM_IOCTL_SET_FD_ROI _IOW(MSM_CAM_IOCTL_MAGIC, 35, struct fd_roi_info *) -#define MSM_CAM_IOCTL_GET_CAMERA_INFO _IOR(MSM_CAM_IOCTL_MAGIC, 36, struct msm_camera_info *) -#define MSM_CAM_IOCTL_UNBLOCK_POLL_PIC_FRAME _IO(MSM_CAM_IOCTL_MAGIC, 37) -#define MSM_CAM_IOCTL_RELEASE_PIC_BUFFER _IOW(MSM_CAM_IOCTL_MAGIC, 38, struct camera_enable_cmd *) -#define MSM_CAM_IOCTL_PUT_ST_FRAME _IOW(MSM_CAM_IOCTL_MAGIC, 39, struct msm_camera_st_frame *) -#define MSM_CAM_IOCTL_V4L2_EVT_NOTIFY _IOW(MSM_CAM_IOCTL_MAGIC, 40, struct v4l2_event_and_payload) -#define MSM_CAM_IOCTL_SET_MEM_MAP_INFO _IOR(MSM_CAM_IOCTL_MAGIC, 41, struct msm_mem_map_info *) -#define MSM_CAM_IOCTL_ACTUATOR_IO_CFG _IOW(MSM_CAM_IOCTL_MAGIC, 42, struct msm_actuator_cfg_data *) -#define MSM_CAM_IOCTL_MCTL_POST_PROC _IOW(MSM_CAM_IOCTL_MAGIC, 43, struct msm_mctl_post_proc_cmd *) -#define MSM_CAM_IOCTL_RESERVE_FREE_FRAME _IOW(MSM_CAM_IOCTL_MAGIC, 44, struct msm_cam_evt_divert_frame *) -#define MSM_CAM_IOCTL_RELEASE_FREE_FRAME _IOR(MSM_CAM_IOCTL_MAGIC, 45, struct msm_cam_evt_divert_frame *) -#define MSM_CAM_IOCTL_PICT_PP_DIVERT_DONE _IOR(MSM_CAM_IOCTL_MAGIC, 46, struct msm_pp_frame *) -#define MSM_CAM_IOCTL_SENSOR_V4l2_S_CTRL _IOR(MSM_CAM_IOCTL_MAGIC, 47, struct v4l2_control) -#define MSM_CAM_IOCTL_SENSOR_V4l2_QUERY_CTRL _IOR(MSM_CAM_IOCTL_MAGIC, 48, struct v4l2_queryctrl) -#define MSM_CAM_IOCTL_GET_KERNEL_SYSTEM_TIME _IOW(MSM_CAM_IOCTL_MAGIC, 49, struct timeval *) -#define MSM_CAM_IOCTL_SET_VFE_OUTPUT_TYPE _IOW(MSM_CAM_IOCTL_MAGIC, 50, uint32_t *) -#define MSM_CAM_IOCTL_MCTL_DIVERT_DONE _IOR(MSM_CAM_IOCTL_MAGIC, 51, struct msm_cam_evt_divert_frame *) -#define MSM_CAM_IOCTL_GET_ACTUATOR_INFO _IOW(MSM_CAM_IOCTL_MAGIC, 52, struct msm_actuator_cfg_data *) -#define MSM_CAM_IOCTL_EEPROM_IO_CFG _IOW(MSM_CAM_IOCTL_MAGIC, 53, struct msm_eeprom_cfg_data *) -#define MSM_CAM_IOCTL_ISPIF_IO_CFG _IOR(MSM_CAM_IOCTL_MAGIC, 54, struct ispif_cfg_data *) -#define MSM_CAM_IOCTL_STATS_REQBUF _IOR(MSM_CAM_IOCTL_MAGIC, 55, struct msm_stats_reqbuf *) -#define MSM_CAM_IOCTL_STATS_ENQUEUEBUF _IOR(MSM_CAM_IOCTL_MAGIC, 56, struct msm_stats_buf_info *) -#define MSM_CAM_IOCTL_STATS_FLUSH_BUFQ _IOR(MSM_CAM_IOCTL_MAGIC, 57, struct msm_stats_flush_bufq *) -#define MSM_CAM_IOCTL_SET_MCTL_SDEV _IOW(MSM_CAM_IOCTL_MAGIC, 58, struct msm_mctl_set_sdev_data *) -#define MSM_CAM_IOCTL_UNSET_MCTL_SDEV _IOW(MSM_CAM_IOCTL_MAGIC, 59, struct msm_mctl_set_sdev_data *) -#define MSM_CAM_IOCTL_GET_INST_HANDLE _IOR(MSM_CAM_IOCTL_MAGIC, 60, uint32_t *) -#define MSM_CAM_IOCTL_STATS_UNREG_BUF _IOR(MSM_CAM_IOCTL_MAGIC, 61, struct msm_stats_flush_bufq *) -#define MSM_CAM_IOCTL_CSIC_IO_CFG _IOWR(MSM_CAM_IOCTL_MAGIC, 62, struct csic_cfg_data *) -#define MSM_CAM_IOCTL_CSID_IO_CFG _IOWR(MSM_CAM_IOCTL_MAGIC, 63, struct csid_cfg_data *) -#define MSM_CAM_IOCTL_CSIPHY_IO_CFG _IOR(MSM_CAM_IOCTL_MAGIC, 64, struct csiphy_cfg_data *) -#define MSM_CAM_IOCTL_OEM _IOW(MSM_CAM_IOCTL_MAGIC, 65, struct sensor_cfg_data *) -#define MSM_CAM_IOCTL_AXI_INIT _IOWR(MSM_CAM_IOCTL_MAGIC, 66, uint8_t *) -#define MSM_CAM_IOCTL_AXI_RELEASE _IO(MSM_CAM_IOCTL_MAGIC, 67) -struct v4l2_event_and_payload { - struct v4l2_event evt; - uint32_t payload_length; - uint32_t transaction_id; - void * payload; -}; -struct msm_stats_reqbuf { - int num_buf; - int stats_type; -}; -struct msm_stats_flush_bufq { - int stats_type; -}; -struct msm_mctl_pp_cmd { - int32_t id; - uint16_t length; - void * value; -}; -struct msm_mctl_post_proc_cmd { - int32_t type; - struct msm_mctl_pp_cmd cmd; -}; -#define MSM_CAMERA_LED_OFF 0 -#define MSM_CAMERA_LED_LOW 1 -#define MSM_CAMERA_LED_HIGH 2 -#define MSM_CAMERA_LED_INIT 3 -#define MSM_CAMERA_LED_RELEASE 4 -#define MSM_CAMERA_STROBE_FLASH_NONE 0 -#define MSM_CAMERA_STROBE_FLASH_XENON 1 -#define MSM_MAX_CAMERA_SENSORS 5 -#define MAX_SENSOR_NAME 32 -#define MAX_CAM_NAME_SIZE 32 -#define MAX_ACT_MOD_NAME_SIZE 32 -#define MAX_ACT_NAME_SIZE 32 -#define NUM_ACTUATOR_DIR 2 -#define MAX_ACTUATOR_SCENARIO 8 -#define MAX_ACTUATOR_REGION 5 -#define MAX_ACTUATOR_INIT_SET 12 -#define MAX_ACTUATOR_TYPE_SIZE 32 -#define MAX_ACTUATOR_REG_TBL_SIZE 8 -#define MSM_MAX_CAMERA_CONFIGS 2 -#define PP_SNAP 0x01 -#define PP_RAW_SNAP ((0x01) << 1) -#define PP_PREV ((0x01) << 2) -#define PP_THUMB ((0x01) << 3) -#define PP_MASK (PP_SNAP | PP_RAW_SNAP | PP_PREV | PP_THUMB) -#define MSM_CAM_CTRL_CMD_DONE 0 -#define MSM_CAM_SENSOR_VFE_CMD 1 -#define MAX_PLANES 8 -struct msm_ctrl_cmd { - uint16_t type; - uint16_t length; - void * value; - uint16_t status; - uint32_t timeout_ms; - int resp_fd; - int vnode_id; - int queue_idx; - uint32_t evt_id; - uint32_t stream_type; - int config_ident; -}; -struct msm_cam_evt_msg { - unsigned short type; - unsigned short msg_id; - unsigned int len; - uint32_t frame_id; - void * data; - struct timespec timestamp; -}; -struct msm_pp_frame_sp { - unsigned long phy_addr; - uint32_t y_off; - uint32_t cbcr_off; - uint32_t length; - int32_t fd; - uint32_t addr_offset; - unsigned long vaddr; -}; -struct msm_pp_frame_mp { - unsigned long phy_addr; - uint32_t data_offset; - uint32_t length; - int32_t fd; - uint32_t addr_offset; - unsigned long vaddr; -}; -struct msm_pp_frame { - uint32_t handle; - uint32_t frame_id; - unsigned short buf_idx; - int path; - unsigned short image_type; - unsigned short num_planes; - struct timeval timestamp; - union { - struct msm_pp_frame_sp sp; - struct msm_pp_frame_mp mp[MAX_PLANES]; - }; - int node_type; - uint32_t inst_handle; -}; -struct msm_pp_crop { - uint32_t src_x; - uint32_t src_y; - uint32_t src_w; - uint32_t src_h; - uint32_t dst_x; - uint32_t dst_y; - uint32_t dst_w; - uint32_t dst_h; - uint8_t update_flag; -}; -struct msm_mctl_pp_frame_cmd { - uint32_t cookie; - uint8_t vpe_output_action; - struct msm_pp_frame src_frame; - struct msm_pp_frame dest_frame; - struct msm_pp_crop crop; - int path; -}; -struct msm_cam_evt_divert_frame { - unsigned short image_mode; - unsigned short op_mode; - unsigned short inst_idx; - unsigned short node_idx; - struct msm_pp_frame frame; - int do_pp; -}; -struct msm_mctl_pp_cmd_ack_event { - uint32_t cmd; - int status; - uint32_t cookie; -}; -struct msm_mctl_pp_event_info { - int32_t event; - union { - struct msm_mctl_pp_cmd_ack_event ack; - }; -}; -struct msm_isp_event_ctrl { - unsigned short resptype; - union { - struct msm_cam_evt_msg isp_msg; - struct msm_ctrl_cmd ctrl; - struct msm_cam_evt_divert_frame div_frame; - struct msm_mctl_pp_event_info pp_event_info; - } isp_data; -}; -#define MSM_CAM_RESP_CTRL 0 -#define MSM_CAM_RESP_STAT_EVT_MSG 1 -#define MSM_CAM_RESP_STEREO_OP_1 2 -#define MSM_CAM_RESP_STEREO_OP_2 3 -#define MSM_CAM_RESP_V4L2 4 -#define MSM_CAM_RESP_DIV_FRAME_EVT_MSG 5 -#define MSM_CAM_RESP_DONE_EVENT 6 -#define MSM_CAM_RESP_MCTL_PP_EVENT 7 -#define MSM_CAM_RESP_MAX 8 -#define MSM_CAM_APP_NOTIFY_EVENT 0 -#define MSM_CAM_APP_NOTIFY_ERROR_EVENT 1 -struct msm_stats_event_ctrl { - int resptype; - int timeout_ms; - struct msm_ctrl_cmd ctrl_cmd; - struct msm_cam_evt_msg stats_event; -}; -struct msm_camera_cfg_cmd { - uint16_t cfg_type; - uint16_t cmd_type; - uint16_t queue; - uint16_t length; - void * value; -}; -#define CMD_GENERAL 0 -#define CMD_AXI_CFG_OUT1 1 -#define CMD_AXI_CFG_SNAP_O1_AND_O2 2 -#define CMD_AXI_CFG_OUT2 3 -#define CMD_PICT_T_AXI_CFG 4 -#define CMD_PICT_M_AXI_CFG 5 -#define CMD_RAW_PICT_AXI_CFG 6 -#define CMD_FRAME_BUF_RELEASE 7 -#define CMD_PREV_BUF_CFG 8 -#define CMD_SNAP_BUF_RELEASE 9 -#define CMD_SNAP_BUF_CFG 10 -#define CMD_STATS_DISABLE 11 -#define CMD_STATS_AEC_AWB_ENABLE 12 -#define CMD_STATS_AF_ENABLE 13 -#define CMD_STATS_AEC_ENABLE 14 -#define CMD_STATS_AWB_ENABLE 15 -#define CMD_STATS_ENABLE 16 -#define CMD_STATS_AXI_CFG 17 -#define CMD_STATS_AEC_AXI_CFG 18 -#define CMD_STATS_AF_AXI_CFG 19 -#define CMD_STATS_AWB_AXI_CFG 20 -#define CMD_STATS_RS_AXI_CFG 21 -#define CMD_STATS_CS_AXI_CFG 22 -#define CMD_STATS_IHIST_AXI_CFG 23 -#define CMD_STATS_SKIN_AXI_CFG 24 -#define CMD_STATS_BUF_RELEASE 25 -#define CMD_STATS_AEC_BUF_RELEASE 26 -#define CMD_STATS_AF_BUF_RELEASE 27 -#define CMD_STATS_AWB_BUF_RELEASE 28 -#define CMD_STATS_RS_BUF_RELEASE 29 -#define CMD_STATS_CS_BUF_RELEASE 30 -#define CMD_STATS_IHIST_BUF_RELEASE 31 -#define CMD_STATS_SKIN_BUF_RELEASE 32 -#define UPDATE_STATS_INVALID 33 -#define CMD_AXI_CFG_SNAP_GEMINI 34 -#define CMD_AXI_CFG_SNAP 35 -#define CMD_AXI_CFG_PREVIEW 36 -#define CMD_AXI_CFG_VIDEO 37 -#define CMD_STATS_IHIST_ENABLE 38 -#define CMD_STATS_RS_ENABLE 39 -#define CMD_STATS_CS_ENABLE 40 -#define CMD_VPE 41 -#define CMD_AXI_CFG_VPE 42 -#define CMD_AXI_CFG_ZSL 43 -#define CMD_AXI_CFG_SNAP_VPE 44 -#define CMD_AXI_CFG_SNAP_THUMB_VPE 45 -#define CMD_CONFIG_PING_ADDR 46 -#define CMD_CONFIG_PONG_ADDR 47 -#define CMD_CONFIG_FREE_BUF_ADDR 48 -#define CMD_AXI_CFG_ZSL_ALL_CHNLS 49 -#define CMD_AXI_CFG_VIDEO_ALL_CHNLS 50 -#define CMD_VFE_BUFFER_RELEASE 51 -#define CMD_VFE_PROCESS_IRQ 52 -#define CMD_STATS_BG_ENABLE 53 -#define CMD_STATS_BF_ENABLE 54 -#define CMD_STATS_BHIST_ENABLE 55 -#define CMD_STATS_BG_BUF_RELEASE 56 -#define CMD_STATS_BF_BUF_RELEASE 57 -#define CMD_STATS_BHIST_BUF_RELEASE 58 -#define CMD_VFE_PIX_SOF_COUNT_UPDATE 59 -#define CMD_VFE_COUNT_PIX_SOF_ENABLE 60 -#define CMD_STATS_BE_ENABLE 61 -#define CMD_STATS_BE_BUF_RELEASE 62 -#define CMD_AXI_CFG_PRIM BIT(8) -#define CMD_AXI_CFG_PRIM_ALL_CHNLS BIT(9) -#define CMD_AXI_CFG_SEC BIT(10) -#define CMD_AXI_CFG_SEC_ALL_CHNLS BIT(11) -#define CMD_AXI_CFG_TERT1 BIT(12) -#define CMD_AXI_CFG_TERT2 BIT(13) -#define CMD_AXI_START 0xE1 -#define CMD_AXI_STOP 0xE2 -#define CMD_AXI_RESET 0xE3 -#define CMD_AXI_ABORT 0xE4 -#define AXI_CMD_PREVIEW BIT(0) -#define AXI_CMD_CAPTURE BIT(1) -#define AXI_CMD_RECORD BIT(2) -#define AXI_CMD_ZSL BIT(3) -#define AXI_CMD_RAW_CAPTURE BIT(4) -#define AXI_CMD_LIVESHOT BIT(5) -struct msm_vfe_cfg_cmd { - int cmd_type; - uint16_t length; - void * value; -}; -struct msm_vpe_cfg_cmd { - int cmd_type; - uint16_t length; - void * value; -}; -#define MAX_CAMERA_ENABLE_NAME_LEN 32 -struct camera_enable_cmd { - char name[MAX_CAMERA_ENABLE_NAME_LEN]; -}; -#define MSM_PMEM_OUTPUT1 0 -#define MSM_PMEM_OUTPUT2 1 -#define MSM_PMEM_OUTPUT1_OUTPUT2 2 -#define MSM_PMEM_THUMBNAIL 3 -#define MSM_PMEM_MAINIMG 4 -#define MSM_PMEM_RAW_MAINIMG 5 -#define MSM_PMEM_AEC_AWB 6 -#define MSM_PMEM_AF 7 -#define MSM_PMEM_AEC 8 -#define MSM_PMEM_AWB 9 -#define MSM_PMEM_RS 10 -#define MSM_PMEM_CS 11 -#define MSM_PMEM_IHIST 12 -#define MSM_PMEM_SKIN 13 -#define MSM_PMEM_VIDEO 14 -#define MSM_PMEM_PREVIEW 15 -#define MSM_PMEM_VIDEO_VPE 16 -#define MSM_PMEM_C2D 17 -#define MSM_PMEM_MAINIMG_VPE 18 -#define MSM_PMEM_THUMBNAIL_VPE 19 -#define MSM_PMEM_BAYER_GRID 20 -#define MSM_PMEM_BAYER_FOCUS 21 -#define MSM_PMEM_BAYER_HIST 22 -#define MSM_PMEM_BAYER_EXPOSURE 23 -#define MSM_PMEM_MAX 24 -#define STAT_AEAW 0 -#define STAT_AEC 1 -#define STAT_AF 2 -#define STAT_AWB 3 -#define STAT_RS 4 -#define STAT_CS 5 -#define STAT_IHIST 6 -#define STAT_SKIN 7 -#define STAT_BG 8 -#define STAT_BF 9 -#define STAT_BE 10 -#define STAT_BHIST 11 -#define STAT_MAX 12 -#define FRAME_PREVIEW_OUTPUT1 0 -#define FRAME_PREVIEW_OUTPUT2 1 -#define FRAME_SNAPSHOT 2 -#define FRAME_THUMBNAIL 3 -#define FRAME_RAW_SNAPSHOT 4 -#define FRAME_MAX 5 -enum msm_stats_enum_type { - MSM_STATS_TYPE_AEC, - MSM_STATS_TYPE_AF, - MSM_STATS_TYPE_AWB, - MSM_STATS_TYPE_RS, - MSM_STATS_TYPE_CS, - MSM_STATS_TYPE_IHIST, - MSM_STATS_TYPE_SKIN, - MSM_STATS_TYPE_BG, - MSM_STATS_TYPE_BF, - MSM_STATS_TYPE_BE, - MSM_STATS_TYPE_BHIST, - MSM_STATS_TYPE_AE_AW, - MSM_STATS_TYPE_COMP, - MSM_STATS_TYPE_MAX -}; -struct msm_stats_buf_info { - int type; - int fd; - void * vaddr; - uint32_t offset; - uint32_t len; - uint32_t y_off; - uint32_t cbcr_off; - uint32_t planar0_off; - uint32_t planar1_off; - uint32_t planar2_off; - uint8_t active; - int buf_idx; -}; -struct msm_pmem_info { - int type; - int fd; - void * vaddr; - uint32_t offset; - uint32_t len; - uint32_t y_off; - uint32_t cbcr_off; - uint32_t planar0_off; - uint32_t planar1_off; - uint32_t planar2_off; - uint8_t active; -}; -struct outputCfg { - uint32_t height; - uint32_t width; - uint32_t window_height_firstline; - uint32_t window_height_lastline; -}; -#define VIDEO_NODE 0 -#define MCTL_NODE 1 -#define OUTPUT_1 0 -#define OUTPUT_2 1 -#define OUTPUT_1_AND_2 2 -#define OUTPUT_1_AND_3 3 -#define CAMIF_TO_AXI_VIA_OUTPUT_2 4 -#define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 5 -#define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 6 -#define OUTPUT_1_2_AND_3 7 -#define OUTPUT_ALL_CHNLS 8 -#define OUTPUT_VIDEO_ALL_CHNLS 9 -#define OUTPUT_ZSL_ALL_CHNLS 10 -#define LAST_AXI_OUTPUT_MODE_ENUM OUTPUT_ZSL_ALL_CHNLS -#define OUTPUT_PRIM BIT(8) -#define OUTPUT_PRIM_ALL_CHNLS BIT(9) -#define OUTPUT_SEC BIT(10) -#define OUTPUT_SEC_ALL_CHNLS BIT(11) -#define OUTPUT_TERT1 BIT(12) -#define OUTPUT_TERT2 BIT(13) -#define MSM_FRAME_PREV_1 0 -#define MSM_FRAME_PREV_2 1 -#define MSM_FRAME_ENC 2 -#define OUTPUT_TYPE_P BIT(0) -#define OUTPUT_TYPE_T BIT(1) -#define OUTPUT_TYPE_S BIT(2) -#define OUTPUT_TYPE_V BIT(3) -#define OUTPUT_TYPE_L BIT(4) -#define OUTPUT_TYPE_ST_L BIT(5) -#define OUTPUT_TYPE_ST_R BIT(6) -#define OUTPUT_TYPE_ST_D BIT(7) -#define OUTPUT_TYPE_R BIT(8) -#define OUTPUT_TYPE_R1 BIT(9) -#define OUTPUT_TYPE_SAEC BIT(10) -#define OUTPUT_TYPE_SAFC BIT(11) -#define OUTPUT_TYPE_SAWB BIT(12) -#define OUTPUT_TYPE_IHST BIT(13) -#define OUTPUT_TYPE_CSTA BIT(14) -struct fd_roi_info { - void * info; - int info_len; -}; -struct msm_mem_map_info { - uint32_t cookie; - uint32_t length; - uint32_t mem_type; -}; -#define MSM_MEM_MMAP 0 -#define MSM_MEM_USERPTR 1 -#define MSM_PLANE_MAX 8 -#define MSM_PLANE_Y 0 -#define MSM_PLANE_UV 1 -struct msm_frame { - struct timespec ts; - int path; - int type; - unsigned long buffer; - uint32_t phy_offset; - uint32_t y_off; - uint32_t cbcr_off; - uint32_t planar0_off; - uint32_t planar1_off; - uint32_t planar2_off; - int fd; - void * cropinfo; - int croplen; - uint32_t error_code; - struct fd_roi_info roi_info; - uint32_t frame_id; - int stcam_quality_ind; - uint32_t stcam_conv_value; - struct ion_allocation_data ion_alloc; - struct ion_fd_data fd_data; - int ion_dev_fd; -}; -enum msm_st_frame_packing { - SIDE_BY_SIDE_HALF, - SIDE_BY_SIDE_FULL, - TOP_DOWN_HALF, - TOP_DOWN_FULL, -}; -struct msm_st_crop { - uint32_t in_w; - uint32_t in_h; - uint32_t out_w; - uint32_t out_h; -}; -struct msm_st_half { - uint32_t buf_p0_off; - uint32_t buf_p1_off; - uint32_t buf_p0_stride; - uint32_t buf_p1_stride; - uint32_t pix_x_off; - uint32_t pix_y_off; - struct msm_st_crop stCropInfo; -}; -struct msm_st_frame { - struct msm_frame buf_info; - int type; - enum msm_st_frame_packing packing; - struct msm_st_half L; - struct msm_st_half R; - int frame_id; -}; -#define MSM_CAMERA_ERR_MASK (0xFFFFFFFF & 1) -struct stats_buff { - unsigned long buff; - int fd; -}; -struct msm_stats_buf { - uint8_t awb_ymin; - struct stats_buff aec; - struct stats_buff awb; - struct stats_buff af; - struct stats_buff be; - struct stats_buff ihist; - struct stats_buff rs; - struct stats_buff cs; - struct stats_buff skin; - int type; - uint32_t status_bits; - unsigned long buffer; - int fd; - int length; - struct ion_handle * handle; - uint32_t frame_id; - int buf_idx; -}; -#define MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT 0 -#define MSM_V4L2_EXT_CAPTURE_MODE_PREVIEW (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 1) -#define MSM_V4L2_EXT_CAPTURE_MODE_VIDEO (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 2) -#define MSM_V4L2_EXT_CAPTURE_MODE_MAIN (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 3) -#define MSM_V4L2_EXT_CAPTURE_MODE_THUMBNAIL (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 4) -#define MSM_V4L2_EXT_CAPTURE_MODE_ISP_PIX_OUTPUT1 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 5) -#define MSM_V4L2_EXT_CAPTURE_MODE_ISP_PIX_OUTPUT2 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 6) -#define MSM_V4L2_EXT_CAPTURE_MODE_RAW (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 7) -#define MSM_V4L2_EXT_CAPTURE_MODE_RDI (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 8) -#define MSM_V4L2_EXT_CAPTURE_MODE_RDI1 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 9) -#define MSM_V4L2_EXT_CAPTURE_MODE_RDI2 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 10) -#define MSM_V4L2_EXT_CAPTURE_MODE_AEC (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 11) -#define MSM_V4L2_EXT_CAPTURE_MODE_AWB (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 12) -#define MSM_V4L2_EXT_CAPTURE_MODE_AF (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 13) -#define MSM_V4L2_EXT_CAPTURE_MODE_IHIST (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 14) -#define MSM_V4L2_EXT_CAPTURE_MODE_CS (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 15) -#define MSM_V4L2_EXT_CAPTURE_MODE_RS (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 16) -#define MSM_V4L2_EXT_CAPTURE_MODE_CSTA (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 17) -#define MSM_V4L2_EXT_CAPTURE_MODE_V2X_LIVESHOT (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 18) -#define MSM_V4L2_EXT_CAPTURE_MODE_MAX (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT + 19) -#define MSM_V4L2_PID_MOTION_ISO V4L2_CID_PRIVATE_BASE -#define MSM_V4L2_PID_EFFECT (V4L2_CID_PRIVATE_BASE + 1) -#define MSM_V4L2_PID_HJR (V4L2_CID_PRIVATE_BASE + 2) -#define MSM_V4L2_PID_LED_MODE (V4L2_CID_PRIVATE_BASE + 3) -#define MSM_V4L2_PID_PREP_SNAPSHOT (V4L2_CID_PRIVATE_BASE + 4) -#define MSM_V4L2_PID_EXP_METERING (V4L2_CID_PRIVATE_BASE + 5) -#define MSM_V4L2_PID_ISO (V4L2_CID_PRIVATE_BASE + 6) -#define MSM_V4L2_PID_CAM_MODE (V4L2_CID_PRIVATE_BASE + 7) -#define MSM_V4L2_PID_LUMA_ADAPTATION (V4L2_CID_PRIVATE_BASE + 8) -#define MSM_V4L2_PID_BEST_SHOT (V4L2_CID_PRIVATE_BASE + 9) -#define MSM_V4L2_PID_FOCUS_MODE (V4L2_CID_PRIVATE_BASE + 10) -#define MSM_V4L2_PID_BL_DETECTION (V4L2_CID_PRIVATE_BASE + 11) -#define MSM_V4L2_PID_SNOW_DETECTION (V4L2_CID_PRIVATE_BASE + 12) -#define MSM_V4L2_PID_CTRL_CMD (V4L2_CID_PRIVATE_BASE + 13) -#define MSM_V4L2_PID_EVT_SUB_INFO (V4L2_CID_PRIVATE_BASE + 14) -#define MSM_V4L2_PID_STROBE_FLASH (V4L2_CID_PRIVATE_BASE + 15) -#define MSM_V4L2_PID_INST_HANDLE (V4L2_CID_PRIVATE_BASE + 16) -#define MSM_V4L2_PID_MMAP_INST (V4L2_CID_PRIVATE_BASE + 17) -#define MSM_V4L2_PID_PP_PLANE_INFO (V4L2_CID_PRIVATE_BASE + 18) -#define MSM_V4L2_PID_MAX MSM_V4L2_PID_PP_PLANE_INFO -#define MSM_V4L2_CAM_OP_DEFAULT 0 -#define MSM_V4L2_CAM_OP_PREVIEW (MSM_V4L2_CAM_OP_DEFAULT + 1) -#define MSM_V4L2_CAM_OP_VIDEO (MSM_V4L2_CAM_OP_DEFAULT + 2) -#define MSM_V4L2_CAM_OP_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT + 3) -#define MSM_V4L2_CAM_OP_ZSL (MSM_V4L2_CAM_OP_DEFAULT + 4) -#define MSM_V4L2_CAM_OP_RAW (MSM_V4L2_CAM_OP_DEFAULT + 5) -#define MSM_V4L2_CAM_OP_JPEG_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT + 6) -#define MSM_V4L2_VID_CAP_TYPE 0 -#define MSM_V4L2_STREAM_ON 1 -#define MSM_V4L2_STREAM_OFF 2 -#define MSM_V4L2_SNAPSHOT 3 -#define MSM_V4L2_QUERY_CTRL 4 -#define MSM_V4L2_GET_CTRL 5 -#define MSM_V4L2_SET_CTRL 6 -#define MSM_V4L2_QUERY 7 -#define MSM_V4L2_GET_CROP 8 -#define MSM_V4L2_SET_CROP 9 -#define MSM_V4L2_OPEN 10 -#define MSM_V4L2_CLOSE 11 -#define MSM_V4L2_SET_CTRL_CMD 12 -#define MSM_V4L2_EVT_SUB_MASK 13 -#define MSM_V4L2_PRIVATE_CMD 14 -#define MSM_V4L2_MAX 15 -#define V4L2_CAMERA_EXIT 43 -struct crop_info { - void * info; - int len; -}; -struct msm_postproc { - int ftnum; - struct msm_frame fthumnail; - int fmnum; - struct msm_frame fmain; -}; -struct msm_snapshot_pp_status { - void * status; -}; -#define CFG_SET_MODE 0 -#define CFG_SET_EFFECT 1 -#define CFG_START 2 -#define CFG_PWR_UP 3 -#define CFG_PWR_DOWN 4 -#define CFG_WRITE_EXPOSURE_GAIN 5 -#define CFG_SET_DEFAULT_FOCUS 6 -#define CFG_MOVE_FOCUS 7 -#define CFG_REGISTER_TO_REAL_GAIN 8 -#define CFG_REAL_TO_REGISTER_GAIN 9 -#define CFG_SET_FPS 10 -#define CFG_SET_PICT_FPS 11 -#define CFG_SET_BRIGHTNESS 12 -#define CFG_SET_CONTRAST 13 -#define CFG_SET_ZOOM 14 -#define CFG_SET_EXPOSURE_MODE 15 -#define CFG_SET_WB 16 -#define CFG_SET_ANTIBANDING 17 -#define CFG_SET_EXP_GAIN 18 -#define CFG_SET_PICT_EXP_GAIN 19 -#define CFG_SET_LENS_SHADING 20 -#define CFG_GET_PICT_FPS 21 -#define CFG_GET_PREV_L_PF 22 -#define CFG_GET_PREV_P_PL 23 -#define CFG_GET_PICT_L_PF 24 -#define CFG_GET_PICT_P_PL 25 -#define CFG_GET_AF_MAX_STEPS 26 -#define CFG_GET_PICT_MAX_EXP_LC 27 -#define CFG_SEND_WB_INFO 28 -#define CFG_SENSOR_INIT 29 -#define CFG_GET_3D_CALI_DATA 30 -#define CFG_GET_CALIB_DATA 31 -#define CFG_GET_OUTPUT_INFO 32 -#define CFG_GET_EEPROM_INFO 33 -#define CFG_GET_EEPROM_DATA 34 -#define CFG_SET_ACTUATOR_INFO 35 -#define CFG_GET_ACTUATOR_INFO 36 -#define CFG_SET_SATURATION 37 -#define CFG_SET_SHARPNESS 38 -#define CFG_SET_TOUCHAEC 39 -#define CFG_SET_AUTO_FOCUS 40 -#define CFG_SET_AUTOFLASH 41 -#define CFG_SET_EXPOSURE_COMPENSATION 42 -#define CFG_SET_ISO 43 -#define CFG_START_STREAM 44 -#define CFG_STOP_STREAM 45 -#define CFG_GET_CSI_PARAMS 46 -#define CFG_POWER_UP 47 -#define CFG_POWER_DOWN 48 -#define CFG_WRITE_I2C_ARRAY 49 -#define CFG_READ_I2C_ARRAY 50 -#define CFG_PCLK_CHANGE 51 -#define CFG_CONFIG_VREG_ARRAY 52 -#define CFG_CONFIG_CLK_ARRAY 53 -#define CFG_GPIO_OP 54 -#define CFG_MAX 55 -#define MOVE_NEAR 0 -#define MOVE_FAR 1 -#define SENSOR_PREVIEW_MODE 0 -#define SENSOR_SNAPSHOT_MODE 1 -#define SENSOR_RAW_SNAPSHOT_MODE 2 -#define SENSOR_HFR_60FPS_MODE 3 -#define SENSOR_HFR_90FPS_MODE 4 -#define SENSOR_HFR_120FPS_MODE 5 -#define SENSOR_QTR_SIZE 0 -#define SENSOR_FULL_SIZE 1 -#define SENSOR_QVGA_SIZE 2 -#define SENSOR_INVALID_SIZE 3 -#define CAMERA_EFFECT_OFF 0 -#define CAMERA_EFFECT_MONO 1 -#define CAMERA_EFFECT_NEGATIVE 2 -#define CAMERA_EFFECT_SOLARIZE 3 -#define CAMERA_EFFECT_SEPIA 4 -#define CAMERA_EFFECT_POSTERIZE 5 -#define CAMERA_EFFECT_WHITEBOARD 6 -#define CAMERA_EFFECT_BLACKBOARD 7 -#define CAMERA_EFFECT_AQUA 8 -#define CAMERA_EFFECT_EMBOSS 9 -#define CAMERA_EFFECT_SKETCH 10 -#define CAMERA_EFFECT_NEON 11 -#define CAMERA_EFFECT_FADED 12 -#define CAMERA_EFFECT_VINTAGECOOL 13 -#define CAMERA_EFFECT_VINTAGEWARM 14 -#define CAMERA_EFFECT_ACCENT_BLUE 15 -#define CAMERA_EFFECT_ACCENT_GREEN 16 -#define CAMERA_EFFECT_ACCENT_ORANGE 17 -#define CAMERA_EFFECT_MAX 18 -#define CAMERA_EFFECT_BW 10 -#define CAMERA_EFFECT_BLUISH 12 -#define CAMERA_EFFECT_REDDISH 13 -#define CAMERA_EFFECT_GREENISH 14 -#define CAMERA_ANTIBANDING_OFF 0 -#define CAMERA_ANTIBANDING_50HZ 2 -#define CAMERA_ANTIBANDING_60HZ 1 -#define CAMERA_ANTIBANDING_AUTO 3 -#define CAMERA_CONTRAST_LV0 0 -#define CAMERA_CONTRAST_LV1 1 -#define CAMERA_CONTRAST_LV2 2 -#define CAMERA_CONTRAST_LV3 3 -#define CAMERA_CONTRAST_LV4 4 -#define CAMERA_CONTRAST_LV5 5 -#define CAMERA_CONTRAST_LV6 6 -#define CAMERA_CONTRAST_LV7 7 -#define CAMERA_CONTRAST_LV8 8 -#define CAMERA_CONTRAST_LV9 9 -#define CAMERA_BRIGHTNESS_LV0 0 -#define CAMERA_BRIGHTNESS_LV1 1 -#define CAMERA_BRIGHTNESS_LV2 2 -#define CAMERA_BRIGHTNESS_LV3 3 -#define CAMERA_BRIGHTNESS_LV4 4 -#define CAMERA_BRIGHTNESS_LV5 5 -#define CAMERA_BRIGHTNESS_LV6 6 -#define CAMERA_BRIGHTNESS_LV7 7 -#define CAMERA_BRIGHTNESS_LV8 8 -#define CAMERA_SATURATION_LV0 0 -#define CAMERA_SATURATION_LV1 1 -#define CAMERA_SATURATION_LV2 2 -#define CAMERA_SATURATION_LV3 3 -#define CAMERA_SATURATION_LV4 4 -#define CAMERA_SATURATION_LV5 5 -#define CAMERA_SATURATION_LV6 6 -#define CAMERA_SATURATION_LV7 7 -#define CAMERA_SATURATION_LV8 8 -#define CAMERA_SHARPNESS_LV0 0 -#define CAMERA_SHARPNESS_LV1 3 -#define CAMERA_SHARPNESS_LV2 6 -#define CAMERA_SHARPNESS_LV3 9 -#define CAMERA_SHARPNESS_LV4 12 -#define CAMERA_SHARPNESS_LV5 15 -#define CAMERA_SHARPNESS_LV6 18 -#define CAMERA_SHARPNESS_LV7 21 -#define CAMERA_SHARPNESS_LV8 24 -#define CAMERA_SHARPNESS_LV9 27 -#define CAMERA_SHARPNESS_LV10 30 -#define CAMERA_SETAE_AVERAGE 0 -#define CAMERA_SETAE_CENWEIGHT 1 -#define CAMERA_WB_AUTO 1 -#define CAMERA_WB_CUSTOM 2 -#define CAMERA_WB_INCANDESCENT 3 -#define CAMERA_WB_FLUORESCENT 4 -#define CAMERA_WB_DAYLIGHT 5 -#define CAMERA_WB_CLOUDY_DAYLIGHT 6 -#define CAMERA_WB_TWILIGHT 7 -#define CAMERA_WB_SHADE 8 -#define CAMERA_EXPOSURE_COMPENSATION_LV0 12 -#define CAMERA_EXPOSURE_COMPENSATION_LV1 6 -#define CAMERA_EXPOSURE_COMPENSATION_LV2 0 -#define CAMERA_EXPOSURE_COMPENSATION_LV3 - 6 -#define CAMERA_EXPOSURE_COMPENSATION_LV4 - 12 -enum msm_v4l2_saturation_level { - MSM_V4L2_SATURATION_L0, - MSM_V4L2_SATURATION_L1, - MSM_V4L2_SATURATION_L2, - MSM_V4L2_SATURATION_L3, - MSM_V4L2_SATURATION_L4, - MSM_V4L2_SATURATION_L5, - MSM_V4L2_SATURATION_L6, - MSM_V4L2_SATURATION_L7, - MSM_V4L2_SATURATION_L8, - MSM_V4L2_SATURATION_L9, - MSM_V4L2_SATURATION_L10, -}; -enum msm_v4l2_contrast_level { - MSM_V4L2_CONTRAST_L0, - MSM_V4L2_CONTRAST_L1, - MSM_V4L2_CONTRAST_L2, - MSM_V4L2_CONTRAST_L3, - MSM_V4L2_CONTRAST_L4, - MSM_V4L2_CONTRAST_L5, - MSM_V4L2_CONTRAST_L6, - MSM_V4L2_CONTRAST_L7, - MSM_V4L2_CONTRAST_L8, - MSM_V4L2_CONTRAST_L9, - MSM_V4L2_CONTRAST_L10, -}; -enum msm_v4l2_exposure_level { - MSM_V4L2_EXPOSURE_N2, - MSM_V4L2_EXPOSURE_N1, - MSM_V4L2_EXPOSURE_D, - MSM_V4L2_EXPOSURE_P1, - MSM_V4L2_EXPOSURE_P2, -}; -enum msm_v4l2_sharpness_level { - MSM_V4L2_SHARPNESS_L0, - MSM_V4L2_SHARPNESS_L1, - MSM_V4L2_SHARPNESS_L2, - MSM_V4L2_SHARPNESS_L3, - MSM_V4L2_SHARPNESS_L4, - MSM_V4L2_SHARPNESS_L5, - MSM_V4L2_SHARPNESS_L6, -}; -enum msm_v4l2_expo_metering_mode { - MSM_V4L2_EXP_FRAME_AVERAGE, - MSM_V4L2_EXP_CENTER_WEIGHTED, - MSM_V4L2_EXP_SPOT_METERING, -}; -enum msm_v4l2_iso_mode { - MSM_V4L2_ISO_AUTO = 0, - MSM_V4L2_ISO_DEBLUR, - MSM_V4L2_ISO_100, - MSM_V4L2_ISO_200, - MSM_V4L2_ISO_400, - MSM_V4L2_ISO_800, - MSM_V4L2_ISO_1600, -}; -enum msm_v4l2_wb_mode { - MSM_V4L2_WB_OFF, - MSM_V4L2_WB_AUTO, - MSM_V4L2_WB_CUSTOM, - MSM_V4L2_WB_INCANDESCENT, - MSM_V4L2_WB_FLUORESCENT, - MSM_V4L2_WB_DAYLIGHT, - MSM_V4L2_WB_CLOUDY_DAYLIGHT, -}; -enum msm_v4l2_special_effect { - MSM_V4L2_EFFECT_OFF, - MSM_V4L2_EFFECT_MONO, - MSM_V4L2_EFFECT_NEGATIVE, - MSM_V4L2_EFFECT_SOLARIZE, - MSM_V4L2_EFFECT_SEPIA, - MSM_V4L2_EFFECT_POSTERAIZE, - MSM_V4L2_EFFECT_WHITEBOARD, - MSM_V4L2_EFFECT_BLACKBOARD, - MSM_V4L2_EFFECT_AQUA, - MSM_V4L2_EFFECT_EMBOSS, - MSM_V4L2_EFFECT_SKETCH, - MSM_V4L2_EFFECT_NEON, - MSM_V4L2_EFFECT_MAX, -}; -enum msm_v4l2_power_line_frequency { - MSM_V4L2_POWER_LINE_OFF, - MSM_V4L2_POWER_LINE_60HZ, - MSM_V4L2_POWER_LINE_50HZ, - MSM_V4L2_POWER_LINE_AUTO, -}; -#define CAMERA_ISO_TYPE_AUTO 0 -#define CAMEAR_ISO_TYPE_HJR 1 -#define CAMEAR_ISO_TYPE_100 2 -#define CAMERA_ISO_TYPE_200 3 -#define CAMERA_ISO_TYPE_400 4 -#define CAMEAR_ISO_TYPE_800 5 -#define CAMERA_ISO_TYPE_1600 6 -struct sensor_pict_fps { - uint16_t prevfps; - uint16_t pictfps; -}; -struct exp_gain_cfg { - uint16_t gain; - uint32_t line; -}; -struct focus_cfg { - int32_t steps; - int dir; -}; -struct fps_cfg { - uint16_t f_mult; - uint16_t fps_div; - uint32_t pict_fps_div; -}; -struct wb_info_cfg { - uint16_t red_gain; - uint16_t green_gain; - uint16_t blue_gain; -}; -struct sensor_3d_exp_cfg { - uint16_t gain; - uint32_t line; - uint16_t r_gain; - uint16_t b_gain; - uint16_t gr_gain; - uint16_t gb_gain; - uint16_t gain_adjust; -}; -struct sensor_3d_cali_data_t { - unsigned char left_p_matrix[3][4][8]; - unsigned char right_p_matrix[3][4][8]; - unsigned char square_len[8]; - unsigned char focal_len[8]; - unsigned char pixel_pitch[8]; - uint16_t left_r; - uint16_t left_b; - uint16_t left_gb; - uint16_t left_af_far; - uint16_t left_af_mid; - uint16_t left_af_short; - uint16_t left_af_5um; - uint16_t left_af_50up; - uint16_t left_af_50down; - uint16_t right_r; - uint16_t right_b; - uint16_t right_gb; - uint16_t right_af_far; - uint16_t right_af_mid; - uint16_t right_af_short; - uint16_t right_af_5um; - uint16_t right_af_50up; - uint16_t right_af_50down; -}; -struct sensor_init_cfg { - uint8_t prev_res; - uint8_t pict_res; -}; -struct sensor_calib_data { - uint16_t r_over_g; - uint16_t b_over_g; - uint16_t gr_over_gb; - uint16_t macro_2_inf; - uint16_t inf_2_macro; - uint16_t stroke_amt; - uint16_t af_pos_1m; - uint16_t af_pos_inf; -}; -enum msm_sensor_resolution_t { - MSM_SENSOR_RES_FULL, - MSM_SENSOR_RES_QTR, - MSM_SENSOR_RES_2, - MSM_SENSOR_RES_3, - MSM_SENSOR_RES_4, - MSM_SENSOR_RES_5, - MSM_SENSOR_RES_6, - MSM_SENSOR_RES_7, - MSM_SENSOR_INVALID_RES, -}; -struct msm_sensor_output_info_t { - uint16_t x_output; - uint16_t y_output; - uint16_t line_length_pclk; - uint16_t frame_length_lines; - uint32_t vt_pixel_clk; - uint32_t op_pixel_clk; - uint16_t binning_factor; -}; -struct sensor_output_info_t { - struct msm_sensor_output_info_t * output_info; - uint16_t num_info; -}; -struct msm_sensor_exp_gain_info_t { - uint16_t coarse_int_time_addr; - uint16_t global_gain_addr; - uint16_t vert_offset; -}; -struct msm_sensor_output_reg_addr_t { - uint16_t x_output; - uint16_t y_output; - uint16_t line_length_pclk; - uint16_t frame_length_lines; -}; -struct sensor_driver_params_type { - struct msm_camera_i2c_reg_setting * init_settings; - uint16_t init_settings_size; - struct msm_camera_i2c_reg_setting * mode_settings; - uint16_t mode_settings_size; - struct msm_sensor_output_reg_addr_t * sensor_output_reg_addr; - struct msm_camera_i2c_reg_setting * start_settings; - struct msm_camera_i2c_reg_setting * stop_settings; - struct msm_camera_i2c_reg_setting * groupon_settings; - struct msm_camera_i2c_reg_setting * groupoff_settings; - struct msm_sensor_exp_gain_info_t * sensor_exp_gain_info; - struct msm_sensor_output_info_t * output_info; -}; -struct mirror_flip { - int32_t x_mirror; - int32_t y_flip; -}; -struct cord { - uint32_t x; - uint32_t y; -}; -struct msm_eeprom_data_t { - void * eeprom_data; - uint16_t index; -}; -struct msm_camera_csid_vc_cfg { - uint8_t cid; - uint8_t dt; - uint8_t decode_format; -}; -struct csi_lane_params_t { - uint16_t csi_lane_assign; - uint8_t csi_lane_mask; - uint8_t csi_if; - uint8_t csid_core[2]; - uint8_t csi_phy_sel; -}; -struct msm_camera_csid_lut_params { - uint8_t num_cid; - struct msm_camera_csid_vc_cfg * vc_cfg; -}; -struct msm_camera_csid_params { - uint8_t lane_cnt; - uint16_t lane_assign; - uint8_t phy_sel; - struct msm_camera_csid_lut_params lut_params; -}; -struct msm_camera_csiphy_params { - uint8_t lane_cnt; - uint8_t settle_cnt; - uint16_t lane_mask; - uint8_t combo_mode; - uint8_t csid_core; - uint64_t data_rate; -}; -struct msm_camera_csi2_params { - struct msm_camera_csid_params csid_params; - struct msm_camera_csiphy_params csiphy_params; -}; -enum msm_camera_csi_data_format { - CSI_8BIT, - CSI_10BIT, - CSI_12BIT, -}; -struct msm_camera_csi_params { - enum msm_camera_csi_data_format data_format; - uint8_t lane_cnt; - uint8_t lane_assign; - uint8_t settle_cnt; - uint8_t dpcm_scheme; -}; -enum csic_cfg_type_t { - CSIC_INIT, - CSIC_CFG, -}; -struct csic_cfg_data { - enum csic_cfg_type_t cfgtype; - struct msm_camera_csi_params * csic_params; -}; -enum csid_cfg_type_t { - CSID_INIT, - CSID_CFG, -}; -struct csid_cfg_data { - enum csid_cfg_type_t cfgtype; - union { - uint32_t csid_version; - struct msm_camera_csid_params * csid_params; - } cfg; -}; -enum csiphy_cfg_type_t { - CSIPHY_INIT, - CSIPHY_CFG, -}; -struct csiphy_cfg_data { - enum csiphy_cfg_type_t cfgtype; - struct msm_camera_csiphy_params * csiphy_params; -}; -#define CSI_EMBED_DATA 0x12 -#define CSI_RESERVED_DATA_0 0x13 -#define CSI_YUV422_8 0x1E -#define CSI_RAW8 0x2A -#define CSI_RAW10 0x2B -#define CSI_RAW12 0x2C -#define CSI_DECODE_6BIT 0 -#define CSI_DECODE_8BIT 1 -#define CSI_DECODE_10BIT 2 -#define CSI_DECODE_DPCM_10_8_10 5 -#define ISPIF_STREAM(intf,action,vfe) (((intf) << ISPIF_S_STREAM_SHIFT) + (action) + ((vfe) << ISPIF_VFE_INTF_SHIFT)) -#define ISPIF_ON_FRAME_BOUNDARY (0x01 << 0) -#define ISPIF_OFF_FRAME_BOUNDARY (0x01 << 1) -#define ISPIF_OFF_IMMEDIATELY (0x01 << 2) -#define ISPIF_S_STREAM_SHIFT 4 -#define ISPIF_VFE_INTF_SHIFT 12 -#define PIX_0 (0x01 << 0) -#define RDI_0 (0x01 << 1) -#define PIX_1 (0x01 << 2) -#define RDI_1 (0x01 << 3) -#define RDI_2 (0x01 << 4) -enum msm_ispif_vfe_intf { - VFE0, - VFE1, - VFE_MAX, -}; -enum msm_ispif_intftype { - PIX0, - RDI0, - PIX1, - RDI1, - RDI2, - INTF_MAX, -}; -enum msm_ispif_vc { - VC0, - VC1, - VC2, - VC3, -}; -enum msm_ispif_cid { - CID0, - CID1, - CID2, - CID3, - CID4, - CID5, - CID6, - CID7, - CID8, - CID9, - CID10, - CID11, - CID12, - CID13, - CID14, - CID15, -}; -struct msm_ispif_params { - uint8_t intftype; - uint16_t cid_mask; - uint8_t csid; - uint8_t vfe_intf; -}; -struct msm_ispif_params_list { - uint32_t len; - struct msm_ispif_params params[4]; -}; -enum ispif_cfg_type_t { - ISPIF_INIT, - ISPIF_SET_CFG, - ISPIF_SET_ON_FRAME_BOUNDARY, - ISPIF_SET_OFF_FRAME_BOUNDARY, - ISPIF_SET_OFF_IMMEDIATELY, - ISPIF_RELEASE, -}; -struct ispif_cfg_data { - enum ispif_cfg_type_t cfgtype; - union { - uint32_t csid_version; - int cmd; - struct msm_ispif_params_list ispif_params; - } cfg; -}; -enum msm_camera_i2c_reg_addr_type { - MSM_CAMERA_I2C_BYTE_ADDR = 1, - MSM_CAMERA_I2C_WORD_ADDR, - MSM_CAMERA_I2C_3B_ADDR, - MSM_CAMERA_I2C_DWORD_ADDR, -}; -#define MSM_CAMERA_I2C_DWORD_ADDR MSM_CAMERA_I2C_DWORD_ADDR -struct msm_camera_i2c_reg_array { - uint16_t reg_addr; - uint16_t reg_data; -}; -enum msm_camera_i2c_data_type { - MSM_CAMERA_I2C_BYTE_DATA = 1, - MSM_CAMERA_I2C_WORD_DATA, - MSM_CAMERA_I2C_SET_BYTE_MASK, - MSM_CAMERA_I2C_UNSET_BYTE_MASK, - MSM_CAMERA_I2C_SET_WORD_MASK, - MSM_CAMERA_I2C_UNSET_WORD_MASK, - MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA, -}; -struct msm_camera_i2c_reg_setting { - struct msm_camera_i2c_reg_array * reg_setting; - uint16_t size; - enum msm_camera_i2c_reg_addr_type addr_type; - enum msm_camera_i2c_data_type data_type; - uint16_t delay; -}; -enum oem_setting_type { - I2C_READ = 1, - I2C_WRITE, - GPIO_OP, - EEPROM_READ, - VREG_SET, - CLK_SET, -}; -struct sensor_oem_setting { - enum oem_setting_type type; - void * data; -}; -enum camera_vreg_type { - REG_LDO, - REG_VS, - REG_GPIO, -}; -enum msm_camera_vreg_name_t { - CAM_VDIG, - CAM_VIO, - CAM_VANA, - CAM_VAF, - CAM_VREG_MAX, -}; -struct msm_camera_csi_lane_params { - uint16_t csi_lane_assign; - uint16_t csi_lane_mask; -}; -struct camera_vreg_t { - const char * reg_name; - int min_voltage; - int max_voltage; - int op_mode; - uint32_t delay; -}; -struct msm_camera_vreg_setting { - struct camera_vreg_t * cam_vreg; - uint16_t num_vreg; - uint8_t enable; -}; -struct msm_cam_clk_info { - const char * clk_name; - long clk_rate; - uint32_t delay; -}; -struct msm_cam_clk_setting { - struct msm_cam_clk_info * clk_info; - uint16_t num_clk_info; - uint8_t enable; -}; -struct sensor_cfg_data { - int cfgtype; - int mode; - int rs; - uint8_t max_steps; - union { - int8_t effect; - uint8_t lens_shading; - uint16_t prevl_pf; - uint16_t prevp_pl; - uint16_t pictl_pf; - uint16_t pictp_pl; - uint32_t pict_max_exp_lc; - uint16_t p_fps; - uint8_t iso_type; - struct sensor_init_cfg init_info; - struct sensor_pict_fps gfps; - struct exp_gain_cfg exp_gain; - struct focus_cfg focus; - struct fps_cfg fps; - struct wb_info_cfg wb_info; - struct sensor_3d_exp_cfg sensor_3d_exp; - struct sensor_calib_data calib_info; - struct sensor_output_info_t output_info; - struct msm_eeprom_data_t eeprom_data; - struct csi_lane_params_t csi_lane_params; - uint16_t antibanding; - uint8_t contrast; - uint8_t saturation; - uint8_t sharpness; - int8_t brightness; - int ae_mode; - uint8_t wb_val; - int8_t exp_compensation; - uint32_t pclk; - struct cord aec_cord; - int is_autoflash; - struct mirror_flip mirror_flip; - void * setting; - } cfg; -}; -enum gpio_operation_type { - GPIO_REQUEST, - GPIO_FREE, - GPIO_SET_DIRECTION_OUTPUT, - GPIO_SET_DIRECTION_INPUT, - GPIO_GET_VALUE, - GPIO_SET_VALUE, -}; -struct msm_cam_gpio_operation { - enum gpio_operation_type op_type; - unsigned int address; - int value; - const char * tag; -}; -struct damping_params_t { - uint32_t damping_step; - uint32_t damping_delay; - uint32_t hw_params; -}; -enum actuator_type { - ACTUATOR_VCM, - ACTUATOR_PIEZO, - ACTUATOR_HVCM, - ACTUATOR_BIVCM, -}; -enum msm_actuator_data_type { - MSM_ACTUATOR_BYTE_DATA = 1, - MSM_ACTUATOR_WORD_DATA, -}; -enum msm_actuator_addr_type { - MSM_ACTUATOR_BYTE_ADDR = 1, - MSM_ACTUATOR_WORD_ADDR, -}; -enum msm_actuator_write_type { - MSM_ACTUATOR_WRITE_HW_DAMP, - MSM_ACTUATOR_WRITE_DAC, - MSM_ACTUATOR_WRITE, - MSM_ACTUATOR_WRITE_DIR_REG, - MSM_ACTUATOR_POLL, - MSM_ACTUATOR_READ_WRITE, -}; -struct msm_actuator_reg_params_t { - enum msm_actuator_write_type reg_write_type; - uint32_t hw_mask; - uint16_t reg_addr; - uint16_t hw_shift; - uint16_t data_type; - uint16_t addr_type; - uint16_t reg_data; - uint16_t delay; -}; -struct reg_settings_t { - uint16_t reg_addr; - uint16_t reg_data; -}; -struct region_params_t { - uint16_t step_bound[2]; - uint16_t code_per_step; -}; -struct msm_actuator_move_params_t { - int8_t dir; - int8_t sign_dir; - int16_t dest_step_pos; - int32_t num_steps; - struct damping_params_t * ringing_params; -}; -struct msm_actuator_tuning_params_t { - int16_t initial_code; - uint16_t pwd_step; - uint16_t region_size; - uint32_t total_steps; - struct region_params_t * region_params; -}; -struct msm_actuator_params_t { - enum actuator_type act_type; - uint8_t reg_tbl_size; - uint16_t data_size; - uint16_t init_setting_size; - uint32_t i2c_addr; - enum msm_actuator_addr_type i2c_addr_type; - enum msm_actuator_data_type i2c_data_type; - struct msm_actuator_reg_params_t * reg_tbl_params; - struct reg_settings_t * init_settings; -}; -struct msm_actuator_set_info_t { - struct msm_actuator_params_t actuator_params; - struct msm_actuator_tuning_params_t af_tuning_params; -}; -struct msm_actuator_get_info_t { - uint32_t focal_length_num; - uint32_t focal_length_den; - uint32_t f_number_num; - uint32_t f_number_den; - uint32_t f_pix_num; - uint32_t f_pix_den; - uint32_t total_f_dist_num; - uint32_t total_f_dist_den; - uint32_t hor_view_angle_num; - uint32_t hor_view_angle_den; - uint32_t ver_view_angle_num; - uint32_t ver_view_angle_den; -}; -enum af_camera_name { - ACTUATOR_MAIN_CAM_0, - ACTUATOR_MAIN_CAM_1, - ACTUATOR_MAIN_CAM_2, - ACTUATOR_MAIN_CAM_3, - ACTUATOR_MAIN_CAM_4, - ACTUATOR_MAIN_CAM_5, - ACTUATOR_WEB_CAM_0, - ACTUATOR_WEB_CAM_1, - ACTUATOR_WEB_CAM_2, -}; -struct msm_actuator_cfg_data { - int cfgtype; - uint8_t is_af_supported; - union { - struct msm_actuator_move_params_t move; - struct msm_actuator_set_info_t set_info; - struct msm_actuator_get_info_t get_info; - enum af_camera_name cam_name; - } cfg; -}; -struct msm_eeprom_support { - uint16_t is_supported; - uint16_t size; - uint16_t index; - uint16_t qvalue; -}; -struct msm_calib_wb { - uint16_t r_over_g; - uint16_t b_over_g; - uint16_t gr_over_gb; -}; -struct msm_calib_af { - uint16_t macro_dac; - uint16_t inf_dac; - uint16_t start_dac; -}; -struct msm_calib_lsc { - uint16_t r_gain[221]; - uint16_t b_gain[221]; - uint16_t gr_gain[221]; - uint16_t gb_gain[221]; -}; -struct pixel_t { - int x; - int y; -}; -struct msm_calib_dpc { - uint16_t validcount; - struct pixel_t snapshot_coord[128]; - struct pixel_t preview_coord[128]; - struct pixel_t video_coord[128]; -}; -struct msm_calib_raw { - uint8_t * data; - uint32_t size; -}; -struct msm_camera_eeprom_info_t { - struct msm_eeprom_support af; - struct msm_eeprom_support wb; - struct msm_eeprom_support lsc; - struct msm_eeprom_support dpc; - struct msm_eeprom_support raw; -}; -struct msm_eeprom_cfg_data { - int cfgtype; - uint8_t is_eeprom_supported; - union { - struct msm_eeprom_data_t get_data; - struct msm_camera_eeprom_info_t get_info; - } cfg; -}; -struct sensor_large_data { - int cfgtype; - union { - struct sensor_3d_cali_data_t sensor_3d_cali_data; - } data; -}; -enum sensor_type_t { - BAYER, - YUV, - JPEG_SOC, -}; -enum flash_type { - LED_FLASH, - STROBE_FLASH, -}; -enum strobe_flash_ctrl_type { - STROBE_FLASH_CTRL_INIT, - STROBE_FLASH_CTRL_CHARGE, - STROBE_FLASH_CTRL_RELEASE -}; -struct strobe_flash_ctrl_data { - enum strobe_flash_ctrl_type type; - int charge_en; -}; -struct msm_camera_info { - int num_cameras; - uint8_t has_3d_support[MSM_MAX_CAMERA_SENSORS]; - uint8_t is_internal_cam[MSM_MAX_CAMERA_SENSORS]; - uint32_t s_mount_angle[MSM_MAX_CAMERA_SENSORS]; - const char * video_dev_name[MSM_MAX_CAMERA_SENSORS]; - enum sensor_type_t sensor_type[MSM_MAX_CAMERA_SENSORS]; -}; -struct msm_cam_config_dev_info { - int num_config_nodes; - const char * config_dev_name[MSM_MAX_CAMERA_CONFIGS]; - int config_dev_id[MSM_MAX_CAMERA_CONFIGS]; -}; -struct msm_mctl_node_info { - int num_mctl_nodes; - const char * mctl_node_name[MSM_MAX_CAMERA_SENSORS]; -}; -struct flash_ctrl_data { - int flashtype; - union { - int led_state; - struct strobe_flash_ctrl_data strobe_ctrl; - } ctrl_data; -}; -#define GET_NAME 0 -#define GET_PREVIEW_LINE_PER_FRAME 1 -#define GET_PREVIEW_PIXELS_PER_LINE 2 -#define GET_SNAPSHOT_LINE_PER_FRAME 3 -#define GET_SNAPSHOT_PIXELS_PER_LINE 4 -#define GET_SNAPSHOT_FPS 5 -#define GET_SNAPSHOT_MAX_EP_LINE_CNT 6 -struct msm_camsensor_info { - char name[MAX_SENSOR_NAME]; - uint8_t flash_enabled; - uint8_t strobe_flash_enabled; - uint8_t actuator_enabled; - uint8_t ispif_supported; - int8_t total_steps; - uint8_t support_3d; - enum flash_type flashtype; - enum sensor_type_t sensor_type; - uint32_t pxlcode; - uint32_t camera_type; - int mount_angle; - uint32_t max_width; - uint32_t max_height; -}; -#define V4L2_SINGLE_PLANE 0 -#define V4L2_MULTI_PLANE_Y 0 -#define V4L2_MULTI_PLANE_CBCR 1 -#define V4L2_MULTI_PLANE_CB 1 -#define V4L2_MULTI_PLANE_CR 2 -struct plane_data { - int plane_id; - uint32_t offset; - unsigned long size; -}; -struct img_plane_info { - uint32_t width; - uint32_t height; - uint32_t pixelformat; - uint8_t buffer_type; - uint8_t output_port; - uint32_t ext_mode; - uint8_t num_planes; - struct plane_data plane[MAX_PLANES]; - uint32_t sp_y_offset; - uint32_t inst_handle; -}; -#define QCAMERA_NAME "qcamera" -#define QCAMERA_SERVER_NAME "qcamera_server" -#define QCAMERA_VNODE_GROUP_ID MEDIA_ENT_F_IO_V4L -enum msm_cam_subdev_type { - CSIPHY_DEV, - CSID_DEV, - CSIC_DEV, - ISPIF_DEV, - VFE_DEV, - AXI_DEV, - VPE_DEV, - SENSOR_DEV, - ACTUATOR_DEV, - EEPROM_DEV, - GESTURE_DEV, - IRQ_ROUTER_DEV, - CPP_DEV, - CCI_DEV, - FLASH_DEV, -}; -struct msm_mctl_set_sdev_data { - uint32_t revision; - enum msm_cam_subdev_type sdev_type; -}; -#define MSM_CAM_V4L2_IOCTL_GET_CAMERA_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) -#define MSM_CAM_V4L2_IOCTL_GET_CONFIG_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) -#define MSM_CAM_V4L2_IOCTL_GET_MCTL_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t) -#define MSM_CAM_V4L2_IOCTL_CTRL_CMD_DONE _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t) -#define MSM_CAM_V4L2_IOCTL_GET_EVENT_PAYLOAD _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t) -#define MSM_CAM_IOCTL_SEND_EVENT _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct v4l2_event) -#define MSM_CAM_V4L2_IOCTL_CFG_VPE _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_vpe_cfg_cmd) -#define MSM_CAM_V4L2_IOCTL_PRIVATE_S_CTRL _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t) -#define MSM_CAM_V4L2_IOCTL_PRIVATE_G_CTRL _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t) -#define MSM_CAM_V4L2_IOCTL_PRIVATE_GENERAL _IOW('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_VPE_INIT _IO('V', BASE_VIDIOC_PRIVATE + 15) -#define VIDIOC_MSM_VPE_RELEASE _IO('V', BASE_VIDIOC_PRIVATE + 16) -#define VIDIOC_MSM_VPE_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_mctl_pp_params *) -#define VIDIOC_MSM_AXI_INIT _IOWR('V', BASE_VIDIOC_PRIVATE + 18, uint8_t *) -#define VIDIOC_MSM_AXI_RELEASE _IO('V', BASE_VIDIOC_PRIVATE + 19) -#define VIDIOC_MSM_AXI_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 20, void *) -#define VIDIOC_MSM_AXI_IRQ _IOWR('V', BASE_VIDIOC_PRIVATE + 21, void *) -#define VIDIOC_MSM_AXI_BUF_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 22, void *) -#define VIDIOC_MSM_AXI_RDI_COUNT_UPDATE _IOWR('V', BASE_VIDIOC_PRIVATE + 23, void *) -#define VIDIOC_MSM_VFE_INIT _IO('V', BASE_VIDIOC_PRIVATE + 24) -#define VIDIOC_MSM_VFE_RELEASE _IO('V', BASE_VIDIOC_PRIVATE + 25) -struct msm_camera_v4l2_ioctl_t { - uint32_t id; - uint32_t len; - uint32_t trans_code; - void * ioctl_ptr; -}; -struct msm_camera_vfe_params_t { - uint32_t operation_mode; - uint32_t capture_count; - uint8_t skip_reset; - uint8_t stop_immediately; - uint16_t port_info; - uint32_t inst_handle; - uint16_t cmd_type; -}; -enum msm_camss_irq_idx { - CAMERA_SS_IRQ_0, - CAMERA_SS_IRQ_1, - CAMERA_SS_IRQ_2, - CAMERA_SS_IRQ_3, - CAMERA_SS_IRQ_4, - CAMERA_SS_IRQ_5, - CAMERA_SS_IRQ_6, - CAMERA_SS_IRQ_7, - CAMERA_SS_IRQ_8, - CAMERA_SS_IRQ_9, - CAMERA_SS_IRQ_10, - CAMERA_SS_IRQ_11, - CAMERA_SS_IRQ_12, - CAMERA_SS_IRQ_MAX -}; -enum msm_cam_hw_idx { - MSM_CAM_HW_MICRO, - MSM_CAM_HW_CCI, - MSM_CAM_HW_CSI0, - MSM_CAM_HW_CSI1, - MSM_CAM_HW_CSI2, - MSM_CAM_HW_CSI3, - MSM_CAM_HW_ISPIF, - MSM_CAM_HW_CPP, - MSM_CAM_HW_VFE0, - MSM_CAM_HW_VFE1, - MSM_CAM_HW_JPEG0, - MSM_CAM_HW_JPEG1, - MSM_CAM_HW_JPEG2, - MSM_CAM_HW_MAX -}; -struct msm_camera_irq_cfg { - uint32_t cam_hw_mask; - uint8_t irq_idx; - uint8_t num_hwcore; -}; -#define MSM_IRQROUTER_CFG_COMPIRQ _IOWR('V', BASE_VIDIOC_PRIVATE, void *) -#define MAX_NUM_CPP_STRIPS 8 -enum msm_cpp_frame_type { - MSM_CPP_OFFLINE_FRAME, - MSM_CPP_REALTIME_FRAME, -}; -struct msm_cpp_frame_info_t { - int32_t frame_id; - uint32_t inst_id; - uint32_t client_id; - enum msm_cpp_frame_type frame_type; - uint32_t num_strips; -}; -struct msm_ver_num_info { - uint32_t main; - uint32_t minor; - uint32_t rev; -}; -#define VIDIOC_MSM_CPP_CFG _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_GET_INST_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) -#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0) -#define CLR_DEVID_MODE(handle) (handle &= 0x00FFFFFF) -#define SET_DEVID_MODE(handle,data) (handle |= ((0x1 << 31) | ((data & 0x7F) << 24))) -#define GET_DEVID_MODE(handle) ((handle & 0x80000000) ? ((handle & 0x7F000000) >> 24) : 0xFF) -#define CLR_IMG_MODE(handle) (handle &= 0xFF00FFFF) -#define SET_IMG_MODE(handle,data) (handle |= ((0x1 << 23) | ((data & 0x7F) << 16))) -#define GET_IMG_MODE(handle) ((handle & 0x800000) ? ((handle & 0x7F0000) >> 16) : 0xFF) -#define CLR_MCTLPP_INST_IDX(handle) (handle &= 0xFFFF00FF) -#define SET_MCTLPP_INST_IDX(handle,data) (handle |= ((0x1 << 15) | ((data & 0x7F) << 8))) -#define GET_MCTLPP_INST_IDX(handle) ((handle & 0x8000) ? ((handle & 0x7F00) >> 8) : 0xFF) -#define CLR_VIDEO_INST_IDX(handle) (handle &= 0xFFFFFF00) -#define GET_VIDEO_INST_IDX(handle) ((handle & 0x80) ? (handle & 0x7F) : 0xFF) -#define SET_VIDEO_INST_IDX(handle,data) (handle |= (0x1 << 7) | (data & 0x7F)) -#endif - diff --git a/sdm710/kernel-headers/media/msm_camsensor_sdk.h b/sdm710/kernel-headers/media/msm_camsensor_sdk.h deleted file mode 100644 index c5a5a739..00000000 --- a/sdm710/kernel-headers/media/msm_camsensor_sdk.h +++ /dev/null @@ -1,383 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_LINUX_MSM_CAMSENSOR_SDK_H -#define __UAPI_LINUX_MSM_CAMSENSOR_SDK_H -#include <linux/videodev2.h> -#define KVERSION 0x1 -#define MAX_POWER_CONFIG 12 -#define GPIO_OUT_LOW (0 << 1) -#define GPIO_OUT_HIGH (1 << 1) -#define CSI_EMBED_DATA 0x12 -#define CSI_RESERVED_DATA_0 0x13 -#define CSI_YUV422_8 0x1E -#define CSI_RAW8 0x2A -#define CSI_RAW10 0x2B -#define CSI_RAW12 0x2C -#define CSI_DECODE_6BIT 0 -#define CSI_DECODE_8BIT 1 -#define CSI_DECODE_10BIT 2 -#define CSI_DECODE_12BIT 3 -#define CSI_DECODE_DPCM_10_6_10 4 -#define CSI_DECODE_DPCM_10_8_10 5 -#define MAX_CID 16 -#define I2C_SEQ_REG_DATA_MAX 1024 -#define I2C_REG_DATA_MAX (8 * 1024) -#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') -#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') -#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') -#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') -#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') -#define MAX_ACTUATOR_REG_TBL_SIZE 8 -#define MAX_ACTUATOR_REGION 5 -#define NUM_ACTUATOR_DIR 2 -#define MAX_ACTUATOR_SCENARIO 8 -#define MAX_ACT_MOD_NAME_SIZE 32 -#define MAX_ACT_NAME_SIZE 32 -#define MAX_ACTUATOR_INIT_SET 120 -#define MAX_I2C_REG_SET 12 -#define MAX_LED_TRIGGERS 3 -#define MSM_EEPROM_MEMORY_MAP_MAX_SIZE 80 -#define MSM_EEPROM_MAX_MEM_MAP_CNT 8 -#define MSM_SENSOR_BYPASS_VIDEO_NODE 1 -enum msm_sensor_camera_id_t { - CAMERA_0, - CAMERA_1, - CAMERA_2, - CAMERA_3, - MAX_CAMERAS, -}; -enum i2c_freq_mode_t { - I2C_STANDARD_MODE, - I2C_FAST_MODE, - I2C_CUSTOM_MODE, - I2C_FAST_PLUS_MODE, - I2C_MAX_MODES, -}; -enum camb_position_t { - BACK_CAMERA_B, - FRONT_CAMERA_B, - AUX_CAMERA_B = 0x100, - INVALID_CAMERA_B, -}; -enum msm_sensor_power_seq_type_t { - SENSOR_CLK, - SENSOR_GPIO, - SENSOR_VREG, - SENSOR_I2C_MUX, - SENSOR_I2C, -}; -enum msm_camera_i2c_reg_addr_type { - MSM_CAMERA_I2C_BYTE_ADDR = 1, - MSM_CAMERA_I2C_WORD_ADDR, - MSM_CAMERA_I2C_3B_ADDR, - MSM_CAMERA_I2C_DWORD_ADDR, - MSM_CAMERA_I2C_ADDR_TYPE_MAX, -}; -#define MSM_CAMERA_I2C_DWORD_ADDR MSM_CAMERA_I2C_DWORD_ADDR -enum msm_camera_i2c_data_type { - MSM_CAMERA_I2C_BYTE_DATA = 1, - MSM_CAMERA_I2C_WORD_DATA, - MSM_CAMERA_I2C_DWORD_DATA, - MSM_CAMERA_I2C_SET_BYTE_MASK, - MSM_CAMERA_I2C_UNSET_BYTE_MASK, - MSM_CAMERA_I2C_SET_WORD_MASK, - MSM_CAMERA_I2C_UNSET_WORD_MASK, - MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA, - MSM_CAMERA_I2C_DATA_TYPE_MAX, -}; -enum msm_sensor_power_seq_gpio_t { - SENSOR_GPIO_RESET, - SENSOR_GPIO_STANDBY, - SENSOR_GPIO_AF_PWDM, - SENSOR_GPIO_VIO, - SENSOR_GPIO_VANA, - SENSOR_GPIO_VDIG, - SENSOR_GPIO_VAF, - SENSOR_GPIO_FL_EN, - SENSOR_GPIO_FL_NOW, - SENSOR_GPIO_FL_RESET, - SENSOR_GPIO_CUSTOM1, - SENSOR_GPIO_CUSTOM2, - SENSOR_GPIO_CUSTOM3, - SENSOR_GPIO_MAX, -}; -#define SENSOR_GPIO_CUSTOM3 SENSOR_GPIO_CUSTOM3 -enum msm_ir_cut_filter_gpio_t { - IR_CUT_FILTER_GPIO_P = 0, - IR_CUT_FILTER_GPIO_M, - IR_CUT_FILTER_GPIO_MAX, -}; -#define IR_CUT_FILTER_GPIO_P IR_CUT_FILTER_GPIO_P -#define IR_CUT_FILTER_GPIO_M IR_CUT_FILTER_GPIO_M -#define R_CUT_FILTER_GPIO_MAX IR_CUT_FILTER_GPIO_MAX -enum msm_camera_vreg_name_t { - CAM_VDIG, - CAM_VIO, - CAM_VANA, - CAM_VAF, - CAM_V_CUSTOM1, - CAM_V_CUSTOM2, - CAM_VREG_MAX, -}; -enum msm_sensor_clk_type_t { - SENSOR_CAM_MCLK, - SENSOR_CAM_CLK, - SENSOR_CAM_CLK_MAX, -}; -enum camerab_mode_t { - CAMERA_MODE_2D_B = (1 << 0), - CAMERA_MODE_3D_B = (1 << 1), - CAMERA_MODE_INVALID = (1 << 2), -}; -enum msm_actuator_data_type { - MSM_ACTUATOR_BYTE_DATA = 1, - MSM_ACTUATOR_WORD_DATA, -}; -enum msm_actuator_addr_type { - MSM_ACTUATOR_BYTE_ADDR = 1, - MSM_ACTUATOR_WORD_ADDR, -}; -enum msm_actuator_write_type { - MSM_ACTUATOR_WRITE_HW_DAMP, - MSM_ACTUATOR_WRITE_DAC, - MSM_ACTUATOR_WRITE, - MSM_ACTUATOR_WRITE_DIR_REG, - MSM_ACTUATOR_POLL, - MSM_ACTUATOR_READ_WRITE, -}; -enum msm_actuator_i2c_operation { - MSM_ACT_WRITE = 0, - MSM_ACT_POLL, -}; -enum actuator_type { - ACTUATOR_VCM, - ACTUATOR_PIEZO, - ACTUATOR_HVCM, - ACTUATOR_BIVCM, -}; -enum msm_flash_driver_type { - FLASH_DRIVER_PMIC, - FLASH_DRIVER_I2C, - FLASH_DRIVER_GPIO, - FLASH_DRIVER_DEFAULT -}; -enum msm_flash_cfg_type_t { - CFG_FLASH_INIT, - CFG_FLASH_RELEASE, - CFG_FLASH_OFF, - CFG_FLASH_LOW, - CFG_FLASH_HIGH, -}; -enum msm_ir_led_cfg_type_t { - CFG_IR_LED_INIT = 0, - CFG_IR_LED_RELEASE, - CFG_IR_LED_OFF, - CFG_IR_LED_ON, -}; -#define CFG_IR_LED_INIT CFG_IR_LED_INIT -#define CFG_IR_LED_RELEASE CFG_IR_LED_RELEASE -#define CFG_IR_LED_OFF CFG_IR_LED_OFF -#define CFG_IR_LED_ON CFG_IR_LED_ON -enum msm_laser_led_cfg_type_t { - CFG_LASER_LED_INIT, - CFG_LASER_LED_CONTROL, -}; -#define CFG_LASER_LED_INIT CFG_LASER_LED_INIT -#define CFG_LASER_LED_CONTROL CFG_LASER_LED_CONTROL -enum msm_ir_cut_cfg_type_t { - CFG_IR_CUT_INIT = 0, - CFG_IR_CUT_RELEASE, - CFG_IR_CUT_OFF, - CFG_IR_CUT_ON, -}; -#define CFG_IR_CUT_INIT CFG_IR_CUT_INIT -#define CFG_IR_CUT_RELEASE CFG_IR_CUT_RELEASE -#define CFG_IR_CUT_OFF CFG_IR_CUT_OFF -#define CFG_IR_CUT_ON CFG_IR_CUT_ON -enum msm_sensor_output_format_t { - MSM_SENSOR_BAYER, - MSM_SENSOR_YCBCR, - MSM_SENSOR_META, -}; -struct msm_sensor_power_setting { - enum msm_sensor_power_seq_type_t seq_type; - unsigned short seq_val; - long config_val; - unsigned short delay; - void * data[10]; -}; -struct msm_sensor_power_setting_array { - struct msm_sensor_power_setting power_setting_a[MAX_POWER_CONFIG]; - struct msm_sensor_power_setting * power_setting; - unsigned short size; - struct msm_sensor_power_setting power_down_setting_a[MAX_POWER_CONFIG]; - struct msm_sensor_power_setting * power_down_setting; - unsigned short size_down; -}; -enum msm_camera_i2c_operation { - MSM_CAM_WRITE = 0, - MSM_CAM_POLL, - MSM_CAM_READ, -}; -struct msm_sensor_i2c_sync_params { - unsigned int cid; - int csid; - unsigned short line; - unsigned short delay; -}; -struct msm_camera_reg_settings_t { - uint16_t reg_addr; - enum msm_camera_i2c_reg_addr_type addr_type; - uint16_t reg_data; - enum msm_camera_i2c_data_type data_type; - enum msm_camera_i2c_operation i2c_operation; - uint16_t delay; -}; -struct msm_eeprom_mem_map_t { - int slave_addr; - struct msm_camera_reg_settings_t mem_settings[MSM_EEPROM_MEMORY_MAP_MAX_SIZE]; - int memory_map_size; -}; -struct msm_eeprom_memory_map_array { - struct msm_eeprom_mem_map_t memory_map[MSM_EEPROM_MAX_MEM_MAP_CNT]; - uint32_t msm_size_of_max_mappings; -}; -struct msm_sensor_init_params { - int modes_supported; - enum camb_position_t position; - unsigned int sensor_mount_angle; -}; -struct msm_sensor_id_info_t { - unsigned short sensor_id_reg_addr; - unsigned short sensor_id; - unsigned short sensor_id_mask; -}; -struct msm_camera_sensor_slave_info { - char sensor_name[32]; - char eeprom_name[32]; - char actuator_name[32]; - char ois_name[32]; - char flash_name[32]; - enum msm_sensor_camera_id_t camera_id; - unsigned short slave_addr; - enum i2c_freq_mode_t i2c_freq_mode; - enum msm_camera_i2c_reg_addr_type addr_type; - struct msm_sensor_id_info_t sensor_id_info; - struct msm_sensor_power_setting_array power_setting_array; - unsigned char is_init_params_valid; - struct msm_sensor_init_params sensor_init_params; - enum msm_sensor_output_format_t output_format; - uint8_t bypass_video_node_creation; -}; -struct msm_camera_i2c_reg_array { - unsigned short reg_addr; - unsigned short reg_data; - unsigned int delay; -}; -struct msm_camera_i2c_reg_setting { - struct msm_camera_i2c_reg_array * reg_setting; - unsigned short size; - enum msm_camera_i2c_reg_addr_type addr_type; - enum msm_camera_i2c_data_type data_type; - unsigned short delay; -}; -struct msm_camera_csid_vc_cfg { - unsigned char cid; - unsigned char dt; - unsigned char decode_format; -}; -struct msm_camera_csid_lut_params { - unsigned char num_cid; - struct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID]; - struct msm_camera_csid_vc_cfg * vc_cfg[MAX_CID]; -}; -struct msm_camera_csid_params { - unsigned char lane_cnt; - unsigned short lane_assign; - unsigned char phy_sel; - unsigned int csi_clk; - struct msm_camera_csid_lut_params lut_params; - unsigned char csi_3p_sel; -}; -struct msm_camera_csid_testmode_parms { - unsigned int num_bytes_per_line; - unsigned int num_lines; - unsigned int h_blanking_count; - unsigned int v_blanking_count; - unsigned int payload_mode; -}; -struct msm_camera_csiphy_params { - unsigned char lane_cnt; - unsigned char settle_cnt; - unsigned short lane_mask; - unsigned char combo_mode; - unsigned char csid_core; - unsigned int csiphy_clk; - unsigned char csi_3phase; - uint64_t data_rate; -}; -struct msm_camera_i2c_seq_reg_array { - unsigned short reg_addr; - unsigned char reg_data[I2C_SEQ_REG_DATA_MAX]; - unsigned short reg_data_size; -}; -struct msm_camera_i2c_seq_reg_setting { - struct msm_camera_i2c_seq_reg_array * reg_setting; - unsigned short size; - enum msm_camera_i2c_reg_addr_type addr_type; - unsigned short delay; -}; -struct msm_actuator_reg_params_t { - enum msm_actuator_write_type reg_write_type; - unsigned int hw_mask; - unsigned short reg_addr; - unsigned short hw_shift; - unsigned short data_shift; - unsigned short data_type; - unsigned short addr_type; - unsigned short reg_data; - unsigned short delay; -}; -struct damping_params_t { - unsigned int damping_step; - unsigned int damping_delay; - unsigned int hw_params; -}; -struct region_params_t { - unsigned short step_bound[2]; - unsigned short code_per_step; - unsigned int qvalue; -}; -struct reg_settings_t { - unsigned short reg_addr; - enum msm_camera_i2c_reg_addr_type addr_type; - unsigned short reg_data; - enum msm_camera_i2c_data_type data_type; - enum msm_actuator_i2c_operation i2c_operation; - unsigned int delay; -}; -struct msm_camera_i2c_reg_setting_array { - struct msm_camera_i2c_reg_array reg_setting_a[MAX_I2C_REG_SET]; - unsigned short size; - enum msm_camera_i2c_reg_addr_type addr_type; - enum msm_camera_i2c_data_type data_type; - unsigned short delay; -}; -#endif - diff --git a/sdm710/kernel-headers/media/msm_fd.h b/sdm710/kernel-headers/media/msm_fd.h deleted file mode 100644 index 08a02174..00000000 --- a/sdm710/kernel-headers/media/msm_fd.h +++ /dev/null @@ -1,57 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_MSM_FD__ -#define __UAPI_MSM_FD__ -#include <linux/videodev2.h> -#include <linux/types.h> -struct msm_fd_event { - __u32 buf_index; - __u32 frame_id; - __u32 face_cnt; -}; -enum msm_fd_pose { - MSM_FD_POSE_FRONT, - MSM_FD_POSE_RIGHT_DIAGONAL, - MSM_FD_POSE_RIGHT, - MSM_FD_POSE_LEFT_DIAGONAL, - MSM_FD_POSE_LEFT, -}; -struct msm_fd_face_data { - __u32 pose; - __u32 angle; - __u32 confidence; - __u32 reserved; - struct v4l2_rect face; -}; -struct msm_fd_result { - __u32 frame_id; - __u32 face_cnt; - struct msm_fd_face_data * face_data; -}; -#define VIDIOC_MSM_FD_GET_RESULT _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_fd_result) -#define MSM_EVENT_FD (V4L2_EVENT_PRIVATE_START) -#define V4L2_CID_FD_SPEED (V4L2_CID_PRIVATE_BASE) -#define V4L2_CID_FD_FACE_ANGLE (V4L2_CID_PRIVATE_BASE + 1) -#define V4L2_CID_FD_MIN_FACE_SIZE (V4L2_CID_PRIVATE_BASE + 2) -#define V4L2_CID_FD_FACE_DIRECTION (V4L2_CID_PRIVATE_BASE + 3) -#define V4L2_CID_FD_DETECTION_THRESHOLD (V4L2_CID_PRIVATE_BASE + 4) -#define V4L2_CID_FD_WORK_MEMORY_SIZE (V4L2_CID_PRIVATE_BASE + 5) -#define V4L2_CID_FD_WORK_MEMORY_FD (V4L2_CID_PRIVATE_BASE + 6) -#endif - diff --git a/sdm710/kernel-headers/media/msm_gemini.h b/sdm710/kernel-headers/media/msm_gemini.h deleted file mode 100644 index 1467352e..00000000 --- a/sdm710/kernel-headers/media/msm_gemini.h +++ /dev/null @@ -1,90 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_MSM_GEMINI_H -#define __UAPI_MSM_GEMINI_H -#include <linux/types.h> -#include <linux/ioctl.h> -#define MSM_GMN_IOCTL_MAGIC 'g' -#define MSM_GMN_IOCTL_GET_HW_VERSION _IOW(MSM_GMN_IOCTL_MAGIC, 1, struct msm_gemini_hw_cmd *) -#define MSM_GMN_IOCTL_RESET _IOW(MSM_GMN_IOCTL_MAGIC, 2, struct msm_gemini_ctrl_cmd *) -#define MSM_GMN_IOCTL_STOP _IOW(MSM_GMN_IOCTL_MAGIC, 3, struct msm_gemini_hw_cmds *) -#define MSM_GMN_IOCTL_START _IOW(MSM_GMN_IOCTL_MAGIC, 4, struct msm_gemini_hw_cmds *) -#define MSM_GMN_IOCTL_INPUT_BUF_ENQUEUE _IOW(MSM_GMN_IOCTL_MAGIC, 5, struct msm_gemini_buf *) -#define MSM_GMN_IOCTL_INPUT_GET _IOW(MSM_GMN_IOCTL_MAGIC, 6, struct msm_gemini_buf *) -#define MSM_GMN_IOCTL_INPUT_GET_UNBLOCK _IOW(MSM_GMN_IOCTL_MAGIC, 7, int) -#define MSM_GMN_IOCTL_OUTPUT_BUF_ENQUEUE _IOW(MSM_GMN_IOCTL_MAGIC, 8, struct msm_gemini_buf *) -#define MSM_GMN_IOCTL_OUTPUT_GET _IOW(MSM_GMN_IOCTL_MAGIC, 9, struct msm_gemini_buf *) -#define MSM_GMN_IOCTL_OUTPUT_GET_UNBLOCK _IOW(MSM_GMN_IOCTL_MAGIC, 10, int) -#define MSM_GMN_IOCTL_EVT_GET _IOW(MSM_GMN_IOCTL_MAGIC, 11, struct msm_gemini_ctrl_cmd *) -#define MSM_GMN_IOCTL_EVT_GET_UNBLOCK _IOW(MSM_GMN_IOCTL_MAGIC, 12, int) -#define MSM_GMN_IOCTL_HW_CMD _IOW(MSM_GMN_IOCTL_MAGIC, 13, struct msm_gemini_hw_cmd *) -#define MSM_GMN_IOCTL_HW_CMDS _IOW(MSM_GMN_IOCTL_MAGIC, 14, struct msm_gemini_hw_cmds *) -#define MSM_GMN_IOCTL_TEST_DUMP_REGION _IOW(MSM_GMN_IOCTL_MAGIC, 15, unsigned long) -#define MSM_GMN_IOCTL_SET_MODE _IOW(MSM_GMN_IOCTL_MAGIC, 16, enum msm_gmn_out_mode) -#define MSM_GEMINI_MODE_REALTIME_ENCODE 0 -#define MSM_GEMINI_MODE_OFFLINE_ENCODE 1 -#define MSM_GEMINI_MODE_REALTIME_ROTATION 2 -#define MSM_GEMINI_MODE_OFFLINE_ROTATION 3 -enum msm_gmn_out_mode { - MSM_GMN_OUTMODE_FRAGMENTED, - MSM_GMN_OUTMODE_SINGLE -}; -struct msm_gemini_ctrl_cmd { - uint32_t type; - uint32_t len; - void * value; -}; -#define MSM_GEMINI_EVT_RESET 0 -#define MSM_GEMINI_EVT_FRAMEDONE 1 -#define MSM_GEMINI_EVT_ERR 2 -struct msm_gemini_buf { - uint32_t type; - int fd; - void * vaddr; - uint32_t y_off; - uint32_t y_len; - uint32_t framedone_len; - uint32_t cbcr_off; - uint32_t cbcr_len; - uint32_t num_of_mcu_rows; - uint32_t offset; -}; -#define MSM_GEMINI_HW_CMD_TYPE_READ 0 -#define MSM_GEMINI_HW_CMD_TYPE_WRITE 1 -#define MSM_GEMINI_HW_CMD_TYPE_WRITE_OR 2 -#define MSM_GEMINI_HW_CMD_TYPE_UWAIT 3 -#define MSM_GEMINI_HW_CMD_TYPE_MWAIT 4 -#define MSM_GEMINI_HW_CMD_TYPE_MDELAY 5 -#define MSM_GEMINI_HW_CMD_TYPE_UDELAY 6 -struct msm_gemini_hw_cmd { - uint32_t type : 4; - uint32_t n : 12; - uint32_t offset : 16; - uint32_t mask; - union { - uint32_t data; - uint32_t * pdata; - }; -}; -struct msm_gemini_hw_cmds { - uint32_t m; - struct msm_gemini_hw_cmd hw_cmd[1]; -}; -#endif - diff --git a/sdm710/kernel-headers/media/msm_gestures.h b/sdm710/kernel-headers/media/msm_gestures.h deleted file mode 100644 index 3a7f1cf2..00000000 --- a/sdm710/kernel-headers/media/msm_gestures.h +++ /dev/null @@ -1,54 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_MSM_GESTURES_H -#define __UAPI_MSM_GESTURES_H -#include <linux/types.h> -#include <linux/ioctl.h> -#include <media/msm_camera.h> -#define MSM_GES_IOCTL_CTRL_COMMAND _IOW('V', BASE_VIDIOC_PRIVATE + 20, struct v4l2_control) -#define VIDIOC_MSM_GESTURE_EVT _IOWR('V', BASE_VIDIOC_PRIVATE + 21, struct v4l2_event) -#define MSM_GES_GET_EVT_PAYLOAD _IOW('V', BASE_VIDIOC_PRIVATE + 22, struct msm_ges_evt) -#define VIDIOC_MSM_GESTURE_CAM_EVT _IOWR('V', BASE_VIDIOC_PRIVATE + 23, int) -#define MSM_GES_RESP_V4L2 MSM_CAM_RESP_MAX -#define MSM_GES_RESP_MAX (MSM_GES_RESP_V4L2 + 1) -#define MSM_SVR_RESP_MAX MSM_GES_RESP_MAX -#define MSM_V4L2_GES_BASE 100 -#define MSM_V4L2_GES_OPEN (MSM_V4L2_GES_BASE + 0) -#define MSM_V4L2_GES_CLOSE (MSM_V4L2_GES_BASE + 1) -#define MSM_V4L2_GES_CAM_OPEN (MSM_V4L2_GES_BASE + 2) -#define MSM_V4L2_GES_CAM_CLOSE (MSM_V4L2_GES_BASE + 3) -#define MSM_GES_APP_EVT_MIN (V4L2_EVENT_PRIVATE_START + 0x14) -#define MSM_GES_APP_NOTIFY_EVENT (MSM_GES_APP_EVT_MIN + 0) -#define MSM_GES_APP_NOTIFY_ERROR_EVENT (MSM_GES_APP_EVT_MIN + 1) -#define MSM_GES_APP_EVT_MAX (MSM_GES_APP_EVT_MIN + 2) -#define MSM_GESTURE_CID_CTRL_CMD V4L2_CID_BRIGHTNESS -#define MAX_GES_EVENTS 25 -struct msm_ges_ctrl_cmd { - int type; - void * value; - int len; - int fd; - uint32_t cookie; -}; -struct msm_ges_evt { - void * evt_data; - int evt_len; -}; -#endif - diff --git a/sdm710/kernel-headers/media/msm_isp.h b/sdm710/kernel-headers/media/msm_isp.h deleted file mode 100644 index bd11cb5e..00000000 --- a/sdm710/kernel-headers/media/msm_isp.h +++ /dev/null @@ -1,334 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_MSM_ISP_H__ -#define __UAPI_MSM_ISP_H__ -#define BIT(nr) (1UL << (nr)) -#define MSG_ID_RESET_ACK 0 -#define MSG_ID_START_ACK 1 -#define MSG_ID_STOP_ACK 2 -#define MSG_ID_UPDATE_ACK 3 -#define MSG_ID_OUTPUT_P 4 -#define MSG_ID_OUTPUT_T 5 -#define MSG_ID_OUTPUT_S 6 -#define MSG_ID_OUTPUT_V 7 -#define MSG_ID_SNAPSHOT_DONE 8 -#define MSG_ID_STATS_AEC 9 -#define MSG_ID_STATS_AF 10 -#define MSG_ID_STATS_AWB 11 -#define MSG_ID_STATS_RS 12 -#define MSG_ID_STATS_CS 13 -#define MSG_ID_STATS_IHIST 14 -#define MSG_ID_STATS_SKIN 15 -#define MSG_ID_EPOCH1 16 -#define MSG_ID_EPOCH2 17 -#define MSG_ID_SYNC_TIMER0_DONE 18 -#define MSG_ID_SYNC_TIMER1_DONE 19 -#define MSG_ID_SYNC_TIMER2_DONE 20 -#define MSG_ID_ASYNC_TIMER0_DONE 21 -#define MSG_ID_ASYNC_TIMER1_DONE 22 -#define MSG_ID_ASYNC_TIMER2_DONE 23 -#define MSG_ID_ASYNC_TIMER3_DONE 24 -#define MSG_ID_AE_OVERFLOW 25 -#define MSG_ID_AF_OVERFLOW 26 -#define MSG_ID_AWB_OVERFLOW 27 -#define MSG_ID_RS_OVERFLOW 28 -#define MSG_ID_CS_OVERFLOW 29 -#define MSG_ID_IHIST_OVERFLOW 30 -#define MSG_ID_SKIN_OVERFLOW 31 -#define MSG_ID_AXI_ERROR 32 -#define MSG_ID_CAMIF_OVERFLOW 33 -#define MSG_ID_VIOLATION 34 -#define MSG_ID_CAMIF_ERROR 35 -#define MSG_ID_BUS_OVERFLOW 36 -#define MSG_ID_SOF_ACK 37 -#define MSG_ID_STOP_REC_ACK 38 -#define MSG_ID_STATS_AWB_AEC 39 -#define MSG_ID_OUTPUT_PRIMARY 40 -#define MSG_ID_OUTPUT_SECONDARY 41 -#define MSG_ID_STATS_COMPOSITE 42 -#define MSG_ID_OUTPUT_TERTIARY1 43 -#define MSG_ID_STOP_LS_ACK 44 -#define MSG_ID_OUTPUT_TERTIARY2 45 -#define MSG_ID_STATS_BG 46 -#define MSG_ID_STATS_BF 47 -#define MSG_ID_STATS_BHIST 48 -#define MSG_ID_RDI0_UPDATE_ACK 49 -#define MSG_ID_RDI1_UPDATE_ACK 50 -#define MSG_ID_RDI2_UPDATE_ACK 51 -#define MSG_ID_PIX0_UPDATE_ACK 52 -#define MSG_ID_PREV_STOP_ACK 53 -#define MSG_ID_STATS_BE 54 -#define VFE_CMD_DUMMY_0 0 -#define VFE_CMD_SET_CLK 1 -#define VFE_CMD_RESET 2 -#define VFE_CMD_START 3 -#define VFE_CMD_TEST_GEN_START 4 -#define VFE_CMD_OPERATION_CFG 5 -#define VFE_CMD_AXI_OUT_CFG 6 -#define VFE_CMD_CAMIF_CFG 7 -#define VFE_CMD_AXI_INPUT_CFG 8 -#define VFE_CMD_BLACK_LEVEL_CFG 9 -#define VFE_CMD_MESH_ROLL_OFF_CFG 10 -#define VFE_CMD_DEMUX_CFG 11 -#define VFE_CMD_FOV_CFG 12 -#define VFE_CMD_MAIN_SCALER_CFG 13 -#define VFE_CMD_WB_CFG 14 -#define VFE_CMD_COLOR_COR_CFG 15 -#define VFE_CMD_RGB_G_CFG 16 -#define VFE_CMD_LA_CFG 17 -#define VFE_CMD_CHROMA_EN_CFG 18 -#define VFE_CMD_CHROMA_SUP_CFG 19 -#define VFE_CMD_MCE_CFG 20 -#define VFE_CMD_SK_ENHAN_CFG 21 -#define VFE_CMD_ASF_CFG 22 -#define VFE_CMD_S2Y_CFG 23 -#define VFE_CMD_S2CbCr_CFG 24 -#define VFE_CMD_CHROMA_SUBS_CFG 25 -#define VFE_CMD_OUT_CLAMP_CFG 26 -#define VFE_CMD_FRAME_SKIP_CFG 27 -#define VFE_CMD_DUMMY_1 28 -#define VFE_CMD_DUMMY_2 29 -#define VFE_CMD_DUMMY_3 30 -#define VFE_CMD_UPDATE 31 -#define VFE_CMD_BL_LVL_UPDATE 32 -#define VFE_CMD_DEMUX_UPDATE 33 -#define VFE_CMD_FOV_UPDATE 34 -#define VFE_CMD_MAIN_SCALER_UPDATE 35 -#define VFE_CMD_WB_UPDATE 36 -#define VFE_CMD_COLOR_COR_UPDATE 37 -#define VFE_CMD_RGB_G_UPDATE 38 -#define VFE_CMD_LA_UPDATE 39 -#define VFE_CMD_CHROMA_EN_UPDATE 40 -#define VFE_CMD_CHROMA_SUP_UPDATE 41 -#define VFE_CMD_MCE_UPDATE 42 -#define VFE_CMD_SK_ENHAN_UPDATE 43 -#define VFE_CMD_S2CbCr_UPDATE 44 -#define VFE_CMD_S2Y_UPDATE 45 -#define VFE_CMD_ASF_UPDATE 46 -#define VFE_CMD_FRAME_SKIP_UPDATE 47 -#define VFE_CMD_CAMIF_FRAME_UPDATE 48 -#define VFE_CMD_STATS_AF_UPDATE 49 -#define VFE_CMD_STATS_AE_UPDATE 50 -#define VFE_CMD_STATS_AWB_UPDATE 51 -#define VFE_CMD_STATS_RS_UPDATE 52 -#define VFE_CMD_STATS_CS_UPDATE 53 -#define VFE_CMD_STATS_SKIN_UPDATE 54 -#define VFE_CMD_STATS_IHIST_UPDATE 55 -#define VFE_CMD_DUMMY_4 56 -#define VFE_CMD_EPOCH1_ACK 57 -#define VFE_CMD_EPOCH2_ACK 58 -#define VFE_CMD_START_RECORDING 59 -#define VFE_CMD_STOP_RECORDING 60 -#define VFE_CMD_DUMMY_5 61 -#define VFE_CMD_DUMMY_6 62 -#define VFE_CMD_CAPTURE 63 -#define VFE_CMD_DUMMY_7 64 -#define VFE_CMD_STOP 65 -#define VFE_CMD_GET_HW_VERSION 66 -#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67 -#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68 -#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69 -#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70 -#define VFE_CMD_JPEG_OUT_BUF_ENQ 71 -#define VFE_CMD_RAW_OUT_BUF_ENQ 72 -#define VFE_CMD_RAW_IN_BUF_ENQ 73 -#define VFE_CMD_STATS_AF_ENQ 74 -#define VFE_CMD_STATS_AE_ENQ 75 -#define VFE_CMD_STATS_AWB_ENQ 76 -#define VFE_CMD_STATS_RS_ENQ 77 -#define VFE_CMD_STATS_CS_ENQ 78 -#define VFE_CMD_STATS_SKIN_ENQ 79 -#define VFE_CMD_STATS_IHIST_ENQ 80 -#define VFE_CMD_DUMMY_8 81 -#define VFE_CMD_JPEG_ENC_CFG 82 -#define VFE_CMD_DUMMY_9 83 -#define VFE_CMD_STATS_AF_START 84 -#define VFE_CMD_STATS_AF_STOP 85 -#define VFE_CMD_STATS_AE_START 86 -#define VFE_CMD_STATS_AE_STOP 87 -#define VFE_CMD_STATS_AWB_START 88 -#define VFE_CMD_STATS_AWB_STOP 89 -#define VFE_CMD_STATS_RS_START 90 -#define VFE_CMD_STATS_RS_STOP 91 -#define VFE_CMD_STATS_CS_START 92 -#define VFE_CMD_STATS_CS_STOP 93 -#define VFE_CMD_STATS_SKIN_START 94 -#define VFE_CMD_STATS_SKIN_STOP 95 -#define VFE_CMD_STATS_IHIST_START 96 -#define VFE_CMD_STATS_IHIST_STOP 97 -#define VFE_CMD_DUMMY_10 98 -#define VFE_CMD_SYNC_TIMER_SETTING 99 -#define VFE_CMD_ASYNC_TIMER_SETTING 100 -#define VFE_CMD_LIVESHOT 101 -#define VFE_CMD_LA_SETUP 102 -#define VFE_CMD_LINEARIZATION_CFG 103 -#define VFE_CMD_DEMOSAICV3 104 -#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105 -#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106 -#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107 -#define VFE_CMD_DEMOSAICV3_ABF_CFG 108 -#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109 -#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110 -#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111 -#define VFE_CMD_XBAR_CFG 112 -#define VFE_CMD_MODULE_CFG 113 -#define VFE_CMD_ZSL 114 -#define VFE_CMD_LINEARIZATION_UPDATE 115 -#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116 -#define VFE_CMD_CLF_CFG 117 -#define VFE_CMD_CLF_LUMA_UPDATE 118 -#define VFE_CMD_CLF_CHROMA_UPDATE 119 -#define VFE_CMD_PCA_ROLL_OFF_CFG 120 -#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121 -#define VFE_CMD_GET_REG_DUMP 122 -#define VFE_CMD_GET_LINEARIZATON_TABLE 123 -#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124 -#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125 -#define VFE_CMD_GET_RGB_G_TABLE 126 -#define VFE_CMD_GET_LA_TABLE 127 -#define VFE_CMD_DEMOSAICV3_UPDATE 128 -#define VFE_CMD_ACTIVE_REGION_CFG 129 -#define VFE_CMD_COLOR_PROCESSING_CONFIG 130 -#define VFE_CMD_STATS_WB_AEC_CONFIG 131 -#define VFE_CMD_STATS_WB_AEC_UPDATE 132 -#define VFE_CMD_Y_GAMMA_CONFIG 133 -#define VFE_CMD_SCALE_OUTPUT1_CONFIG 134 -#define VFE_CMD_SCALE_OUTPUT2_CONFIG 135 -#define VFE_CMD_CAPTURE_RAW 136 -#define VFE_CMD_STOP_LIVESHOT 137 -#define VFE_CMD_RECONFIG_VFE 138 -#define VFE_CMD_STATS_REQBUF 139 -#define VFE_CMD_STATS_ENQUEUEBUF 140 -#define VFE_CMD_STATS_FLUSH_BUFQ 141 -#define VFE_CMD_STATS_UNREGBUF 142 -#define VFE_CMD_STATS_BG_START 143 -#define VFE_CMD_STATS_BG_STOP 144 -#define VFE_CMD_STATS_BF_START 145 -#define VFE_CMD_STATS_BF_STOP 146 -#define VFE_CMD_STATS_BHIST_START 147 -#define VFE_CMD_STATS_BHIST_STOP 148 -#define VFE_CMD_RESET_2 149 -#define VFE_CMD_FOV_ENC_CFG 150 -#define VFE_CMD_FOV_VIEW_CFG 151 -#define VFE_CMD_FOV_ENC_UPDATE 152 -#define VFE_CMD_FOV_VIEW_UPDATE 153 -#define VFE_CMD_SCALER_ENC_CFG 154 -#define VFE_CMD_SCALER_VIEW_CFG 155 -#define VFE_CMD_SCALER_ENC_UPDATE 156 -#define VFE_CMD_SCALER_VIEW_UPDATE 157 -#define VFE_CMD_COLORXFORM_ENC_CFG 158 -#define VFE_CMD_COLORXFORM_VIEW_CFG 159 -#define VFE_CMD_COLORXFORM_ENC_UPDATE 160 -#define VFE_CMD_COLORXFORM_VIEW_UPDATE 161 -#define VFE_CMD_TEST_GEN_CFG 162 -#define VFE_CMD_STATS_BE_START 163 -#define VFE_CMD_STATS_BE_STOP 164 -struct msm_isp_cmd { - int32_t id; - uint16_t length; - void * value; -}; -#define VPE_CMD_DUMMY_0 0 -#define VPE_CMD_INIT 1 -#define VPE_CMD_DEINIT 2 -#define VPE_CMD_ENABLE 3 -#define VPE_CMD_DISABLE 4 -#define VPE_CMD_RESET 5 -#define VPE_CMD_FLUSH 6 -#define VPE_CMD_OPERATION_MODE_CFG 7 -#define VPE_CMD_INPUT_PLANE_CFG 8 -#define VPE_CMD_OUTPUT_PLANE_CFG 9 -#define VPE_CMD_INPUT_PLANE_UPDATE 10 -#define VPE_CMD_SCALE_CFG_TYPE 11 -#define VPE_CMD_ZOOM 13 -#define VPE_CMD_MAX 14 -#define MSM_PP_CMD_TYPE_NOT_USED 0 -#define MSM_PP_CMD_TYPE_VPE 1 -#define MSM_PP_CMD_TYPE_MCTL 2 -#define MCTL_CMD_DUMMY_0 0 -#define MCTL_CMD_GET_FRAME_BUFFER 1 -#define MCTL_CMD_PUT_FRAME_BUFFER 2 -#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 -#define MCTL_PP_EVENT_NOTUSED 0 -#define MCTL_PP_EVENT_CMD_ACK 1 -#define VPE_OPERATION_MODE_CFG_LEN 4 -#define VPE_INPUT_PLANE_CFG_LEN 24 -#define VPE_OUTPUT_PLANE_CFG_LEN 20 -#define VPE_INPUT_PLANE_UPDATE_LEN 12 -#define VPE_SCALER_CONFIG_LEN 260 -#define VPE_DIS_OFFSET_CFG_LEN 12 -#define CAPTURE_WIDTH 1280 -#define IMEM_Y_SIZE (CAPTURE_WIDTH * 16) -#define IMEM_CBCR_SIZE (CAPTURE_WIDTH * 8) -#define IMEM_Y_PING_OFFSET 0x2E000000 -#define IMEM_CBCR_PING_OFFSET (IMEM_Y_PING_OFFSET + IMEM_Y_SIZE) -#define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE) -#define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE) -struct msm_vpe_op_mode_cfg { - uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN]; -}; -struct msm_vpe_input_plane_cfg { - uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN]; -}; -struct msm_vpe_output_plane_cfg { - uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN]; -}; -struct msm_vpe_input_plane_update_cfg { - uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN]; -}; -struct msm_vpe_scaler_cfg { - uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN]; -}; -struct msm_vpe_flush_frame_buffer { - uint32_t src_buf_handle; - uint32_t dest_buf_handle; - int path; -}; -struct msm_mctl_pp_frame_buffer { - uint32_t buf_handle; - int path; -}; -struct msm_mctl_pp_divert_pp { - int path; - int enable; -}; -struct msm_vpe_clock_rate { - uint32_t rate; -}; -#define MSM_MCTL_PP_VPE_FRAME_ACK (1 << 0) -#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1 << 1) -#define VFE_OUTPUTS_MAIN_AND_PREVIEW BIT(0) -#define VFE_OUTPUTS_MAIN_AND_VIDEO BIT(1) -#define VFE_OUTPUTS_MAIN_AND_THUMB BIT(2) -#define VFE_OUTPUTS_THUMB_AND_MAIN BIT(3) -#define VFE_OUTPUTS_PREVIEW_AND_VIDEO BIT(4) -#define VFE_OUTPUTS_VIDEO_AND_PREVIEW BIT(5) -#define VFE_OUTPUTS_PREVIEW BIT(6) -#define VFE_OUTPUTS_VIDEO BIT(7) -#define VFE_OUTPUTS_RAW BIT(8) -#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9) -#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10) -#define VFE_OUTPUTS_RDI0 BIT(11) -#define VFE_OUTPUTS_RDI1 BIT(12) -struct msm_frame_info { - uint32_t inst_handle; - uint32_t path; -}; -#endif - diff --git a/sdm710/kernel-headers/media/msm_jpeg.h b/sdm710/kernel-headers/media/msm_jpeg.h deleted file mode 100644 index 6f156b8c..00000000 --- a/sdm710/kernel-headers/media/msm_jpeg.h +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_LINUX_MSM_JPEG_H -#define __UAPI_LINUX_MSM_JPEG_H -#include <linux/types.h> -#include <linux/ioctl.h> -#define OUTPUT_H2V1 0 -#define OUTPUT_H2V2 1 -#define OUTPUT_BYTE 6 -#define MSM_JPEG_IOCTL_MAGIC 'g' -#define MSM_JPEG_IOCTL_GET_HW_VERSION _IOW(MSM_JPEG_IOCTL_MAGIC, 1, struct msm_jpeg_hw_cmd) -#define MSM_JPEG_IOCTL_RESET _IOW(MSM_JPEG_IOCTL_MAGIC, 2, struct msm_jpeg_ctrl_cmd) -#define MSM_JPEG_IOCTL_STOP _IOW(MSM_JPEG_IOCTL_MAGIC, 3, struct msm_jpeg_hw_cmds) -#define MSM_JPEG_IOCTL_START _IOW(MSM_JPEG_IOCTL_MAGIC, 4, struct msm_jpeg_hw_cmds) -#define MSM_JPEG_IOCTL_INPUT_BUF_ENQUEUE _IOW(MSM_JPEG_IOCTL_MAGIC, 5, struct msm_jpeg_buf) -#define MSM_JPEG_IOCTL_INPUT_GET _IOW(MSM_JPEG_IOCTL_MAGIC, 6, struct msm_jpeg_buf) -#define MSM_JPEG_IOCTL_INPUT_GET_UNBLOCK _IOW(MSM_JPEG_IOCTL_MAGIC, 7, int) -#define MSM_JPEG_IOCTL_OUTPUT_BUF_ENQUEUE _IOW(MSM_JPEG_IOCTL_MAGIC, 8, struct msm_jpeg_buf) -#define MSM_JPEG_IOCTL_OUTPUT_GET _IOW(MSM_JPEG_IOCTL_MAGIC, 9, struct msm_jpeg_buf) -#define MSM_JPEG_IOCTL_OUTPUT_GET_UNBLOCK _IOW(MSM_JPEG_IOCTL_MAGIC, 10, int) -#define MSM_JPEG_IOCTL_EVT_GET _IOW(MSM_JPEG_IOCTL_MAGIC, 11, struct msm_jpeg_ctrl_cmd) -#define MSM_JPEG_IOCTL_EVT_GET_UNBLOCK _IOW(MSM_JPEG_IOCTL_MAGIC, 12, int) -#define MSM_JPEG_IOCTL_HW_CMD _IOW(MSM_JPEG_IOCTL_MAGIC, 13, struct msm_jpeg_hw_cmd) -#define MSM_JPEG_IOCTL_HW_CMDS _IOW(MSM_JPEG_IOCTL_MAGIC, 14, struct msm_jpeg_hw_cmds) -#define MSM_JPEG_IOCTL_TEST_DUMP_REGION _IOW(MSM_JPEG_IOCTL_MAGIC, 15, unsigned long) -#define MSM_JPEG_IOCTL_SET_CLK_RATE _IOW(MSM_JPEG_IOCTL_MAGIC, 16, unsigned int) -#define MSM_JPEG_MODE_REALTIME_ENCODE 0 -#define MSM_JPEG_MODE_OFFLINE_ENCODE 1 -#define MSM_JPEG_MODE_REALTIME_ROTATION 2 -#define MSM_JPEG_MODE_OFFLINE_ROTATION 3 -struct msm_jpeg_ctrl_cmd { - uint32_t type; - uint32_t len; - void * value; -}; -#define MSM_JPEG_EVT_RESET 0 -#define MSM_JPEG_EVT_SESSION_DONE 1 -#define MSM_JPEG_EVT_ERR 2 -struct msm_jpeg_buf { - uint32_t type; - int fd; - void * vaddr; - uint32_t y_off; - uint32_t y_len; - uint32_t framedone_len; - uint32_t cbcr_off; - uint32_t cbcr_len; - uint32_t num_of_mcu_rows; - uint32_t offset; - uint32_t pln2_off; - uint32_t pln2_len; -}; -#define MSM_JPEG_HW_CMD_TYPE_READ 0 -#define MSM_JPEG_HW_CMD_TYPE_WRITE 1 -#define MSM_JPEG_HW_CMD_TYPE_WRITE_OR 2 -#define MSM_JPEG_HW_CMD_TYPE_UWAIT 3 -#define MSM_JPEG_HW_CMD_TYPE_MWAIT 4 -#define MSM_JPEG_HW_CMD_TYPE_MDELAY 5 -#define MSM_JPEG_HW_CMD_TYPE_UDELAY 6 -struct msm_jpeg_hw_cmd { - uint32_t type : 4; - uint32_t n : 12; - uint32_t offset : 16; - uint32_t mask; - union { - uint32_t data; - uint32_t * pdata; - }; -}; -struct msm_jpeg_hw_cmds { - uint32_t m; - struct msm_jpeg_hw_cmd hw_cmd[1]; -}; -#endif - diff --git a/sdm710/kernel-headers/media/msm_jpeg_dma.h b/sdm710/kernel-headers/media/msm_jpeg_dma.h deleted file mode 100644 index 51f888be..00000000 --- a/sdm710/kernel-headers/media/msm_jpeg_dma.h +++ /dev/null @@ -1,29 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_MSM_JPEG_DMA__ -#define __UAPI_MSM_JPEG_DMA__ -#include <linux/videodev2.h> -#define V4L2_CID_JPEG_DMA_SPEED (V4L2_CID_PRIVATE_BASE) -#define V4L2_CID_JPEG_DMA_MAX_DOWN_SCALE (V4L2_CID_PRIVATE_BASE + 1) -struct msm_jpeg_dma_buff { - int32_t fd; - uint32_t offset; -}; -#endif - diff --git a/sdm710/kernel-headers/media/msm_media_info.h b/sdm710/kernel-headers/media/msm_media_info.h deleted file mode 100644 index 0f4d7f75..00000000 --- a/sdm710/kernel-headers/media/msm_media_info.h +++ /dev/null @@ -1,1398 +0,0 @@ -#ifndef __MEDIA_INFO_H__ -#define __MEDIA_INFO_H__ - -#ifndef MSM_MEDIA_ALIGN -#define MSM_MEDIA_ALIGN(__sz, __align) (((__align) & ((__align) - 1)) ?\ - ((((__sz) + (__align) - 1) / (__align)) * (__align)) :\ - (((__sz) + (__align) - 1) & (~((__align) - 1)))) -#endif - -#ifndef MSM_MEDIA_ROUNDUP -#define MSM_MEDIA_ROUNDUP(__sz, __r) (((__sz) + ((__r) - 1)) / (__r)) -#endif - -#ifndef MSM_MEDIA_MAX -#define MSM_MEDIA_MAX(__a, __b) ((__a) > (__b)?(__a):(__b)) -#endif - -enum color_fmts { - /* Venus NV12: - * YUV 4:2:0 image with a plane of 8 bit Y samples followed - * by an interleaved U/V plane containing 8 bit 2x2 subsampled - * colour difference samples. - * - * <-------- Y/UV_Stride --------> - * <------- Width -------> - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * U V U V U V U V U V U V . . . . ^ - * U V U V U V U V U V U V . . . . | - * U V U V U V U V U V U V . . . . | - * U V U V U V U V U V U V . . . . UV_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . --> Buffer size alignment - * - * Y_Stride : Width aligned to 128 - * UV_Stride : Width aligned to 128 - * Y_Scanlines: Height aligned to 32 - * UV_Scanlines: Height/2 aligned to 16 - * Extradata: Arbitrary (software-imposed) padding - * Total size = align((Y_Stride * Y_Scanlines - * + UV_Stride * UV_Scanlines - * + max(Extradata, Y_Stride * 8), 4096) - */ - COLOR_FMT_NV12, - - /* Venus NV21: - * YUV 4:2:0 image with a plane of 8 bit Y samples followed - * by an interleaved V/U plane containing 8 bit 2x2 subsampled - * colour difference samples. - * - * <-------- Y/UV_Stride --------> - * <------- Width -------> - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * V U V U V U V U V U V U . . . . ^ - * V U V U V U V U V U V U . . . . | - * V U V U V U V U V U V U . . . . | - * V U V U V U V U V U V U . . . . UV_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . --> Padding & Buffer size alignment - * - * Y_Stride : Width aligned to 128 - * UV_Stride : Width aligned to 128 - * Y_Scanlines: Height aligned to 32 - * UV_Scanlines: Height/2 aligned to 16 - * Extradata: Arbitrary (software-imposed) padding - * Total size = align((Y_Stride * Y_Scanlines - * + UV_Stride * UV_Scanlines - * + max(Extradata, Y_Stride * 8), 4096) - */ - COLOR_FMT_NV21, - /* Venus NV12_MVTB: - * Two YUV 4:2:0 images/views one after the other - * in a top-bottom layout, same as NV12 - * with a plane of 8 bit Y samples followed - * by an interleaved U/V plane containing 8 bit 2x2 subsampled - * colour difference samples. - * - * - * <-------- Y/UV_Stride --------> - * <------- Width -------> - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^ - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | | - * . . . . . . . . . . . . . . . . | View_1 - * . . . . . . . . . . . . . . . . | | - * . . . . . . . . . . . . . . . . | | - * . . . . . . . . . . . . . . . . V | - * U V U V U V U V U V U V . . . . ^ | - * U V U V U V U V U V U V . . . . | | - * U V U V U V U V U V U V . . . . | | - * U V U V U V U V U V U V . . . . UV_Scanlines | - * . . . . . . . . . . . . . . . . | | - * . . . . . . . . . . . . . . . . V V - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^ - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | | - * . . . . . . . . . . . . . . . . | View_2 - * . . . . . . . . . . . . . . . . | | - * . . . . . . . . . . . . . . . . | | - * . . . . . . . . . . . . . . . . V | - * U V U V U V U V U V U V . . . . ^ | - * U V U V U V U V U V U V . . . . | | - * U V U V U V U V U V U V . . . . | | - * U V U V U V U V U V U V . . . . UV_Scanlines | - * . . . . . . . . . . . . . . . . | | - * . . . . . . . . . . . . . . . . V V - * . . . . . . . . . . . . . . . . --> Buffer size alignment - * - * Y_Stride : Width aligned to 128 - * UV_Stride : Width aligned to 128 - * Y_Scanlines: Height aligned to 32 - * UV_Scanlines: Height/2 aligned to 16 - * View_1 begin at: 0 (zero) - * View_2 begin at: Y_Stride * Y_Scanlines + UV_Stride * UV_Scanlines - * Extradata: Arbitrary (software-imposed) padding - * Total size = align((2*(Y_Stride * Y_Scanlines) - * + 2*(UV_Stride * UV_Scanlines) + Extradata), 4096) - */ - COLOR_FMT_NV12_MVTB, - /* - * The buffer can be of 2 types: - * (1) Venus NV12 UBWC Progressive - * (2) Venus NV12 UBWC Interlaced - * - * (1) Venus NV12 UBWC Progressive Buffer Format: - * Compressed Macro-tile format for NV12. - * Contains 4 planes in the following order - - * (A) Y_Meta_Plane - * (B) Y_UBWC_Plane - * (C) UV_Meta_Plane - * (D) UV_UBWC_Plane - * - * Y_Meta_Plane consists of meta information to decode compressed - * tile data in Y_UBWC_Plane. - * Y_UBWC_Plane consists of Y data in compressed macro-tile format. - * UBWC decoder block will use the Y_Meta_Plane data together with - * Y_UBWC_Plane data to produce loss-less uncompressed 8 bit Y samples. - * - * UV_Meta_Plane consists of meta information to decode compressed - * tile data in UV_UBWC_Plane. - * UV_UBWC_Plane consists of UV data in compressed macro-tile format. - * UBWC decoder block will use UV_Meta_Plane data together with - * UV_UBWC_Plane data to produce loss-less uncompressed 8 bit 2x2 - * subsampled color difference samples. - * - * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable - * and randomly accessible. There is no dependency between tiles. - * - * <----- Y_Meta_Stride ----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Height | - * M M M M M M M M M M M M . . | Meta_Y_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <--Compressed tile Y Stride---> - * <------- Width -------> - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * <----- UV_Meta_Stride ----> - * M M M M M M M M M M M M . . ^ - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . M_UV_Scanlines - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * <--Compressed tile UV Stride---> - * U* V* U* V* U* V* U* V* . . . . ^ - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . UV_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * - * Y_Stride = align(Width, 128) - * UV_Stride = align(Width, 128) - * Y_Scanlines = align(Height, 32) - * UV_Scanlines = align(Height/2, 16) - * Y_UBWC_Plane_size = align(Y_Stride * Y_Scanlines, 4096) - * UV_UBWC_Plane_size = align(UV_Stride * UV_Scanlines, 4096) - * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) - * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16) - * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096) - * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) - * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16) - * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align( Y_UBWC_Plane_size + UV_UBWC_Plane_size + - * Y_Meta_Plane_size + UV_Meta_Plane_size - * + max(Extradata, Y_Stride * 48), 4096) - * - * - * (2) Venus NV12 UBWC Interlaced Buffer Format: - * Compressed Macro-tile format for NV12 interlaced. - * Contains 8 planes in the following order - - * (A) Y_Meta_Top_Field_Plane - * (B) Y_UBWC_Top_Field_Plane - * (C) UV_Meta_Top_Field_Plane - * (D) UV_UBWC_Top_Field_Plane - * (E) Y_Meta_Bottom_Field_Plane - * (F) Y_UBWC_Bottom_Field_Plane - * (G) UV_Meta_Bottom_Field_Plane - * (H) UV_UBWC_Bottom_Field_Plane - * Y_Meta_Top_Field_Plane consists of meta information to decode - * compressed tile data for Y_UBWC_Top_Field_Plane. - * Y_UBWC_Top_Field_Plane consists of Y data in compressed macro-tile - * format for top field of an interlaced frame. - * UBWC decoder block will use the Y_Meta_Top_Field_Plane data together - * with Y_UBWC_Top_Field_Plane data to produce loss-less uncompressed - * 8 bit Y samples for top field of an interlaced frame. - * - * UV_Meta_Top_Field_Plane consists of meta information to decode - * compressed tile data in UV_UBWC_Top_Field_Plane. - * UV_UBWC_Top_Field_Plane consists of UV data in compressed macro-tile - * format for top field of an interlaced frame. - * UBWC decoder block will use UV_Meta_Top_Field_Plane data together - * with UV_UBWC_Top_Field_Plane data to produce loss-less uncompressed - * 8 bit subsampled color difference samples for top field of an - * interlaced frame. - * - * Each tile in Y_UBWC_Top_Field_Plane/UV_UBWC_Top_Field_Plane is - * independently decodable and randomly accessible. There is no - * dependency between tiles. - * - * Y_Meta_Bottom_Field_Plane consists of meta information to decode - * compressed tile data for Y_UBWC_Bottom_Field_Plane. - * Y_UBWC_Bottom_Field_Plane consists of Y data in compressed macro-tile - * format for bottom field of an interlaced frame. - * UBWC decoder block will use the Y_Meta_Bottom_Field_Plane data - * together with Y_UBWC_Bottom_Field_Plane data to produce loss-less - * uncompressed 8 bit Y samples for bottom field of an interlaced frame. - * - * UV_Meta_Bottom_Field_Plane consists of meta information to decode - * compressed tile data in UV_UBWC_Bottom_Field_Plane. - * UV_UBWC_Bottom_Field_Plane consists of UV data in compressed - * macro-tile format for bottom field of an interlaced frame. - * UBWC decoder block will use UV_Meta_Bottom_Field_Plane data together - * with UV_UBWC_Bottom_Field_Plane data to produce loss-less - * uncompressed 8 bit subsampled color difference samples for bottom - * field of an interlaced frame. - * - * Each tile in Y_UBWC_Bottom_Field_Plane/UV_UBWC_Bottom_Field_Plane is - * independently decodable and randomly accessible. There is no - * dependency between tiles. - * - * <-----Y_TF_Meta_Stride----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Half_height | - * M M M M M M M M M M M M . . | Meta_Y_TF_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <-Compressed tile Y_TF Stride-> - * <------- Width -------> - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Half_height | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_TF_Scanlines - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * <----UV_TF_Meta_Stride----> - * M M M M M M M M M M M M . . ^ - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . M_UV_TF_Scanlines - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * <-Compressed tile UV_TF Stride-> - * U* V* U* V* U* V* U* V* . . . . ^ - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . UV_TF_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * <-----Y_BF_Meta_Stride----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Half_height | - * M M M M M M M M M M M M . . | Meta_Y_BF_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <-Compressed tile Y_BF Stride-> - * <------- Width -------> - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Half_height | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_BF_Scanlines - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * <----UV_BF_Meta_Stride----> - * M M M M M M M M M M M M . . ^ - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . M_UV_BF_Scanlines - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * <-Compressed tile UV_BF Stride-> - * U* V* U* V* U* V* U* V* . . . . ^ - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . UV_BF_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * - * Half_height = (Height+1)>>1 - * Y_TF_Stride = align(Width, 128) - * UV_TF_Stride = align(Width, 128) - * Y_TF_Scanlines = align(Half_height, 32) - * UV_TF_Scanlines = align((Half_height+1)/2, 32) - * Y_UBWC_TF_Plane_size = align(Y_TF_Stride * Y_TF_Scanlines, 4096) - * UV_UBWC_TF_Plane_size = align(UV_TF_Stride * UV_TF_Scanlines, 4096) - * Y_TF_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) - * Y_TF_Meta_Scanlines = align(roundup(Half_height, Y_TileHeight), 16) - * Y_TF_Meta_Plane_size = - * align(Y_TF_Meta_Stride * Y_TF_Meta_Scanlines, 4096) - * UV_TF_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) - * UV_TF_Meta_Scanlines = align(roundup(Half_height, UV_TileHeight), 16) - * UV_TF_Meta_Plane_size = - * align(UV_TF_Meta_Stride * UV_TF_Meta_Scanlines, 4096) - * Y_BF_Stride = align(Width, 128) - * UV_BF_Stride = align(Width, 128) - * Y_BF_Scanlines = align(Half_height, 32) - * UV_BF_Scanlines = align((Half_height+1)/2, 32) - * Y_UBWC_BF_Plane_size = align(Y_BF_Stride * Y_BF_Scanlines, 4096) - * UV_UBWC_BF_Plane_size = align(UV_BF_Stride * UV_BF_Scanlines, 4096) - * Y_BF_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) - * Y_BF_Meta_Scanlines = align(roundup(Half_height, Y_TileHeight), 16) - * Y_BF_Meta_Plane_size = - * align(Y_BF_Meta_Stride * Y_BF_Meta_Scanlines, 4096) - * UV_BF_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) - * UV_BF_Meta_Scanlines = align(roundup(Half_height, UV_TileHeight), 16) - * UV_BF_Meta_Plane_size = - * align(UV_BF_Meta_Stride * UV_BF_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align( Y_UBWC_TF_Plane_size + UV_UBWC_TF_Plane_size + - * Y_TF_Meta_Plane_size + UV_TF_Meta_Plane_size + - * Y_UBWC_BF_Plane_size + UV_UBWC_BF_Plane_size + - * Y_BF_Meta_Plane_size + UV_BF_Meta_Plane_size + - * + max(Extradata, Y_TF_Stride * 48), 4096) - */ - COLOR_FMT_NV12_UBWC, - /* Venus NV12 10-bit UBWC: - * Compressed Macro-tile format for NV12. - * Contains 4 planes in the following order - - * (A) Y_Meta_Plane - * (B) Y_UBWC_Plane - * (C) UV_Meta_Plane - * (D) UV_UBWC_Plane - * - * Y_Meta_Plane consists of meta information to decode compressed - * tile data in Y_UBWC_Plane. - * Y_UBWC_Plane consists of Y data in compressed macro-tile format. - * UBWC decoder block will use the Y_Meta_Plane data together with - * Y_UBWC_Plane data to produce loss-less uncompressed 10 bit Y samples. - * - * UV_Meta_Plane consists of meta information to decode compressed - * tile data in UV_UBWC_Plane. - * UV_UBWC_Plane consists of UV data in compressed macro-tile format. - * UBWC decoder block will use UV_Meta_Plane data together with - * UV_UBWC_Plane data to produce loss-less uncompressed 10 bit 2x2 - * subsampled color difference samples. - * - * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable - * and randomly accessible. There is no dependency between tiles. - * - * <----- Y_Meta_Stride -----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Height | - * M M M M M M M M M M M M . . | Meta_Y_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <--Compressed tile Y Stride---> - * <------- Width -------> - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * <----- UV_Meta_Stride ----> - * M M M M M M M M M M M M . . ^ - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . M_UV_Scanlines - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * <--Compressed tile UV Stride---> - * U* V* U* V* U* V* U* V* . . . . ^ - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . UV_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * - * - * Y_Stride = align(Width * 4/3, 128) - * UV_Stride = align(Width * 4/3, 128) - * Y_Scanlines = align(Height, 32) - * UV_Scanlines = align(Height/2, 16) - * Y_UBWC_Plane_Size = align(Y_Stride * Y_Scanlines, 4096) - * UV_UBWC_Plane_Size = align(UV_Stride * UV_Scanlines, 4096) - * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) - * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16) - * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096) - * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) - * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16) - * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align(Y_UBWC_Plane_size + UV_UBWC_Plane_size + - * Y_Meta_Plane_size + UV_Meta_Plane_size - * + max(Extradata, Y_Stride * 48), 4096) - */ - COLOR_FMT_NV12_BPP10_UBWC, - /* Venus RGBA8888 format: - * Contains 1 plane in the following order - - * (A) RGBA plane - * - * <-------- RGB_Stride --------> - * <------- Width -------> - * R R R R R R R R R R R R . . . . ^ ^ - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . Height | - * R R R R R R R R R R R R . . . . | RGB_Scanlines - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * - * RGB_Stride = align(Width * 4, 128) - * RGB_Scanlines = align(Height, 32) - * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align(RGB_Plane_size + Extradata, 4096) - */ - COLOR_FMT_RGBA8888, - /* Venus RGBA8888 UBWC format: - * Contains 2 planes in the following order - - * (A) Meta plane - * (B) RGBA plane - * - * <--- RGB_Meta_Stride ----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Height | - * M M M M M M M M M M M M . . | Meta_RGB_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <-------- RGB_Stride --------> - * <------- Width -------> - * R R R R R R R R R R R R . . . . ^ ^ - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . Height | - * R R R R R R R R R R R R . . . . | RGB_Scanlines - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * - * RGB_Stride = align(Width * 4, 128) - * RGB_Scanlines = align(Height, 32) - * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096) - * RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64) - * RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16) - * RGB_Meta_Plane_size = align(RGB_Meta_Stride * - * RGB_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align(RGB_Meta_Plane_size + RGB_Plane_size + - * Extradata, 4096) - */ - COLOR_FMT_RGBA8888_UBWC, - /* Venus RGBA1010102 UBWC format: - * Contains 2 planes in the following order - - * (A) Meta plane - * (B) RGBA plane - * - * <--- RGB_Meta_Stride ----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Height | - * M M M M M M M M M M M M . . | Meta_RGB_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <-------- RGB_Stride --------> - * <------- Width -------> - * R R R R R R R R R R R R . . . . ^ ^ - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . Height | - * R R R R R R R R R R R R . . . . | RGB_Scanlines - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * - * RGB_Stride = align(Width * 4, 256) - * RGB_Scanlines = align(Height, 16) - * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096) - * RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64) - * RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16) - * RGB_Meta_Plane_size = align(RGB_Meta_Stride * - * RGB_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align(RGB_Meta_Plane_size + RGB_Plane_size + - * Extradata, 4096) - */ - COLOR_FMT_RGBA1010102_UBWC, - /* Venus RGB565 UBWC format: - * Contains 2 planes in the following order - - * (A) Meta plane - * (B) RGB plane - * - * <--- RGB_Meta_Stride ----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Height | - * M M M M M M M M M M M M . . | Meta_RGB_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <-------- RGB_Stride --------> - * <------- Width -------> - * R R R R R R R R R R R R . . . . ^ ^ - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . Height | - * R R R R R R R R R R R R . . . . | RGB_Scanlines - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * - * RGB_Stride = align(Width * 2, 128) - * RGB_Scanlines = align(Height, 16) - * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096) - * RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64) - * RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16) - * RGB_Meta_Plane_size = align(RGB_Meta_Stride * - * RGB_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align(RGB_Meta_Plane_size + RGB_Plane_size + - * Extradata, 4096) - */ - COLOR_FMT_RGB565_UBWC, - /* P010 UBWC: - * Compressed Macro-tile format for NV12. - * Contains 4 planes in the following order - - * (A) Y_Meta_Plane - * (B) Y_UBWC_Plane - * (C) UV_Meta_Plane - * (D) UV_UBWC_Plane - * - * Y_Meta_Plane consists of meta information to decode compressed - * tile data in Y_UBWC_Plane. - * Y_UBWC_Plane consists of Y data in compressed macro-tile format. - * UBWC decoder block will use the Y_Meta_Plane data together with - * Y_UBWC_Plane data to produce loss-less uncompressed 10 bit Y samples. - * - * UV_Meta_Plane consists of meta information to decode compressed - * tile data in UV_UBWC_Plane. - * UV_UBWC_Plane consists of UV data in compressed macro-tile format. - * UBWC decoder block will use UV_Meta_Plane data together with - * UV_UBWC_Plane data to produce loss-less uncompressed 10 bit 2x2 - * subsampled color difference samples. - * - * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable - * and randomly accessible. There is no dependency between tiles. - * - * <----- Y_Meta_Stride -----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Height | - * M M M M M M M M M M M M . . | Meta_Y_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <--Compressed tile Y Stride---> - * <------- Width -------> - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * <----- UV_Meta_Stride ----> - * M M M M M M M M M M M M . . ^ - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . M_UV_Scanlines - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * <--Compressed tile UV Stride---> - * U* V* U* V* U* V* U* V* . . . . ^ - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . UV_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * - * - * Y_Stride = align(Width * 2, 256) - * UV_Stride = align(Width * 2, 256) - * Y_Scanlines = align(Height, 16) - * UV_Scanlines = align(Height/2, 16) - * Y_UBWC_Plane_Size = align(Y_Stride * Y_Scanlines, 4096) - * UV_UBWC_Plane_Size = align(UV_Stride * UV_Scanlines, 4096) - * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) - * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16) - * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096) - * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) - * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16) - * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align(Y_UBWC_Plane_size + UV_UBWC_Plane_size + - * Y_Meta_Plane_size + UV_Meta_Plane_size - * + max(Extradata, Y_Stride * 48), 4096) - */ - COLOR_FMT_P010_UBWC, - /* Venus P010: - * YUV 4:2:0 image with a plane of 10 bit Y samples followed - * by an interleaved U/V plane containing 10 bit 2x2 subsampled - * colour difference samples. - * - * <-------- Y/UV_Stride --------> - * <------- Width -------> - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * U V U V U V U V U V U V . . . . ^ - * U V U V U V U V U V U V . . . . | - * U V U V U V U V U V U V . . . . | - * U V U V U V U V U V U V . . . . UV_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . --> Buffer size alignment - * - * Y_Stride : Width * 2 aligned to 128 - * UV_Stride : Width * 2 aligned to 128 - * Y_Scanlines: Height aligned to 32 - * UV_Scanlines: Height/2 aligned to 16 - * Extradata: Arbitrary (software-imposed) padding - * Total size = align((Y_Stride * Y_Scanlines - * + UV_Stride * UV_Scanlines - * + max(Extradata, Y_Stride * 8), 4096) - */ - COLOR_FMT_P010, -}; - -#define COLOR_FMT_RGBA1010102_UBWC COLOR_FMT_RGBA1010102_UBWC -#define COLOR_FMT_RGB565_UBWC COLOR_FMT_RGB565_UBWC -#define COLOR_FMT_P010_UBWC COLOR_FMT_P010_UBWC -#define COLOR_FMT_P010 COLOR_FMT_P010 - -static __inline__ unsigned int VENUS_EXTRADATA_SIZE(int width, int height) -{ - (void)height; - (void)width; - - /* - * In the future, calculate the size based on the w/h but just - * hardcode it for now since 16K satisfies all current usecases. - */ - return 16 * 1024; -} - -/* - * Function arguments: - * @color_fmt - * @width - * Progressive: width - * Interlaced: width - */ -static __inline__ unsigned int VENUS_Y_STRIDE(int color_fmt, int width) -{ - unsigned int alignment, stride = 0; - - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - case COLOR_FMT_NV12_MVTB: - case COLOR_FMT_NV12_UBWC: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width, alignment); - break; - case COLOR_FMT_NV12_BPP10_UBWC: - alignment = 256; - stride = MSM_MEDIA_ALIGN(width, 192); - stride = MSM_MEDIA_ALIGN(stride * 4/3, alignment); - break; - case COLOR_FMT_P010_UBWC: - alignment = 256; - stride = MSM_MEDIA_ALIGN(width * 2, alignment); - break; - case COLOR_FMT_P010: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width*2, alignment); - break; - default: - break; - } -invalid_input: - return stride; -} - -/* - * Function arguments: - * @color_fmt - * @width - * Progressive: width - * Interlaced: width - */ -static __inline__ unsigned int VENUS_UV_STRIDE(int color_fmt, int width) -{ - unsigned int alignment, stride = 0; - - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - case COLOR_FMT_NV12_MVTB: - case COLOR_FMT_NV12_UBWC: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width, alignment); - break; - case COLOR_FMT_NV12_BPP10_UBWC: - alignment = 256; - stride = MSM_MEDIA_ALIGN(width, 192); - stride = MSM_MEDIA_ALIGN(stride * 4/3, alignment); - break; - case COLOR_FMT_P010_UBWC: - alignment = 256; - stride = MSM_MEDIA_ALIGN(width * 2, alignment); - break; - case COLOR_FMT_P010: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width*2, alignment); - break; - default: - break; - } -invalid_input: - return stride; -} - -/* - * Function arguments: - * @color_fmt - * @height - * Progressive: height - * Interlaced: (height+1)>>1 - */ -static __inline__ unsigned int VENUS_Y_SCANLINES(int color_fmt, int height) -{ - unsigned int alignment, sclines = 0; - - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - case COLOR_FMT_NV12_MVTB: - case COLOR_FMT_NV12_UBWC: - case COLOR_FMT_P010: - alignment = 32; - break; - case COLOR_FMT_NV12_BPP10_UBWC: - case COLOR_FMT_P010_UBWC: - alignment = 16; - break; - default: - return 0; - } - sclines = MSM_MEDIA_ALIGN(height, alignment); -invalid_input: - return sclines; -} - -/* - * Function arguments: - * @color_fmt - * @height - * Progressive: height - * Interlaced: (height+1)>>1 - */ -static __inline__ unsigned int VENUS_UV_SCANLINES(int color_fmt, int height) -{ - unsigned int alignment, sclines = 0; - - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - case COLOR_FMT_NV12_MVTB: - case COLOR_FMT_NV12_BPP10_UBWC: - case COLOR_FMT_P010_UBWC: - case COLOR_FMT_P010: - alignment = 16; - break; - case COLOR_FMT_NV12_UBWC: - alignment = 32; - break; - default: - goto invalid_input; - } - - sclines = MSM_MEDIA_ALIGN((height+1)>>1, alignment); - -invalid_input: - return sclines; -} - -/* - * Function arguments: - * @color_fmt - * @width - * Progressive: width - * Interlaced: width - */ -static __inline__ unsigned int VENUS_Y_META_STRIDE(int color_fmt, int width) -{ - int y_tile_width = 0, y_meta_stride = 0; - - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV12_UBWC: - case COLOR_FMT_P010_UBWC: - y_tile_width = 32; - break; - case COLOR_FMT_NV12_BPP10_UBWC: - y_tile_width = 48; - break; - default: - goto invalid_input; - } - - y_meta_stride = MSM_MEDIA_ROUNDUP(width, y_tile_width); - y_meta_stride = MSM_MEDIA_ALIGN(y_meta_stride, 64); - -invalid_input: - return y_meta_stride; -} - -/* - * Function arguments: - * @color_fmt - * @height - * Progressive: height - * Interlaced: (height+1)>>1 - */ -static __inline__ unsigned int VENUS_Y_META_SCANLINES(int color_fmt, int height) -{ - int y_tile_height = 0, y_meta_scanlines = 0; - - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV12_UBWC: - y_tile_height = 8; - break; - case COLOR_FMT_NV12_BPP10_UBWC: - case COLOR_FMT_P010_UBWC: - y_tile_height = 4; - break; - default: - goto invalid_input; - } - - y_meta_scanlines = MSM_MEDIA_ROUNDUP(height, y_tile_height); - y_meta_scanlines = MSM_MEDIA_ALIGN(y_meta_scanlines, 16); - -invalid_input: - return y_meta_scanlines; -} - -/* - * Function arguments: - * @color_fmt - * @width - * Progressive: width - * Interlaced: width - */ -static __inline__ unsigned int VENUS_UV_META_STRIDE(int color_fmt, int width) -{ - int uv_tile_width = 0, uv_meta_stride = 0; - - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV12_UBWC: - case COLOR_FMT_P010_UBWC: - uv_tile_width = 16; - break; - case COLOR_FMT_NV12_BPP10_UBWC: - uv_tile_width = 24; - break; - default: - goto invalid_input; - } - - uv_meta_stride = MSM_MEDIA_ROUNDUP((width+1)>>1, uv_tile_width); - uv_meta_stride = MSM_MEDIA_ALIGN(uv_meta_stride, 64); - -invalid_input: - return uv_meta_stride; -} - -/* - * Function arguments: - * @color_fmt - * @height - * Progressive: height - * Interlaced: (height+1)>>1 - */ -static __inline__ unsigned int VENUS_UV_META_SCANLINES(int color_fmt, int height) -{ - int uv_tile_height = 0, uv_meta_scanlines = 0; - - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV12_UBWC: - uv_tile_height = 8; - break; - case COLOR_FMT_NV12_BPP10_UBWC: - case COLOR_FMT_P010_UBWC: - uv_tile_height = 4; - break; - default: - goto invalid_input; - } - - uv_meta_scanlines = MSM_MEDIA_ROUNDUP((height+1)>>1, uv_tile_height); - uv_meta_scanlines = MSM_MEDIA_ALIGN(uv_meta_scanlines, 16); - -invalid_input: - return uv_meta_scanlines; -} - -static __inline__ unsigned int VENUS_RGB_STRIDE(int color_fmt, int width) -{ - unsigned int alignment = 0, stride = 0, bpp = 4; - - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_RGBA8888: - alignment = 128; - break; - case COLOR_FMT_RGB565_UBWC: - alignment = 256; - bpp = 2; - break; - case COLOR_FMT_RGBA8888_UBWC: - case COLOR_FMT_RGBA1010102_UBWC: - alignment = 256; - break; - default: - goto invalid_input; - } - - stride = MSM_MEDIA_ALIGN(width * bpp, alignment); - -invalid_input: - return stride; -} - -static __inline__ unsigned int VENUS_RGB_SCANLINES(int color_fmt, int height) -{ - unsigned int alignment = 0, scanlines = 0; - - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_RGBA8888: - alignment = 32; - break; - case COLOR_FMT_RGBA8888_UBWC: - case COLOR_FMT_RGBA1010102_UBWC: - case COLOR_FMT_RGB565_UBWC: - alignment = 16; - break; - default: - goto invalid_input; - } - - scanlines = MSM_MEDIA_ALIGN(height, alignment); - -invalid_input: - return scanlines; -} - -static __inline__ unsigned int VENUS_RGB_META_STRIDE(int color_fmt, int width) -{ - int rgb_tile_width = 0, rgb_meta_stride = 0; - - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_RGBA8888_UBWC: - case COLOR_FMT_RGBA1010102_UBWC: - case COLOR_FMT_RGB565_UBWC: - rgb_tile_width = 16; - break; - default: - goto invalid_input; - } - - rgb_meta_stride = MSM_MEDIA_ROUNDUP(width, rgb_tile_width); - rgb_meta_stride = MSM_MEDIA_ALIGN(rgb_meta_stride, 64); - -invalid_input: - return rgb_meta_stride; -} - -static __inline__ unsigned int VENUS_RGB_META_SCANLINES(int color_fmt, int height) -{ - int rgb_tile_height = 0, rgb_meta_scanlines = 0; - - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_RGBA8888_UBWC: - case COLOR_FMT_RGBA1010102_UBWC: - case COLOR_FMT_RGB565_UBWC: - rgb_tile_height = 4; - break; - default: - goto invalid_input; - } - - rgb_meta_scanlines = MSM_MEDIA_ROUNDUP(height, rgb_tile_height); - rgb_meta_scanlines = MSM_MEDIA_ALIGN(rgb_meta_scanlines, 16); - -invalid_input: - return rgb_meta_scanlines; -} - -/* - * Function arguments: - * @color_fmt - * @width - * Progressive: width - * Interlaced: width - * @height - * Progressive: height - * Interlaced: height - */ -static __inline__ unsigned int VENUS_BUFFER_SIZE( - int color_fmt, int width, int height) -{ - const unsigned int extra_size = VENUS_EXTRADATA_SIZE(width, height); - unsigned int uv_alignment = 0, size = 0; - unsigned int w_alignment = 512; - unsigned int y_plane, uv_plane, y_stride, - uv_stride, y_sclines, uv_sclines; - unsigned int y_ubwc_plane = 0, uv_ubwc_plane = 0; - unsigned int y_meta_stride = 0, y_meta_scanlines = 0; - unsigned int uv_meta_stride = 0, uv_meta_scanlines = 0; - unsigned int y_meta_plane = 0, uv_meta_plane = 0; - unsigned int rgb_stride = 0, rgb_scanlines = 0; - unsigned int rgb_plane = 0, rgb_ubwc_plane = 0, rgb_meta_plane = 0; - unsigned int rgb_meta_stride = 0, rgb_meta_scanlines = 0; - - if (!width || !height) - goto invalid_input; - - y_stride = VENUS_Y_STRIDE(color_fmt, width); - uv_stride = VENUS_UV_STRIDE(color_fmt, width); - y_sclines = VENUS_Y_SCANLINES(color_fmt, height); - uv_sclines = VENUS_UV_SCANLINES(color_fmt, height); - rgb_stride = VENUS_RGB_STRIDE(color_fmt, width); - rgb_scanlines = VENUS_RGB_SCANLINES(color_fmt, height); - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - uv_alignment = 4096; - y_plane = y_stride * y_sclines; - uv_plane = uv_stride * uv_sclines + uv_alignment; - size = y_plane + uv_plane + - MSM_MEDIA_MAX(extra_size, 8 * y_stride); - size = MSM_MEDIA_ALIGN(size, 4096); - - /* Additional size to cover last row of non-aligned frame */ - if (width >= 2400 && height >= 2400) { - size += MSM_MEDIA_ALIGN(width, w_alignment) * - w_alignment; - size = MSM_MEDIA_ALIGN(size, 4096); - } - break; - case COLOR_FMT_P010: - uv_alignment = 4096; - y_plane = y_stride * y_sclines; - uv_plane = uv_stride * uv_sclines + uv_alignment; - size = y_plane + uv_plane + - MSM_MEDIA_MAX(extra_size, 8 * y_stride); - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_NV12_MVTB: - uv_alignment = 4096; - y_plane = y_stride * y_sclines; - uv_plane = uv_stride * uv_sclines + uv_alignment; - size = y_plane + uv_plane; - size = 2 * size + extra_size; - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_NV12_UBWC: - y_sclines = VENUS_Y_SCANLINES(color_fmt, (height+1)>>1); - y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); - uv_sclines = VENUS_UV_SCANLINES(color_fmt, (height+1)>>1); - uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); - y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); - y_meta_scanlines = - VENUS_Y_META_SCANLINES(color_fmt, (height+1)>>1); - y_meta_plane = MSM_MEDIA_ALIGN( - y_meta_stride * y_meta_scanlines, 4096); - uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); - uv_meta_scanlines = - VENUS_UV_META_SCANLINES(color_fmt, (height+1)>>1); - uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * - uv_meta_scanlines, 4096); - - size = (y_ubwc_plane + uv_ubwc_plane + y_meta_plane + - uv_meta_plane)*2 + - MSM_MEDIA_MAX(extra_size + 8192, 48 * y_stride); - size = MSM_MEDIA_ALIGN(size, 4096); - - /* Additional size to cover last row of non-aligned frame */ - if (width >= 2400 && height >= 2400) { - size += MSM_MEDIA_ALIGN(width, w_alignment) * - w_alignment; - size = MSM_MEDIA_ALIGN(size, 4096); - } - break; - case COLOR_FMT_NV12_BPP10_UBWC: - y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); - uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); - y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); - y_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt, height); - y_meta_plane = MSM_MEDIA_ALIGN( - y_meta_stride * y_meta_scanlines, 4096); - uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); - uv_meta_scanlines = VENUS_UV_META_SCANLINES(color_fmt, height); - uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * - uv_meta_scanlines, 4096); - - size = y_ubwc_plane + uv_ubwc_plane + y_meta_plane + - uv_meta_plane + - MSM_MEDIA_MAX(extra_size + 8192, 48 * y_stride); - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_P010_UBWC: - y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); - uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); - y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); - y_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt, height); - y_meta_plane = MSM_MEDIA_ALIGN( - y_meta_stride * y_meta_scanlines, 4096); - uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); - uv_meta_scanlines = VENUS_UV_META_SCANLINES(color_fmt, height); - uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * - uv_meta_scanlines, 4096); - - size = y_ubwc_plane + uv_ubwc_plane + y_meta_plane + - uv_meta_plane; - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_RGBA8888: - rgb_plane = MSM_MEDIA_ALIGN(rgb_stride * rgb_scanlines, 4096); - size = rgb_plane; - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_RGBA8888_UBWC: - case COLOR_FMT_RGBA1010102_UBWC: - case COLOR_FMT_RGB565_UBWC: - rgb_ubwc_plane = MSM_MEDIA_ALIGN(rgb_stride * rgb_scanlines, - 4096); - rgb_meta_stride = VENUS_RGB_META_STRIDE(color_fmt, width); - rgb_meta_scanlines = VENUS_RGB_META_SCANLINES(color_fmt, - height); - rgb_meta_plane = MSM_MEDIA_ALIGN(rgb_meta_stride * - rgb_meta_scanlines, 4096); - size = rgb_ubwc_plane + rgb_meta_plane; - size = MSM_MEDIA_ALIGN(size, 4096); - break; - default: - break; - } -invalid_input: - return size; -} - -static __inline__ unsigned int VENUS_VIEW2_OFFSET( - int color_fmt, int width, int height) -{ - unsigned int offset = 0; - unsigned int y_plane, uv_plane, y_stride, - uv_stride, y_sclines, uv_sclines; - if (!width || !height) - goto invalid_input; - - y_stride = VENUS_Y_STRIDE(color_fmt, width); - uv_stride = VENUS_UV_STRIDE(color_fmt, width); - y_sclines = VENUS_Y_SCANLINES(color_fmt, height); - uv_sclines = VENUS_UV_SCANLINES(color_fmt, height); - switch (color_fmt) { - case COLOR_FMT_NV12_MVTB: - y_plane = y_stride * y_sclines; - uv_plane = uv_stride * uv_sclines; - offset = y_plane + uv_plane; - break; - default: - break; - } -invalid_input: - return offset; -} - -#endif diff --git a/sdm710/kernel-headers/media/msm_mercury.h b/sdm710/kernel-headers/media/msm_mercury.h deleted file mode 100644 index cae9b2d2..00000000 --- a/sdm710/kernel-headers/media/msm_mercury.h +++ /dev/null @@ -1,90 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_MSM_MERCURY_H -#define __UAPI_MSM_MERCURY_H -#include <linux/types.h> -#include <linux/ioctl.h> -#define MSM_MERCURY_HW_VERSION_REG 0x0004 -#define OUTPUT_H2V1 0 -#define OUTPUT_H2V2 1 -#define OUTPUT_BYTE 6 -#define MSM_MERCURY_MODE_REALTIME_ENCODE 0 -#define MSM_MERCURY_MODE_OFFLINE_ENCODE 1 -#define MSM_MERCURY_MODE_REALTIME_ROTATION 2 -#define MSM_MERCURY_MODE_OFFLINE_ROTATION 3 -#define MSM_MERCURY_EVT_RESET 1 -#define MSM_MERCURY_EVT_FRAMEDONE 2 -#define MSM_MERCURY_EVT_ERR 3 -#define MSM_MERCURY_EVT_UNBLOCK 4 -#define MSM_MERCURY_HW_CMD_TYPE_READ 0 -#define MSM_MERCURY_HW_CMD_TYPE_WRITE 1 -#define MSM_MERCURY_HW_CMD_TYPE_WRITE_OR 2 -#define MSM_MERCURY_HW_CMD_TYPE_UWAIT 3 -#define MSM_MERCURY_HW_CMD_TYPE_MWAIT 4 -#define MSM_MERCURY_HW_CMD_TYPE_MDELAY 5 -#define MSM_MERCURY_HW_CMD_TYPE_UDELAY 6 -#define MSM_MCR_IOCTL_MAGIC 'g' -#define MSM_MCR_IOCTL_GET_HW_VERSION _IOW(MSM_MCR_IOCTL_MAGIC, 1, struct msm_mercury_hw_cmd *) -#define MSM_MCR_IOCTL_RESET _IOW(MSM_MCR_IOCTL_MAGIC, 2, struct msm_mercury_ctrl_cmd *) -#define MSM_MCR_IOCTL_STOP _IOW(MSM_MCR_IOCTL_MAGIC, 3, struct msm_mercury_hw_cmds *) -#define MSM_MCR_IOCTL_START _IOW(MSM_MCR_IOCTL_MAGIC, 4, struct msm_mercury_hw_cmds *) -#define MSM_MCR_IOCTL_INPUT_BUF_CFG _IOW(MSM_MCR_IOCTL_MAGIC, 5, struct msm_mercury_buf *) -#define MSM_MCR_IOCTL_INPUT_GET _IOW(MSM_MCR_IOCTL_MAGIC, 6, struct msm_mercury_buf *) -#define MSM_MCR_IOCTL_INPUT_GET_UNBLOCK _IOW(MSM_MCR_IOCTL_MAGIC, 7, int) -#define MSM_MCR_IOCTL_OUTPUT_BUF_CFG _IOW(MSM_MCR_IOCTL_MAGIC, 8, struct msm_mercury_buf *) -#define MSM_MCR_IOCTL_OUTPUT_GET _IOW(MSM_MCR_IOCTL_MAGIC, 9, struct msm_mercury_buf *) -#define MSM_MCR_IOCTL_OUTPUT_GET_UNBLOCK _IOW(MSM_MCR_IOCTL_MAGIC, 10, int) -#define MSM_MCR_IOCTL_EVT_GET _IOW(MSM_MCR_IOCTL_MAGIC, 11, struct msm_mercury_ctrl_cmd *) -#define MSM_MCR_IOCTL_EVT_GET_UNBLOCK _IOW(MSM_MCR_IOCTL_MAGIC, 12, int) -#define MSM_MCR_IOCTL_HW_CMD _IOW(MSM_MCR_IOCTL_MAGIC, 13, struct msm_mercury_hw_cmd *) -#define MSM_MCR_IOCTL_HW_CMDS _IOW(MSM_MCR_IOCTL_MAGIC, 14, struct msm_mercury_hw_cmds *) -#define MSM_MCR_IOCTL_TEST_DUMP_REGION _IOW(MSM_MCR_IOCTL_MAGIC, 15, unsigned long) -struct msm_mercury_ctrl_cmd { - uint32_t type; - uint32_t len; - void * value; -}; -struct msm_mercury_buf { - uint32_t type; - int fd; - void * vaddr; - uint32_t y_off; - uint32_t y_len; - uint32_t framedone_len; - uint32_t cbcr_off; - uint32_t cbcr_len; - uint32_t num_of_mcu_rows; - uint32_t offset; -}; -struct msm_mercury_hw_cmd { - uint32_t type : 4; - uint32_t n : 12; - uint32_t offset : 16; - uint32_t mask; - union { - uint32_t data; - uint32_t * pdata; - }; -}; -struct msm_mercury_hw_cmds { - uint32_t m; - struct msm_mercury_hw_cmd hw_cmd[1]; -}; -#endif - diff --git a/sdm710/kernel-headers/media/msm_sde_rotator.h b/sdm710/kernel-headers/media/msm_sde_rotator.h deleted file mode 100644 index b6b813f9..00000000 --- a/sdm710/kernel-headers/media/msm_sde_rotator.h +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_MSM_SDE_ROTATOR_H__ -#define __UAPI_MSM_SDE_ROTATOR_H__ -#include <linux/videodev2.h> -#include <linux/types.h> -#include <linux/ioctl.h> -#define SDE_PIX_FMT_XRGB_8888 V4L2_PIX_FMT_XBGR32 -#define SDE_PIX_FMT_ARGB_8888 V4L2_PIX_FMT_ABGR32 -#define SDE_PIX_FMT_ABGR_8888 V4L2_PIX_FMT_SDE_ABGR_8888 -#define SDE_PIX_FMT_RGBA_8888 V4L2_PIX_FMT_SDE_RGBA_8888 -#define SDE_PIX_FMT_BGRA_8888 V4L2_PIX_FMT_ARGB32 -#define SDE_PIX_FMT_RGBX_8888 V4L2_PIX_FMT_SDE_RGBX_8888 -#define SDE_PIX_FMT_BGRX_8888 V4L2_PIX_FMT_XRGB32 -#define SDE_PIX_FMT_XBGR_8888 V4L2_PIX_FMT_SDE_XBGR_8888 -#define SDE_PIX_FMT_RGBA_5551 V4L2_PIX_FMT_SDE_RGBA_5551 -#define SDE_PIX_FMT_ARGB_1555 V4L2_PIX_FMT_ARGB555 -#define SDE_PIX_FMT_ABGR_1555 V4L2_PIX_FMT_SDE_ABGR_1555 -#define SDE_PIX_FMT_BGRA_5551 V4L2_PIX_FMT_SDE_BGRA_5551 -#define SDE_PIX_FMT_BGRX_5551 V4L2_PIX_FMT_SDE_BGRX_5551 -#define SDE_PIX_FMT_RGBX_5551 V4L2_PIX_FMT_SDE_RGBX_5551 -#define SDE_PIX_FMT_XBGR_1555 V4L2_PIX_FMT_SDE_XBGR_1555 -#define SDE_PIX_FMT_XRGB_1555 V4L2_PIX_FMT_XRGB555 -#define SDE_PIX_FMT_ARGB_4444 V4L2_PIX_FMT_ARGB444 -#define SDE_PIX_FMT_RGBA_4444 V4L2_PIX_FMT_SDE_RGBA_4444 -#define SDE_PIX_FMT_BGRA_4444 V4L2_PIX_FMT_SDE_BGRA_4444 -#define SDE_PIX_FMT_ABGR_4444 V4L2_PIX_FMT_SDE_ABGR_4444 -#define SDE_PIX_FMT_RGBX_4444 V4L2_PIX_FMT_SDE_RGBX_4444 -#define SDE_PIX_FMT_XRGB_4444 V4L2_PIX_FMT_XRGB444 -#define SDE_PIX_FMT_BGRX_4444 V4L2_PIX_FMT_SDE_BGRX_4444 -#define SDE_PIX_FMT_XBGR_4444 V4L2_PIX_FMT_SDE_XBGR_4444 -#define SDE_PIX_FMT_RGB_888 V4L2_PIX_FMT_RGB24 -#define SDE_PIX_FMT_BGR_888 V4L2_PIX_FMT_BGR24 -#define SDE_PIX_FMT_RGB_565 V4L2_PIX_FMT_RGB565 -#define SDE_PIX_FMT_BGR_565 V4L2_PIX_FMT_SDE_BGR_565 -#define SDE_PIX_FMT_Y_CB_CR_H2V2 V4L2_PIX_FMT_YUV420 -#define SDE_PIX_FMT_Y_CR_CB_H2V2 V4L2_PIX_FMT_YVU420 -#define SDE_PIX_FMT_Y_CR_CB_GH2V2 V4L2_PIX_FMT_SDE_Y_CR_CB_GH2V2 -#define SDE_PIX_FMT_Y_CBCR_H2V2 V4L2_PIX_FMT_NV12 -#define SDE_PIX_FMT_Y_CRCB_H2V2 V4L2_PIX_FMT_NV21 -#define SDE_PIX_FMT_Y_CBCR_H1V2 V4L2_PIX_FMT_SDE_Y_CBCR_H1V2 -#define SDE_PIX_FMT_Y_CRCB_H1V2 V4L2_PIX_FMT_SDE_Y_CRCB_H1V2 -#define SDE_PIX_FMT_Y_CBCR_H2V1 V4L2_PIX_FMT_NV16 -#define SDE_PIX_FMT_Y_CRCB_H2V1 V4L2_PIX_FMT_NV61 -#define SDE_PIX_FMT_YCBYCR_H2V1 V4L2_PIX_FMT_YUYV -#define SDE_PIX_FMT_Y_CBCR_H2V2_VENUS V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_VENUS -#define SDE_PIX_FMT_Y_CRCB_H2V2_VENUS V4L2_PIX_FMT_SDE_Y_CRCB_H2V2_VENUS -#define SDE_PIX_FMT_RGBA_8888_UBWC V4L2_PIX_FMT_RGBA8888_UBWC -#define SDE_PIX_FMT_RGBX_8888_UBWC V4L2_PIX_FMT_SDE_RGBX_8888_UBWC -#define SDE_PIX_FMT_RGB_565_UBWC V4L2_PIX_FMT_SDE_RGB_565_UBWC -#define SDE_PIX_FMT_Y_CBCR_H2V2_UBWC V4L2_PIX_FMT_NV12_UBWC -#define SDE_PIX_FMT_RGBA_1010102 V4L2_PIX_FMT_SDE_RGBA_1010102 -#define SDE_PIX_FMT_RGBX_1010102 V4L2_PIX_FMT_SDE_RGBX_1010102 -#define SDE_PIX_FMT_ARGB_2101010 V4L2_PIX_FMT_SDE_ARGB_2101010 -#define SDE_PIX_FMT_XRGB_2101010 V4L2_PIX_FMT_SDE_XRGB_2101010 -#define SDE_PIX_FMT_BGRA_1010102 V4L2_PIX_FMT_SDE_BGRA_1010102 -#define SDE_PIX_FMT_BGRX_1010102 V4L2_PIX_FMT_SDE_BGRX_1010102 -#define SDE_PIX_FMT_ABGR_2101010 V4L2_PIX_FMT_SDE_ABGR_2101010 -#define SDE_PIX_FMT_XBGR_2101010 V4L2_PIX_FMT_SDE_XBGR_2101010 -#define SDE_PIX_FMT_RGBA_1010102_UBWC V4L2_PIX_FMT_SDE_RGBA_1010102_UBWC -#define SDE_PIX_FMT_RGBX_1010102_UBWC V4L2_PIX_FMT_SDE_RGBX_1010102_UBWC -#define SDE_PIX_FMT_Y_CBCR_H2V2_P010 V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010 -#define SDE_PIX_FMT_Y_CBCR_H2V2_P010_VENUS V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010_VENUS -#define SDE_PIX_FMT_Y_CBCR_H2V2_TP10 V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_TP10 -#define SDE_PIX_FMT_Y_CBCR_H2V2_TP10_UBWC V4L2_PIX_FMT_NV12_TP10_UBWC -#define SDE_PIX_FMT_Y_CBCR_H2V2_P010_UBWC V4L2_PIX_FMT_NV12_P010_UBWC -struct msm_sde_rotator_fence { - __u32 index; - __u32 type; - __s32 fd; - __u32 reserved[5]; -}; -struct msm_sde_rotator_comp_ratio { - __u32 index; - __u32 type; - __u32 numer; - __u32 denom; - __u32 reserved[4]; -}; -#define VIDIOC_G_SDE_ROTATOR_FENCE _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_sde_rotator_fence) -#define VIDIOC_S_SDE_ROTATOR_FENCE _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_sde_rotator_fence) -#define VIDIOC_G_SDE_ROTATOR_COMP_RATIO _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_sde_rotator_comp_ratio) -#define VIDIOC_S_SDE_ROTATOR_COMP_RATIO _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_sde_rotator_comp_ratio) -#define V4L2_CID_SDE_ROTATOR_SECURE (V4L2_CID_USER_BASE + 0x1000) -#define V4L2_CID_SDE_ROTATOR_SECURE_CAMERA (V4L2_CID_USER_BASE + 0x2000) -#endif - diff --git a/sdm710/kernel-headers/media/msm_vidc.h b/sdm710/kernel-headers/media/msm_vidc.h deleted file mode 100644 index 85e47ee3..00000000 --- a/sdm710/kernel-headers/media/msm_vidc.h +++ /dev/null @@ -1,384 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __MSM_VIDC_H__ -#define __MSM_VIDC_H__ -#include <linux/types.h> -#define MSM_VIDC_HAL_INTERLACE_COLOR_FORMAT_NV12 0x2 -#define MSM_VIDC_HAL_INTERLACE_COLOR_FORMAT_NV12_UBWC 0x8002 -#define MSM_VIDC_4x_1 0x1 -#define MSM_VIDC_EXTRADATA_FRAME_QP_ADV 0x1 -struct msm_vidc_extradata_header { - unsigned int size; - unsigned int : 32; - unsigned int : 32; - unsigned int type; - unsigned int data_size; - unsigned char data[1]; -}; -struct msm_vidc_interlace_payload { - unsigned int format; - unsigned int color_format; -}; -struct msm_vidc_framerate_payload { - unsigned int frame_rate; -}; -struct msm_vidc_ts_payload { - unsigned int timestamp_lo; - unsigned int timestamp_hi; -}; -struct msm_vidc_concealmb_payload { - unsigned int num_mbs; -}; -struct msm_vidc_recoverysei_payload { - unsigned int flags; -}; -struct msm_vidc_aspect_ratio_payload { - unsigned int size; - unsigned int version; - unsigned int port_index; - unsigned int aspect_width; - unsigned int aspect_height; -}; -struct msm_vidc_mpeg2_seqdisp_payload { - unsigned int video_format; - unsigned int color_descp; - unsigned int color_primaries; - unsigned int transfer_char; - unsigned int matrix_coeffs; - unsigned int disp_width; - unsigned int disp_height; -}; -struct msm_vidc_vc1_seqdisp_payload { - unsigned int prog_seg_format; - unsigned int uv_sampl_fmt; - unsigned int color_format; - unsigned int color_primaries; - unsigned int transfer_char; - unsigned int matrix_coeffs; - unsigned int aspect_ratio; - unsigned int aspect_horiz; - unsigned int aspect_vert; -}; -struct msm_vidc_input_crop_payload { - unsigned int size; - unsigned int version; - unsigned int port_index; - unsigned int left; - unsigned int top; - unsigned int width; - unsigned int height; -}; -struct msm_vidc_misr_info { - unsigned int misr_dpb_luma; - unsigned int misr_dpb_chroma; - unsigned int misr_opb_luma; - unsigned int misr_opb_chroma; -}; -struct msm_vidc_output_crop_payload { - unsigned int size; - unsigned int version; - unsigned int port_index; - unsigned int left; - unsigned int top; - unsigned int display_width; - unsigned int display_height; - unsigned int width; - unsigned int height; - unsigned int frame_num; - unsigned int bit_depth_y; - unsigned int bit_depth_c; - struct msm_vidc_misr_info misr_info[2]; -}; -struct msm_vidc_digital_zoom_payload { - unsigned int size; - unsigned int version; - unsigned int port_index; - unsigned int zoom_width; - unsigned int zoom_height; -}; -struct msm_vidc_extradata_index { - unsigned int type; - union { - struct msm_vidc_input_crop_payload input_crop; - struct msm_vidc_digital_zoom_payload digital_zoom; - struct msm_vidc_aspect_ratio_payload aspect_ratio; - }; -}; -struct msm_vidc_panscan_window { - unsigned int panscan_height_offset; - unsigned int panscan_width_offset; - unsigned int panscan_window_width; - unsigned int panscan_window_height; -}; -struct msm_vidc_panscan_window_payload { - unsigned int num_panscan_windows; - struct msm_vidc_panscan_window wnd[1]; -}; -struct msm_vidc_stream_userdata_payload { - unsigned int type; - unsigned int data[1]; -}; -struct msm_vidc_frame_qp_payload { - unsigned int frame_qp; - unsigned int qp_sum; - unsigned int skip_qp_sum; - unsigned int skip_num_blocks; - unsigned int total_num_blocks; -}; -struct msm_vidc_frame_bits_info_payload { - unsigned int frame_bits; - unsigned int header_bits; -}; -struct msm_vidc_s3d_frame_packing_payload { - unsigned int fpa_id; - unsigned int cancel_flag; - unsigned int fpa_type; - unsigned int quin_cunx_flag; - unsigned int content_interprtation_type; - unsigned int spatial_flipping_flag; - unsigned int frame0_flipped_flag; - unsigned int field_views_flag; - unsigned int current_frame_is_frame0_flag; - unsigned int frame0_self_contained_flag; - unsigned int frame1_self_contained_flag; - unsigned int frame0_graid_pos_x; - unsigned int frame0_graid_pos_y; - unsigned int frame1_graid_pos_x; - unsigned int frame1_graid_pos_y; - unsigned int fpa_reserved_byte; - unsigned int fpa_repetition_period; - unsigned int fpa_extension_flag; -}; -struct msm_vidc_vqzip_sei_payload { - unsigned int size; - unsigned int data[1]; -}; -struct msm_vidc_ubwc_cr_stats_info { - unsigned int stats_tile_32; - unsigned int stats_tile_64; - unsigned int stats_tile_96; - unsigned int stats_tile_128; - unsigned int stats_tile_160; - unsigned int stats_tile_192; - unsigned int stats_tile_256; -}; -struct msm_vidc_yuv_stats_payload { - unsigned int frame_qp; - unsigned int texture; - unsigned int luma_in_q16; - unsigned int frame_difference; -}; -struct msm_vidc_vpx_colorspace_payload { - unsigned int color_space; - unsigned int yuv_range_flag; - unsigned int sumsampling_x; - unsigned int sumsampling_y; -}; -struct msm_vidc_roi_qp_payload { - int upper_qp_offset; - int lower_qp_offset; - unsigned int b_roi_info; - int mbi_info_size; - unsigned int data[1]; -}; -struct msm_vidc_mastering_display_colour_sei_payload { - unsigned int nDisplayPrimariesX[3]; - unsigned int nDisplayPrimariesY[3]; - unsigned int nWhitePointX; - unsigned int nWhitePointY; - unsigned int nMaxDisplayMasteringLuminance; - unsigned int nMinDisplayMasteringLuminance; -}; -struct msm_vidc_content_light_level_sei_payload { - unsigned int nMaxContentLight; - unsigned int nMaxPicAverageLight; -}; -struct msm_vidc_vui_display_info_payload { - unsigned int video_signal_present_flag; - unsigned int video_format; - unsigned int bit_depth_y; - unsigned int bit_depth_c; - unsigned int video_full_range_flag; - unsigned int color_description_present_flag; - unsigned int color_primaries; - unsigned int transfer_characteristics; - unsigned int matrix_coefficients; - unsigned int chroma_location_info_present_flag; - unsigned int chroma_format_idc; - unsigned int separate_color_plane_flag; - unsigned int chroma_sample_loc_type_top_field; - unsigned int chroma_sample_loc_type_bottom_field; -}; -enum msm_vidc_extradata_type { - MSM_VIDC_EXTRADATA_NONE = 0x00000000, - MSM_VIDC_EXTRADATA_MB_QUANTIZATION = 0x00000001, - MSM_VIDC_EXTRADATA_INTERLACE_VIDEO = 0x00000002, - MSM_VIDC_EXTRADATA_VC1_FRAMEDISP = 0x00000003, - MSM_VIDC_EXTRADATA_VC1_SEQDISP = 0x00000004, - MSM_VIDC_EXTRADATA_TIMESTAMP = 0x00000005, - MSM_VIDC_EXTRADATA_S3D_FRAME_PACKING = 0x00000006, - MSM_VIDC_EXTRADATA_FRAME_RATE = 0x00000007, - MSM_VIDC_EXTRADATA_PANSCAN_WINDOW = 0x00000008, - MSM_VIDC_EXTRADATA_RECOVERY_POINT_SEI = 0x00000009, - MSM_VIDC_EXTRADATA_MPEG2_SEQDISP = 0x0000000D, - MSM_VIDC_EXTRADATA_STREAM_USERDATA = 0x0000000E, - MSM_VIDC_EXTRADATA_FRAME_QP = 0x0000000F, - MSM_VIDC_EXTRADATA_FRAME_BITS_INFO = 0x00000010, - MSM_VIDC_EXTRADATA_VQZIP_SEI = 0x00000011, - MSM_VIDC_EXTRADATA_ROI_QP = 0x00000013, -#define MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO - MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO = 0x00000014, -#define MSM_VIDC_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI MSM_VIDC_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI - MSM_VIDC_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI = 0x00000015, -#define MSM_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI MSM_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI - MSM_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI = 0x00000016, -#define MSM_VIDC_EXTRADATA_PQ_INFO MSM_VIDC_EXTRADATA_PQ_INFO - MSM_VIDC_EXTRADATA_PQ_INFO = 0x00000017, -#define MSM_VIDC_EXTRADATA_COLOUR_REMAPPING_INFO_SEI MSM_VIDC_EXTRADATA_COLOUR_REMAPPING_INFO_SEI - MSM_VIDC_EXTRADATA_COLOUR_REMAPPING_INFO_SEI = 0x00000018, -#define MSM_VIDC_EXTRADATA_UBWC_CR_STAT_INFO MSM_VIDC_EXTRADATA_UBWC_CR_STAT_INFO - MSM_VIDC_EXTRADATA_UBWC_CR_STAT_INFO = 0x00000019, - MSM_VIDC_EXTRADATA_INPUT_CROP = 0x0700000E, -#define MSM_VIDC_EXTRADATA_OUTPUT_CROP MSM_VIDC_EXTRADATA_OUTPUT_CROP - MSM_VIDC_EXTRADATA_OUTPUT_CROP = 0x0700000F, - MSM_VIDC_EXTRADATA_DIGITAL_ZOOM = 0x07000010, - MSM_VIDC_EXTRADATA_MULTISLICE_INFO = 0x7F100000, - MSM_VIDC_EXTRADATA_NUM_CONCEALED_MB = 0x7F100001, - MSM_VIDC_EXTRADATA_INDEX = 0x7F100002, - MSM_VIDC_EXTRADATA_ASPECT_RATIO = 0x7F100003, - MSM_VIDC_EXTRADATA_METADATA_LTR = 0x7F100004, - MSM_VIDC_EXTRADATA_METADATA_FILLER = 0x7FE00002, - MSM_VIDC_EXTRADATA_METADATA_MBI = 0x7F100005, -#define MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO - MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO = 0x7F100006, - MSM_VIDC_EXTRADATA_YUVSTATS_INFO = 0x7F100007, -}; -enum msm_vidc_interlace_type { - MSM_VIDC_INTERLACE_FRAME_PROGRESSIVE = 0x01, - MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_TOPFIELDFIRST = 0x02, - MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_BOTTOMFIELDFIRST = 0x04, - MSM_VIDC_INTERLACE_FRAME_TOPFIELDFIRST = 0x08, - MSM_VIDC_INTERLACE_FRAME_BOTTOMFIELDFIRST = 0x10, -#define MSM_VIDC_INTERLACE_FRAME_MBAFF MSM_VIDC_INTERLACE_FRAME_MBAFF - MSM_VIDC_INTERLACE_FRAME_MBAFF = 0x20, -}; -#define MSM_VIDC_FRAMEPACK_CHECKERBOARD 0x00 -#define MSM_VIDC_FRAMEPACK_COLUMN_INTERLEAVE 0x01 -#define MSM_VIDC_FRAMEPACK_ROW_INTERLEAVE 0x02 -#define MSM_VIDC_FRAMEPACK_SIDE_BY_SIDE 0x03 -#define MSM_VIDC_FRAMEPACK_TOP_BOTTOM 0x04 -#define MSM_VIDC_FRAMEPACK_TEMPORAL_INTERLEAVE 0x05 -enum msm_vidc_recovery_sei { - MSM_VIDC_FRAME_RECONSTRUCTION_INCORRECT = 0x0, - MSM_VIDC_FRAME_RECONSTRUCTION_CORRECT = 0x01, - MSM_VIDC_FRAME_RECONSTRUCTION_APPROXIMATELY_CORRECT = 0x02, -}; -enum msm_vidc_userdata_type { - MSM_VIDC_USERDATA_TYPE_FRAME = 0x1, - MSM_VIDC_USERDATA_TYPE_TOP_FIELD = 0x2, - MSM_VIDC_USERDATA_TYPE_BOTTOM_FIELD = 0x3, -}; -enum msm_vidc_h264_color_primaries_values { - MSM_VIDC_RESERVED_1 = 0, - MSM_VIDC_BT709_5 = 1, - MSM_VIDC_UNSPECIFIED = 2, - MSM_VIDC_RESERVED_2 = 3, - MSM_VIDC_BT470_6_M = 4, - MSM_VIDC_BT601_6_625 = 5, - MSM_VIDC_BT470_6_BG = MSM_VIDC_BT601_6_625, - MSM_VIDC_BT601_6_525 = 6, - MSM_VIDC_SMPTE_240M = 7, - MSM_VIDC_GENERIC_FILM = 8, - MSM_VIDC_BT2020 = 9, -}; -enum msm_vidc_vp9_color_primaries_values { - MSM_VIDC_CS_UNKNOWN, - MSM_VIDC_CS_BT_601, - MSM_VIDC_CS_BT_709, - MSM_VIDC_CS_SMPTE_170, - MSM_VIDC_CS_SMPTE_240, - MSM_VIDC_CS_BT_2020, - MSM_VIDC_CS_RESERVED, - MSM_VIDC_CS_RGB, -}; -enum msm_vidc_h264_matrix_coeff_values { - MSM_VIDC_MATRIX_RGB = 0, - MSM_VIDC_MATRIX_BT_709_5 = 1, - MSM_VIDC_MATRIX_UNSPECIFIED = 2, - MSM_VIDC_MATRIX_RESERVED = 3, - MSM_VIDC_MATRIX_FCC_47 = 4, - MSM_VIDC_MATRIX_601_6_625 = 5, - MSM_VIDC_MATRIX_BT470_BG = MSM_VIDC_MATRIX_601_6_625, - MSM_VIDC_MATRIX_601_6_525 = 6, - MSM_VIDC_MATRIX_SMPTE_170M = MSM_VIDC_MATRIX_601_6_525, - MSM_VIDC_MATRIX_SMPTE_240M = 7, - MSM_VIDC_MATRIX_Y_CG_CO = 8, - MSM_VIDC_MATRIX_BT_2020 = 9, - MSM_VIDC_MATRIX_BT_2020_CONST = 10, -}; -enum msm_vidc_h264_transfer_chars_values { - MSM_VIDC_TRANSFER_RESERVED_1 = 0, - MSM_VIDC_TRANSFER_BT709_5 = 1, - MSM_VIDC_TRANSFER_UNSPECIFIED = 2, - MSM_VIDC_TRANSFER_RESERVED_2 = 3, - MSM_VIDC_TRANSFER_BT_470_6_M = 4, - MSM_VIDC_TRANSFER_BT_470_6_BG = 5, - MSM_VIDC_TRANSFER_601_6_625 = 6, - MSM_VIDC_TRANSFER_601_6_525 = MSM_VIDC_TRANSFER_601_6_625, - MSM_VIDC_TRANSFER_SMPTE_240M = 7, - MSM_VIDC_TRANSFER_LINEAR = 8, - MSM_VIDC_TRANSFER_LOG_100_1 = 9, - MSM_VIDC_TRANSFER_LOG_100_SQRT10_1 = 10, - MSM_VIDC_TRANSFER_IEC_61966 = 11, - MSM_VIDC_TRANSFER_BT_1361 = 12, - MSM_VIDC_TRANSFER_SRGB = 13, - MSM_VIDC_TRANSFER_BT_2020_10 = 14, - MSM_VIDC_TRANSFER_BT_2020_12 = 15, -#define MSM_VIDC_TRANSFER_SMPTE_ST2084 MSM_VIDC_TRANSFER_SMPTE_ST2084 - MSM_VIDC_TRANSFER_SMPTE_ST2084 = 16, -#define MSM_VIDC_TRANSFER_SMPTE_ST428_1 MSM_VIDC_TRANSFER_SMPTE_ST428_1 - MSM_VIDC_TRANSFER_SMPTE_ST428_1 = 17, -#define MSM_VIDC_TRANSFER_HLG MSM_VIDC_TRANSFER_HLG - MSM_VIDC_TRANSFER_HLG = 18, -}; -enum msm_vidc_pixel_depth { - MSM_VIDC_BIT_DEPTH_8, - MSM_VIDC_BIT_DEPTH_10, - MSM_VIDC_BIT_DEPTH_UNSUPPORTED = 0XFFFFFFFF, -}; -enum msm_vidc_video_format { - MSM_VIDC_COMPONENT, - MSM_VIDC_PAL, - MSM_VIDC_NTSC, - MSM_VIDC_SECAM, - MSM_VIDC_MAC, - MSM_VIDC_UNSPECIFIED_FORMAT, - MSM_VIDC_RESERVED_1_FORMAT, - MSM_VIDC_RESERVED_2_FORMAT, -}; -enum msm_vidc_color_desc_flag { - MSM_VIDC_COLOR_DESC_NOT_PRESENT, - MSM_VIDC_COLOR_DESC_PRESENT, -}; -#define MSM_VIDC_PIC_STRUCT_MAYBE_INTERLACED 0x0 -#define MSM_VIDC_PIC_STRUCT_PROGRESSIVE 0x1 -#define MSM_VIDC_PIC_STRUCT_UNKNOWN 0XFFFFFFFF -#define MSM_VIDC_ALL_LAYER_ID 0xFF -#endif - diff --git a/sdm710/kernel-headers/media/msm_vpu.h b/sdm710/kernel-headers/media/msm_vpu.h deleted file mode 100644 index 6752383f..00000000 --- a/sdm710/kernel-headers/media/msm_vpu.h +++ /dev/null @@ -1,184 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _H_MSM_VPU_H_ -#define _H_MSM_VPU_H_ -#include <linux/videodev2.h> -#define V4L2_BUF_FLAG_CDS_ENABLE 0x10000000 -#define V4L2_PLANE_MEM_OFFSET 0 -enum vpu_colorspace { - VPU_CS_MIN = 0, - VPU_CS_RGB_FULL = 1, - VPU_CS_RGB_LIMITED = 2, - VPU_CS_REC601_FULL = 3, - VPU_CS_REC601_LIMITED = 4, - VPU_CS_REC709_FULL = 5, - VPU_CS_REC709_LIMITED = 6, - VPU_CS_SMPTE240_FULL = 7, - VPU_CS_SMPTE240_LIMITED = 8, - VPU_CS_MAX = 9, -}; -#define VPU_FMT_EXT_FLAG_BT 1 -#define VPU_FMT_EXT_FLAG_TB 2 -#define VPU_FMT_EXT_FLAG_3D 4 -struct v4l2_format_vpu_extension { - __u8 flag; - __u8 gap_in_lines; -}; -#define V4L2_PIX_FMT_XRGB2 v4l2_fourcc('X', 'R', 'G', '2') -#define V4L2_PIX_FMT_XBGR2 v4l2_fourcc('X', 'B', 'G', '2') -#define V4L2_PIX_FMT_YUYV10 v4l2_fourcc('Y', 'U', 'Y', 'L') -#define V4L2_PIX_FMT_YUV8 v4l2_fourcc('Y', 'U', 'V', '8') -#define V4L2_PIX_FMT_YUV10 v4l2_fourcc('Y', 'U', 'V', 'L') -#define V4L2_PIX_FMT_YUYV10BWC v4l2_fourcc('Y', 'B', 'W', 'C') -#define VPU_INPUT_TYPE_HOST 0 -#define VPU_INPUT_TYPE_VCAP 1 -#define VPU_OUTPUT_TYPE_HOST 0 -#define VPU_OUTPUT_TYPE_DISPLAY 1 -#define VPU_PIPE_VCAP0 (1 << 16) -#define VPU_PIPE_VCAP1 (1 << 17) -#define VPU_PIPE_DISPLAY0 (1 << 18) -#define VPU_PIPE_DISPLAY1 (1 << 19) -#define VPU_PIPE_DISPLAY2 (1 << 20) -#define VPU_PIPE_DISPLAY3 (1 << 21) -#define VPU_PRIVATE_EVENT_BASE (V4L2_EVENT_PRIVATE_START + 6 * 1000) -enum VPU_PRIVATE_EVENT { - VPU_EVENT_START = VPU_PRIVATE_EVENT_BASE, - VPU_EVENT_FLUSH_DONE = VPU_EVENT_START + 1, - VPU_EVENT_ACTIVE_REGION_CHANGED = VPU_EVENT_START + 2, - VPU_EVENT_SESSION_TIMESTAMP = VPU_EVENT_START + 3, - VPU_EVENT_SESSION_CREATED = VPU_EVENT_START + 4, - VPU_EVENT_SESSION_FREED = VPU_EVENT_START + 5, - VPU_EVENT_SESSION_CLIENT_EXITED = VPU_EVENT_START + 6, - VPU_EVENT_HW_ERROR = VPU_EVENT_START + 11, - VPU_EVENT_INVALID_CONFIG = VPU_EVENT_START + 12, - VPU_EVENT_FAILED_SESSION_STREAMING = VPU_EVENT_START + 13, - VPU_EVENT_END -}; -struct vpu_ctrl_standard { - __u32 enable; - __s32 value; -}; -struct vpu_ctrl_auto_manual { - __u32 enable; - __u32 auto_mode; - __s32 value; -}; -struct vpu_ctrl_range_mapping { - __u32 enable; - __u32 y_range; - __u32 uv_range; -}; -#define VPU_ACTIVE_REGION_N_EXCLUSIONS 1 -struct vpu_ctrl_active_region_param { - __u32 enable; - __u32 num_exclusions; - struct v4l2_rect detection_region; - struct v4l2_rect excluded_regions[VPU_ACTIVE_REGION_N_EXCLUSIONS]; -}; -struct vpu_ctrl_deinterlacing_mode { - __u32 field_polarity; - __u32 mvp_mode; -}; -struct vpu_ctrl_hqv { - __u32 enable; - __u32 sharpen_strength; - __u32 auto_nr_strength; -}; -struct vpu_info_frame_timestamp { - __u32 pts_low; - __u32 pts_high; - __u32 qtime_low; - __u32 qtime_high; -}; -struct vpu_control { - __u32 control_id; - union control_data { - __s32 value; - struct vpu_ctrl_standard standard; - struct vpu_ctrl_auto_manual auto_manual; - struct vpu_ctrl_range_mapping range_mapping; - struct vpu_ctrl_active_region_param active_region_param; - struct v4l2_rect active_region_result; - struct vpu_ctrl_deinterlacing_mode deinterlacing_mode; - struct vpu_ctrl_hqv hqv; - struct vpu_info_frame_timestamp timestamp; - __u8 reserved[124]; - } data; -}; -#define VPU_CTRL_ID_MIN 0 -#define VPU_CTRL_NOISE_REDUCTION 1 -#define VPU_CTRL_IMAGE_ENHANCEMENT 2 -#define VPU_CTRL_ANAMORPHIC_SCALING 3 -#define VPU_CTRL_DIRECTIONAL_INTERPOLATION 4 -#define VPU_CTRL_BACKGROUND_COLOR 5 -#define VPU_CTRL_RANGE_MAPPING 6 -#define VPU_CTRL_DEINTERLACING_MODE 7 -#define VPU_CTRL_ACTIVE_REGION_PARAM 8 -#define VPU_CTRL_ACTIVE_REGION_RESULT 9 -#define VPU_CTRL_PRIORITY 10 -#define VPU_CTRL_CONTENT_PROTECTION 11 -#define VPU_CTRL_DISPLAY_REFRESH_RATE 12 -#define VPU_CTRL_HQV 20 -#define VPU_CTRL_HQV_SHARPEN 21 -#define VPU_CTRL_HQV_AUTONR 22 -#define VPU_CTRL_ACE 23 -#define VPU_CTRL_ACE_BRIGHTNESS 24 -#define VPU_CTRL_ACE_CONTRAST 25 -#define VPU_CTRL_2D3D 26 -#define VPU_CTRL_2D3D_DEPTH 27 -#define VPU_CTRL_FRC 28 -#define VPU_CTRL_FRC_MOTION_SMOOTHNESS 29 -#define VPU_CTRL_FRC_MOTION_CLEAR 30 -#define VPU_INFO_TIMESTAMP 35 -#define VPU_CTRL_TIMESTAMP_INFO_MODE 36 -#define VPU_INFO_STATISTICS 37 -#define VPU_CTRL_LATENCY 38 -#define VPU_CTRL_LATENCY_MODE 39 -#define VPU_CTRL_ID_MAX 40 -#define VPU_MAX_EXT_DATA_SIZE 720 -struct vpu_control_extended { - __u32 type; - __u32 data_len; - void * data_ptr; - __u32 buf_size; - void * buf_ptr; -}; -struct vpu_control_port { - __u32 control_id; - __u32 port; - union control_port_data { - __u32 framerate; - } data; -}; -#define VPU_CTRL_FPS 1000 -#define VPU_ATTACH_TO_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 1), int) -#define VPU_QUERY_SESSIONS _IOR('V', (BASE_VIDIOC_PRIVATE + 0), int) -#define VPU_CREATE_SESSION _IOR('V', (BASE_VIDIOC_PRIVATE + 2), int) -#define VPU_JOIN_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 3), int) -#define VPU_CREATE_OUTPUT2 _IO('V', (BASE_VIDIOC_PRIVATE + 5)) -#define VPU_COMMIT_CONFIGURATION _IO('V', (BASE_VIDIOC_PRIVATE + 10)) -#define VPU_FLUSH_BUFS _IOW('V', (BASE_VIDIOC_PRIVATE + 15), enum v4l2_buf_type) -#define VPU_G_CONTROL _IOWR('V', (BASE_VIDIOC_PRIVATE + 20), struct vpu_control) -#define VPU_S_CONTROL _IOW('V', (BASE_VIDIOC_PRIVATE + 21), struct vpu_control) -#define VPU_G_CONTROL_EXTENDED _IOWR('V', (BASE_VIDIOC_PRIVATE + 22), struct vpu_control_extended) -#define VPU_S_CONTROL_EXTENDED _IOW('V', (BASE_VIDIOC_PRIVATE + 23), struct vpu_control_extended) -#define VPU_G_CONTROL_PORT _IOWR('V', (BASE_VIDIOC_PRIVATE + 24), struct vpu_control_port) -#define VPU_S_CONTROL_PORT _IOW('V', (BASE_VIDIOC_PRIVATE + 25), struct vpu_control_port) -#endif - diff --git a/sdm710/kernel-headers/media/msmb_camera.h b/sdm710/kernel-headers/media/msmb_camera.h deleted file mode 100644 index eed3ad98..00000000 --- a/sdm710/kernel-headers/media/msmb_camera.h +++ /dev/null @@ -1,162 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_LINUX_MSMB_CAMERA_H -#define __UAPI_LINUX_MSMB_CAMERA_H -#include <linux/videodev2.h> -#include <linux/types.h> -#include <linux/ioctl.h> -#include <linux/media.h> -#define MSM_CAM_LOGSYNC_FILE_NAME "logsync" -#define MSM_CAM_LOGSYNC_FILE_BASEDIR "camera" -#define MSM_CAM_V4L2_IOCTL_NOTIFY _IOW('V', BASE_VIDIOC_PRIVATE + 30, struct msm_v4l2_event_data) -#define MSM_CAM_V4L2_IOCTL_NOTIFY_META _IOW('V', BASE_VIDIOC_PRIVATE + 31, struct msm_v4l2_event_data) -#define MSM_CAM_V4L2_IOCTL_CMD_ACK _IOW('V', BASE_VIDIOC_PRIVATE + 32, struct msm_v4l2_event_data) -#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR _IOW('V', BASE_VIDIOC_PRIVATE + 33, struct msm_v4l2_event_data) -#define MSM_CAM_V4L2_IOCTL_NOTIFY_DEBUG _IOW('V', BASE_VIDIOC_PRIVATE + 34, struct msm_v4l2_event_data) -#define MSM_CAM_V4L2_IOCTL_DAEMON_DISABLED _IOW('V', BASE_VIDIOC_PRIVATE + 35, struct msm_v4l2_event_data) -#define QCAMERA_VNODE_GROUP_ID MEDIA_ENT_F_IO_V4L -#define MSM_CAMERA_NAME "msm_camera" -#define MSM_CONFIGURATION_NAME "msm_config" -#define MSM_CAMERA_SUBDEV_BASE (MEDIA_ENT_F_OLD_BASE + 0xF00) -#define MSM_CAMERA_SUBDEV_CSIPHY (MSM_CAMERA_SUBDEV_BASE + 0) -#define MSM_CAMERA_SUBDEV_CSID (MSM_CAMERA_SUBDEV_BASE + 13) -#define MSM_CAMERA_SUBDEV_ISPIF (MSM_CAMERA_SUBDEV_BASE + 2) -#define MSM_CAMERA_SUBDEV_VFE (MSM_CAMERA_SUBDEV_BASE + 3) -#define MSM_CAMERA_SUBDEV_AXI (MSM_CAMERA_SUBDEV_BASE + 4) -#define MSM_CAMERA_SUBDEV_VPE (MSM_CAMERA_SUBDEV_BASE + 5) -#define MSM_CAMERA_SUBDEV_SENSOR (MSM_CAMERA_SUBDEV_BASE + 6) -#define MSM_CAMERA_SUBDEV_ACTUATOR (MSM_CAMERA_SUBDEV_BASE + 7) -#define MSM_CAMERA_SUBDEV_EEPROM (MSM_CAMERA_SUBDEV_BASE + 8) -#define MSM_CAMERA_SUBDEV_CPP (MSM_CAMERA_SUBDEV_BASE + 9) -#define MSM_CAMERA_SUBDEV_CCI (MSM_CAMERA_SUBDEV_BASE + 10) -#define MSM_CAMERA_SUBDEV_LED_FLASH (MSM_CAMERA_SUBDEV_BASE + 11) -#define MSM_CAMERA_SUBDEV_STROBE_FLASH (MSM_CAMERA_SUBDEV_BASE + 12) -#define MSM_CAMERA_SUBDEV_BUF_MNGR (MSM_CAMERA_SUBDEV_BASE + 1) -#define MSM_CAMERA_SUBDEV_SENSOR_INIT (MSM_CAMERA_SUBDEV_BASE + 14) -#define MSM_CAMERA_SUBDEV_OIS (MSM_CAMERA_SUBDEV_BASE + 15) -#define MSM_CAMERA_SUBDEV_FLASH (MSM_CAMERA_SUBDEV_BASE + 16) -#define MSM_CAMERA_SUBDEV_IR_LED (MSM_CAMERA_SUBDEV_BASE + 17) -#define MSM_CAMERA_SUBDEV_IR_CUT (MSM_CAMERA_SUBDEV_BASE + 18) -#define MSM_CAMERA_SUBDEV_EXT (MSM_CAMERA_SUBDEV_BASE + 19) -#define MSM_CAMERA_SUBDEV_TOF (MSM_CAMERA_SUBDEV_BASE + 20) -#define MSM_CAMERA_SUBDEV_LASER_LED (MSM_CAMERA_SUBDEV_BASE + 21) -#define MSM_MAX_CAMERA_SENSORS 5 -#define MSM_CAMERA_MAX_STREAM_BUF 72 -#define MSM_CAMERA_MAX_USER_BUFF_CNT 16 -#define MSM_CAMERA_FEATURE_BASE 0x00010000 -#define MSM_CAMERA_FEATURE_SHUTDOWN (MSM_CAMERA_FEATURE_BASE + 1) -#define MSM_CAMERA_STATUS_BASE 0x00020000 -#define MSM_CAMERA_STATUS_FAIL (MSM_CAMERA_STATUS_BASE + 1) -#define MSM_CAMERA_STATUS_SUCCESS (MSM_CAMERA_STATUS_BASE + 2) -#define MSM_CAMERA_V4L2_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x00002000) -#define MSM_CAMERA_EVENT_MIN 0 -#define MSM_CAMERA_NEW_SESSION (MSM_CAMERA_EVENT_MIN + 1) -#define MSM_CAMERA_DEL_SESSION (MSM_CAMERA_EVENT_MIN + 2) -#define MSM_CAMERA_SET_PARM (MSM_CAMERA_EVENT_MIN + 3) -#define MSM_CAMERA_GET_PARM (MSM_CAMERA_EVENT_MIN + 4) -#define MSM_CAMERA_MAPPING_CFG (MSM_CAMERA_EVENT_MIN + 5) -#define MSM_CAMERA_MAPPING_SES (MSM_CAMERA_EVENT_MIN + 6) -#define MSM_CAMERA_MSM_NOTIFY (MSM_CAMERA_EVENT_MIN + 7) -#define MSM_CAMERA_EVENT_MAX (MSM_CAMERA_EVENT_MIN + 8) -#define MSM_CAMERA_PRIV_S_CROP (V4L2_CID_PRIVATE_BASE + 1) -#define MSM_CAMERA_PRIV_G_CROP (V4L2_CID_PRIVATE_BASE + 2) -#define MSM_CAMERA_PRIV_G_FMT (V4L2_CID_PRIVATE_BASE + 3) -#define MSM_CAMERA_PRIV_S_FMT (V4L2_CID_PRIVATE_BASE + 4) -#define MSM_CAMERA_PRIV_TRY_FMT (V4L2_CID_PRIVATE_BASE + 5) -#define MSM_CAMERA_PRIV_METADATA (V4L2_CID_PRIVATE_BASE + 6) -#define MSM_CAMERA_PRIV_QUERY_CAP (V4L2_CID_PRIVATE_BASE + 7) -#define MSM_CAMERA_PRIV_STREAM_ON (V4L2_CID_PRIVATE_BASE + 8) -#define MSM_CAMERA_PRIV_STREAM_OFF (V4L2_CID_PRIVATE_BASE + 9) -#define MSM_CAMERA_PRIV_NEW_STREAM (V4L2_CID_PRIVATE_BASE + 10) -#define MSM_CAMERA_PRIV_DEL_STREAM (V4L2_CID_PRIVATE_BASE + 11) -#define MSM_CAMERA_PRIV_SHUTDOWN (V4L2_CID_PRIVATE_BASE + 12) -#define MSM_CAMERA_PRIV_STREAM_INFO_SYNC (V4L2_CID_PRIVATE_BASE + 13) -#define MSM_CAMERA_PRIV_G_SESSION_ID (V4L2_CID_PRIVATE_BASE + 14) -#define MSM_CAMERA_PRIV_CMD_MAX 20 -#define MSM_CAMERA_CMD_SUCCESS 0x00000001 -#define MSM_CAMERA_BUF_MAP_SUCCESS 0x00000002 -#define MSM_CAMERA_ERR_EVT_BASE 0x00010000 -#define MSM_CAMERA_ERR_CMD_FAIL (MSM_CAMERA_ERR_EVT_BASE + 1) -#define MSM_CAMERA_ERR_MAPPING (MSM_CAMERA_ERR_EVT_BASE + 2) -#define MSM_CAMERA_ERR_DEVICE_BUSY (MSM_CAMERA_ERR_EVT_BASE + 3) -struct msm_v4l2_event_data { - unsigned int command; - unsigned int status; - unsigned int session_id; - unsigned int stream_id; - unsigned int map_op; - unsigned int map_buf_idx; - unsigned int notify; - unsigned int arg_value; - unsigned int ret_value; - unsigned int v4l2_event_type; - unsigned int v4l2_event_id; - unsigned int handle; - unsigned int nop6; - unsigned int nop7; - unsigned int nop8; - unsigned int nop9; -}; -struct msm_v4l2_format_data { - enum v4l2_buf_type type; - unsigned int width; - unsigned int height; - unsigned int pixelformat; - unsigned char num_planes; - unsigned int plane_sizes[VIDEO_MAX_PLANES]; -}; -#define msm_v4l2_fourcc(a,b,c,d) ((__u32) (a) | ((__u32) (b) << 8) | ((__u32) (c) << 16) | ((__u32) (d) << 24)) -#define MSM_V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M') -#define MSM_V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E') -#define MSM_V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F') -#define MSM_V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B') -#define MSM_V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T') -#define MSM_V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S') -#define MSM_V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S') -#define MSM_V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G') -#define MSM_V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F') -#define MSM_V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T') -enum smmu_attach_mode { - NON_SECURE_MODE = 0x01, - SECURE_MODE = 0x02, - MAX_PROTECTION_MODE = 0x03, -}; -struct msm_camera_smmu_attach_type { - enum smmu_attach_mode attach; -}; -struct msm_camera_user_buf_cont_t { - unsigned int buf_cnt; - unsigned int buf_idx[MSM_CAMERA_MAX_USER_BUFF_CNT]; -}; -struct msm_camera_return_buf { - __u32 index; - __u32 reserved; -}; -#define MSM_CAMERA_PRIV_IOCTL_ID_BASE 0 -#define MSM_CAMERA_PRIV_IOCTL_ID_RETURN_BUF 1 -struct msm_camera_private_ioctl_arg { - __u32 id; - __u32 size; - __u32 result; - __u32 reserved; - __u64 ioctl_ptr; -}; -#define VIDIOC_MSM_CAMERA_PRIVATE_IOCTL_CMD _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_private_ioctl_arg) -#endif - diff --git a/sdm710/kernel-headers/media/msmb_generic_buf_mgr.h b/sdm710/kernel-headers/media/msmb_generic_buf_mgr.h deleted file mode 100644 index 4bb4c084..00000000 --- a/sdm710/kernel-headers/media/msmb_generic_buf_mgr.h +++ /dev/null @@ -1,61 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_MEDIA_MSMB_GENERIC_BUF_MGR_H__ -#define __UAPI_MEDIA_MSMB_GENERIC_BUF_MGR_H__ -#include <media/msmb_camera.h> -enum msm_camera_buf_mngr_cmd { - MSM_CAMERA_BUF_MNGR_CONT_MAP, - MSM_CAMERA_BUF_MNGR_CONT_UNMAP, - MSM_CAMERA_BUF_MNGR_CONT_MAX, -}; -enum msm_camera_buf_mngr_buf_type { - MSM_CAMERA_BUF_MNGR_BUF_PLANAR, - MSM_CAMERA_BUF_MNGR_BUF_USER, - MSM_CAMERA_BUF_MNGR_BUF_INVALID, -}; -struct msm_buf_mngr_info { - uint32_t session_id; - uint32_t stream_id; - uint32_t frame_id; - struct timeval timestamp; - uint32_t index; - uint32_t reserved; - enum msm_camera_buf_mngr_buf_type type; - struct msm_camera_user_buf_cont_t user_buf; -}; -struct msm_buf_mngr_main_cont_info { - uint32_t session_id; - uint32_t stream_id; - enum msm_camera_buf_mngr_cmd cmd; - uint32_t cnt; - int32_t cont_fd; -}; -#define MSM_CAMERA_BUF_MNGR_IOCTL_ID_BASE 0 -#define MSM_CAMERA_BUF_MNGR_IOCTL_ID_GET_BUF_BY_IDX 1 -#define VIDIOC_MSM_BUF_MNGR_GET_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 33, struct msm_buf_mngr_info) -#define VIDIOC_MSM_BUF_MNGR_PUT_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 34, struct msm_buf_mngr_info) -#define VIDIOC_MSM_BUF_MNGR_BUF_DONE _IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct msm_buf_mngr_info) -#define VIDIOC_MSM_BUF_MNGR_CONT_CMD _IOWR('V', BASE_VIDIOC_PRIVATE + 36, struct msm_buf_mngr_main_cont_info) -#define VIDIOC_MSM_BUF_MNGR_INIT _IOWR('V', BASE_VIDIOC_PRIVATE + 37, struct msm_buf_mngr_info) -#define VIDIOC_MSM_BUF_MNGR_DEINIT _IOWR('V', BASE_VIDIOC_PRIVATE + 38, struct msm_buf_mngr_info) -#define VIDIOC_MSM_BUF_MNGR_FLUSH _IOWR('V', BASE_VIDIOC_PRIVATE + 39, struct msm_buf_mngr_info) -#define VIDIOC_MSM_BUF_MNGR_IOCTL_CMD _IOWR('V', BASE_VIDIOC_PRIVATE + 40, struct msm_camera_private_ioctl_arg) -#define VIDIOC_MSM_BUF_MNGR_BUF_ERROR _IOWR('V', BASE_VIDIOC_PRIVATE + 41, struct msm_buf_mngr_info) -#endif - diff --git a/sdm710/kernel-headers/media/msmb_isp.h b/sdm710/kernel-headers/media/msmb_isp.h deleted file mode 100644 index f8552971..00000000 --- a/sdm710/kernel-headers/media/msmb_isp.h +++ /dev/null @@ -1,778 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_MSMB_ISP__ -#define __UAPI_MSMB_ISP__ -#include <linux/videodev2.h> -#include <media/msmb_camera.h> -#define MAX_PLANES_PER_STREAM 3 -#define MAX_NUM_STREAM 7 -#define ISP_VERSION_48 48 -#define ISP_VERSION_47 47 -#define ISP_VERSION_46 46 -#define ISP_VERSION_44 44 -#define ISP_VERSION_40 40 -#define ISP_VERSION_32 32 -#define ISP_NATIVE_BUF_BIT (0x10000 << 0) -#define ISP0_BIT (0x10000 << 1) -#define ISP1_BIT (0x10000 << 2) -#define ISP_META_CHANNEL_BIT (0x10000 << 3) -#define ISP_SCRATCH_BUF_BIT (0x10000 << 4) -#define ISP_OFFLINE_STATS_BIT (0x10000 << 5) -#define ISP_SVHDR_IN_BIT (0x10000 << 6) -#define ISP_SVHDR_OUT_BIT (0x10000 << 7) -#define ISP_STATS_STREAM_BIT 0x80000000 -#define VFE_HW_LIMIT 1 -struct msm_vfe_cfg_cmd_list; -enum ISP_START_PIXEL_PATTERN { - ISP_BAYER_RGRGRG, - ISP_BAYER_GRGRGR, - ISP_BAYER_BGBGBG, - ISP_BAYER_GBGBGB, - ISP_YUV_YCbYCr, - ISP_YUV_YCrYCb, - ISP_YUV_CbYCrY, - ISP_YUV_CrYCbY, - ISP_PIX_PATTERN_MAX -}; -enum msm_vfe_plane_fmt { - Y_PLANE, - CB_PLANE, - CR_PLANE, - CRCB_PLANE, - CBCR_PLANE, - VFE_PLANE_FMT_MAX -}; -enum msm_vfe_input_src { - VFE_PIX_0, - VFE_RAW_0, - VFE_RAW_1, - VFE_RAW_2, - VFE_SRC_MAX, -}; -enum msm_vfe_axi_stream_src { - PIX_ENCODER, - PIX_VIEWFINDER, - PIX_VIDEO, - CAMIF_RAW, - IDEAL_RAW, - RDI_INTF_0, - RDI_INTF_1, - RDI_INTF_2, - VFE_AXI_SRC_MAX -}; -enum msm_vfe_frame_skip_pattern { - NO_SKIP, - EVERY_2FRAME, - EVERY_3FRAME, - EVERY_4FRAME, - EVERY_5FRAME, - EVERY_6FRAME, - EVERY_7FRAME, - EVERY_8FRAME, - EVERY_16FRAME, - EVERY_32FRAME, - SKIP_ALL, - SKIP_RANGE, - MAX_SKIP, -}; -#define MSM_VFE_STREAM_STOP_PERIOD 15 -enum msm_isp_stats_type { - MSM_ISP_STATS_AEC, - MSM_ISP_STATS_AF, - MSM_ISP_STATS_AWB, - MSM_ISP_STATS_RS, - MSM_ISP_STATS_CS, - MSM_ISP_STATS_IHIST, - MSM_ISP_STATS_SKIN, - MSM_ISP_STATS_BG, - MSM_ISP_STATS_BF, - MSM_ISP_STATS_BE, - MSM_ISP_STATS_BHIST, - MSM_ISP_STATS_BF_SCALE, - MSM_ISP_STATS_HDR_BE, - MSM_ISP_STATS_HDR_BHIST, - MSM_ISP_STATS_AEC_BG, - MSM_ISP_STATS_MAX -}; -struct msm_isp_sw_framskip { - uint32_t stats_type_mask; - uint32_t stream_src_mask; - enum msm_vfe_frame_skip_pattern skip_mode; - uint32_t min_frame_id; - uint32_t max_frame_id; -}; -enum msm_vfe_testgen_color_pattern { - COLOR_BAR_8_COLOR, - UNICOLOR_WHITE, - UNICOLOR_YELLOW, - UNICOLOR_CYAN, - UNICOLOR_GREEN, - UNICOLOR_MAGENTA, - UNICOLOR_RED, - UNICOLOR_BLUE, - UNICOLOR_BLACK, - MAX_COLOR, -}; -enum msm_vfe_camif_input { - CAMIF_DISABLED, - CAMIF_PAD_REG_INPUT, - CAMIF_MIDDI_INPUT, - CAMIF_MIPI_INPUT, -}; -struct msm_vfe_fetch_engine_cfg { - uint32_t input_format; - uint32_t buf_width; - uint32_t buf_height; - uint32_t fetch_width; - uint32_t fetch_height; - uint32_t x_offset; - uint32_t y_offset; - uint32_t buf_stride; -}; -enum msm_vfe_camif_output_format { - CAMIF_QCOM_RAW, - CAMIF_MIPI_RAW, - CAMIF_PLAIN_8, - CAMIF_PLAIN_16, - CAMIF_MAX_FORMAT, -}; -struct msm_vfe_camif_subsample_cfg { - uint32_t irq_subsample_period; - uint32_t irq_subsample_pattern; - uint32_t sof_counter_step; - uint32_t pixel_skip; - uint32_t line_skip; - uint32_t first_line; - uint32_t last_line; - uint32_t first_pixel; - uint32_t last_pixel; - enum msm_vfe_camif_output_format output_format; -}; -struct msm_vfe_camif_cfg { - uint32_t lines_per_frame; - uint32_t pixels_per_line; - uint32_t first_pixel; - uint32_t last_pixel; - uint32_t first_line; - uint32_t last_line; - uint32_t epoch_line0; - uint32_t epoch_line1; - uint32_t is_split; - enum msm_vfe_camif_input camif_input; - struct msm_vfe_camif_subsample_cfg subsample_cfg; -}; -struct msm_vfe_testgen_cfg { - uint32_t lines_per_frame; - uint32_t pixels_per_line; - uint32_t v_blank; - uint32_t h_blank; - enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern; - uint32_t rotate_period; - enum msm_vfe_testgen_color_pattern color_bar_pattern; - uint32_t burst_num_frame; -}; -enum msm_vfe_inputmux { - CAMIF, - TESTGEN, - EXTERNAL_READ, -}; -enum msm_vfe_stats_composite_group { - STATS_COMPOSITE_GRP_NONE, - STATS_COMPOSITE_GRP_1, - STATS_COMPOSITE_GRP_2, - STATS_COMPOSITE_GRP_MAX, -}; -enum msm_vfe_hvx_streaming_cmd { - HVX_DISABLE, - HVX_ONE_WAY, - HVX_ROUND_TRIP -}; -struct msm_vfe_pix_cfg { - struct msm_vfe_camif_cfg camif_cfg; - struct msm_vfe_testgen_cfg testgen_cfg; - struct msm_vfe_fetch_engine_cfg fetch_engine_cfg; - enum msm_vfe_inputmux input_mux; - enum ISP_START_PIXEL_PATTERN pixel_pattern; - uint32_t input_format; - enum msm_vfe_hvx_streaming_cmd hvx_cmd; - uint32_t is_split; -}; -struct msm_vfe_rdi_cfg { - uint8_t cid; - uint8_t frame_based; -}; -struct msm_vfe_input_cfg { - union { - struct msm_vfe_pix_cfg pix_cfg; - struct msm_vfe_rdi_cfg rdi_cfg; - } d; - enum msm_vfe_input_src input_src; - uint32_t input_pix_clk; -}; -struct msm_vfe_fetch_eng_start { - uint32_t session_id; - uint32_t stream_id; - uint32_t buf_idx; - uint8_t offline_mode; - uint32_t fd; - uint32_t buf_addr; - uint32_t frame_id; -}; -enum msm_vfe_fetch_eng_pass { - OFFLINE_FIRST_PASS, - OFFLINE_SECOND_PASS, - OFFLINE_MAX_PASS, -}; -struct msm_vfe_fetch_eng_multi_pass_start { - uint32_t session_id; - uint32_t stream_id; - uint32_t buf_idx; - uint8_t offline_mode; - uint32_t fd; - uint32_t buf_addr; - uint32_t frame_id; - uint32_t output_buf_idx; - uint32_t input_buf_offset; - enum msm_vfe_fetch_eng_pass offline_pass; - uint32_t output_stream_id; -}; -struct msm_vfe_axi_plane_cfg { - uint32_t output_width; - uint32_t output_height; - uint32_t output_stride; - uint32_t output_scan_lines; - uint32_t output_plane_format; - uint32_t plane_addr_offset; - uint8_t csid_src; - uint8_t rdi_cid; -}; -enum msm_stream_rdi_input_type { - MSM_CAMERA_RDI_MIN, - MSM_CAMERA_RDI_PDAF, - MSM_CAMERA_RDI_MAX, -}; -struct msm_vfe_axi_stream_request_cmd { - uint32_t session_id; - uint32_t stream_id; - uint32_t vt_enable; - uint32_t output_format; - enum msm_vfe_axi_stream_src stream_src; - struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; - uint32_t burst_count; - uint32_t hfr_mode; - uint8_t frame_base; - uint32_t init_frame_drop; - enum msm_vfe_frame_skip_pattern frame_skip_pattern; - uint8_t buf_divert; - uint32_t axi_stream_handle; - uint32_t controllable_output; - uint32_t burst_len; - enum msm_stream_rdi_input_type rdi_input_type; -}; -struct msm_vfe_axi_stream_release_cmd { - uint32_t stream_handle; -}; -enum msm_vfe_axi_stream_cmd { - STOP_STREAM, - START_STREAM, - STOP_IMMEDIATELY, -}; -struct msm_vfe_axi_stream_cfg_cmd { - uint8_t num_streams; - uint32_t stream_handle[VFE_AXI_SRC_MAX]; - enum msm_vfe_axi_stream_cmd cmd; - uint8_t sync_frame_id_src; -}; -enum msm_vfe_axi_stream_update_type { - ENABLE_STREAM_BUF_DIVERT, - DISABLE_STREAM_BUF_DIVERT, - UPDATE_STREAM_FRAMEDROP_PATTERN, - UPDATE_STREAM_STATS_FRAMEDROP_PATTERN, - UPDATE_STREAM_AXI_CONFIG, - UPDATE_STREAM_REQUEST_FRAMES, - UPDATE_STREAM_ADD_BUFQ, - UPDATE_STREAM_REMOVE_BUFQ, - UPDATE_STREAM_SW_FRAME_DROP, - UPDATE_STREAM_REQUEST_FRAMES_VER2, - UPDATE_STREAM_OFFLINE_AXI_CONFIG, -}; -#define UPDATE_STREAM_REQUEST_FRAMES_VER2 UPDATE_STREAM_REQUEST_FRAMES_VER2 -enum msm_vfe_iommu_type { - IOMMU_ATTACH, - IOMMU_DETACH, -}; -enum msm_vfe_buff_queue_id { - VFE_BUF_QUEUE_DEFAULT, - VFE_BUF_QUEUE_SHARED, - VFE_BUF_QUEUE_MAX, -}; -struct msm_vfe_axi_stream_cfg_update_info { - uint32_t stream_handle; - uint32_t output_format; - uint32_t user_stream_id; - uint32_t frame_id; - enum msm_vfe_frame_skip_pattern skip_pattern; - struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; - struct msm_isp_sw_framskip sw_skip_info; -}; -struct msm_vfe_axi_stream_cfg_update_info_req_frm { - uint32_t stream_handle; - uint32_t user_stream_id; - uint32_t frame_id; - uint32_t buf_index; -}; -struct msm_vfe_axi_halt_cmd { - uint32_t stop_camif; - uint32_t overflow_detected; - uint32_t blocking_halt; -}; -struct msm_vfe_axi_reset_cmd { - uint32_t blocking; - uint32_t frame_id; -}; -struct msm_vfe_axi_restart_cmd { - uint32_t enable_camif; -}; -struct msm_vfe_axi_stream_update_cmd { - uint32_t num_streams; - enum msm_vfe_axi_stream_update_type update_type; - union { - struct msm_vfe_axi_stream_cfg_update_info update_info[MSM_ISP_STATS_MAX]; - struct msm_vfe_axi_stream_cfg_update_info_req_frm req_frm_ver2; - }; -}; -struct msm_vfe_smmu_attach_cmd { - uint32_t security_mode; - uint32_t iommu_attach_mode; -}; -struct msm_vfe_stats_stream_request_cmd { - uint32_t session_id; - uint32_t stream_id; - enum msm_isp_stats_type stats_type; - uint32_t composite_flag; - uint32_t framedrop_pattern; - uint32_t init_frame_drop; - uint32_t irq_subsample_pattern; - uint32_t buffer_offset; - uint32_t stream_handle; -}; -struct msm_vfe_stats_stream_release_cmd { - uint32_t stream_handle; -}; -struct msm_vfe_stats_stream_cfg_cmd { - uint8_t num_streams; - uint32_t stream_handle[MSM_ISP_STATS_MAX]; - uint8_t enable; - uint32_t stats_burst_len; -}; -enum msm_vfe_reg_cfg_type { - VFE_WRITE, - VFE_WRITE_MB, - VFE_READ, - VFE_CFG_MASK, - VFE_WRITE_DMI_16BIT, - VFE_WRITE_DMI_32BIT, - VFE_WRITE_DMI_64BIT, - VFE_READ_DMI_16BIT, - VFE_READ_DMI_32BIT, - VFE_READ_DMI_64BIT, - GET_MAX_CLK_RATE, - GET_CLK_RATES, - GET_ISP_ID, - VFE_HW_UPDATE_LOCK, - VFE_HW_UPDATE_UNLOCK, - SET_WM_UB_SIZE, - SET_UB_POLICY, - GET_VFE_HW_LIMIT, -}; -struct msm_vfe_cfg_cmd2 { - uint16_t num_cfg; - uint16_t cmd_len; - void * cfg_data; - void * cfg_cmd; -}; -struct msm_vfe_cfg_cmd_list { - struct msm_vfe_cfg_cmd2 cfg_cmd; - struct msm_vfe_cfg_cmd_list * next; - uint32_t next_size; -}; -struct msm_vfe_reg_rw_info { - uint32_t reg_offset; - uint32_t cmd_data_offset; - uint32_t len; -}; -struct msm_vfe_reg_mask_info { - uint32_t reg_offset; - uint32_t mask; - uint32_t val; -}; -struct msm_vfe_reg_dmi_info { - uint32_t hi_tbl_offset; - uint32_t lo_tbl_offset; - uint32_t len; -}; -struct msm_vfe_reg_cfg_cmd { - union { - struct msm_vfe_reg_rw_info rw_info; - struct msm_vfe_reg_mask_info mask_info; - struct msm_vfe_reg_dmi_info dmi_info; - } u; - enum msm_vfe_reg_cfg_type cmd_type; -}; -enum vfe_sd_type { - VFE_SD_0 = 0, - VFE_SD_1, - VFE_SD_COMMON, - VFE_SD_MAX, -}; -#define MS_NUM_SLAVE_MAX 1 -enum msm_vfe_dual_hw_type { - DUAL_NONE = 0, - DUAL_HW_VFE_SPLIT = 1, - DUAL_HW_MASTER_SLAVE = 2, -}; -enum msm_vfe_dual_hw_ms_type { - MS_TYPE_NONE, - MS_TYPE_MASTER, - MS_TYPE_SLAVE, -}; -struct msm_isp_set_dual_hw_ms_cmd { - uint8_t num_src; - enum msm_vfe_dual_hw_ms_type dual_hw_ms_type; - enum msm_vfe_input_src primary_intf; - enum msm_vfe_input_src input_src[VFE_SRC_MAX]; - uint32_t sof_delta_threshold; -}; -enum msm_isp_buf_type { - ISP_PRIVATE_BUF, - ISP_SHARE_BUF, - MAX_ISP_BUF_TYPE, -}; -struct msm_isp_unmap_buf_req { - uint32_t fd; -}; -struct msm_isp_buf_request { - uint32_t session_id; - uint32_t stream_id; - uint8_t num_buf; - uint32_t handle; - enum msm_isp_buf_type buf_type; -}; -struct msm_isp_buf_request_ver2 { - uint32_t session_id; - uint32_t stream_id; - uint8_t num_buf; - uint32_t handle; - enum msm_isp_buf_type buf_type; - enum smmu_attach_mode security_mode; - uint32_t reserved[4]; -}; -struct msm_isp_qbuf_plane { - uint32_t addr; - uint32_t offset; - uint32_t length; -}; -struct msm_isp_qbuf_buffer { - struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM]; - uint32_t num_planes; -}; -struct msm_isp_qbuf_info { - uint32_t handle; - int32_t buf_idx; - struct msm_isp_qbuf_buffer buffer; - uint32_t dirty_buf; -}; -struct msm_isp_clk_rates { - uint32_t svs_rate; - uint32_t nominal_rate; - uint32_t high_rate; -}; -struct msm_vfe_axi_src_state { - enum msm_vfe_input_src input_src; - uint32_t src_active; - uint32_t src_frame_id; -}; -enum msm_isp_event_mask_index { - ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0, - ISP_EVENT_MASK_INDEX_ERROR = 1, - ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2, - ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3, - ISP_EVENT_MASK_INDEX_REG_UPDATE = 4, - ISP_EVENT_MASK_INDEX_SOF = 5, - ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6, - ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7, - ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8, - ISP_EVENT_MASK_INDEX_BUF_DONE = 9, - ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING = 10, - ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH = 11, - ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR = 12, -}; -#define ISP_EVENT_SUBS_MASK_NONE 0 -#define ISP_EVENT_SUBS_MASK_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY) -#define ISP_EVENT_SUBS_MASK_ERROR (1 << ISP_EVENT_MASK_INDEX_ERROR) -#define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT (1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT) -#define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE (1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE) -#define ISP_EVENT_SUBS_MASK_REG_UPDATE (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE) -#define ISP_EVENT_SUBS_MASK_SOF (1 << ISP_EVENT_MASK_INDEX_SOF) -#define ISP_EVENT_SUBS_MASK_BUF_DIVERT (1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT) -#define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY) -#define ISP_EVENT_SUBS_MASK_FE_READ_DONE (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE) -#define ISP_EVENT_SUBS_MASK_BUF_DONE (1 << ISP_EVENT_MASK_INDEX_BUF_DONE) -#define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING) -#define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH (1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH) -#define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR (1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR) -enum msm_isp_event_idx { - ISP_REG_UPDATE = 0, - ISP_EPOCH_0 = 1, - ISP_EPOCH_1 = 2, - ISP_START_ACK = 3, - ISP_STOP_ACK = 4, - ISP_IRQ_VIOLATION = 5, - ISP_STATS_OVERFLOW = 6, - ISP_BUF_DONE = 7, - ISP_FE_RD_DONE = 8, - ISP_IOMMU_P_FAULT = 9, - ISP_ERROR = 10, - ISP_HW_FATAL_ERROR = 11, - ISP_PING_PONG_MISMATCH = 12, - ISP_REG_UPDATE_MISSING = 13, - ISP_BUF_FATAL_ERROR = 14, - ISP_EVENT_MAX = 15 -}; -#define ISP_EVENT_OFFSET 8 -#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) -#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) -#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) -#define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET)) -#define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET)) -#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) -#define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0) -#define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1) -#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) -#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) -#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) -#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) -#define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR) -#define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE) -#define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1) -#define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE) -#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) -#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) -#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) -#define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE) -#define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT) -#define ISP_EVENT_HW_FATAL_ERROR (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR) -#define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH) -#define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING) -#define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR) -#define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE) -struct msm_isp_buf_event { - uint32_t session_id; - uint32_t stream_id; - uint32_t handle; - uint32_t output_format; - int8_t buf_idx; -}; -struct msm_isp_fetch_eng_event { - uint32_t session_id; - uint32_t stream_id; - uint32_t handle; - uint32_t fd; - int8_t buf_idx; - int8_t offline_mode; -}; -struct msm_isp_stats_event { - uint32_t stats_mask; - uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; - uint8_t pd_stats_idx; -}; -struct msm_isp_stream_ack { - uint32_t session_id; - uint32_t stream_id; - uint32_t handle; -}; -enum msm_vfe_error_type { - ISP_ERROR_NONE, - ISP_ERROR_CAMIF, - ISP_ERROR_BUS_OVERFLOW, - ISP_ERROR_RETURN_EMPTY_BUFFER, - ISP_ERROR_FRAME_ID_MISMATCH, - ISP_ERROR_MAX, -}; -struct msm_isp_error_info { - enum msm_vfe_error_type err_type; - uint32_t session_id; - uint32_t stream_id; - uint32_t stream_id_mask; -}; -struct msm_isp_ms_delta_info { - uint8_t num_delta_info; - uint32_t delta[MS_NUM_SLAVE_MAX]; -}; -struct msm_isp_output_info { - uint8_t regs_not_updated; - uint16_t output_err_mask; - uint8_t stream_framedrop_mask; - uint16_t stats_framedrop_mask; -}; -struct msm_isp_sof_info { - uint8_t regs_not_updated; - uint16_t reg_update_fail_mask; - uint32_t stream_get_buf_fail_mask; - uint16_t stats_get_buf_fail_mask; - struct msm_isp_ms_delta_info ms_delta_info; - uint16_t axi_updating_mask; - uint32_t reg_update_fail_mask_ext; -}; -#define AXI_UPDATING_MASK 1 -#define REG_UPDATE_FAIL_MASK_EXT 1 -struct msm_isp_event_data { - struct timeval timestamp; - struct timeval mono_timestamp; - uint32_t frame_id; - union { - struct msm_isp_stats_event stats; - struct msm_isp_buf_event buf_done; - struct msm_isp_fetch_eng_event fetch_done; - struct msm_isp_error_info error_info; - struct msm_isp_output_info output_info; - struct msm_isp_sof_info sof_info; - } u; -}; -enum msm_vfe_ahb_clk_vote { - MSM_ISP_CAMERA_AHB_SVS_VOTE = 1, - MSM_ISP_CAMERA_AHB_TURBO_VOTE = 2, - MSM_ISP_CAMERA_AHB_NOMINAL_VOTE = 3, - MSM_ISP_CAMERA_AHB_SUSPEND_VOTE = 4, -}; -struct msm_isp_ahb_clk_cfg { - uint32_t vote; - uint32_t reserved[2]; -}; -enum msm_vfe_dual_cam_sync_mode { - MSM_ISP_DUAL_CAM_ASYNC, - MSM_ISP_DUAL_CAM_SYNC, -}; -struct msm_isp_dual_hw_master_slave_sync { - uint32_t sync_mode; - uint32_t reserved[2]; -}; -struct msm_vfe_dual_lpm_mode { - enum msm_vfe_axi_stream_src stream_src[VFE_AXI_SRC_MAX]; - uint32_t num_src; - uint32_t lpm_mode; -}; -#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') -#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') -#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') -#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') -#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') -#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') -#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') -#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') -#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') -#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') -#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') -#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') -#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4') -#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4') -#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4') -#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4') -#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0') -#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0') -#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0') -#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0') -#define V4L2_PIX_FMT_P16BGGR12 v4l2_fourcc('P', 'B', 'G', '2') -#define V4L2_PIX_FMT_P16GBRG12 v4l2_fourcc('P', 'G', 'B', '2') -#define V4L2_PIX_FMT_P16GRBG12 v4l2_fourcc('P', 'G', 'R', '2') -#define V4L2_PIX_FMT_P16RGGB12 v4l2_fourcc('P', 'R', 'G', '2') -#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4') -#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1') -#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T') -#define V4L2_PIX_FMT_META10 v4l2_fourcc('Q', 'M', '1', '0') -#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') -#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') -#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') -#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') -enum msm_isp_ioctl_cmd_code { - MSM_VFE_REG_CFG = BASE_VIDIOC_PRIVATE, - MSM_ISP_REQUEST_BUF, - MSM_ISP_ENQUEUE_BUF, - MSM_ISP_RELEASE_BUF, - MSM_ISP_REQUEST_STREAM, - MSM_ISP_CFG_STREAM, - MSM_ISP_RELEASE_STREAM, - MSM_ISP_INPUT_CFG, - MSM_ISP_SET_SRC_STATE, - MSM_ISP_REQUEST_STATS_STREAM, - MSM_ISP_CFG_STATS_STREAM, - MSM_ISP_RELEASE_STATS_STREAM, - MSM_ISP_REG_UPDATE_CMD, - MSM_ISP_UPDATE_STREAM, - MSM_VFE_REG_LIST_CFG, - MSM_ISP_SMMU_ATTACH, - MSM_ISP_UPDATE_STATS_STREAM, - MSM_ISP_AXI_HALT, - MSM_ISP_AXI_RESET, - MSM_ISP_AXI_RESTART, - MSM_ISP_FETCH_ENG_START, - MSM_ISP_DEQUEUE_BUF, - MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, - MSM_ISP_MAP_BUF_START_FE, - MSM_ISP_UNMAP_BUF, - MSM_ISP_AHB_CLK_CFG, - MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, - MSM_ISP_FETCH_ENG_MULTI_PASS_START, - MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, - MSM_ISP_REQUEST_BUF_VER2, - MSM_ISP_DUAL_HW_LPM_MODE, -}; -#define VIDIOC_MSM_VFE_REG_CFG _IOWR('V', MSM_VFE_REG_CFG, struct msm_vfe_cfg_cmd2) -#define VIDIOC_MSM_ISP_REQUEST_BUF _IOWR('V', MSM_ISP_REQUEST_BUF, struct msm_isp_buf_request) -#define VIDIOC_MSM_ISP_ENQUEUE_BUF _IOWR('V', MSM_ISP_ENQUEUE_BUF, struct msm_isp_qbuf_info) -#define VIDIOC_MSM_ISP_RELEASE_BUF _IOWR('V', MSM_ISP_RELEASE_BUF, struct msm_isp_buf_request) -#define VIDIOC_MSM_ISP_REQUEST_STREAM _IOWR('V', MSM_ISP_REQUEST_STREAM, struct msm_vfe_axi_stream_request_cmd) -#define VIDIOC_MSM_ISP_CFG_STREAM _IOWR('V', MSM_ISP_CFG_STREAM, struct msm_vfe_axi_stream_cfg_cmd) -#define VIDIOC_MSM_ISP_RELEASE_STREAM _IOWR('V', MSM_ISP_RELEASE_STREAM, struct msm_vfe_axi_stream_release_cmd) -#define VIDIOC_MSM_ISP_INPUT_CFG _IOWR('V', MSM_ISP_INPUT_CFG, struct msm_vfe_input_cfg) -#define VIDIOC_MSM_ISP_SET_SRC_STATE _IOWR('V', MSM_ISP_SET_SRC_STATE, struct msm_vfe_axi_src_state) -#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM _IOWR('V', MSM_ISP_REQUEST_STATS_STREAM, struct msm_vfe_stats_stream_request_cmd) -#define VIDIOC_MSM_ISP_CFG_STATS_STREAM _IOWR('V', MSM_ISP_CFG_STATS_STREAM, struct msm_vfe_stats_stream_cfg_cmd) -#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM _IOWR('V', MSM_ISP_RELEASE_STATS_STREAM, struct msm_vfe_stats_stream_release_cmd) -#define VIDIOC_MSM_ISP_REG_UPDATE_CMD _IOWR('V', MSM_ISP_REG_UPDATE_CMD, enum msm_vfe_input_src) -#define VIDIOC_MSM_ISP_UPDATE_STREAM _IOWR('V', MSM_ISP_UPDATE_STREAM, struct msm_vfe_axi_stream_update_cmd) -#define VIDIOC_MSM_VFE_REG_LIST_CFG _IOWR('V', MSM_VFE_REG_LIST_CFG, struct msm_vfe_cfg_cmd_list) -#define VIDIOC_MSM_ISP_SMMU_ATTACH _IOWR('V', MSM_ISP_SMMU_ATTACH, struct msm_vfe_smmu_attach_cmd) -#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM _IOWR('V', MSM_ISP_UPDATE_STATS_STREAM, struct msm_vfe_axi_stream_update_cmd) -#define VIDIOC_MSM_ISP_AXI_HALT _IOWR('V', MSM_ISP_AXI_HALT, struct msm_vfe_axi_halt_cmd) -#define VIDIOC_MSM_ISP_AXI_RESET _IOWR('V', MSM_ISP_AXI_RESET, struct msm_vfe_axi_reset_cmd) -#define VIDIOC_MSM_ISP_AXI_RESTART _IOWR('V', MSM_ISP_AXI_RESTART, struct msm_vfe_axi_restart_cmd) -#define VIDIOC_MSM_ISP_FETCH_ENG_START _IOWR('V', MSM_ISP_FETCH_ENG_START, struct msm_vfe_fetch_eng_start) -#define VIDIOC_MSM_ISP_DEQUEUE_BUF _IOWR('V', MSM_ISP_DEQUEUE_BUF, struct msm_isp_qbuf_info) -#define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE _IOWR('V', MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, struct msm_isp_set_dual_hw_ms_cmd) -#define VIDIOC_MSM_ISP_MAP_BUF_START_FE _IOWR('V', MSM_ISP_MAP_BUF_START_FE, struct msm_vfe_fetch_eng_start) -#define VIDIOC_MSM_ISP_UNMAP_BUF _IOWR('V', MSM_ISP_UNMAP_BUF, struct msm_isp_unmap_buf_req) -#define VIDIOC_MSM_ISP_AHB_CLK_CFG _IOWR('V', MSM_ISP_AHB_CLK_CFG, struct msm_isp_ahb_clk_cfg) -#define VIDIOC_MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC _IOWR('V', MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, struct msm_isp_dual_hw_master_slave_sync) -#define VIDIOC_MSM_ISP_FETCH_ENG_MULTI_PASS_START _IOWR('V', MSM_ISP_FETCH_ENG_MULTI_PASS_START, struct msm_vfe_fetch_eng_multi_pass_start) -#define VIDIOC_MSM_ISP_MAP_BUF_START_MULTI_PASS_FE _IOWR('V', MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, struct msm_vfe_fetch_eng_multi_pass_start) -#define VIDIOC_MSM_ISP_REQUEST_BUF_VER2 _IOWR('V', MSM_ISP_REQUEST_BUF_VER2, struct msm_isp_buf_request_ver2) -#define VIDIOC_MSM_ISP_DUAL_HW_LPM_MODE _IOWR('V', MSM_ISP_DUAL_HW_LPM_MODE, struct msm_vfe_dual_lpm_mode) -#endif - diff --git a/sdm710/kernel-headers/media/msmb_ispif.h b/sdm710/kernel-headers/media/msmb_ispif.h deleted file mode 100644 index 5f50fd4d..00000000 --- a/sdm710/kernel-headers/media/msmb_ispif.h +++ /dev/null @@ -1,169 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef UAPI_MSMB_ISPIF_H -#define UAPI_MSMB_ISPIF_H -#include <linux/types.h> -#include <linux/ioctl.h> -#include <linux/videodev2.h> -#define CSID_VERSION_V20 0x02000011 -#define CSID_VERSION_V22 0x02001000 -#define CSID_VERSION_V30 0x30000000 -#define CSID_VERSION_V3 0x30000000 -enum msm_ispif_vfe_intf { - VFE0, - VFE1, - VFE_MAX -}; -#define VFE0_MASK (1 << VFE0) -#define VFE1_MASK (1 << VFE1) -enum msm_ispif_intftype { - PIX0, - RDI0, - PIX1, - RDI1, - RDI2, - INTF_MAX -}; -#define MAX_PARAM_ENTRIES (INTF_MAX * 2) -#define MAX_CID_CH 8 -#define MAX_CID_CH_PARAM_ENTRY 3 -#define PIX0_MASK (1 << PIX0) -#define PIX1_MASK (1 << PIX1) -#define RDI0_MASK (1 << RDI0) -#define RDI1_MASK (1 << RDI1) -#define RDI2_MASK (1 << RDI2) -enum msm_ispif_vc { - VC0, - VC1, - VC2, - VC3, - VC_MAX -}; -enum msm_ispif_cid { - CID0, - CID1, - CID2, - CID3, - CID4, - CID5, - CID6, - CID7, - CID8, - CID9, - CID10, - CID11, - CID12, - CID13, - CID14, - CID15, - CID_MAX -}; -enum msm_ispif_csid { - CSID0, - CSID1, - CSID2, - CSID3, - CSID_MAX -}; -enum msm_ispif_pixel_odd_even { - PIX_EVEN, - PIX_ODD -}; -enum msm_ispif_pixel_pack_mode { - PACK_BYTE, - PACK_PLAIN_PACK, - PACK_NV_P8, - PACK_NV_P16 -}; -struct msm_ispif_pack_cfg { - int pixel_swap_en; - enum msm_ispif_pixel_odd_even even_odd_sel; - enum msm_ispif_pixel_pack_mode pack_mode; -}; -struct msm_ispif_params_entry { - enum msm_ispif_vfe_intf vfe_intf; - enum msm_ispif_intftype intftype; - int num_cids; - enum msm_ispif_cid cids[MAX_CID_CH_PARAM_ENTRY]; - enum msm_ispif_csid csid; - int crop_enable; - uint16_t crop_start_pixel; - uint16_t crop_end_pixel; -}; -struct msm_ispif_right_param_entry { - enum msm_ispif_cid cids[MAX_CID_CH_PARAM_ENTRY]; - enum msm_ispif_csid csid; -}; -struct msm_ispif_param_data_ext { - uint32_t num; - struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES]; - struct msm_ispif_pack_cfg pack_cfg[CID_MAX]; - struct msm_ispif_right_param_entry right_entries[MAX_PARAM_ENTRIES]; - uint32_t stereo_enable; - uint16_t line_width[VFE_MAX]; -}; -struct msm_ispif_param_data { - uint32_t num; - struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES]; -}; -struct msm_isp_info { - uint32_t max_resolution; - uint32_t id; - uint32_t ver; -}; -struct msm_ispif_vfe_info { - int num_vfe; - struct msm_isp_info info[VFE_MAX]; -}; -enum ispif_cfg_type_t { - ISPIF_CLK_ENABLE, - ISPIF_CLK_DISABLE, - ISPIF_INIT, - ISPIF_CFG, - ISPIF_START_FRAME_BOUNDARY, - ISPIF_RESTART_FRAME_BOUNDARY, - ISPIF_STOP_FRAME_BOUNDARY, - ISPIF_STOP_IMMEDIATELY, - ISPIF_RELEASE, - ISPIF_ENABLE_REG_DUMP, - ISPIF_SET_VFE_INFO, - ISPIF_CFG2, - ISPIF_CFG_STEREO, -}; -struct ispif_cfg_data { - enum ispif_cfg_type_t cfg_type; - union { - int reg_dump; - uint32_t csid_version; - struct msm_ispif_vfe_info vfe_info; - struct msm_ispif_param_data params; - }; -}; -struct ispif_cfg_data_ext { - enum ispif_cfg_type_t cfg_type; - void * data; - uint32_t size; -}; -#define ISPIF_RDI_PACK_MODE_SUPPORT 1 -#define ISPIF_3D_SUPPORT 1 -#define ISPIF_LINE_WIDTH_SUPPORT 1 -#define VIDIOC_MSM_ISPIF_CFG _IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data) -#define VIDIOC_MSM_ISPIF_CFG_EXT _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct ispif_cfg_data_ext) -#endif - diff --git a/sdm710/kernel-headers/media/msmb_pproc.h b/sdm710/kernel-headers/media/msmb_pproc.h deleted file mode 100644 index 2cb4155a..00000000 --- a/sdm710/kernel-headers/media/msmb_pproc.h +++ /dev/null @@ -1,193 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __UAPI_MSMB_PPROC_H -#define __UAPI_MSMB_PPROC_H -#include <linux/videodev2.h> -#include <linux/types.h> -#include <media/msmb_generic_buf_mgr.h> -#define MAX_PLANES VIDEO_MAX_PLANES -#define PARTIAL_FRAME_STRIPE_COUNT 4 -#define MAX_NUM_CPP_STRIPS 8 -#define MSM_CPP_MAX_NUM_PLANES 3 -#define MSM_CPP_MIN_FRAME_LENGTH 13 -#define MSM_CPP_MAX_FRAME_LENGTH 4096 -#define MSM_CPP_MAX_FW_NAME_LEN 32 -#define MAX_FREQ_TBL 10 -#define MSM_OUTPUT_BUF_CNT 8 -enum msm_cpp_frame_type { - MSM_CPP_OFFLINE_FRAME, - MSM_CPP_REALTIME_FRAME, -}; -enum msm_vpe_frame_type { - MSM_VPE_OFFLINE_FRAME, - MSM_VPE_REALTIME_FRAME, -}; -struct msm_cpp_buffer_info_t { - int32_t fd; - uint32_t index; - uint32_t offset; - uint8_t native_buff; - uint8_t processed_divert; - uint32_t identity; -}; -struct msm_cpp_stream_buff_info_t { - uint32_t identity; - uint32_t num_buffs; - struct msm_cpp_buffer_info_t * buffer_info; -}; -enum msm_cpp_batch_mode_t { - BATCH_MODE_NONE, - BATCH_MODE_VIDEO, - BATCH_MODE_PREVIEW -}; -struct msm_cpp_batch_info_t { - enum msm_cpp_batch_mode_t batch_mode; - uint32_t batch_size; - uint32_t intra_plane_offset[MAX_PLANES]; - uint32_t pick_preview_idx; - uint32_t cont_idx; -}; -struct msm_cpp_frame_info_t { - int32_t frame_id; - struct timeval timestamp; - uint32_t inst_id; - uint32_t identity; - uint32_t client_id; - enum msm_cpp_frame_type frame_type; - uint32_t num_strips; - uint32_t msg_len; - uint32_t * cpp_cmd_msg; - int src_fd; - int dst_fd; - struct timeval in_time, out_time; - void * cookie; - int32_t * status; - int32_t duplicate_output; - uint32_t duplicate_identity; - uint32_t feature_mask; - uint8_t we_disable; - struct msm_cpp_buffer_info_t input_buffer_info; - struct msm_cpp_buffer_info_t output_buffer_info[MSM_OUTPUT_BUF_CNT]; - struct msm_cpp_buffer_info_t duplicate_buffer_info; - struct msm_cpp_buffer_info_t tnr_scratch_buffer_info[2]; - uint32_t reserved; - uint8_t partial_frame_indicator; - uint8_t first_payload; - uint8_t last_payload; - uint32_t first_stripe_index; - uint32_t last_stripe_index; - uint32_t stripe_info_offset; - uint32_t stripe_info; - struct msm_cpp_batch_info_t batch_info; -}; -struct msm_cpp_pop_stream_info_t { - int32_t frame_id; - uint32_t identity; -}; -struct cpp_hw_info { - uint32_t cpp_hw_version; - uint32_t cpp_hw_caps; - unsigned long freq_tbl[MAX_FREQ_TBL]; - uint32_t freq_tbl_count; -}; -struct msm_vpe_frame_strip_info { - uint32_t src_w; - uint32_t src_h; - uint32_t dst_w; - uint32_t dst_h; - uint32_t src_x; - uint32_t src_y; - uint32_t phase_step_x; - uint32_t phase_step_y; - uint32_t phase_init_x; - uint32_t phase_init_y; -}; -struct msm_vpe_buffer_info_t { - int32_t fd; - uint32_t index; - uint32_t offset; - uint8_t native_buff; - uint8_t processed_divert; -}; -struct msm_vpe_stream_buff_info_t { - uint32_t identity; - uint32_t num_buffs; - struct msm_vpe_buffer_info_t * buffer_info; -}; -struct msm_vpe_frame_info_t { - int32_t frame_id; - struct timeval timestamp; - uint32_t inst_id; - uint32_t identity; - uint32_t client_id; - enum msm_vpe_frame_type frame_type; - struct msm_vpe_frame_strip_info strip_info; - unsigned long src_fd; - unsigned long dst_fd; - struct ion_handle * src_ion_handle; - struct ion_handle * dest_ion_handle; - unsigned long src_phyaddr; - unsigned long dest_phyaddr; - unsigned long src_chroma_plane_offset; - unsigned long dest_chroma_plane_offset; - struct timeval in_time, out_time; - void * cookie; - struct msm_vpe_buffer_info_t input_buffer_info; - struct msm_vpe_buffer_info_t output_buffer_info; -}; -struct msm_pproc_queue_buf_info { - struct msm_buf_mngr_info buff_mgr_info; - uint8_t is_buf_dirty; -}; -struct msm_cpp_clock_settings_t { - unsigned long clock_rate; - uint64_t avg; - uint64_t inst; -}; -#define VIDIOC_MSM_CPP_CFG _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_GET_INST_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_LOAD_FIRMWARE _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_GET_HW_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_FLUSH_QUEUE _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_ENQUEUE_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_DEQUEUE_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_VPE_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_VPE_TRANSACTION_SETUP _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_VPE_GET_EVENTPAYLOAD _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_VPE_GET_INST_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_VPE_ENQUEUE_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_VPE_DEQUEUE_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_QUEUE_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_APPEND_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_SET_CLOCK _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_POP_STREAM_BUFFER _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_IOMMU_ATTACH _IOWR('V', BASE_VIDIOC_PRIVATE + 18, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_IOMMU_DETACH _IOWR('V', BASE_VIDIOC_PRIVATE + 19, struct msm_camera_v4l2_ioctl_t) -#define VIDIOC_MSM_CPP_DELETE_STREAM_BUFF _IOWR('V', BASE_VIDIOC_PRIVATE + 20, struct msm_camera_v4l2_ioctl_t) -#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0) -#define V4L2_EVENT_VPE_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 1) -struct msm_camera_v4l2_ioctl_t { - uint32_t id; - size_t len; - int32_t trans_code; - void * ioctl_ptr; -}; -#endif - diff --git a/sdm710/kernel-headers/scsi/ufs/ioctl.h b/sdm710/kernel-headers/scsi/ufs/ioctl.h deleted file mode 100644 index 524ca86a..00000000 --- a/sdm710/kernel-headers/scsi/ufs/ioctl.h +++ /dev/null @@ -1,30 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef UAPI_UFS_IOCTL_H_ -#define UAPI_UFS_IOCTL_H_ -#include <linux/types.h> -#define UFS_IOCTL_QUERY 0x5388 -struct ufs_ioctl_query_data { - __u32 opcode; - __u8 idn; - __u16 buf_size; - __u8 buffer[0]; -}; -#endif - diff --git a/sdm710/kernel-headers/scsi/ufs/ufs.h b/sdm710/kernel-headers/scsi/ufs/ufs.h deleted file mode 100644 index d15229d8..00000000 --- a/sdm710/kernel-headers/scsi/ufs/ufs.h +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef UAPI_UFS_H_ -#define UAPI_UFS_H_ -#define MAX_QUERY_IDN 0x18 -enum flag_idn { - QUERY_FLAG_IDN_FDEVICEINIT = 0x01, - QUERY_FLAG_IDN_PERMANENT_WPE = 0x02, - QUERY_FLAG_IDN_PWR_ON_WPE = 0x03, - QUERY_FLAG_IDN_BKOPS_EN = 0x04, - QUERY_FLAG_IDN_RESERVED1 = 0x05, - QUERY_FLAG_IDN_PURGE_ENABLE = 0x06, - QUERY_FLAG_IDN_RESERVED2 = 0x07, - QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08, - QUERY_FLAG_IDN_BUSY_RTC = 0x09, - QUERY_FLAG_IDN_MANUAL_GC_CONT = 0x0E, -}; -enum attr_idn { - QUERY_ATTR_IDN_BOOT_LU_EN = 0x00, - QUERY_ATTR_IDN_RESERVED = 0x01, - QUERY_ATTR_IDN_POWER_MODE = 0x02, - QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03, - QUERY_ATTR_IDN_OOO_DATA_EN = 0x04, - QUERY_ATTR_IDN_BKOPS_STATUS = 0x05, - QUERY_ATTR_IDN_PURGE_STATUS = 0x06, - QUERY_ATTR_IDN_MAX_DATA_IN = 0x07, - QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08, - QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09, - QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A, - QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B, - QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C, - QUERY_ATTR_IDN_EE_CONTROL = 0x0D, - QUERY_ATTR_IDN_EE_STATUS = 0x0E, - QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F, - QUERY_ATTR_IDN_CNTX_CONF = 0x10, - QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11, - QUERY_ATTR_IDN_MANUAL_GC_STATUS = 0x17, -}; -#define QUERY_ATTR_IDN_BOOT_LU_EN_MAX 0x02 -enum desc_idn { - QUERY_DESC_IDN_DEVICE = 0x0, - QUERY_DESC_IDN_CONFIGURAION = 0x1, - QUERY_DESC_IDN_UNIT = 0x2, - QUERY_DESC_IDN_RFU_0 = 0x3, - QUERY_DESC_IDN_INTERCONNECT = 0x4, - QUERY_DESC_IDN_STRING = 0x5, - QUERY_DESC_IDN_RFU_1 = 0x6, - QUERY_DESC_IDN_GEOMETRY = 0x7, - QUERY_DESC_IDN_POWER = 0x8, - QUERY_DESC_IDN_HEALTH = 0x9, - QUERY_DESC_IDN_RFU_2 = 0xA, - QUERY_DESC_IDN_MAX, -}; -enum query_opcode { - UPIU_QUERY_OPCODE_NOP = 0x0, - UPIU_QUERY_OPCODE_READ_DESC = 0x1, - UPIU_QUERY_OPCODE_WRITE_DESC = 0x2, - UPIU_QUERY_OPCODE_READ_ATTR = 0x3, - UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4, - UPIU_QUERY_OPCODE_READ_FLAG = 0x5, - UPIU_QUERY_OPCODE_SET_FLAG = 0x6, - UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7, - UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8, - UPIU_QUERY_OPCODE_MAX, -}; -#define UPIU_QUERY_OPCODE_HIGH_HPB 0x5500 -#define UPIU_QUERY_OPCODE_HIGH(opcode) ((opcode) >> 16) -#define UPIU_QUERY_OPCODE_LOW(opcode) ((opcode) & 0xffff) -#endif - diff --git a/sdm710/kernel-headers/sound/asound.h b/sdm710/kernel-headers/sound/asound.h deleted file mode 100644 index e25145d3..00000000 --- a/sdm710/kernel-headers/sound/asound.h +++ /dev/null @@ -1,830 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __SOUND_ASOUND_H -#define __SOUND_ASOUND_H -#ifdef __linux__ -#include <linux/types.h> -#else -#include <sys/ioctl.h> -#endif -#include <stdlib.h> -#include <time.h> -#define SNDRV_PROTOCOL_VERSION(major,minor,subminor) (((major) << 16) | ((minor) << 8) | (subminor)) -#define SNDRV_PROTOCOL_MAJOR(version) (((version) >> 16) & 0xffff) -#define SNDRV_PROTOCOL_MINOR(version) (((version) >> 8) & 0xff) -#define SNDRV_PROTOCOL_MICRO(version) ((version) & 0xff) -#define SNDRV_PROTOCOL_INCOMPATIBLE(kversion,uversion) (SNDRV_PROTOCOL_MAJOR(kversion) != SNDRV_PROTOCOL_MAJOR(uversion) || (SNDRV_PROTOCOL_MAJOR(kversion) == SNDRV_PROTOCOL_MAJOR(uversion) && SNDRV_PROTOCOL_MINOR(kversion) != SNDRV_PROTOCOL_MINOR(uversion))) -struct snd_aes_iec958 { - unsigned char status[24]; - unsigned char subcode[147]; - unsigned char pad; - unsigned char dig_subframe[4]; -}; -struct snd_cea_861_aud_if { - unsigned char db1_ct_cc; - unsigned char db2_sf_ss; - unsigned char db3; - unsigned char db4_ca; - unsigned char db5_dminh_lsv; -}; -#define SNDRV_HWDEP_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1) -enum { - SNDRV_HWDEP_IFACE_OPL2 = 0, - SNDRV_HWDEP_IFACE_OPL3, - SNDRV_HWDEP_IFACE_OPL4, - SNDRV_HWDEP_IFACE_SB16CSP, - SNDRV_HWDEP_IFACE_EMU10K1, - SNDRV_HWDEP_IFACE_YSS225, - SNDRV_HWDEP_IFACE_ICS2115, - SNDRV_HWDEP_IFACE_SSCAPE, - SNDRV_HWDEP_IFACE_VX, - SNDRV_HWDEP_IFACE_MIXART, - SNDRV_HWDEP_IFACE_USX2Y, - SNDRV_HWDEP_IFACE_EMUX_WAVETABLE, - SNDRV_HWDEP_IFACE_BLUETOOTH, - SNDRV_HWDEP_IFACE_USX2Y_PCM, - SNDRV_HWDEP_IFACE_PCXHR, - SNDRV_HWDEP_IFACE_SB_RC, - SNDRV_HWDEP_IFACE_HDA, - SNDRV_HWDEP_IFACE_USB_STREAM, - SNDRV_HWDEP_IFACE_FW_DICE, - SNDRV_HWDEP_IFACE_FW_FIREWORKS, - SNDRV_HWDEP_IFACE_FW_BEBOB, - SNDRV_HWDEP_IFACE_FW_OXFW, - SNDRV_HWDEP_IFACE_FW_DIGI00X, - SNDRV_HWDEP_IFACE_FW_TASCAM, - SNDRV_HWDEP_IFACE_LINE6, - SNDRV_HWDEP_IFACE_AUDIO_BE, - SNDRV_HWDEP_IFACE_AUDIO_CODEC, - SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_AUDIO_CODEC -}; -struct snd_hwdep_info { - unsigned int device; - int card; - unsigned char id[64]; - unsigned char name[80]; - int iface; - unsigned char reserved[64]; -}; -struct snd_hwdep_dsp_status { - unsigned int version; - unsigned char id[32]; - unsigned int num_dsps; - unsigned int dsp_loaded; - unsigned int chip_ready; - unsigned char reserved[16]; -}; -struct snd_hwdep_dsp_image { - unsigned int index; - unsigned char name[64]; - unsigned char * image; - size_t length; - unsigned long driver_data; -}; -#define SNDRV_HWDEP_IOCTL_PVERSION _IOR('H', 0x00, int) -#define SNDRV_HWDEP_IOCTL_INFO _IOR('H', 0x01, struct snd_hwdep_info) -#define SNDRV_HWDEP_IOCTL_DSP_STATUS _IOR('H', 0x02, struct snd_hwdep_dsp_status) -#define SNDRV_HWDEP_IOCTL_DSP_LOAD _IOW('H', 0x03, struct snd_hwdep_dsp_image) -#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 13) -typedef unsigned long snd_pcm_uframes_t; -typedef signed long snd_pcm_sframes_t; -enum { - SNDRV_PCM_CLASS_GENERIC = 0, - SNDRV_PCM_CLASS_MULTI, - SNDRV_PCM_CLASS_MODEM, - SNDRV_PCM_CLASS_DIGITIZER, - SNDRV_PCM_CLASS_LAST = SNDRV_PCM_CLASS_DIGITIZER, -}; -enum { - SNDRV_PCM_SUBCLASS_GENERIC_MIX = 0, - SNDRV_PCM_SUBCLASS_MULTI_MIX, - SNDRV_PCM_SUBCLASS_LAST = SNDRV_PCM_SUBCLASS_MULTI_MIX, -}; -enum { - SNDRV_PCM_STREAM_PLAYBACK = 0, - SNDRV_PCM_STREAM_CAPTURE, - SNDRV_PCM_STREAM_LAST = SNDRV_PCM_STREAM_CAPTURE, -}; -typedef int __bitwise snd_pcm_access_t; -#define SNDRV_PCM_ACCESS_MMAP_INTERLEAVED ((snd_pcm_access_t) 0) -#define SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED ((snd_pcm_access_t) 1) -#define SNDRV_PCM_ACCESS_MMAP_COMPLEX ((snd_pcm_access_t) 2) -#define SNDRV_PCM_ACCESS_RW_INTERLEAVED ((snd_pcm_access_t) 3) -#define SNDRV_PCM_ACCESS_RW_NONINTERLEAVED ((snd_pcm_access_t) 4) -#define SNDRV_PCM_ACCESS_LAST SNDRV_PCM_ACCESS_RW_NONINTERLEAVED -typedef int __bitwise snd_pcm_format_t; -#define SNDRV_PCM_FORMAT_S8 ((snd_pcm_format_t) 0) -#define SNDRV_PCM_FORMAT_U8 ((snd_pcm_format_t) 1) -#define SNDRV_PCM_FORMAT_S16_LE ((snd_pcm_format_t) 2) -#define SNDRV_PCM_FORMAT_S16_BE ((snd_pcm_format_t) 3) -#define SNDRV_PCM_FORMAT_U16_LE ((snd_pcm_format_t) 4) -#define SNDRV_PCM_FORMAT_U16_BE ((snd_pcm_format_t) 5) -#define SNDRV_PCM_FORMAT_S24_LE ((snd_pcm_format_t) 6) -#define SNDRV_PCM_FORMAT_S24_BE ((snd_pcm_format_t) 7) -#define SNDRV_PCM_FORMAT_U24_LE ((snd_pcm_format_t) 8) -#define SNDRV_PCM_FORMAT_U24_BE ((snd_pcm_format_t) 9) -#define SNDRV_PCM_FORMAT_S32_LE ((snd_pcm_format_t) 10) -#define SNDRV_PCM_FORMAT_S32_BE ((snd_pcm_format_t) 11) -#define SNDRV_PCM_FORMAT_U32_LE ((snd_pcm_format_t) 12) -#define SNDRV_PCM_FORMAT_U32_BE ((snd_pcm_format_t) 13) -#define SNDRV_PCM_FORMAT_FLOAT_LE ((snd_pcm_format_t) 14) -#define SNDRV_PCM_FORMAT_FLOAT_BE ((snd_pcm_format_t) 15) -#define SNDRV_PCM_FORMAT_FLOAT64_LE ((snd_pcm_format_t) 16) -#define SNDRV_PCM_FORMAT_FLOAT64_BE ((snd_pcm_format_t) 17) -#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE ((snd_pcm_format_t) 18) -#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE ((snd_pcm_format_t) 19) -#define SNDRV_PCM_FORMAT_MU_LAW ((snd_pcm_format_t) 20) -#define SNDRV_PCM_FORMAT_A_LAW ((snd_pcm_format_t) 21) -#define SNDRV_PCM_FORMAT_IMA_ADPCM ((snd_pcm_format_t) 22) -#define SNDRV_PCM_FORMAT_MPEG ((snd_pcm_format_t) 23) -#define SNDRV_PCM_FORMAT_GSM ((snd_pcm_format_t) 24) -#define SNDRV_PCM_FORMAT_SPECIAL ((snd_pcm_format_t) 31) -#define SNDRV_PCM_FORMAT_S24_3LE ((snd_pcm_format_t) 32) -#define SNDRV_PCM_FORMAT_S24_3BE ((snd_pcm_format_t) 33) -#define SNDRV_PCM_FORMAT_U24_3LE ((snd_pcm_format_t) 34) -#define SNDRV_PCM_FORMAT_U24_3BE ((snd_pcm_format_t) 35) -#define SNDRV_PCM_FORMAT_S20_3LE ((snd_pcm_format_t) 36) -#define SNDRV_PCM_FORMAT_S20_3BE ((snd_pcm_format_t) 37) -#define SNDRV_PCM_FORMAT_U20_3LE ((snd_pcm_format_t) 38) -#define SNDRV_PCM_FORMAT_U20_3BE ((snd_pcm_format_t) 39) -#define SNDRV_PCM_FORMAT_S18_3LE ((snd_pcm_format_t) 40) -#define SNDRV_PCM_FORMAT_S18_3BE ((snd_pcm_format_t) 41) -#define SNDRV_PCM_FORMAT_U18_3LE ((snd_pcm_format_t) 42) -#define SNDRV_PCM_FORMAT_U18_3BE ((snd_pcm_format_t) 43) -#define SNDRV_PCM_FORMAT_G723_24 ((snd_pcm_format_t) 44) -#define SNDRV_PCM_FORMAT_G723_24_1B ((snd_pcm_format_t) 45) -#define SNDRV_PCM_FORMAT_G723_40 ((snd_pcm_format_t) 46) -#define SNDRV_PCM_FORMAT_G723_40_1B ((snd_pcm_format_t) 47) -#define SNDRV_PCM_FORMAT_DSD_U8 ((snd_pcm_format_t) 48) -#define SNDRV_PCM_FORMAT_DSD_U16_LE ((snd_pcm_format_t) 49) -#define SNDRV_PCM_FORMAT_DSD_U32_LE ((snd_pcm_format_t) 50) -#define SNDRV_PCM_FORMAT_DSD_U16_BE ((snd_pcm_format_t) 51) -#define SNDRV_PCM_FORMAT_DSD_U32_BE ((snd_pcm_format_t) 52) -#define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_DSD_U32_BE -#ifdef SNDRV_LITTLE_ENDIAN -#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_LE -#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_LE -#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_LE -#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_LE -#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_LE -#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_LE -#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE -#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE -#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE -#endif -#ifdef SNDRV_BIG_ENDIAN -#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE -#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_BE -#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_BE -#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_BE -#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_BE -#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_BE -#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE -#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE -#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE -#endif -typedef int __bitwise snd_pcm_subformat_t; -#define SNDRV_PCM_SUBFORMAT_STD ((snd_pcm_subformat_t) 0) -#define SNDRV_PCM_SUBFORMAT_LAST SNDRV_PCM_SUBFORMAT_STD -#define SNDRV_PCM_INFO_MMAP 0x00000001 -#define SNDRV_PCM_INFO_MMAP_VALID 0x00000002 -#define SNDRV_PCM_INFO_DOUBLE 0x00000004 -#define SNDRV_PCM_INFO_BATCH 0x00000010 -#define SNDRV_PCM_INFO_INTERLEAVED 0x00000100 -#define SNDRV_PCM_INFO_NONINTERLEAVED 0x00000200 -#define SNDRV_PCM_INFO_COMPLEX 0x00000400 -#define SNDRV_PCM_INFO_BLOCK_TRANSFER 0x00010000 -#define SNDRV_PCM_INFO_OVERRANGE 0x00020000 -#define SNDRV_PCM_INFO_RESUME 0x00040000 -#define SNDRV_PCM_INFO_PAUSE 0x00080000 -#define SNDRV_PCM_INFO_HALF_DUPLEX 0x00100000 -#define SNDRV_PCM_INFO_JOINT_DUPLEX 0x00200000 -#define SNDRV_PCM_INFO_SYNC_START 0x00400000 -#define SNDRV_PCM_INFO_NO_PERIOD_WAKEUP 0x00800000 -#define SNDRV_PCM_INFO_HAS_WALL_CLOCK 0x01000000 -#define SNDRV_PCM_INFO_HAS_LINK_ATIME 0x01000000 -#define SNDRV_PCM_INFO_HAS_LINK_ABSOLUTE_ATIME 0x02000000 -#define SNDRV_PCM_INFO_HAS_LINK_ESTIMATED_ATIME 0x04000000 -#define SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 0x08000000 -#define SNDRV_PCM_INFO_DRAIN_TRIGGER 0x40000000 -#define SNDRV_PCM_INFO_FIFO_IN_FRAMES 0x80000000 -typedef int __bitwise snd_pcm_state_t; -#define SNDRV_PCM_STATE_OPEN ((snd_pcm_state_t) 0) -#define SNDRV_PCM_STATE_SETUP ((snd_pcm_state_t) 1) -#define SNDRV_PCM_STATE_PREPARED ((snd_pcm_state_t) 2) -#define SNDRV_PCM_STATE_RUNNING ((snd_pcm_state_t) 3) -#define SNDRV_PCM_STATE_XRUN ((snd_pcm_state_t) 4) -#define SNDRV_PCM_STATE_DRAINING ((snd_pcm_state_t) 5) -#define SNDRV_PCM_STATE_PAUSED ((snd_pcm_state_t) 6) -#define SNDRV_PCM_STATE_SUSPENDED ((snd_pcm_state_t) 7) -#define SNDRV_PCM_STATE_DISCONNECTED ((snd_pcm_state_t) 8) -#define SNDRV_PCM_STATE_LAST SNDRV_PCM_STATE_DISCONNECTED -enum { - SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000, - SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000, - SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000, -}; -union snd_pcm_sync_id { - unsigned char id[16]; - unsigned short id16[8]; - unsigned int id32[4]; -}; -struct snd_pcm_info { - unsigned int device; - unsigned int subdevice; - int stream; - int card; - unsigned char id[64]; - unsigned char name[80]; - unsigned char subname[32]; - int dev_class; - int dev_subclass; - unsigned int subdevices_count; - unsigned int subdevices_avail; - union snd_pcm_sync_id sync; - unsigned char reserved[64]; -}; -typedef int snd_pcm_hw_param_t; -#define SNDRV_PCM_HW_PARAM_ACCESS 0 -#define SNDRV_PCM_HW_PARAM_FORMAT 1 -#define SNDRV_PCM_HW_PARAM_SUBFORMAT 2 -#define SNDRV_PCM_HW_PARAM_FIRST_MASK SNDRV_PCM_HW_PARAM_ACCESS -#define SNDRV_PCM_HW_PARAM_LAST_MASK SNDRV_PCM_HW_PARAM_SUBFORMAT -#define SNDRV_PCM_HW_PARAM_SAMPLE_BITS 8 -#define SNDRV_PCM_HW_PARAM_FRAME_BITS 9 -#define SNDRV_PCM_HW_PARAM_CHANNELS 10 -#define SNDRV_PCM_HW_PARAM_RATE 11 -#define SNDRV_PCM_HW_PARAM_PERIOD_TIME 12 -#define SNDRV_PCM_HW_PARAM_PERIOD_SIZE 13 -#define SNDRV_PCM_HW_PARAM_PERIOD_BYTES 14 -#define SNDRV_PCM_HW_PARAM_PERIODS 15 -#define SNDRV_PCM_HW_PARAM_BUFFER_TIME 16 -#define SNDRV_PCM_HW_PARAM_BUFFER_SIZE 17 -#define SNDRV_PCM_HW_PARAM_BUFFER_BYTES 18 -#define SNDRV_PCM_HW_PARAM_TICK_TIME 19 -#define SNDRV_PCM_HW_PARAM_FIRST_INTERVAL SNDRV_PCM_HW_PARAM_SAMPLE_BITS -#define SNDRV_PCM_HW_PARAM_LAST_INTERVAL SNDRV_PCM_HW_PARAM_TICK_TIME -#define SNDRV_PCM_HW_PARAMS_NORESAMPLE (1 << 0) -#define SNDRV_PCM_HW_PARAMS_EXPORT_BUFFER (1 << 1) -#define SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP (1 << 2) -struct snd_interval { - unsigned int min, max; - unsigned int openmin : 1, openmax : 1, integer : 1, empty : 1; -}; -#define SNDRV_MASK_MAX 256 -struct snd_mask { - __u32 bits[(SNDRV_MASK_MAX + 31) / 32]; -}; -struct snd_pcm_hw_params { - unsigned int flags; - struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK - SNDRV_PCM_HW_PARAM_FIRST_MASK + 1]; - struct snd_mask mres[5]; - struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL - SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1]; - struct snd_interval ires[9]; - unsigned int rmask; - unsigned int cmask; - unsigned int info; - unsigned int msbits; - unsigned int rate_num; - unsigned int rate_den; - snd_pcm_uframes_t fifo_size; - unsigned char reserved[64]; -}; -enum { - SNDRV_PCM_TSTAMP_NONE = 0, - SNDRV_PCM_TSTAMP_ENABLE, - SNDRV_PCM_TSTAMP_LAST = SNDRV_PCM_TSTAMP_ENABLE, -}; -struct snd_pcm_sw_params { - int tstamp_mode; - unsigned int period_step; - unsigned int sleep_min; - snd_pcm_uframes_t avail_min; - snd_pcm_uframes_t xfer_align; - snd_pcm_uframes_t start_threshold; - snd_pcm_uframes_t stop_threshold; - snd_pcm_uframes_t silence_threshold; - snd_pcm_uframes_t silence_size; - snd_pcm_uframes_t boundary; - unsigned int proto; - unsigned int tstamp_type; - unsigned char reserved[56]; -}; -struct snd_pcm_channel_info { - unsigned int channel; - __kernel_off_t offset; - unsigned int first; - unsigned int step; -}; -enum { - SNDRV_PCM_AUDIO_TSTAMP_TYPE_COMPAT = 0, - SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT = 1, - SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK = 2, - SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ABSOLUTE = 3, - SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ESTIMATED = 4, - SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED = 5, - SNDRV_PCM_AUDIO_TSTAMP_TYPE_LAST = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED -}; -struct snd_pcm_status { - snd_pcm_state_t state; - struct timespec trigger_tstamp; - struct timespec tstamp; - snd_pcm_uframes_t appl_ptr; - snd_pcm_uframes_t hw_ptr; - snd_pcm_sframes_t delay; - snd_pcm_uframes_t avail; - snd_pcm_uframes_t avail_max; - snd_pcm_uframes_t overrange; - snd_pcm_state_t suspended_state; - __u32 audio_tstamp_data; - struct timespec audio_tstamp; - struct timespec driver_tstamp; - __u32 audio_tstamp_accuracy; - unsigned char reserved[52 - 2 * sizeof(struct timespec)]; -}; -struct snd_pcm_mmap_status { - snd_pcm_state_t state; - int pad1; - snd_pcm_uframes_t hw_ptr; - struct timespec tstamp; - snd_pcm_state_t suspended_state; - struct timespec audio_tstamp; -}; -struct snd_pcm_mmap_control { - snd_pcm_uframes_t appl_ptr; - snd_pcm_uframes_t avail_min; -}; -#define SNDRV_PCM_SYNC_PTR_HWSYNC (1 << 0) -#define SNDRV_PCM_SYNC_PTR_APPL (1 << 1) -#define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1 << 2) -struct snd_pcm_sync_ptr { - unsigned int flags; - union { - struct snd_pcm_mmap_status status; - unsigned char reserved[64]; - } s; - union { - struct snd_pcm_mmap_control control; - unsigned char reserved[64]; - } c; -}; -struct snd_xferi { - snd_pcm_sframes_t result; - void * buf; - snd_pcm_uframes_t frames; -}; -struct snd_xfern { - snd_pcm_sframes_t result; - void * * bufs; - snd_pcm_uframes_t frames; -}; -enum { - SNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0, - SNDRV_PCM_TSTAMP_TYPE_MONOTONIC, - SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW, - SNDRV_PCM_TSTAMP_TYPE_LAST = SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW, -}; -enum { - SNDRV_CHMAP_UNKNOWN = 0, - SNDRV_CHMAP_NA, - SNDRV_CHMAP_MONO, - SNDRV_CHMAP_FL, - SNDRV_CHMAP_FR, - SNDRV_CHMAP_RL, - SNDRV_CHMAP_RR, - SNDRV_CHMAP_FC, - SNDRV_CHMAP_LFE, - SNDRV_CHMAP_SL, - SNDRV_CHMAP_SR, - SNDRV_CHMAP_RC, - SNDRV_CHMAP_FLC, - SNDRV_CHMAP_FRC, - SNDRV_CHMAP_RLC, - SNDRV_CHMAP_RRC, - SNDRV_CHMAP_FLW, - SNDRV_CHMAP_FRW, - SNDRV_CHMAP_FLH, - SNDRV_CHMAP_FCH, - SNDRV_CHMAP_FRH, - SNDRV_CHMAP_TC, - SNDRV_CHMAP_TFL, - SNDRV_CHMAP_TFR, - SNDRV_CHMAP_TFC, - SNDRV_CHMAP_TRL, - SNDRV_CHMAP_TRR, - SNDRV_CHMAP_TRC, - SNDRV_CHMAP_TFLC, - SNDRV_CHMAP_TFRC, - SNDRV_CHMAP_TSL, - SNDRV_CHMAP_TSR, - SNDRV_CHMAP_LLFE, - SNDRV_CHMAP_RLFE, - SNDRV_CHMAP_BC, - SNDRV_CHMAP_BLC, - SNDRV_CHMAP_BRC, - SNDRV_CHMAP_LAST = SNDRV_CHMAP_BRC, -}; -#define SNDRV_CHMAP_POSITION_MASK 0xffff -#define SNDRV_CHMAP_PHASE_INVERSE (0x01 << 16) -#define SNDRV_CHMAP_DRIVER_SPEC (0x02 << 16) -#define SNDRV_PCM_IOCTL_PVERSION _IOR('A', 0x00, int) -#define SNDRV_PCM_IOCTL_INFO _IOR('A', 0x01, struct snd_pcm_info) -#define SNDRV_PCM_IOCTL_TSTAMP _IOW('A', 0x02, int) -#define SNDRV_PCM_IOCTL_TTSTAMP _IOW('A', 0x03, int) -#define SNDRV_PCM_IOCTL_HW_REFINE _IOWR('A', 0x10, struct snd_pcm_hw_params) -#define SNDRV_PCM_IOCTL_HW_PARAMS _IOWR('A', 0x11, struct snd_pcm_hw_params) -#define SNDRV_PCM_IOCTL_HW_FREE _IO('A', 0x12) -#define SNDRV_PCM_IOCTL_SW_PARAMS _IOWR('A', 0x13, struct snd_pcm_sw_params) -#define SNDRV_PCM_IOCTL_STATUS _IOR('A', 0x20, struct snd_pcm_status) -#define SNDRV_PCM_IOCTL_DELAY _IOR('A', 0x21, snd_pcm_sframes_t) -#define SNDRV_PCM_IOCTL_HWSYNC _IO('A', 0x22) -#define SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct snd_pcm_sync_ptr) -#define SNDRV_PCM_IOCTL_STATUS_EXT _IOWR('A', 0x24, struct snd_pcm_status) -#define SNDRV_PCM_IOCTL_CHANNEL_INFO _IOR('A', 0x32, struct snd_pcm_channel_info) -#define SNDRV_PCM_IOCTL_PREPARE _IO('A', 0x40) -#define SNDRV_PCM_IOCTL_RESET _IO('A', 0x41) -#define SNDRV_PCM_IOCTL_START _IO('A', 0x42) -#define SNDRV_PCM_IOCTL_DROP _IO('A', 0x43) -#define SNDRV_PCM_IOCTL_DRAIN _IO('A', 0x44) -#define SNDRV_PCM_IOCTL_PAUSE _IOW('A', 0x45, int) -#define SNDRV_PCM_IOCTL_REWIND _IOW('A', 0x46, snd_pcm_uframes_t) -#define SNDRV_PCM_IOCTL_RESUME _IO('A', 0x47) -#define SNDRV_PCM_IOCTL_XRUN _IO('A', 0x48) -#define SNDRV_PCM_IOCTL_FORWARD _IOW('A', 0x49, snd_pcm_uframes_t) -#define SNDRV_PCM_IOCTL_WRITEI_FRAMES _IOW('A', 0x50, struct snd_xferi) -#define SNDRV_PCM_IOCTL_READI_FRAMES _IOR('A', 0x51, struct snd_xferi) -#define SNDRV_PCM_IOCTL_WRITEN_FRAMES _IOW('A', 0x52, struct snd_xfern) -#define SNDRV_PCM_IOCTL_READN_FRAMES _IOR('A', 0x53, struct snd_xfern) -#define SNDRV_PCM_IOCTL_LINK _IOW('A', 0x60, int) -#define SNDRV_PCM_IOCTL_UNLINK _IO('A', 0x61) -#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0) -enum { - SNDRV_RAWMIDI_STREAM_OUTPUT = 0, - SNDRV_RAWMIDI_STREAM_INPUT, - SNDRV_RAWMIDI_STREAM_LAST = SNDRV_RAWMIDI_STREAM_INPUT, -}; -#define SNDRV_RAWMIDI_INFO_OUTPUT 0x00000001 -#define SNDRV_RAWMIDI_INFO_INPUT 0x00000002 -#define SNDRV_RAWMIDI_INFO_DUPLEX 0x00000004 -struct snd_rawmidi_info { - unsigned int device; - unsigned int subdevice; - int stream; - int card; - unsigned int flags; - unsigned char id[64]; - unsigned char name[80]; - unsigned char subname[32]; - unsigned int subdevices_count; - unsigned int subdevices_avail; - unsigned char reserved[64]; -}; -struct snd_rawmidi_params { - int stream; - size_t buffer_size; - size_t avail_min; - unsigned int no_active_sensing : 1; - unsigned char reserved[16]; -}; -struct snd_rawmidi_status { - int stream; - struct timespec tstamp; - size_t avail; - size_t xruns; - unsigned char reserved[16]; -}; -#define SNDRV_RAWMIDI_IOCTL_PVERSION _IOR('W', 0x00, int) -#define SNDRV_RAWMIDI_IOCTL_INFO _IOR('W', 0x01, struct snd_rawmidi_info) -#define SNDRV_RAWMIDI_IOCTL_PARAMS _IOWR('W', 0x10, struct snd_rawmidi_params) -#define SNDRV_RAWMIDI_IOCTL_STATUS _IOWR('W', 0x20, struct snd_rawmidi_status) -#define SNDRV_RAWMIDI_IOCTL_DROP _IOW('W', 0x30, int) -#define SNDRV_RAWMIDI_IOCTL_DRAIN _IOW('W', 0x31, int) -#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 6) -enum { - SNDRV_TIMER_CLASS_NONE = - 1, - SNDRV_TIMER_CLASS_SLAVE = 0, - SNDRV_TIMER_CLASS_GLOBAL, - SNDRV_TIMER_CLASS_CARD, - SNDRV_TIMER_CLASS_PCM, - SNDRV_TIMER_CLASS_LAST = SNDRV_TIMER_CLASS_PCM, -}; -enum { - SNDRV_TIMER_SCLASS_NONE = 0, - SNDRV_TIMER_SCLASS_APPLICATION, - SNDRV_TIMER_SCLASS_SEQUENCER, - SNDRV_TIMER_SCLASS_OSS_SEQUENCER, - SNDRV_TIMER_SCLASS_LAST = SNDRV_TIMER_SCLASS_OSS_SEQUENCER, -}; -#define SNDRV_TIMER_GLOBAL_SYSTEM 0 -#define SNDRV_TIMER_GLOBAL_RTC 1 -#define SNDRV_TIMER_GLOBAL_HPET 2 -#define SNDRV_TIMER_GLOBAL_HRTIMER 3 -#define SNDRV_TIMER_FLG_SLAVE (1 << 0) -struct snd_timer_id { - int dev_class; - int dev_sclass; - int card; - int device; - int subdevice; -}; -struct snd_timer_ginfo { - struct snd_timer_id tid; - unsigned int flags; - int card; - unsigned char id[64]; - unsigned char name[80]; - unsigned long reserved0; - unsigned long resolution; - unsigned long resolution_min; - unsigned long resolution_max; - unsigned int clients; - unsigned char reserved[32]; -}; -struct snd_timer_gparams { - struct snd_timer_id tid; - unsigned long period_num; - unsigned long period_den; - unsigned char reserved[32]; -}; -struct snd_timer_gstatus { - struct snd_timer_id tid; - unsigned long resolution; - unsigned long resolution_num; - unsigned long resolution_den; - unsigned char reserved[32]; -}; -struct snd_timer_select { - struct snd_timer_id id; - unsigned char reserved[32]; -}; -struct snd_timer_info { - unsigned int flags; - int card; - unsigned char id[64]; - unsigned char name[80]; - unsigned long reserved0; - unsigned long resolution; - unsigned char reserved[64]; -}; -#define SNDRV_TIMER_PSFLG_AUTO (1 << 0) -#define SNDRV_TIMER_PSFLG_EXCLUSIVE (1 << 1) -#define SNDRV_TIMER_PSFLG_EARLY_EVENT (1 << 2) -struct snd_timer_params { - unsigned int flags; - unsigned int ticks; - unsigned int queue_size; - unsigned int reserved0; - unsigned int filter; - unsigned char reserved[60]; -}; -struct snd_timer_status { - struct timespec tstamp; - unsigned int resolution; - unsigned int lost; - unsigned int overrun; - unsigned int queue; - unsigned char reserved[64]; -}; -#define SNDRV_TIMER_IOCTL_PVERSION _IOR('T', 0x00, int) -#define SNDRV_TIMER_IOCTL_NEXT_DEVICE _IOWR('T', 0x01, struct snd_timer_id) -#define SNDRV_TIMER_IOCTL_TREAD _IOW('T', 0x02, int) -#define SNDRV_TIMER_IOCTL_GINFO _IOWR('T', 0x03, struct snd_timer_ginfo) -#define SNDRV_TIMER_IOCTL_GPARAMS _IOW('T', 0x04, struct snd_timer_gparams) -#define SNDRV_TIMER_IOCTL_GSTATUS _IOWR('T', 0x05, struct snd_timer_gstatus) -#define SNDRV_TIMER_IOCTL_SELECT _IOW('T', 0x10, struct snd_timer_select) -#define SNDRV_TIMER_IOCTL_INFO _IOR('T', 0x11, struct snd_timer_info) -#define SNDRV_TIMER_IOCTL_PARAMS _IOW('T', 0x12, struct snd_timer_params) -#define SNDRV_TIMER_IOCTL_STATUS _IOR('T', 0x14, struct snd_timer_status) -#define SNDRV_TIMER_IOCTL_START _IO('T', 0xa0) -#define SNDRV_TIMER_IOCTL_STOP _IO('T', 0xa1) -#define SNDRV_TIMER_IOCTL_CONTINUE _IO('T', 0xa2) -#define SNDRV_TIMER_IOCTL_PAUSE _IO('T', 0xa3) -struct snd_timer_read { - unsigned int resolution; - unsigned int ticks; -}; -enum { - SNDRV_TIMER_EVENT_RESOLUTION = 0, - SNDRV_TIMER_EVENT_TICK, - SNDRV_TIMER_EVENT_START, - SNDRV_TIMER_EVENT_STOP, - SNDRV_TIMER_EVENT_CONTINUE, - SNDRV_TIMER_EVENT_PAUSE, - SNDRV_TIMER_EVENT_EARLY, - SNDRV_TIMER_EVENT_SUSPEND, - SNDRV_TIMER_EVENT_RESUME, - SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10, - SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10, - SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10, - SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10, - SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10, - SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10, -}; -struct snd_timer_tread { - int event; - struct timespec tstamp; - unsigned int val; -}; -#define SNDRV_CTL_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 7) -struct snd_ctl_card_info { - int card; - int pad; - unsigned char id[16]; - unsigned char driver[16]; - unsigned char name[32]; - unsigned char longname[80]; - unsigned char reserved_[16]; - unsigned char mixername[80]; - unsigned char components[128]; -}; -typedef int __bitwise snd_ctl_elem_type_t; -#define SNDRV_CTL_ELEM_TYPE_NONE ((snd_ctl_elem_type_t) 0) -#define SNDRV_CTL_ELEM_TYPE_BOOLEAN ((snd_ctl_elem_type_t) 1) -#define SNDRV_CTL_ELEM_TYPE_INTEGER ((snd_ctl_elem_type_t) 2) -#define SNDRV_CTL_ELEM_TYPE_ENUMERATED ((snd_ctl_elem_type_t) 3) -#define SNDRV_CTL_ELEM_TYPE_BYTES ((snd_ctl_elem_type_t) 4) -#define SNDRV_CTL_ELEM_TYPE_IEC958 ((snd_ctl_elem_type_t) 5) -#define SNDRV_CTL_ELEM_TYPE_INTEGER64 ((snd_ctl_elem_type_t) 6) -#define SNDRV_CTL_ELEM_TYPE_LAST SNDRV_CTL_ELEM_TYPE_INTEGER64 -typedef int __bitwise snd_ctl_elem_iface_t; -#define SNDRV_CTL_ELEM_IFACE_CARD ((snd_ctl_elem_iface_t) 0) -#define SNDRV_CTL_ELEM_IFACE_HWDEP ((snd_ctl_elem_iface_t) 1) -#define SNDRV_CTL_ELEM_IFACE_MIXER ((snd_ctl_elem_iface_t) 2) -#define SNDRV_CTL_ELEM_IFACE_PCM ((snd_ctl_elem_iface_t) 3) -#define SNDRV_CTL_ELEM_IFACE_RAWMIDI ((snd_ctl_elem_iface_t) 4) -#define SNDRV_CTL_ELEM_IFACE_TIMER ((snd_ctl_elem_iface_t) 5) -#define SNDRV_CTL_ELEM_IFACE_SEQUENCER ((snd_ctl_elem_iface_t) 6) -#define SNDRV_CTL_ELEM_IFACE_LAST SNDRV_CTL_ELEM_IFACE_SEQUENCER -#define SNDRV_CTL_ELEM_ACCESS_READ (1 << 0) -#define SNDRV_CTL_ELEM_ACCESS_WRITE (1 << 1) -#define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE) -#define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1 << 2) -#define SNDRV_CTL_ELEM_ACCESS_TIMESTAMP (1 << 3) -#define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1 << 4) -#define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1 << 5) -#define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_TLV_WRITE) -#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1 << 6) -#define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1 << 8) -#define SNDRV_CTL_ELEM_ACCESS_LOCK (1 << 9) -#define SNDRV_CTL_ELEM_ACCESS_OWNER (1 << 10) -#define SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK (1 << 28) -#define SNDRV_CTL_ELEM_ACCESS_USER (1 << 29) -#define SNDRV_CTL_POWER_D0 0x0000 -#define SNDRV_CTL_POWER_D1 0x0100 -#define SNDRV_CTL_POWER_D2 0x0200 -#define SNDRV_CTL_POWER_D3 0x0300 -#define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3 | 0x0000) -#define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3 | 0x0001) -#define SNDRV_CTL_ELEM_ID_NAME_MAXLEN 44 -struct snd_ctl_elem_id { - unsigned int numid; - snd_ctl_elem_iface_t iface; - unsigned int device; - unsigned int subdevice; - unsigned char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; - unsigned int index; -}; -struct snd_ctl_elem_list { - unsigned int offset; - unsigned int space; - unsigned int used; - unsigned int count; - struct snd_ctl_elem_id * pids; - unsigned char reserved[50]; -}; -struct snd_ctl_elem_info { - struct snd_ctl_elem_id id; - snd_ctl_elem_type_t type; - unsigned int access; - unsigned int count; - __kernel_pid_t owner; - union { - struct { - long min; - long max; - long step; - } integer; - struct { - long long min; - long long max; - long long step; - } integer64; - struct { - unsigned int items; - unsigned int item; - char name[64]; - __u64 names_ptr; - unsigned int names_length; - } enumerated; - unsigned char reserved[128]; - } value; - union { - unsigned short d[4]; - unsigned short * d_ptr; - } dimen; - unsigned char reserved[64 - 4 * sizeof(unsigned short)]; -}; -struct snd_ctl_elem_value { - struct snd_ctl_elem_id id; - unsigned int indirect : 1; - union { - union { - long value[128]; - long * value_ptr; - } integer; - union { - long long value[64]; - long long * value_ptr; - } integer64; - union { - unsigned int item[128]; - unsigned int * item_ptr; - } enumerated; - union { - unsigned char data[512]; - unsigned char * data_ptr; - } bytes; - struct snd_aes_iec958 iec958; - } value; - struct timespec tstamp; - unsigned char reserved[128 - sizeof(struct timespec)]; -}; -struct snd_ctl_tlv { - unsigned int numid; - unsigned int length; - unsigned int tlv[0]; -}; -#define SNDRV_CTL_IOCTL_PVERSION _IOR('U', 0x00, int) -#define SNDRV_CTL_IOCTL_CARD_INFO _IOR('U', 0x01, struct snd_ctl_card_info) -#define SNDRV_CTL_IOCTL_ELEM_LIST _IOWR('U', 0x10, struct snd_ctl_elem_list) -#define SNDRV_CTL_IOCTL_ELEM_INFO _IOWR('U', 0x11, struct snd_ctl_elem_info) -#define SNDRV_CTL_IOCTL_ELEM_READ _IOWR('U', 0x12, struct snd_ctl_elem_value) -#define SNDRV_CTL_IOCTL_ELEM_WRITE _IOWR('U', 0x13, struct snd_ctl_elem_value) -#define SNDRV_CTL_IOCTL_ELEM_LOCK _IOW('U', 0x14, struct snd_ctl_elem_id) -#define SNDRV_CTL_IOCTL_ELEM_UNLOCK _IOW('U', 0x15, struct snd_ctl_elem_id) -#define SNDRV_CTL_IOCTL_SUBSCRIBE_EVENTS _IOWR('U', 0x16, int) -#define SNDRV_CTL_IOCTL_ELEM_ADD _IOWR('U', 0x17, struct snd_ctl_elem_info) -#define SNDRV_CTL_IOCTL_ELEM_REPLACE _IOWR('U', 0x18, struct snd_ctl_elem_info) -#define SNDRV_CTL_IOCTL_ELEM_REMOVE _IOWR('U', 0x19, struct snd_ctl_elem_id) -#define SNDRV_CTL_IOCTL_TLV_READ _IOWR('U', 0x1a, struct snd_ctl_tlv) -#define SNDRV_CTL_IOCTL_TLV_WRITE _IOWR('U', 0x1b, struct snd_ctl_tlv) -#define SNDRV_CTL_IOCTL_TLV_COMMAND _IOWR('U', 0x1c, struct snd_ctl_tlv) -#define SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE _IOWR('U', 0x20, int) -#define SNDRV_CTL_IOCTL_HWDEP_INFO _IOR('U', 0x21, struct snd_hwdep_info) -#define SNDRV_CTL_IOCTL_PCM_NEXT_DEVICE _IOR('U', 0x30, int) -#define SNDRV_CTL_IOCTL_PCM_INFO _IOWR('U', 0x31, struct snd_pcm_info) -#define SNDRV_CTL_IOCTL_PCM_PREFER_SUBDEVICE _IOW('U', 0x32, int) -#define SNDRV_CTL_IOCTL_RAWMIDI_NEXT_DEVICE _IOWR('U', 0x40, int) -#define SNDRV_CTL_IOCTL_RAWMIDI_INFO _IOWR('U', 0x41, struct snd_rawmidi_info) -#define SNDRV_CTL_IOCTL_RAWMIDI_PREFER_SUBDEVICE _IOW('U', 0x42, int) -#define SNDRV_CTL_IOCTL_POWER _IOWR('U', 0xd0, int) -#define SNDRV_CTL_IOCTL_POWER_STATE _IOR('U', 0xd1, int) -enum sndrv_ctl_event_type { - SNDRV_CTL_EVENT_ELEM = 0, - SNDRV_CTL_EVENT_LAST = SNDRV_CTL_EVENT_ELEM, -}; -#define SNDRV_CTL_EVENT_MASK_VALUE (1 << 0) -#define SNDRV_CTL_EVENT_MASK_INFO (1 << 1) -#define SNDRV_CTL_EVENT_MASK_ADD (1 << 2) -#define SNDRV_CTL_EVENT_MASK_TLV (1 << 3) -#define SNDRV_CTL_EVENT_MASK_REMOVE (~0U) -struct snd_ctl_event { - int type; - union { - struct { - unsigned int mask; - struct snd_ctl_elem_id id; - } elem; - unsigned char data8[60]; - } data; -}; -#define SNDRV_CTL_NAME_NONE "" -#define SNDRV_CTL_NAME_PLAYBACK "Playback " -#define SNDRV_CTL_NAME_CAPTURE "Capture " -#define SNDRV_CTL_NAME_IEC958_NONE "" -#define SNDRV_CTL_NAME_IEC958_SWITCH "Switch" -#define SNDRV_CTL_NAME_IEC958_VOLUME "Volume" -#define SNDRV_CTL_NAME_IEC958_DEFAULT "Default" -#define SNDRV_CTL_NAME_IEC958_MASK "Mask" -#define SNDRV_CTL_NAME_IEC958_CON_MASK "Con Mask" -#define SNDRV_CTL_NAME_IEC958_PRO_MASK "Pro Mask" -#define SNDRV_CTL_NAME_IEC958_PCM_STREAM "PCM Stream" -#define SNDRV_CTL_NAME_IEC958(expl,direction,what) "IEC958 " expl SNDRV_CTL_NAME_ ##direction SNDRV_CTL_NAME_IEC958_ ##what -#endif - diff --git a/sdm710/kernel-headers/sound/audio_effects.h b/sdm710/kernel-headers/sound/audio_effects.h deleted file mode 100644 index 0ac887cd..00000000 --- a/sdm710/kernel-headers/sound/audio_effects.h +++ /dev/null @@ -1,361 +0,0 @@ -#ifndef _AUDIO_EFFECTS_H -#define _AUDIO_EFFECTS_H - -/** AUDIO EFFECTS **/ - - -/* CONFIG GET/SET */ -#define CONFIG_CACHE 0 -#define CONFIG_SET 1 -#define CONFIG_GET 2 - -/* CONFIG HEADER */ -/* - * MODULE_ID, - * DEVICE, - * NUM_COMMANDS, - * COMMAND_ID_1, - * CONFIG_CACHE/SET/GET, - * OFFSET_1, - * LENGTH_1, - * VALUES_1, - * ..., - * ..., - * COMMAND_ID_2, - * CONFIG_CACHE/SET/GET, - * OFFSET_2, - * LENGTH_2, - * VALUES_2, - * ..., - * ..., - * COMMAND_ID_3, - * ... - */ - - -/* CONFIG PARAM IDs */ -#define VIRTUALIZER_MODULE 0x00001000 -#define VIRTUALIZER_ENABLE 0x00001001 -#define VIRTUALIZER_STRENGTH 0x00001002 -#define VIRTUALIZER_OUT_TYPE 0x00001003 -#define VIRTUALIZER_GAIN_ADJUST 0x00001004 -#define VIRTUALIZER_ENABLE_PARAM_LEN 1 -#define VIRTUALIZER_STRENGTH_PARAM_LEN 1 -#define VIRTUALIZER_OUT_TYPE_PARAM_LEN 1 -#define VIRTUALIZER_GAIN_ADJUST_PARAM_LEN 1 - -#define REVERB_MODULE 0x00002000 -#define REVERB_ENABLE 0x00002001 -#define REVERB_MODE 0x00002002 -#define REVERB_PRESET 0x00002003 -#define REVERB_WET_MIX 0x00002004 -#define REVERB_GAIN_ADJUST 0x00002005 -#define REVERB_ROOM_LEVEL 0x00002006 -#define REVERB_ROOM_HF_LEVEL 0x00002007 -#define REVERB_DECAY_TIME 0x00002008 -#define REVERB_DECAY_HF_RATIO 0x00002009 -#define REVERB_REFLECTIONS_LEVEL 0x0000200a -#define REVERB_REFLECTIONS_DELAY 0x0000200b -#define REVERB_LEVEL 0x0000200c -#define REVERB_DELAY 0x0000200d -#define REVERB_DIFFUSION 0x0000200e -#define REVERB_DENSITY 0x0000200f -#define REVERB_ENABLE_PARAM_LEN 1 -#define REVERB_MODE_PARAM_LEN 1 -#define REVERB_PRESET_PARAM_LEN 1 -#define REVERB_WET_MIX_PARAM_LEN 1 -#define REVERB_GAIN_ADJUST_PARAM_LEN 1 -#define REVERB_ROOM_LEVEL_PARAM_LEN 1 -#define REVERB_ROOM_HF_LEVEL_PARAM_LEN 1 -#define REVERB_DECAY_TIME_PARAM_LEN 1 -#define REVERB_DECAY_HF_RATIO_PARAM_LEN 1 -#define REVERB_REFLECTIONS_LEVEL_PARAM_LEN 1 -#define REVERB_REFLECTIONS_DELAY_PARAM_LEN 1 -#define REVERB_LEVEL_PARAM_LEN 1 -#define REVERB_DELAY_PARAM_LEN 1 -#define REVERB_DIFFUSION_PARAM_LEN 1 -#define REVERB_DENSITY_PARAM_LEN 1 - -#define BASS_BOOST_MODULE 0x00003000 -#define BASS_BOOST_ENABLE 0x00003001 -#define BASS_BOOST_MODE 0x00003002 -#define BASS_BOOST_STRENGTH 0x00003003 -#define BASS_BOOST_ENABLE_PARAM_LEN 1 -#define BASS_BOOST_MODE_PARAM_LEN 1 -#define BASS_BOOST_STRENGTH_PARAM_LEN 1 - -#define EQ_MODULE 0x00004000 -#define EQ_ENABLE 0x00004001 -#define EQ_CONFIG 0x00004002 -#define EQ_NUM_BANDS 0x00004003 -#define EQ_BAND_LEVELS 0x00004004 -#define EQ_BAND_LEVEL_RANGE 0x00004005 -#define EQ_BAND_FREQS 0x00004006 -#define EQ_SINGLE_BAND_FREQ_RANGE 0x00004007 -#define EQ_SINGLE_BAND_FREQ 0x00004008 -#define EQ_BAND_INDEX 0x00004009 -#define EQ_PRESET_ID 0x0000400a -#define EQ_NUM_PRESETS 0x0000400b -#define EQ_PRESET_NAME 0x0000400c -#define EQ_ENABLE_PARAM_LEN 1 -#define EQ_CONFIG_PARAM_LEN 3 -#define EQ_CONFIG_PER_BAND_PARAM_LEN 5 -#define EQ_NUM_BANDS_PARAM_LEN 1 -#define EQ_BAND_LEVELS_PARAM_LEN 13 -#define EQ_BAND_LEVEL_RANGE_PARAM_LEN 2 -#define EQ_BAND_FREQS_PARAM_LEN 13 -#define EQ_SINGLE_BAND_FREQ_RANGE_PARAM_LEN 2 -#define EQ_SINGLE_BAND_FREQ_PARAM_LEN 1 -#define EQ_BAND_INDEX_PARAM_LEN 1 -#define EQ_PRESET_ID_PARAM_LEN 1 -#define EQ_NUM_PRESETS_PARAM_LEN 1 -#define EQ_PRESET_NAME_PARAM_LEN 32 - -#define EQ_TYPE_NONE 0 -#define EQ_BASS_BOOST 1 -#define EQ_BASS_CUT 2 -#define EQ_TREBLE_BOOST 3 -#define EQ_TREBLE_CUT 4 -#define EQ_BAND_BOOST 5 -#define EQ_BAND_CUT 6 - -#define SOFT_VOLUME_MODULE 0x00006000 -#define SOFT_VOLUME_ENABLE 0x00006001 -#define SOFT_VOLUME_GAIN_2CH 0x00006002 -#define SOFT_VOLUME_GAIN_MASTER 0x00006003 -#define SOFT_VOLUME_ENABLE_PARAM_LEN 1 -#define SOFT_VOLUME_GAIN_2CH_PARAM_LEN 2 -#define SOFT_VOLUME_GAIN_MASTER_PARAM_LEN 1 - -#define SOFT_VOLUME2_MODULE 0x00007000 -#define SOFT_VOLUME2_ENABLE 0x00007001 -#define SOFT_VOLUME2_GAIN_2CH 0x00007002 -#define SOFT_VOLUME2_GAIN_MASTER 0x00007003 -#define SOFT_VOLUME2_ENABLE_PARAM_LEN SOFT_VOLUME_ENABLE_PARAM_LEN -#define SOFT_VOLUME2_GAIN_2CH_PARAM_LEN SOFT_VOLUME_GAIN_2CH_PARAM_LEN -#define SOFT_VOLUME2_GAIN_MASTER_PARAM_LEN \ - SOFT_VOLUME_GAIN_MASTER_PARAM_LEN - -#define PBE_CONF_MODULE_ID 0x00010C2A -#define PBE_CONF_PARAM_ID 0x00010C49 - -#define PBE_MODULE 0x00008000 -#define PBE_ENABLE 0x00008001 -#define PBE_CONFIG 0x00008002 -#define PBE_ENABLE_PARAM_LEN 1 -#define PBE_CONFIG_PARAM_LEN 28 - -#define COMMAND_PAYLOAD_LEN 3 -#define COMMAND_PAYLOAD_SZ (COMMAND_PAYLOAD_LEN * sizeof(uint32_t)) -#define MAX_INBAND_PARAM_SZ 4096 -#define Q27_UNITY (1 << 27) -#define Q8_UNITY (1 << 8) -#define CUSTOM_OPENSL_PRESET 18 - -#define VIRTUALIZER_ENABLE_PARAM_SZ \ - (VIRTUALIZER_ENABLE_PARAM_LEN*sizeof(uint32_t)) -#define VIRTUALIZER_STRENGTH_PARAM_SZ \ - (VIRTUALIZER_STRENGTH_PARAM_LEN*sizeof(uint32_t)) -#define VIRTUALIZER_OUT_TYPE_PARAM_SZ \ - (VIRTUALIZER_OUT_TYPE_PARAM_LEN*sizeof(uint32_t)) -#define VIRTUALIZER_GAIN_ADJUST_PARAM_SZ \ - (VIRTUALIZER_GAIN_ADJUST_PARAM_LEN*sizeof(uint32_t)) -struct virtualizer_params { - uint32_t device; - uint32_t enable_flag; - uint32_t strength; - uint32_t out_type; - int32_t gain_adjust; -}; - -#define NUM_OSL_REVERB_PRESETS_SUPPORTED 6 -#define REVERB_ENABLE_PARAM_SZ \ - (REVERB_ENABLE_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_MODE_PARAM_SZ \ - (REVERB_MODE_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_PRESET_PARAM_SZ \ - (REVERB_PRESET_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_WET_MIX_PARAM_SZ \ - (REVERB_WET_MIX_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_GAIN_ADJUST_PARAM_SZ \ - (REVERB_GAIN_ADJUST_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_ROOM_LEVEL_PARAM_SZ \ - (REVERB_ROOM_LEVEL_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_ROOM_HF_LEVEL_PARAM_SZ \ - (REVERB_ROOM_HF_LEVEL_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_DECAY_TIME_PARAM_SZ \ - (REVERB_DECAY_TIME_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_DECAY_HF_RATIO_PARAM_SZ \ - (REVERB_DECAY_HF_RATIO_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_REFLECTIONS_LEVEL_PARAM_SZ \ - (REVERB_REFLECTIONS_LEVEL_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_REFLECTIONS_DELAY_PARAM_SZ \ - (REVERB_REFLECTIONS_DELAY_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_LEVEL_PARAM_SZ \ - (REVERB_LEVEL_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_DELAY_PARAM_SZ \ - (REVERB_DELAY_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_DIFFUSION_PARAM_SZ \ - (REVERB_DIFFUSION_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_DENSITY_PARAM_SZ \ - (REVERB_DENSITY_PARAM_LEN*sizeof(uint32_t)) -struct reverb_params { - uint32_t device; - uint32_t enable_flag; - uint32_t mode; - uint32_t preset; - uint32_t wet_mix; - int32_t gain_adjust; - int32_t room_level; - int32_t room_hf_level; - uint32_t decay_time; - uint32_t decay_hf_ratio; - int32_t reflections_level; - uint32_t reflections_delay; - int32_t level; - uint32_t delay; - uint32_t diffusion; - uint32_t density; -}; - -#define BASS_BOOST_ENABLE_PARAM_SZ \ - (BASS_BOOST_ENABLE_PARAM_LEN*sizeof(uint32_t)) -#define BASS_BOOST_MODE_PARAM_SZ \ - (BASS_BOOST_MODE_PARAM_LEN*sizeof(uint32_t)) -#define BASS_BOOST_STRENGTH_PARAM_SZ \ - (BASS_BOOST_STRENGTH_PARAM_LEN*sizeof(uint32_t)) -struct bass_boost_params { - uint32_t device; - uint32_t enable_flag; - uint32_t mode; - uint32_t strength; -}; - - -#define MAX_EQ_BANDS 12 -#define MAX_OSL_EQ_BANDS 5 -#define EQ_ENABLE_PARAM_SZ \ - (EQ_ENABLE_PARAM_LEN*sizeof(uint32_t)) -#define EQ_CONFIG_PARAM_SZ \ - (EQ_CONFIG_PARAM_LEN*sizeof(uint32_t)) -#define EQ_CONFIG_PER_BAND_PARAM_SZ \ - (EQ_CONFIG_PER_BAND_PARAM_LEN*sizeof(uint32_t)) -#define EQ_CONFIG_PARAM_MAX_LEN (EQ_CONFIG_PARAM_LEN+\ - MAX_EQ_BANDS*EQ_CONFIG_PER_BAND_PARAM_LEN) -#define EQ_CONFIG_PARAM_MAX_SZ \ - (EQ_CONFIG_PARAM_MAX_LEN*sizeof(uint32_t)) -#define EQ_NUM_BANDS_PARAM_SZ \ - (EQ_NUM_BANDS_PARAM_LEN*sizeof(uint32_t)) -#define EQ_BAND_LEVELS_PARAM_SZ \ - (EQ_BAND_LEVELS_PARAM_LEN*sizeof(uint32_t)) -#define EQ_BAND_LEVEL_RANGE_PARAM_SZ \ - (EQ_BAND_LEVEL_RANGE_PARAM_LEN*sizeof(uint32_t)) -#define EQ_BAND_FREQS_PARAM_SZ \ - (EQ_BAND_FREQS_PARAM_LEN*sizeof(uint32_t)) -#define EQ_SINGLE_BAND_FREQ_RANGE_PARAM_SZ \ - (EQ_SINGLE_BAND_FREQ_RANGE_PARAM_LEN*sizeof(uint32_t)) -#define EQ_SINGLE_BAND_FREQ_PARAM_SZ \ - (EQ_SINGLE_BAND_FREQ_PARAM_LEN*sizeof(uint32_t)) -#define EQ_BAND_INDEX_PARAM_SZ \ - (EQ_BAND_INDEX_PARAM_LEN*sizeof(uint32_t)) -#define EQ_PRESET_ID_PARAM_SZ \ - (EQ_PRESET_ID_PARAM_LEN*sizeof(uint32_t)) -#define EQ_NUM_PRESETS_PARAM_SZ \ - (EQ_NUM_PRESETS_PARAM_LEN*sizeof(uint8_t)) -struct eq_config_t { - int32_t eq_pregain; - int32_t preset_id; - uint32_t num_bands; -}; -struct eq_per_band_config_t { - int32_t band_idx; - uint32_t filter_type; - uint32_t freq_millihertz; - int32_t gain_millibels; - uint32_t quality_factor; -}; -struct eq_per_band_freq_range_t { - uint32_t band_index; - uint32_t min_freq_millihertz; - uint32_t max_freq_millihertz; -}; - -struct eq_params { - uint32_t device; - uint32_t enable_flag; - struct eq_config_t config; - struct eq_per_band_config_t per_band_cfg[MAX_EQ_BANDS]; - struct eq_per_band_freq_range_t per_band_freq_range[MAX_EQ_BANDS]; - uint32_t band_index; - uint32_t freq_millihertz; -}; - -#define PBE_ENABLE_PARAM_SZ \ - (PBE_ENABLE_PARAM_LEN*sizeof(uint32_t)) -#define PBE_CONFIG_PARAM_SZ \ - (PBE_CONFIG_PARAM_LEN*sizeof(uint16_t)) -struct pbe_config_t { - int16_t real_bass_mix; - int16_t bass_color_control; - uint16_t main_chain_delay; - uint16_t xover_filter_order; - uint16_t bandpass_filter_order; - int16_t drc_delay; - uint16_t rms_tav; - int16_t exp_threshold; - uint16_t exp_slope; - int16_t comp_threshold; - uint16_t comp_slope; - uint16_t makeup_gain; - uint32_t comp_attack; - uint32_t comp_release; - uint32_t exp_attack; - uint32_t exp_release; - int16_t limiter_bass_threshold; - int16_t limiter_high_threshold; - int16_t limiter_bass_makeup_gain; - int16_t limiter_high_makeup_gain; - int16_t limiter_bass_gc; - int16_t limiter_high_gc; - int16_t limiter_delay; - uint16_t reserved; - /* place holder for filter coeffs to be followed */ - int32_t p1LowPassCoeffs[5*2]; - int32_t p1HighPassCoeffs[5*2]; - int32_t p1BandPassCoeffs[5*3]; - int32_t p1BassShelfCoeffs[5]; - int32_t p1TrebleShelfCoeffs[5]; -} __attribute__((packed)); - -struct pbe_params { - uint32_t device; - uint32_t enable_flag; - uint32_t cfg_len; - struct pbe_config_t config; -}; - -#define SOFT_VOLUME_ENABLE_PARAM_SZ \ - (SOFT_VOLUME_ENABLE_PARAM_LEN*sizeof(uint32_t)) -#define SOFT_VOLUME_GAIN_MASTER_PARAM_SZ \ - (SOFT_VOLUME_GAIN_MASTER_PARAM_LEN*sizeof(uint32_t)) -#define SOFT_VOLUME_GAIN_2CH_PARAM_SZ \ - (SOFT_VOLUME_GAIN_2CH_PARAM_LEN*sizeof(uint16_t)) -struct soft_volume_params { - uint32_t device; - uint32_t enable_flag; - uint32_t master_gain; - uint32_t left_gain; - uint32_t right_gain; -}; - -struct msm_nt_eff_all_config { - struct bass_boost_params bass_boost; - struct pbe_params pbe; - struct virtualizer_params virtualizer; - struct reverb_params reverb; - struct eq_params equalizer; - struct soft_volume_params saplus_vol; - struct soft_volume_params topo_switch_vol; -}; - -#endif /*_MSM_AUDIO_EFFECTS_H*/ diff --git a/sdm710/kernel-headers/sound/audio_slimslave.h b/sdm710/kernel-headers/sound/audio_slimslave.h deleted file mode 100644 index 316a5573..00000000 --- a/sdm710/kernel-headers/sound/audio_slimslave.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __AUDIO_SLIMSLAVE_H__ -#define __AUDIO_SLIMSLAVE_H__ - -#include <linux/types.h> -#include <linux/ioctl.h> - -#define AUDIO_SLIMSLAVE_IOCTL_NAME "audio_slimslave" -#define AUDIO_SLIMSLAVE_MAGIC 'S' - -#define AUDIO_SLIMSLAVE_IOCTL_UNVOTE _IO(AUDIO_SLIMSLAVE_MAGIC, 0x00) -#define AUDIO_SLIMSLAVE_IOCTL_VOTE _IO(AUDIO_SLIMSLAVE_MAGIC, 0x01) - -enum { - AUDIO_SLIMSLAVE_UNVOTE, - AUDIO_SLIMSLAVE_VOTE -}; - -#endif diff --git a/sdm710/kernel-headers/sound/compress_offload.h b/sdm710/kernel-headers/sound/compress_offload.h deleted file mode 100644 index dd78a2d5..00000000 --- a/sdm710/kernel-headers/sound/compress_offload.h +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __COMPRESS_OFFLOAD_H -#define __COMPRESS_OFFLOAD_H -#include <linux/types.h> -#include <sound/asound.h> -#include <sound/compress_params.h> -#define SNDRV_COMPRESS_VERSION SNDRV_PROTOCOL_VERSION(0, 1, 2) -struct snd_compressed_buffer { - __u32 fragment_size; - __u32 fragments; -} __attribute__((packed, aligned(4))); -struct snd_compr_params { - struct snd_compressed_buffer buffer; - struct snd_codec codec; - __u8 no_wake_mode; -} __attribute__((packed, aligned(4))); -struct snd_compr_tstamp { - __u32 byte_offset; - __u64 copied_total; - __u32 pcm_frames; - __u32 pcm_io_frames; - __u32 sampling_rate; - __u64 timestamp; -} __attribute__((packed, aligned(4))); -struct snd_compr_avail { - __u64 avail; - struct snd_compr_tstamp tstamp; -} __attribute__((packed, aligned(4))); -enum snd_compr_direction { - SND_COMPRESS_PLAYBACK = 0, - SND_COMPRESS_CAPTURE -}; -struct snd_compr_caps { - __u32 num_codecs; - __u32 direction; - __u32 min_fragment_size; - __u32 max_fragment_size; - __u32 min_fragments; - __u32 max_fragments; - __u32 codecs[MAX_NUM_CODECS]; - __u32 reserved[11]; -} __attribute__((packed, aligned(4))); -struct snd_compr_codec_caps { - __u32 codec; - __u32 num_descriptors; - struct snd_codec_desc descriptor[MAX_NUM_CODEC_DESCRIPTORS]; -} __attribute__((packed, aligned(4))); -struct snd_compr_audio_info { - __u32 frame_size; - __u32 reserved[15]; -} __attribute__((packed, aligned(4))); -#define SNDRV_COMPRESS_RENDER_MODE_AUDIO_MASTER 0 -#define SNDRV_COMPRESS_RENDER_MODE_STC_MASTER 1 -#define SNDRV_COMPRESS_CLK_REC_MODE_NONE 0 -#define SNDRV_COMPRESS_CLK_REC_MODE_AUTO 1 -enum sndrv_compress_encoder { - SNDRV_COMPRESS_ENCODER_PADDING = 1, - SNDRV_COMPRESS_ENCODER_DELAY = 2, - SNDRV_COMPRESS_MIN_BLK_SIZE = 3, - SNDRV_COMPRESS_MAX_BLK_SIZE = 4, - SNDRV_COMPRESS_PATH_DELAY = 5, - SNDRV_COMPRESS_RENDER_MODE = 6, - SNDRV_COMPRESS_CLK_REC_MODE = 7, - SNDRV_COMPRESS_RENDER_WINDOW = 8, - SNDRV_COMPRESS_START_DELAY = 9, - SNDRV_COMPRESS_ENABLE_ADJUST_SESSION_CLOCK = 10, - SNDRV_COMPRESS_ADJUST_SESSION_CLOCK = 11, -}; -#define SNDRV_COMPRESS_PATH_DELAY SNDRV_COMPRESS_PATH_DELAY -#define SNDRV_COMPRESS_RENDER_MODE SNDRV_COMPRESS_RENDER_MODE -#define SNDRV_COMPRESS_CLK_REC_MODE SNDRV_COMPRESS_CLK_REC_MODE -#define SNDRV_COMPRESS_RENDER_WINDOW SNDRV_COMPRESS_RENDER_WINDOW -#define SNDRV_COMPRESS_START_DELAY SNDRV_COMPRESS_START_DELAY -#define SNDRV_COMPRESS_ENABLE_ADJUST_SESSION_CLOCK SNDRV_COMPRESS_ENABLE_ADJUST_SESSION_CLOCK -#define SNDRV_COMPRESS_ADJUST_SESSION_CLOCK SNDRV_COMPRESS_ADJUST_SESSION_CLOCK -struct snd_compr_metadata { - __u32 key; - __u32 value[8]; -} __attribute__((packed, aligned(4))); -#define SNDRV_COMPRESS_IOCTL_VERSION _IOR('C', 0x00, int) -#define SNDRV_COMPRESS_GET_CAPS _IOWR('C', 0x10, struct snd_compr_caps) -#define SNDRV_COMPRESS_GET_CODEC_CAPS _IOWR('C', 0x11, struct snd_compr_codec_caps) -#define SNDRV_COMPRESS_SET_PARAMS _IOW('C', 0x12, struct snd_compr_params) -#define SNDRV_COMPRESS_GET_PARAMS _IOR('C', 0x13, struct snd_codec) -#define SNDRV_COMPRESS_SET_METADATA _IOW('C', 0x14, struct snd_compr_metadata) -#define SNDRV_COMPRESS_GET_METADATA _IOWR('C', 0x15, struct snd_compr_metadata) -#define SNDRV_COMPRESS_TSTAMP _IOR('C', 0x20, struct snd_compr_tstamp) -#define SNDRV_COMPRESS_AVAIL _IOR('C', 0x21, struct snd_compr_avail) -#define SNDRV_COMPRESS_PAUSE _IO('C', 0x30) -#define SNDRV_COMPRESS_RESUME _IO('C', 0x31) -#define SNDRV_COMPRESS_START _IO('C', 0x32) -#define SNDRV_COMPRESS_STOP _IO('C', 0x33) -#define SNDRV_COMPRESS_DRAIN _IO('C', 0x34) -#define SNDRV_COMPRESS_NEXT_TRACK _IO('C', 0x35) -#define SNDRV_COMPRESS_PARTIAL_DRAIN _IO('C', 0x36) -#define SNDRV_COMPRESS_SET_NEXT_TRACK_PARAM _IOW('C', 0x80, union snd_codec_options) -#define SND_COMPR_TRIGGER_DRAIN 7 -#define SND_COMPR_TRIGGER_NEXT_TRACK 8 -#define SND_COMPR_TRIGGER_PARTIAL_DRAIN 9 -#endif - diff --git a/sdm710/kernel-headers/sound/compress_params.h b/sdm710/kernel-headers/sound/compress_params.h deleted file mode 100644 index 1172f26b..00000000 --- a/sdm710/kernel-headers/sound/compress_params.h +++ /dev/null @@ -1,296 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __SND_COMPRESS_PARAMS_H -#define __SND_COMPRESS_PARAMS_H -#include <linux/types.h> -#define SND_DEC_DDP_MAX_PARAMS 18 -#define MAX_NUM_CODECS 32 -#define MAX_NUM_CODEC_DESCRIPTORS 32 -#define MAX_NUM_BITRATES 32 -#define MAX_NUM_SAMPLE_RATES 32 -#define MAX_NUM_FRAMES_PER_BUFFER 1 -#define COMPRESSED_META_DATA_MODE 0x10 -#define META_DATA_LEN_BYTES 36 -#define Q6_AC3_DECODER 0x00010BF6 -#define Q6_EAC3_DECODER 0x00010C3C -#define Q6_DTS 0x00010D88 -#define Q6_DTS_LBR 0x00010DBB -#define COMPRESSED_TIMESTAMP_FLAG 0x0001 -#define SND_AUDIOCODEC_PCM ((__u32) 0x00000001) -#define SND_AUDIOCODEC_MP3 ((__u32) 0x00000002) -#define SND_AUDIOCODEC_AMR ((__u32) 0x00000003) -#define SND_AUDIOCODEC_AMRWB ((__u32) 0x00000004) -#define SND_AUDIOCODEC_AMRWBPLUS ((__u32) 0x00000005) -#define SND_AUDIOCODEC_AAC ((__u32) 0x00000006) -#define SND_AUDIOCODEC_WMA ((__u32) 0x00000007) -#define SND_AUDIOCODEC_REAL ((__u32) 0x00000008) -#define SND_AUDIOCODEC_VORBIS ((__u32) 0x00000009) -#define SND_AUDIOCODEC_FLAC ((__u32) 0x0000000A) -#define SND_AUDIOCODEC_IEC61937 ((__u32) 0x0000000B) -#define SND_AUDIOCODEC_G723_1 ((__u32) 0x0000000C) -#define SND_AUDIOCODEC_G729 ((__u32) 0x0000000D) -#define SND_AUDIOCODEC_BESPOKE ((__u32) 0x0000000E) -#define SND_AUDIOCODEC_DTS_PASS_THROUGH ((__u32) 0x0000000F) -#define SND_AUDIOCODEC_DTS_LBR ((__u32) 0x00000010) -#define SND_AUDIOCODEC_DTS_TRANSCODE_LOOPBACK ((__u32) 0x00000011) -#define SND_AUDIOCODEC_PASS_THROUGH ((__u32) 0x00000012) -#define SND_AUDIOCODEC_MP2 ((__u32) 0x00000013) -#define SND_AUDIOCODEC_DTS_LBR_PASS_THROUGH ((__u32) 0x00000014) -#define SND_AUDIOCODEC_AC3 ((__u32) 0x00000015) -#define SND_AUDIOCODEC_AC3_PASS_THROUGH ((__u32) 0x00000016) -#define SND_AUDIOCODEC_WMA_PRO ((__u32) 0x00000017) -#define SND_AUDIOCODEC_DTS ((__u32) 0x00000018) -#define SND_AUDIOCODEC_EAC3 ((__u32) 0x00000019) -#define SND_AUDIOCODEC_ALAC ((__u32) 0x00000020) -#define SND_AUDIOCODEC_APE ((__u32) 0x00000021) -#define SND_AUDIOCODEC_DSD ((__u32) 0x00000022) -#define SND_AUDIOCODEC_APTX ((__u32) 0x00000023) -#define SND_AUDIOCODEC_TRUEHD ((__u32) 0x00000024) -#define SND_AUDIOCODEC_MAX SND_AUDIOCODEC_TRUEHD -#define SND_AUDIOPROFILE_PCM ((__u32) 0x00000001) -#define SND_AUDIOCHANMODE_MP3_MONO ((__u32) 0x00000001) -#define SND_AUDIOCHANMODE_MP3_STEREO ((__u32) 0x00000002) -#define SND_AUDIOCHANMODE_MP3_JOINTSTEREO ((__u32) 0x00000004) -#define SND_AUDIOCHANMODE_MP3_DUAL ((__u32) 0x00000008) -#define SND_AUDIOPROFILE_AMR ((__u32) 0x00000001) -#define SND_AUDIOMODE_AMR_DTX_OFF ((__u32) 0x00000001) -#define SND_AUDIOMODE_AMR_VAD1 ((__u32) 0x00000002) -#define SND_AUDIOMODE_AMR_VAD2 ((__u32) 0x00000004) -#define SND_AUDIOSTREAMFORMAT_UNDEFINED ((__u32) 0x00000000) -#define SND_AUDIOSTREAMFORMAT_CONFORMANCE ((__u32) 0x00000001) -#define SND_AUDIOSTREAMFORMAT_IF1 ((__u32) 0x00000002) -#define SND_AUDIOSTREAMFORMAT_IF2 ((__u32) 0x00000004) -#define SND_AUDIOSTREAMFORMAT_FSF ((__u32) 0x00000008) -#define SND_AUDIOSTREAMFORMAT_RTPPAYLOAD ((__u32) 0x00000010) -#define SND_AUDIOSTREAMFORMAT_ITU ((__u32) 0x00000020) -#define SND_AUDIOPROFILE_AMRWB ((__u32) 0x00000001) -#define SND_AUDIOMODE_AMRWB_DTX_OFF ((__u32) 0x00000001) -#define SND_AUDIOMODE_AMRWB_VAD1 ((__u32) 0x00000002) -#define SND_AUDIOMODE_AMRWB_VAD2 ((__u32) 0x00000004) -#define SND_AUDIOPROFILE_AMRWBPLUS ((__u32) 0x00000001) -#define SND_AUDIOPROFILE_AAC ((__u32) 0x00000001) -#define SND_AUDIOMODE_AAC_MAIN ((__u32) 0x00000001) -#define SND_AUDIOMODE_AAC_LC ((__u32) 0x00000002) -#define SND_AUDIOMODE_AAC_SSR ((__u32) 0x00000004) -#define SND_AUDIOMODE_AAC_LTP ((__u32) 0x00000008) -#define SND_AUDIOMODE_AAC_HE ((__u32) 0x00000010) -#define SND_AUDIOMODE_AAC_SCALABLE ((__u32) 0x00000020) -#define SND_AUDIOMODE_AAC_ERLC ((__u32) 0x00000040) -#define SND_AUDIOMODE_AAC_LD ((__u32) 0x00000080) -#define SND_AUDIOMODE_AAC_HE_PS ((__u32) 0x00000100) -#define SND_AUDIOMODE_AAC_HE_MPS ((__u32) 0x00000200) -#define SND_AUDIOSTREAMFORMAT_MP2ADTS ((__u32) 0x00000001) -#define SND_AUDIOSTREAMFORMAT_MP4ADTS ((__u32) 0x00000002) -#define SND_AUDIOSTREAMFORMAT_MP4LOAS ((__u32) 0x00000004) -#define SND_AUDIOSTREAMFORMAT_MP4LATM ((__u32) 0x00000008) -#define SND_AUDIOSTREAMFORMAT_ADIF ((__u32) 0x00000010) -#define SND_AUDIOSTREAMFORMAT_MP4FF ((__u32) 0x00000020) -#define SND_AUDIOSTREAMFORMAT_RAW ((__u32) 0x00000040) -#define SND_AUDIOPROFILE_WMA7 ((__u32) 0x00000001) -#define SND_AUDIOPROFILE_WMA8 ((__u32) 0x00000002) -#define SND_AUDIOPROFILE_WMA9 ((__u32) 0x00000004) -#define SND_AUDIOPROFILE_WMA10 ((__u32) 0x00000008) -#define SND_AUDIOMODE_WMA_LEVEL1 ((__u32) 0x00000001) -#define SND_AUDIOMODE_WMA_LEVEL2 ((__u32) 0x00000002) -#define SND_AUDIOMODE_WMA_LEVEL3 ((__u32) 0x00000004) -#define SND_AUDIOMODE_WMA_LEVEL4 ((__u32) 0x00000008) -#define SND_AUDIOMODE_WMAPRO_LEVELM0 ((__u32) 0x00000010) -#define SND_AUDIOMODE_WMAPRO_LEVELM1 ((__u32) 0x00000020) -#define SND_AUDIOMODE_WMAPRO_LEVELM2 ((__u32) 0x00000040) -#define SND_AUDIOMODE_WMAPRO_LEVELM3 ((__u32) 0x00000080) -#define SND_AUDIOSTREAMFORMAT_WMA_ASF ((__u32) 0x00000001) -#define SND_AUDIOSTREAMFORMAT_WMA_NOASF_HDR ((__u32) 0x00000002) -#define SND_AUDIOPROFILE_REALAUDIO ((__u32) 0x00000001) -#define SND_AUDIOMODE_REALAUDIO_G2 ((__u32) 0x00000001) -#define SND_AUDIOMODE_REALAUDIO_8 ((__u32) 0x00000002) -#define SND_AUDIOMODE_REALAUDIO_10 ((__u32) 0x00000004) -#define SND_AUDIOMODE_REALAUDIO_SURROUND ((__u32) 0x00000008) -#define SND_AUDIOPROFILE_VORBIS ((__u32) 0x00000001) -#define SND_AUDIOMODE_VORBIS ((__u32) 0x00000001) -#define SND_AUDIOPROFILE_FLAC ((__u32) 0x00000001) -#define SND_AUDIOMODE_FLAC_LEVEL0 ((__u32) 0x00000001) -#define SND_AUDIOMODE_FLAC_LEVEL1 ((__u32) 0x00000002) -#define SND_AUDIOMODE_FLAC_LEVEL2 ((__u32) 0x00000004) -#define SND_AUDIOMODE_FLAC_LEVEL3 ((__u32) 0x00000008) -#define SND_AUDIOMODE_FLAC_LEVEL4 ((__u32) 0x00000010) -#define SND_AUDIOMODE_FLAC_LEVEL5 ((__u32) 0x00000020) -#define SND_AUDIOMODE_FLAC_LEVEL6 ((__u32) 0x00000040) -#define SND_AUDIOMODE_FLAC_LEVEL7 ((__u32) 0x00000080) -#define SND_AUDIOMODE_FLAC_LEVEL8 ((__u32) 0x00000100) -#define SND_AUDIOSTREAMFORMAT_FLAC ((__u32) 0x00000001) -#define SND_AUDIOSTREAMFORMAT_FLAC_OGG ((__u32) 0x00000002) -#define SND_AUDIOPROFILE_IEC61937 ((__u32) 0x00000001) -#define SND_AUDIOPROFILE_IEC61937_SPDIF ((__u32) 0x00000002) -#define SND_AUDIOMODE_IEC_REF_STREAM_HEADER ((__u32) 0x00000000) -#define SND_AUDIOMODE_IEC_LPCM ((__u32) 0x00000001) -#define SND_AUDIOMODE_IEC_AC3 ((__u32) 0x00000002) -#define SND_AUDIOMODE_IEC_MPEG1 ((__u32) 0x00000004) -#define SND_AUDIOMODE_IEC_MP3 ((__u32) 0x00000008) -#define SND_AUDIOMODE_IEC_MPEG2 ((__u32) 0x00000010) -#define SND_AUDIOMODE_IEC_AACLC ((__u32) 0x00000020) -#define SND_AUDIOMODE_IEC_DTS ((__u32) 0x00000040) -#define SND_AUDIOMODE_IEC_ATRAC ((__u32) 0x00000080) -#define SND_AUDIOMODE_IEC_SACD ((__u32) 0x00000100) -#define SND_AUDIOMODE_IEC_EAC3 ((__u32) 0x00000200) -#define SND_AUDIOMODE_IEC_DTS_HD ((__u32) 0x00000400) -#define SND_AUDIOMODE_IEC_MLP ((__u32) 0x00000800) -#define SND_AUDIOMODE_IEC_DST ((__u32) 0x00001000) -#define SND_AUDIOMODE_IEC_WMAPRO ((__u32) 0x00002000) -#define SND_AUDIOMODE_IEC_REF_CXT ((__u32) 0x00004000) -#define SND_AUDIOMODE_IEC_HE_AAC ((__u32) 0x00008000) -#define SND_AUDIOMODE_IEC_HE_AAC2 ((__u32) 0x00010000) -#define SND_AUDIOMODE_IEC_MPEG_SURROUND ((__u32) 0x00020000) -#define SND_AUDIOPROFILE_G723_1 ((__u32) 0x00000001) -#define SND_AUDIOMODE_G723_1_ANNEX_A ((__u32) 0x00000001) -#define SND_AUDIOMODE_G723_1_ANNEX_B ((__u32) 0x00000002) -#define SND_AUDIOMODE_G723_1_ANNEX_C ((__u32) 0x00000004) -#define SND_AUDIOPROFILE_G729 ((__u32) 0x00000001) -#define SND_AUDIOMODE_G729_ANNEX_A ((__u32) 0x00000001) -#define SND_AUDIOMODE_G729_ANNEX_B ((__u32) 0x00000002) -#define SND_RATECONTROLMODE_CONSTANTBITRATE ((__u32) 0x00000001) -#define SND_RATECONTROLMODE_VARIABLEBITRATE ((__u32) 0x00000002) -struct snd_enc_wma { - __u32 super_block_align; - __u32 bits_per_sample; - __u32 channelmask; - __u32 encodeopt; - __u32 encodeopt1; - __u32 encodeopt2; - __u32 avg_bit_rate; -}; -struct snd_enc_vorbis { - __s32 quality; - __u32 managed; - __u32 max_bit_rate; - __u32 min_bit_rate; - __u32 downmix; -} __attribute__((packed, aligned(4))); -struct snd_enc_real { - __u32 quant_bits; - __u32 start_region; - __u32 num_regions; -} __attribute__((packed, aligned(4))); -struct snd_enc_flac { - __u32 num; - __u32 gain; -} __attribute__((packed, aligned(4))); -struct snd_enc_generic { - __u32 bw; - __s32 reserved[15]; -} __attribute__((packed, aligned(4))); -struct snd_dec_ddp { - __u32 params_length; - __u32 params_id[SND_DEC_DDP_MAX_PARAMS]; - __u32 params_value[SND_DEC_DDP_MAX_PARAMS]; -} __attribute__((packed, aligned(4))); -struct snd_dec_flac { - __u16 sample_size; - __u16 min_blk_size; - __u16 max_blk_size; - __u16 min_frame_size; - __u16 max_frame_size; -} __attribute__((packed, aligned(4))); -struct snd_dec_vorbis { - __u32 bit_stream_fmt; -}; -struct snd_dec_alac { - __u32 frame_length; - __u8 compatible_version; - __u8 bit_depth; - __u8 pb; - __u8 mb; - __u8 kb; - __u8 num_channels; - __u16 max_run; - __u32 max_frame_bytes; - __u32 avg_bit_rate; - __u32 sample_rate; - __u32 channel_layout_tag; -}; -struct snd_dec_ape { - __u16 compatible_version; - __u16 compression_level; - __u32 format_flags; - __u32 blocks_per_frame; - __u32 final_frame_blocks; - __u32 total_frames; - __u16 bits_per_sample; - __u16 num_channels; - __u32 sample_rate; - __u32 seek_table_present; -}; -struct snd_dec_aptx { - __u32 lap; - __u32 uap; - __u32 nap; -}; -struct snd_dec_amrwb_plus { - __u32 bit_stream_fmt; -}; -union snd_codec_options { - struct snd_enc_wma wma; - struct snd_enc_vorbis vorbis; - struct snd_enc_real real; - struct snd_enc_flac flac; - struct snd_enc_generic generic; - struct snd_dec_ddp ddp; - struct snd_dec_flac flac_dec; - struct snd_dec_vorbis vorbis_dec; - struct snd_dec_alac alac; - struct snd_dec_ape ape; - struct snd_dec_aptx aptx_dec; - struct snd_dec_amrwb_plus amrwbplus; -}; -struct snd_codec_desc { - __u32 max_ch; - __u32 sample_rates[MAX_NUM_SAMPLE_RATES]; - __u32 num_sample_rates; - __u32 bit_rate[MAX_NUM_BITRATES]; - __u32 num_bitrates; - __u32 rate_control; - __u32 profiles; - __u32 modes; - __u32 formats; - __u32 min_buffer; - __u32 reserved[15]; -} __attribute__((packed, aligned(4))); -struct snd_codec { - __u32 id; - __u32 ch_in; - __u32 ch_out; - __u32 sample_rate; - __u32 bit_rate; - __u32 rate_control; - __u32 profile; - __u32 level; - __u32 ch_mode; - __u32 format; - __u32 align; - __u32 compr_passthr; - union snd_codec_options options; - __u32 flags; - __u32 reserved[2]; -} __attribute__((packed, aligned(4))); -struct snd_codec_metadata { - __u32 length; - __u32 offset; - __u64 timestamp; - __u32 reserved[4]; -}; -#endif diff --git a/sdm710/kernel-headers/sound/devdep_params.h b/sdm710/kernel-headers/sound/devdep_params.h deleted file mode 100644 index b4a185f7..00000000 --- a/sdm710/kernel-headers/sound/devdep_params.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef _DEV_DEP_H -#define _DEV_DEP_H - -struct dolby_param_data { - int32_t version; - int32_t device_id; - int32_t be_id; - int32_t param_id; - int32_t length; - int32_t *data; -}; - -struct dolby_param_license { - int32_t dmid; - int32_t license_key; -}; - -#define SNDRV_DEVDEP_DAP_IOCTL_SET_PARAM\ - _IOWR('U', 0x10, struct dolby_param_data) -#define SNDRV_DEVDEP_DAP_IOCTL_GET_PARAM\ - _IOR('U', 0x11, struct dolby_param_data) -#define SNDRV_DEVDEP_DAP_IOCTL_DAP_COMMAND\ - _IOWR('U', 0x13, struct dolby_param_data) -#define SNDRV_DEVDEP_DAP_IOCTL_DAP_LICENSE\ - _IOWR('U', 0x14, struct dolby_param_license) -#define SNDRV_DEVDEP_DAP_IOCTL_GET_VISUALIZER\ - _IOR('U', 0x15, struct dolby_param_data) - -#define DTS_EAGLE_MODULE 0x00005000 -#define DTS_EAGLE_MODULE_ENABLE 0x00005001 -#define EAGLE_DRIVER_ID 0xF2 -#define DTS_EAGLE_IOCTL_GET_CACHE_SIZE _IOR(EAGLE_DRIVER_ID, 0, int) -#define DTS_EAGLE_IOCTL_SET_CACHE_SIZE _IOW(EAGLE_DRIVER_ID, 1, int) -#define DTS_EAGLE_IOCTL_GET_PARAM _IOR(EAGLE_DRIVER_ID, 2, void*) -#define DTS_EAGLE_IOCTL_SET_PARAM _IOW(EAGLE_DRIVER_ID, 3, void*) -#define DTS_EAGLE_IOCTL_SET_CACHE_BLOCK _IOW(EAGLE_DRIVER_ID, 4, void*) -#define DTS_EAGLE_IOCTL_SET_ACTIVE_DEVICE _IOW(EAGLE_DRIVER_ID, 5, void*) -#define DTS_EAGLE_IOCTL_GET_LICENSE _IOR(EAGLE_DRIVER_ID, 6, void*) -#define DTS_EAGLE_IOCTL_SET_LICENSE _IOW(EAGLE_DRIVER_ID, 7, void*) -#define DTS_EAGLE_IOCTL_SEND_LICENSE _IOW(EAGLE_DRIVER_ID, 8, int) -#define DTS_EAGLE_IOCTL_SET_VOLUME_COMMANDS _IOW(EAGLE_DRIVER_ID, 9, void*) -#define DTS_EAGLE_FLAG_IOCTL_PRE (1<<30) -#define DTS_EAGLE_FLAG_IOCTL_JUSTSETCACHE (1<<31) -#define DTS_EAGLE_FLAG_IOCTL_GETFROMCORE DTS_EAGLE_FLAG_IOCTL_JUSTSETCACHE -#define DTS_EAGLE_FLAG_IOCTL_MASK (~(DTS_EAGLE_FLAG_IOCTL_PRE | \ - DTS_EAGLE_FLAG_IOCTL_JUSTSETCACHE)) -#define DTS_EAGLE_FLAG_ALSA_GET (1<<31) - -struct dts_eagle_param_desc { - uint32_t id; - uint32_t size; - int32_t offset; - uint32_t device; -} __attribute__((packed)); - -#define HWDEP_FE_BASE 3000 /*unique base for FE hw dep nodes*/ -struct snd_pcm_mmap_fd { - int32_t dir; - int32_t fd; - int32_t size; - int32_t actual_size; -}; - -#define SNDRV_PCM_IOCTL_MMAP_DATA_FD _IOWR('U', 0xd2, struct snd_pcm_mmap_fd) - -#endif diff --git a/sdm710/kernel-headers/sound/lsm_params.h b/sdm710/kernel-headers/sound/lsm_params.h deleted file mode 100644 index 50ec97a0..00000000 --- a/sdm710/kernel-headers/sound/lsm_params.h +++ /dev/null @@ -1,200 +0,0 @@ -#ifndef _LSM_PARAMS_H__ -#define _LSM_PARAMS_H__ - -#define LSM_POLLING_ENABLE_SUPPORT -#define LSM_EVENT_TIMESTAMP_MODE_SUPPORT - -#include <linux/types.h> -#include <sound/asound.h> - -#define SNDRV_LSM_VERSION SNDRV_PROTOCOL_VERSION(0, 1, 0) - -#define LSM_OUT_FORMAT_PCM (0) -#define LSM_OUT_FORMAT_ADPCM (1 << 0) - -#define LSM_OUT_DATA_RAW (0) -#define LSM_OUT_DATA_PACKED (1) - -#define LSM_OUT_DATA_EVENTS_DISABLED (0) -#define LSM_OUT_DATA_EVENTS_ENABLED (1) - -#define LSM_OUT_TRANSFER_MODE_RT (0) -#define LSM_OUT_TRANSFER_MODE_FTRT (1) - -#define LSM_ENDPOINT_DETECT_THRESHOLD (0) -#define LSM_OPERATION_MODE (1) -#define LSM_GAIN (2) -#define LSM_MIN_CONFIDENCE_LEVELS (3) -#define LSM_REG_SND_MODEL (4) -#define LSM_DEREG_SND_MODEL (5) -#define LSM_CUSTOM_PARAMS (6) -#define LSM_POLLING_ENABLE (7) -#define LSM_PARAMS_MAX (LSM_POLLING_ENABLE + 1) - -#define LSM_EVENT_NON_TIME_STAMP_MODE (0) -#define LSM_EVENT_TIME_STAMP_MODE (1) - -enum lsm_app_id { - LSM_VOICE_WAKEUP_APP_ID = 1, - LSM_VOICE_WAKEUP_APP_ID_V2 = 2, -}; - -enum lsm_detection_mode { - LSM_MODE_KEYWORD_ONLY_DETECTION = 1, - LSM_MODE_USER_KEYWORD_DETECTION -}; - -enum lsm_vw_status { - LSM_VOICE_WAKEUP_STATUS_RUNNING = 1, - LSM_VOICE_WAKEUP_STATUS_DETECTED, - LSM_VOICE_WAKEUP_STATUS_END_SPEECH, - LSM_VOICE_WAKEUP_STATUS_REJECTED -}; - -/* - * Data for LSM_ENDPOINT_DETECT_THRESHOLD param_type - * @epd_begin: Begin threshold - * @epd_end: End threshold - */ -struct snd_lsm_ep_det_thres { - __u32 epd_begin; - __u32 epd_end; -}; - -/* - * Data for LSM_OPERATION_MODE param_type - * @mode: The detection mode to be used - * @detect_failure: Setting to enable failure detections. - */ -struct snd_lsm_detect_mode { - enum lsm_detection_mode mode; - bool detect_failure; -}; - -/* - * Data for LSM_GAIN param_type - * @gain: The gain to be applied on LSM - */ -struct snd_lsm_gain { - __u16 gain; -}; - -/* - * Data for LSM_POLLING_ENABLE param_type - * @poll_en: Polling enable or disable - */ -struct snd_lsm_poll_enable { - bool poll_en; -}; - - -struct snd_lsm_sound_model_v2 { - __u8 *data; - __u8 *confidence_level; - __u32 data_size; - enum lsm_detection_mode detection_mode; - __u8 num_confidence_levels; - bool detect_failure; -}; - -struct snd_lsm_session_data { - enum lsm_app_id app_id; -}; - -struct snd_lsm_event_status { - __u16 status; - __u16 payload_size; - __u8 payload[0]; -}; - -struct snd_lsm_event_status_v3 { - __u32 timestamp_lsw; - __u32 timestamp_msw; - __u16 status; - __u16 payload_size; - __u8 payload[0]; -}; - -struct snd_lsm_detection_params { - __u8 *conf_level; - enum lsm_detection_mode detect_mode; - __u8 num_confidence_levels; - bool detect_failure; - bool poll_enable; -}; - -/* - * Param info for each parameter type - * @module_id: Module to which parameter is to be set - * @param_id: Parameter that is to be set - * @param_size: size (in number of bytes) for the data - * in param_data. - * For confidence levels, this is num_conf_levels - * For REG_SND_MODEL, this is size of sound model - * For CUSTOM_PARAMS, this is size of the entire blob of data - * @param_data: Data for the parameter. - * For some param_types this is a structure defined, ex: LSM_GAIN - * For CONFIDENCE_LEVELS, this is array of confidence levels - * For REG_SND_MODEL, this is the sound model data - * For CUSTOM_PARAMS, this is the blob of custom data. - */ -struct lsm_params_info { - __u32 module_id; - __u32 param_id; - __u32 param_size; - __u8 *param_data; - uint32_t param_type; -}; - -/* - * Data passed to the SET_PARAM_V2 IOCTL - * @num_params: Number of params that are to be set - * should not be greater than LSM_PARAMS_MAX - * @params: Points to an array of lsm_params_info - * Each entry points to one parameter to set - * @data_size: size (in bytes) for params - * should be equal to - * num_params * sizeof(struct lsm_parms_info) - */ -struct snd_lsm_module_params { - __u8 *params; - __u32 num_params; - __u32 data_size; -}; - -/* - * Data passed to LSM_OUT_FORMAT_CFG IOCTL - * @format: The media format enum - * @packing: indicates the packing method used for data path - * @events: indicates whether data path events need to be enabled - * @transfer_mode: indicates whether FTRT mode or RT mode. - */ -struct snd_lsm_output_format_cfg { - __u8 format; - __u8 packing; - __u8 events; - __u8 mode; -}; - -#define SNDRV_LSM_DEREG_SND_MODEL _IOW('U', 0x01, int) -#define SNDRV_LSM_EVENT_STATUS _IOW('U', 0x02, struct snd_lsm_event_status) -#define SNDRV_LSM_ABORT_EVENT _IOW('U', 0x03, int) -#define SNDRV_LSM_START _IOW('U', 0x04, int) -#define SNDRV_LSM_STOP _IOW('U', 0x05, int) -#define SNDRV_LSM_SET_SESSION_DATA _IOW('U', 0x06, struct snd_lsm_session_data) -#define SNDRV_LSM_REG_SND_MODEL_V2 _IOW('U', 0x07,\ - struct snd_lsm_sound_model_v2) -#define SNDRV_LSM_LAB_CONTROL _IOW('U', 0x08, uint32_t) -#define SNDRV_LSM_STOP_LAB _IO('U', 0x09) -#define SNDRV_LSM_SET_PARAMS _IOW('U', 0x0A, \ - struct snd_lsm_detection_params) -#define SNDRV_LSM_SET_MODULE_PARAMS _IOW('U', 0x0B, \ - struct snd_lsm_module_params) -#define SNDRV_LSM_OUT_FORMAT_CFG _IOW('U', 0x0C, \ - struct snd_lsm_output_format_cfg) -#define SNDRV_LSM_SET_PORT _IO('U', 0x0D) -#define SNDRV_LSM_SET_FWK_MODE_CONFIG _IOW('U', 0x0E, uint32_t) -#define SNDRV_LSM_EVENT_STATUS_V3 _IOW('U', 0x0F, \ - struct snd_lsm_event_status_v3) - -#endif diff --git a/sdm710/kernel-headers/sound/msmcal-hwdep.h b/sdm710/kernel-headers/sound/msmcal-hwdep.h deleted file mode 100644 index 9b29ebf3..00000000 --- a/sdm710/kernel-headers/sound/msmcal-hwdep.h +++ /dev/null @@ -1,37 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _CALIB_HWDEP_H -#define _CALIB_HWDEP_H -#define WCD9XXX_CODEC_HWDEP_NODE 1000 -enum wcd_cal_type { - WCD9XXX_MIN_CAL, - WCD9XXX_ANC_CAL = WCD9XXX_MIN_CAL, - WCD9XXX_MAD_CAL, - WCD9XXX_MBHC_CAL, - WCD9XXX_VBAT_CAL, - WCD9XXX_MAX_CAL, -}; -struct wcdcal_ioctl_buffer { - __u32 size; - __u8 * buffer; - enum wcd_cal_type cal_type; -}; -#define SNDRV_CTL_IOCTL_HWDEP_CAL_TYPE _IOW('U', 0x1, struct wcdcal_ioctl_buffer) -#endif - diff --git a/sdm710/kernel-headers/sound/voice_params.h b/sdm710/kernel-headers/sound/voice_params.h deleted file mode 100644 index 43e3b9d0..00000000 --- a/sdm710/kernel-headers/sound/voice_params.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef __VOICE_PARAMS_H__ -#define __VOICE_PARAMS_H__ - -#include <linux/types.h> -#include <sound/asound.h> - -enum voice_lch_mode { - VOICE_LCH_START = 1, - VOICE_LCH_STOP -}; - -#define SNDRV_VOICE_IOCTL_LCH _IOW('U', 0x00, enum voice_lch_mode) - -#endif diff --git a/sdm710/kernel-headers/sound/voice_svc.h b/sdm710/kernel-headers/sound/voice_svc.h deleted file mode 100644 index 5b471a8b..00000000 --- a/sdm710/kernel-headers/sound/voice_svc.h +++ /dev/null @@ -1,57 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef __VOICE_SVC_H__ -#define __VOICE_SVC_H__ -#include <linux/types.h> -#include <linux/ioctl.h> -#define VOICE_SVC_DRIVER_NAME "voice_svc" -#define VOICE_SVC_MVM_STR "MVM" -#define VOICE_SVC_CVS_STR "CVS" -#define MAX_APR_SERVICE_NAME_LEN 64 -#define MSG_REGISTER 0x1 -#define MSG_REQUEST 0x2 -#define MSG_RESPONSE 0x3 -struct voice_svc_write_msg { - __u32 msg_type; - __u8 payload[0]; -}; -struct voice_svc_register { - char svc_name[MAX_APR_SERVICE_NAME_LEN]; - __u32 src_port; - __u8 reg_flag; -}; -struct voice_svc_cmd_response { - __u32 src_port; - __u32 dest_port; - __u32 token; - __u32 opcode; - __u32 payload_size; - __u8 payload[0]; -}; -struct voice_svc_cmd_request { - char svc_name[MAX_APR_SERVICE_NAME_LEN]; - __u32 src_port; - __u32 dest_port; - __u32 token; - __u32 opcode; - __u32 payload_size; - __u8 payload[0]; -}; -#endif - diff --git a/sdm710/kernel-headers/sound/wcd-dsp-glink.h b/sdm710/kernel-headers/sound/wcd-dsp-glink.h deleted file mode 100644 index 39d128d3..00000000 --- a/sdm710/kernel-headers/sound/wcd-dsp-glink.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef _WCD_DSP_GLINK_H -#define _WCD_DSP_GLINK_H - -#include <linux/types.h> - -#define WDSP_CH_NAME_MAX_LEN 50 - -enum { - WDSP_REG_PKT = 1, - WDSP_CMD_PKT, - WDSP_READY_PKT, -}; -#define WDSP_READY_PKT WDSP_READY_PKT - -/* - * struct wdsp_reg_pkt - Glink channel information structure format - * @no_of_channels: Number of glink channels to open - * @payload[0]: Dynamic array contains all the glink channels information - */ -struct wdsp_reg_pkt { - __u8 no_of_channels; - __u8 payload[0]; -}; - -/* - * struct wdsp_cmd_pkt - WDSP command packet format - * @ch_name: Name of the glink channel - * @payload_size: Size of the payload - * @payload[0]: Actual data payload - */ -struct wdsp_cmd_pkt { - char ch_name[WDSP_CH_NAME_MAX_LEN]; - __u32 payload_size; - __u8 payload[0]; -}; - -/* - * struct wdsp_write_pkt - Format that userspace send the data to driver. - * @pkt_type: Type of the packet(REG or CMD PKT) - * @payload[0]: Payload is either cmd or reg pkt structure based on pkt type - */ -struct wdsp_write_pkt { - __u8 pkt_type; - __u8 payload[0]; -}; - -/* - * struct wdsp_glink_ch_cfg - Defines the glink channel configuration. - * @ch_name: Name of the glink channel - * @latency_in_us: Latency specified in micro seconds for QOS - * @no_of_intents: Number of intents prequeued - * @intents_size[0]: Dynamic array to specify size of each intent - */ -struct wdsp_glink_ch_cfg { - char name[WDSP_CH_NAME_MAX_LEN]; - __u32 latency_in_us; - __u32 no_of_intents; - __u32 intents_size[0]; -}; -#endif /* _WCD_DSP_GLINK_H */ diff --git a/sdm710/kernel-headers/video/msm_hdmi_modes.h b/sdm710/kernel-headers/video/msm_hdmi_modes.h deleted file mode 100644 index 8e76b32f..00000000 --- a/sdm710/kernel-headers/video/msm_hdmi_modes.h +++ /dev/null @@ -1,290 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _MSM_HDMI_MODES_H__ -#define _MSM_HDMI_MODES_H__ -#include <linux/types.h> -#include <linux/errno.h> -#define MSM_HDMI_RGB_888_24BPP_FORMAT (1 << 0) -#define MSM_HDMI_YUV_420_12BPP_FORMAT (1 << 1) -enum aspect_ratio { - HDMI_RES_AR_INVALID, - HDMI_RES_AR_4_3, - HDMI_RES_AR_5_4, - HDMI_RES_AR_16_9, - HDMI_RES_AR_16_10, - HDMI_RES_AR_64_27, - HDMI_RES_AR_256_135, - HDMI_RES_AR_MAX, -}; -enum msm_hdmi_s3d_mode { - HDMI_S3D_NONE, - HDMI_S3D_SIDE_BY_SIDE, - HDMI_S3D_TOP_AND_BOTTOM, - HDMI_S3D_FRAME_PACKING, - HDMI_S3D_MAX, -}; -struct msm_hdmi_mode_timing_info { - uint32_t video_format; - uint32_t active_h; - uint32_t front_porch_h; - uint32_t pulse_width_h; - uint32_t back_porch_h; - uint32_t active_low_h; - uint32_t active_v; - uint32_t front_porch_v; - uint32_t pulse_width_v; - uint32_t back_porch_v; - uint32_t active_low_v; - uint32_t pixel_freq; - uint32_t refresh_rate; - uint32_t interlaced; - uint32_t supported; - enum aspect_ratio ar; - uint32_t pixel_formats; -}; -#define MSM_HDMI_INIT_RES_PAGE 1 -#define MSM_HDMI_MODES_CEA (1 << 0) -#define MSM_HDMI_MODES_XTND (1 << 1) -#define MSM_HDMI_MODES_DVI (1 << 2) -#define MSM_HDMI_MODES_ALL (MSM_HDMI_MODES_CEA | MSM_HDMI_MODES_XTND | MSM_HDMI_MODES_DVI) -#define HDMI_VFRMT_UNKNOWN 0 -#define HDMI_VFRMT_640x480p60_4_3 1 -#define HDMI_VFRMT_720x480p60_4_3 2 -#define HDMI_VFRMT_720x480p60_16_9 3 -#define HDMI_VFRMT_1280x720p60_16_9 4 -#define HDMI_VFRMT_1920x1080i60_16_9 5 -#define HDMI_VFRMT_720x480i60_4_3 6 -#define HDMI_VFRMT_1440x480i60_4_3 HDMI_VFRMT_720x480i60_4_3 -#define HDMI_VFRMT_720x480i60_16_9 7 -#define HDMI_VFRMT_1440x480i60_16_9 HDMI_VFRMT_720x480i60_16_9 -#define HDMI_VFRMT_720x240p60_4_3 8 -#define HDMI_VFRMT_1440x240p60_4_3 HDMI_VFRMT_720x240p60_4_3 -#define HDMI_VFRMT_720x240p60_16_9 9 -#define HDMI_VFRMT_1440x240p60_16_9 HDMI_VFRMT_720x240p60_16_9 -#define HDMI_VFRMT_2880x480i60_4_3 10 -#define HDMI_VFRMT_2880x480i60_16_9 11 -#define HDMI_VFRMT_2880x240p60_4_3 12 -#define HDMI_VFRMT_2880x240p60_16_9 13 -#define HDMI_VFRMT_1440x480p60_4_3 14 -#define HDMI_VFRMT_1440x480p60_16_9 15 -#define HDMI_VFRMT_1920x1080p60_16_9 16 -#define HDMI_VFRMT_720x576p50_4_3 17 -#define HDMI_VFRMT_720x576p50_16_9 18 -#define HDMI_VFRMT_1280x720p50_16_9 19 -#define HDMI_VFRMT_1920x1080i50_16_9 20 -#define HDMI_VFRMT_720x576i50_4_3 21 -#define HDMI_VFRMT_1440x576i50_4_3 HDMI_VFRMT_720x576i50_4_3 -#define HDMI_VFRMT_720x576i50_16_9 22 -#define HDMI_VFRMT_1440x576i50_16_9 HDMI_VFRMT_720x576i50_16_9 -#define HDMI_VFRMT_720x288p50_4_3 23 -#define HDMI_VFRMT_1440x288p50_4_3 HDMI_VFRMT_720x288p50_4_3 -#define HDMI_VFRMT_720x288p50_16_9 24 -#define HDMI_VFRMT_1440x288p50_16_9 HDMI_VFRMT_720x288p50_16_9 -#define HDMI_VFRMT_2880x576i50_4_3 25 -#define HDMI_VFRMT_2880x576i50_16_9 26 -#define HDMI_VFRMT_2880x288p50_4_3 27 -#define HDMI_VFRMT_2880x288p50_16_9 28 -#define HDMI_VFRMT_1440x576p50_4_3 29 -#define HDMI_VFRMT_1440x576p50_16_9 30 -#define HDMI_VFRMT_1920x1080p50_16_9 31 -#define HDMI_VFRMT_1920x1080p24_16_9 32 -#define HDMI_VFRMT_1920x1080p25_16_9 33 -#define HDMI_VFRMT_1920x1080p30_16_9 34 -#define HDMI_VFRMT_2880x480p60_4_3 35 -#define HDMI_VFRMT_2880x480p60_16_9 36 -#define HDMI_VFRMT_2880x576p50_4_3 37 -#define HDMI_VFRMT_2880x576p50_16_9 38 -#define HDMI_VFRMT_1920x1250i50_16_9 39 -#define HDMI_VFRMT_1920x1080i100_16_9 40 -#define HDMI_VFRMT_1280x720p100_16_9 41 -#define HDMI_VFRMT_720x576p100_4_3 42 -#define HDMI_VFRMT_720x576p100_16_9 43 -#define HDMI_VFRMT_720x576i100_4_3 44 -#define HDMI_VFRMT_1440x576i100_4_3 HDMI_VFRMT_720x576i100_4_3 -#define HDMI_VFRMT_720x576i100_16_9 45 -#define HDMI_VFRMT_1440x576i100_16_9 HDMI_VFRMT_720x576i100_16_9 -#define HDMI_VFRMT_1920x1080i120_16_9 46 -#define HDMI_VFRMT_1280x720p120_16_9 47 -#define HDMI_VFRMT_720x480p120_4_3 48 -#define HDMI_VFRMT_720x480p120_16_9 49 -#define HDMI_VFRMT_720x480i120_4_3 50 -#define HDMI_VFRMT_1440x480i120_4_3 HDMI_VFRMT_720x480i120_4_3 -#define HDMI_VFRMT_720x480i120_16_9 51 -#define HDMI_VFRMT_1440x480i120_16_9 HDMI_VFRMT_720x480i120_16_9 -#define HDMI_VFRMT_720x576p200_4_3 52 -#define HDMI_VFRMT_720x576p200_16_9 53 -#define HDMI_VFRMT_720x576i200_4_3 54 -#define HDMI_VFRMT_1440x576i200_4_3 HDMI_VFRMT_720x576i200_4_3 -#define HDMI_VFRMT_720x576i200_16_9 55 -#define HDMI_VFRMT_1440x576i200_16_9 HDMI_VFRMT_720x576i200_16_9 -#define HDMI_VFRMT_720x480p240_4_3 56 -#define HDMI_VFRMT_720x480p240_16_9 57 -#define HDMI_VFRMT_720x480i240_4_3 58 -#define HDMI_VFRMT_1440x480i240_4_3 HDMI_VFRMT_720x480i240_4_3 -#define HDMI_VFRMT_720x480i240_16_9 59 -#define HDMI_VFRMT_1440x480i240_16_9 HDMI_VFRMT_720x480i240_16_9 -#define HDMI_VFRMT_1280x720p24_16_9 60 -#define HDMI_VFRMT_1280x720p25_16_9 61 -#define HDMI_VFRMT_1280x720p30_16_9 62 -#define HDMI_VFRMT_1920x1080p120_16_9 63 -#define HDMI_VFRMT_1920x1080p100_16_9 64 -#define HDMI_VFRMT_1280x720p24_64_27 65 -#define HDMI_VFRMT_1280x720p25_64_27 66 -#define HDMI_VFRMT_1280x720p30_64_27 67 -#define HDMI_VFRMT_1280x720p50_64_27 68 -#define HDMI_VFRMT_1280x720p60_64_27 69 -#define HDMI_VFRMT_1280x720p100_64_27 70 -#define HDMI_VFRMT_1280x720p120_64_27 71 -#define HDMI_VFRMT_1920x1080p24_64_27 72 -#define HDMI_VFRMT_1920x1080p25_64_27 73 -#define HDMI_VFRMT_1920x1080p30_64_27 74 -#define HDMI_VFRMT_1920x1080p50_64_27 75 -#define HDMI_VFRMT_1920x1080p60_64_27 76 -#define HDMI_VFRMT_1920x1080p100_64_27 77 -#define HDMI_VFRMT_1920x1080p120_64_27 78 -#define HDMI_VFRMT_1680x720p24_64_27 79 -#define HDMI_VFRMT_1680x720p25_64_27 80 -#define HDMI_VFRMT_1680x720p30_64_27 81 -#define HDMI_VFRMT_1680x720p50_64_27 82 -#define HDMI_VFRMT_1680x720p60_64_27 83 -#define HDMI_VFRMT_1680x720p100_64_27 84 -#define HDMI_VFRMT_1680x720p120_64_27 85 -#define HDMI_VFRMT_2560x1080p24_64_27 86 -#define HDMI_VFRMT_2560x1080p25_64_27 87 -#define HDMI_VFRMT_2560x1080p30_64_27 88 -#define HDMI_VFRMT_2560x1080p50_64_27 89 -#define HDMI_VFRMT_2560x1080p60_64_27 90 -#define HDMI_VFRMT_2560x1080p100_64_27 91 -#define HDMI_VFRMT_2560x1080p120_64_27 92 -#define HDMI_VFRMT_3840x2160p24_16_9 93 -#define HDMI_VFRMT_3840x2160p25_16_9 94 -#define HDMI_VFRMT_3840x2160p30_16_9 95 -#define HDMI_VFRMT_3840x2160p50_16_9 96 -#define HDMI_VFRMT_3840x2160p60_16_9 97 -#define HDMI_VFRMT_4096x2160p24_256_135 98 -#define HDMI_VFRMT_4096x2160p25_256_135 99 -#define HDMI_VFRMT_4096x2160p30_256_135 100 -#define HDMI_VFRMT_4096x2160p50_256_135 101 -#define HDMI_VFRMT_4096x2160p60_256_135 102 -#define HDMI_VFRMT_3840x2160p24_64_27 103 -#define HDMI_VFRMT_3840x2160p25_64_27 104 -#define HDMI_VFRMT_3840x2160p30_64_27 105 -#define HDMI_VFRMT_3840x2160p50_64_27 106 -#define HDMI_VFRMT_3840x2160p60_64_27 107 -#define HDMI_VFRMT_END 127 -#define EVFRMT_OFF(x) (HDMI_VFRMT_END + x) -#define HDMI_EVFRMT_3840x2160p30_16_9 EVFRMT_OFF(1) -#define HDMI_EVFRMT_3840x2160p25_16_9 EVFRMT_OFF(2) -#define HDMI_EVFRMT_3840x2160p24_16_9 EVFRMT_OFF(3) -#define HDMI_EVFRMT_4096x2160p24_16_9 EVFRMT_OFF(4) -#define HDMI_EVFRMT_END HDMI_EVFRMT_4096x2160p24_16_9 -#define WQXGA_OFF(x) (HDMI_EVFRMT_END + x) -#define HDMI_VFRMT_2560x1600p60_16_9 WQXGA_OFF(1) -#define HDMI_WQXGAFRMT_END HDMI_VFRMT_2560x1600p60_16_9 -#define WXGA_OFF(x) (HDMI_WQXGAFRMT_END + x) -#define HDMI_VFRMT_1280x800p60_16_10 WXGA_OFF(1) -#define HDMI_VFRMT_1366x768p60_16_10 WXGA_OFF(2) -#define HDMI_WXGAFRMT_END HDMI_VFRMT_1366x768p60_16_10 -#define ETI_OFF(x) (HDMI_WXGAFRMT_END + x) -#define HDMI_VFRMT_800x600p60_4_3 ETI_OFF(1) -#define ETI_VFRMT_END HDMI_VFRMT_800x600p60_4_3 -#define ETII_OFF(x) (ETI_VFRMT_END + x) -#define HDMI_VFRMT_1024x768p60_4_3 ETII_OFF(1) -#define HDMI_VFRMT_1280x1024p60_5_4 ETII_OFF(2) -#define ETII_VFRMT_END HDMI_VFRMT_1280x1024p60_5_4 -#define ETIII_OFF(x) (ETII_VFRMT_END + x) -#define HDMI_VFRMT_848x480p60_16_9 ETIII_OFF(1) -#define HDMI_VFRMT_1280x960p60_4_3 ETIII_OFF(2) -#define HDMI_VFRMT_1360x768p60_16_9 ETIII_OFF(3) -#define HDMI_VFRMT_1440x900p60_16_10 ETIII_OFF(4) -#define HDMI_VFRMT_1400x1050p60_4_3 ETIII_OFF(5) -#define HDMI_VFRMT_1680x1050p60_16_10 ETIII_OFF(6) -#define HDMI_VFRMT_1600x1200p60_4_3 ETIII_OFF(7) -#define HDMI_VFRMT_1920x1200p60_16_10 ETIII_OFF(8) -#define ETIII_VFRMT_END HDMI_VFRMT_1920x1200p60_16_10 -#define RESERVE_OFF(x) (ETIII_VFRMT_END + x) -#define HDMI_VFRMT_RESERVE1 RESERVE_OFF(1) -#define HDMI_VFRMT_RESERVE2 RESERVE_OFF(2) -#define HDMI_VFRMT_RESERVE3 RESERVE_OFF(3) -#define HDMI_VFRMT_RESERVE4 RESERVE_OFF(4) -#define HDMI_VFRMT_RESERVE5 RESERVE_OFF(5) -#define HDMI_VFRMT_RESERVE6 RESERVE_OFF(6) -#define HDMI_VFRMT_RESERVE7 RESERVE_OFF(7) -#define HDMI_VFRMT_RESERVE8 RESERVE_OFF(8) -#define RESERVE_VFRMT_END HDMI_VFRMT_RESERVE8 -#define HDMI_VFRMT_MAX (RESERVE_VFRMT_END + 1) -#define VFRMT_NOT_SUPPORTED(VFRMT) { VFRMT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, false, HDMI_RES_AR_INVALID } -#define HDMI_VFRMT_640x480p60_4_3_TIMING { HDMI_VFRMT_640x480p60_4_3, 640, 16, 96, 48, true, 480, 10, 2, 33, true, 25200, 60000, false, true, HDMI_RES_AR_4_3, 0 } -#define HDMI_VFRMT_720x480p60_4_3_TIMING { HDMI_VFRMT_720x480p60_4_3, 720, 16, 62, 60, true, 480, 9, 6, 30, true, 27027, 60000, false, true, HDMI_RES_AR_4_3, 0 } -#define HDMI_VFRMT_720x480p60_16_9_TIMING { HDMI_VFRMT_720x480p60_16_9, 720, 16, 62, 60, true, 480, 9, 6, 30, true, 27027, 60000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_1280x720p60_16_9_TIMING { HDMI_VFRMT_1280x720p60_16_9, 1280, 110, 40, 220, false, 720, 5, 5, 20, false, 74250, 60000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_1920x1080i60_16_9_TIMING { HDMI_VFRMT_1920x1080i60_16_9, 1920, 88, 44, 148, false, 540, 2, 5, 5, false, 74250, 60000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_1440x480i60_4_3_TIMING { HDMI_VFRMT_1440x480i60_4_3, 1440, 38, 124, 114, true, 240, 4, 3, 15, true, 27000, 60000, true, true, HDMI_RES_AR_4_3, 0 } -#define HDMI_VFRMT_1440x480i60_16_9_TIMING { HDMI_VFRMT_1440x480i60_16_9, 1440, 38, 124, 114, true, 240, 4, 3, 15, true, 27000, 60000, true, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_1920x1080p60_16_9_TIMING { HDMI_VFRMT_1920x1080p60_16_9, 1920, 88, 44, 148, false, 1080, 4, 5, 36, false, 148500, 60000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_720x576p50_4_3_TIMING { HDMI_VFRMT_720x576p50_4_3, 720, 12, 64, 68, true, 576, 5, 5, 39, true, 27000, 50000, false, true, HDMI_RES_AR_4_3, 0 } -#define HDMI_VFRMT_720x576p50_16_9_TIMING { HDMI_VFRMT_720x576p50_16_9, 720, 12, 64, 68, true, 576, 5, 5, 39, true, 27000, 50000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_1280x720p50_16_9_TIMING { HDMI_VFRMT_1280x720p50_16_9, 1280, 440, 40, 220, false, 720, 5, 5, 20, false, 74250, 50000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_1440x576i50_4_3_TIMING { HDMI_VFRMT_1440x576i50_4_3, 1440, 24, 126, 138, true, 288, 2, 3, 19, true, 27000, 50000, true, true, HDMI_RES_AR_4_3, 0 } -#define HDMI_VFRMT_1440x576i50_16_9_TIMING { HDMI_VFRMT_1440x576i50_16_9, 1440, 24, 126, 138, true, 288, 2, 3, 19, true, 27000, 50000, true, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_1920x1080p50_16_9_TIMING { HDMI_VFRMT_1920x1080p50_16_9, 1920, 528, 44, 148, false, 1080, 4, 5, 36, false, 148500, 50000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_1920x1080p24_16_9_TIMING { HDMI_VFRMT_1920x1080p24_16_9, 1920, 638, 44, 148, false, 1080, 4, 5, 36, false, 74250, 24000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_1920x1080p25_16_9_TIMING { HDMI_VFRMT_1920x1080p25_16_9, 1920, 528, 44, 148, false, 1080, 4, 5, 36, false, 74250, 25000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_1920x1080p30_16_9_TIMING { HDMI_VFRMT_1920x1080p30_16_9, 1920, 88, 44, 148, false, 1080, 4, 5, 36, false, 74250, 30000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_1024x768p60_4_3_TIMING { HDMI_VFRMT_1024x768p60_4_3, 1024, 24, 136, 160, false, 768, 2, 6, 29, false, 65000, 60000, false, true, HDMI_RES_AR_4_3, 0 } -#define HDMI_VFRMT_1280x1024p60_5_4_TIMING { HDMI_VFRMT_1280x1024p60_5_4, 1280, 48, 112, 248, false, 1024, 1, 3, 38, false, 108000, 60000, false, true, HDMI_RES_AR_5_4, 0 } -#define HDMI_VFRMT_2560x1600p60_16_9_TIMING { HDMI_VFRMT_2560x1600p60_16_9, 2560, 48, 32, 80, false, 1600, 3, 6, 37, false, 268500, 60000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_EVFRMT_3840x2160p30_16_9_TIMING { HDMI_EVFRMT_3840x2160p30_16_9, 3840, 176, 88, 296, false, 2160, 8, 10, 72, false, 297000, 30000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_EVFRMT_3840x2160p25_16_9_TIMING { HDMI_EVFRMT_3840x2160p25_16_9, 3840, 1056, 88, 296, false, 2160, 8, 10, 72, false, 297000, 25000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_EVFRMT_3840x2160p24_16_9_TIMING { HDMI_EVFRMT_3840x2160p24_16_9, 3840, 1276, 88, 296, false, 2160, 8, 10, 72, false, 297000, 24000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_EVFRMT_4096x2160p24_16_9_TIMING { HDMI_EVFRMT_4096x2160p24_16_9, 4096, 1020, 88, 296, false, 2160, 8, 10, 72, false, 297000, 24000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_800x600p60_4_3_TIMING { HDMI_VFRMT_800x600p60_4_3, 800, 40, 128, 88, false, 600, 1, 4, 23, false, 40000, 60000, false, true, HDMI_RES_AR_4_3, 0 } -#define HDMI_VFRMT_848x480p60_16_9_TIMING { HDMI_VFRMT_848x480p60_16_9, 848, 16, 112, 112, false, 480, 6, 8, 23, false, 33750, 60000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_1280x960p60_4_3_TIMING { HDMI_VFRMT_1280x960p60_4_3, 1280, 96, 112, 312, false, 960, 1, 3, 36, false, 108000, 60000, false, true, HDMI_RES_AR_4_3, 0 } -#define HDMI_VFRMT_1360x768p60_16_9_TIMING { HDMI_VFRMT_1360x768p60_16_9, 1360, 64, 112, 256, false, 768, 3, 6, 18, false, 85500, 60000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_1440x900p60_16_10_TIMING { HDMI_VFRMT_1440x900p60_16_10, 1440, 48, 32, 80, false, 900, 3, 6, 17, true, 88750, 60000, false, true, HDMI_RES_AR_16_10, 0 } -#define HDMI_VFRMT_1400x1050p60_4_3_TIMING { HDMI_VFRMT_1400x1050p60_4_3, 1400, 48, 32, 80, false, 1050, 3, 4, 23, true, 101000, 60000, false, true, HDMI_RES_AR_4_3, 0 } -#define HDMI_VFRMT_1680x1050p60_16_10_TIMING { HDMI_VFRMT_1680x1050p60_16_10, 1680, 48, 32, 80, false, 1050, 3, 6, 21, true, 119000, 60000, false, true, HDMI_RES_AR_16_10, 0 } -#define HDMI_VFRMT_1600x1200p60_4_3_TIMING { HDMI_VFRMT_1600x1200p60_4_3, 1600, 64, 192, 304, false, 1200, 1, 3, 46, false, 162000, 60000, false, true, HDMI_RES_AR_4_3, 0 } -#define HDMI_VFRMT_1920x1200p60_16_10_TIMING { HDMI_VFRMT_1920x1200p60_16_10, 1920, 48, 32, 80, false, 1200, 3, 6, 26, true, 154000, 60000, false, true, HDMI_RES_AR_16_10, 0 } -#define HDMI_VFRMT_1366x768p60_16_10_TIMING { HDMI_VFRMT_1366x768p60_16_10, 1366, 70, 143, 213, false, 768, 3, 3, 24, false, 85500, 60000, false, true, HDMI_RES_AR_16_10, 0 } -#define HDMI_VFRMT_1280x800p60_16_10_TIMING { HDMI_VFRMT_1280x800p60_16_10, 1280, 72, 128, 200, true, 800, 3, 6, 22, false, 83500, 60000, false, true, HDMI_RES_AR_16_10, 0 } -#define HDMI_VFRMT_3840x2160p24_16_9_TIMING { HDMI_VFRMT_3840x2160p24_16_9, 3840, 1276, 88, 296, false, 2160, 8, 10, 72, false, 297000, 24000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_3840x2160p25_16_9_TIMING { HDMI_VFRMT_3840x2160p25_16_9, 3840, 1056, 88, 296, false, 2160, 8, 10, 72, false, 297000, 25000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_3840x2160p30_16_9_TIMING { HDMI_VFRMT_3840x2160p30_16_9, 3840, 176, 88, 296, false, 2160, 8, 10, 72, false, 297000, 30000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_3840x2160p50_16_9_TIMING { HDMI_VFRMT_3840x2160p50_16_9, 3840, 1056, 88, 296, false, 2160, 8, 10, 72, false, 594000, 50000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_3840x2160p60_16_9_TIMING { HDMI_VFRMT_3840x2160p60_16_9, 3840, 176, 88, 296, false, 2160, 8, 10, 72, false, 594000, 60000, false, true, HDMI_RES_AR_16_9, 0 } -#define HDMI_VFRMT_4096x2160p24_256_135_TIMING { HDMI_VFRMT_4096x2160p24_256_135, 4096, 1020, 88, 296, false, 2160, 8, 10, 72, false, 297000, 24000, false, true, HDMI_RES_AR_256_135, 0 } -#define HDMI_VFRMT_4096x2160p25_256_135_TIMING { HDMI_VFRMT_4096x2160p25_256_135, 4096, 968, 88, 128, false, 2160, 8, 10, 72, false, 297000, 25000, false, true, HDMI_RES_AR_256_135, 0 } -#define HDMI_VFRMT_4096x2160p30_256_135_TIMING { HDMI_VFRMT_4096x2160p30_256_135, 4096, 88, 88, 128, false, 2160, 8, 10, 72, false, 297000, 30000, false, true, HDMI_RES_AR_256_135, 0 } -#define HDMI_VFRMT_4096x2160p50_256_135_TIMING { HDMI_VFRMT_4096x2160p50_256_135, 4096, 968, 88, 128, false, 2160, 8, 10, 72, false, 594000, 50000, false, true, HDMI_RES_AR_256_135, 0 } -#define HDMI_VFRMT_4096x2160p60_256_135_TIMING { HDMI_VFRMT_4096x2160p60_256_135, 4096, 88, 88, 128, false, 2160, 8, 10, 72, false, 594000, 60000, false, true, HDMI_RES_AR_256_135, 0 } -#define HDMI_VFRMT_3840x2160p24_64_27_TIMING { HDMI_VFRMT_3840x2160p24_64_27, 3840, 1276, 88, 296, false, 2160, 8, 10, 72, false, 297000, 24000, false, true, HDMI_RES_AR_64_27, 0 } -#define HDMI_VFRMT_3840x2160p25_64_27_TIMING { HDMI_VFRMT_3840x2160p25_64_27, 3840, 1056, 88, 296, false, 2160, 8, 10, 72, false, 297000, 25000, false, true, HDMI_RES_AR_64_27, 0 } -#define HDMI_VFRMT_3840x2160p30_64_27_TIMING { HDMI_VFRMT_3840x2160p30_64_27, 3840, 176, 88, 296, false, 2160, 8, 10, 72, false, 297000, 30000, false, true, HDMI_RES_AR_64_27, 0 } -#define HDMI_VFRMT_3840x2160p50_64_27_TIMING { HDMI_VFRMT_3840x2160p50_64_27, 3840, 1056, 88, 296, false, 2160, 8, 10, 72, false, 594000, 50000, false, true, HDMI_RES_AR_64_27, 0 } -#define HDMI_VFRMT_3840x2160p60_64_27_TIMING { HDMI_VFRMT_3840x2160p60_64_27, 3840, 176, 88, 296, false, 2160, 8, 10, 72, false, 594000, 60000, false, true, HDMI_RES_AR_64_27, 0 } -#define MSM_HDMI_MODES_SET_TIMING(LUT,MODE) do { struct msm_hdmi_mode_timing_info mode = MODE ##_TIMING; LUT[MODE] = mode; } while(0) -#define MSM_HDMI_MODES_INIT_TIMINGS(__lut) do { unsigned int i; for(i = 0; i < HDMI_VFRMT_MAX; i ++) { struct msm_hdmi_mode_timing_info mode = VFRMT_NOT_SUPPORTED(i); (__lut)[i] = mode; } \ -} while(0) -#define MSM_HDMI_MODES_SET_SUPP_TIMINGS(__lut,__type) do { if(__type & MSM_HDMI_MODES_CEA) { MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_640x480p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_720x480p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_720x480p60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1280x720p60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1080i60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1440x480i60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1440x480i60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1080p60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_720x576p50_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_720x576p50_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1280x720p50_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1440x576i50_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1440x576i50_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1080p50_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1080p24_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1080p25_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1080p30_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_3840x2160p24_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_3840x2160p25_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_3840x2160p30_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_3840x2160p50_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_3840x2160p60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_4096x2160p24_256_135); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_4096x2160p25_256_135); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_4096x2160p30_256_135); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_4096x2160p50_256_135); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_4096x2160p60_256_135); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_3840x2160p24_64_27); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_3840x2160p25_64_27); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_3840x2160p30_64_27); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_3840x2160p50_64_27); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_3840x2160p60_64_27); } if(__type & MSM_HDMI_MODES_XTND) { MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_EVFRMT_3840x2160p30_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_EVFRMT_3840x2160p25_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_EVFRMT_3840x2160p24_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_EVFRMT_4096x2160p24_16_9); } if(__type & MSM_HDMI_MODES_DVI) { MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1024x768p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1280x1024p60_5_4); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_2560x1600p60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_800x600p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_848x480p60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1280x960p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1360x768p60_16_9); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1440x900p60_16_10); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1400x1050p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1680x1050p60_16_10); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1600x1200p60_4_3); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1920x1200p60_16_10); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1366x768p60_16_10); MSM_HDMI_MODES_SET_TIMING(__lut, HDMI_VFRMT_1280x800p60_16_10); } \ -} while(0) -#define MSM_HDMI_MODES_GET_DETAILS(mode,MODE) do { struct msm_hdmi_mode_timing_info info = MODE ##_TIMING; * mode = info; } while(0) -#endif - diff --git a/sdm710/original-kernel-headers/asm-generic/ioctls.h b/sdm710/original-kernel-headers/asm-generic/ioctls.h deleted file mode 100644 index 6404e697..00000000 --- a/sdm710/original-kernel-headers/asm-generic/ioctls.h +++ /dev/null @@ -1,120 +0,0 @@ -#ifndef __ASM_GENERIC_IOCTLS_H -#define __ASM_GENERIC_IOCTLS_H - -#include <linux/ioctl.h> - -/* - * These are the most common definitions for tty ioctl numbers. - * Most of them do not use the recommended _IOC(), but there is - * probably some source code out there hardcoding the number, - * so we might as well use them for all new platforms. - * - * The architectures that use different values here typically - * try to be compatible with some Unix variants for the same - * architecture. - */ - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T', 0x2A, struct termios2) -#define TCSETS2 _IOW('T', 0x2B, struct termios2) -#define TCSETSW2 _IOW('T', 0x2C, struct termios2) -#define TCSETSF2 _IOW('T', 0x2D, struct termios2) -#define TIOCGRS485 0x542E -#ifndef TIOCSRS485 -#define TIOCSRS485 0x542F -#endif -#define TIOCGPTN _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ -#define TIOCGDEV _IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */ -#define TCGETX 0x5432 /* SYS5 TCGETX compatibility */ -#define TCSETX 0x5433 -#define TCSETXF 0x5434 -#define TCSETXW 0x5435 -#define TIOCSIG _IOW('T', 0x36, int) /* pty: generate signal */ -#define TIOCVHANGUP 0x5437 -#define TIOCGPKT _IOR('T', 0x38, int) /* Get packet mode state */ -#define TIOCGPTLCK _IOR('T', 0x39, int) /* Get Pty lock state */ -#define TIOCGEXCL _IOR('T', 0x40, int) /* Get exclusive mode state */ -#define TIOCPMGET 0x5441 /* PM get */ -#define TIOCPMPUT 0x5442 /* PM put */ -#define TIOCPMACT 0x5443 /* PM is active */ - -#define FIONCLEX 0x5450 -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port __inline__ interrupt counts */ - -/* - * Some arches already define FIOQSIZE due to a historical - * conflict with a Hayes modem-specific ioctl value. - */ -#ifndef FIOQSIZE -# define FIOQSIZE 0x5460 -#endif - -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ - -#endif /* __ASM_GENERIC_IOCTLS_H */ diff --git a/sdm710/original-kernel-headers/drm/msm_drm.h b/sdm710/original-kernel-headers/drm/msm_drm.h deleted file mode 100644 index 99ea02f4..00000000 --- a/sdm710/original-kernel-headers/drm/msm_drm.h +++ /dev/null @@ -1,394 +0,0 @@ -/* - * Copyright (C) 2013 Red Hat - * Author: Rob Clark <robdclark@gmail.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __MSM_DRM_H__ -#define __MSM_DRM_H__ - -#include "drm.h" -#include "sde_drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* Please note that modifications to all structs defined here are - * subject to backwards-compatibility constraints: - * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit - * user/kernel compatibility - * 2) Keep fields aligned to their size - * 3) Because of how drm_ioctl() works, we can add new fields at - * the end of an ioctl if some care is taken: drm_ioctl() will - * zero out the new fields at the tail of the ioctl, so a zero - * value should have a backwards compatible meaning. And for - * output params, userspace won't see the newly added output - * fields.. so that has to be somehow ok. - */ - -#define MSM_PIPE_NONE 0x00 -#define MSM_PIPE_2D0 0x01 -#define MSM_PIPE_2D1 0x02 -#define MSM_PIPE_3D0 0x10 - -/* The pipe-id just uses the lower bits, so can be OR'd with flags in - * the upper 16 bits (which could be extended further, if needed, maybe - * we extend/overload the pipe-id some day to deal with multiple rings, - * but even then I don't think we need the full lower 16 bits). - */ -#define MSM_PIPE_ID_MASK 0xffff -#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) -#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) - -/* timeouts are specified in clock-monotonic absolute times (to simplify - * restarting interrupted ioctls). The following struct is logically the - * same as 'struct timespec' but 32/64b ABI safe. - */ -struct drm_msm_timespec { - __s64 tv_sec; /* seconds */ - __s64 tv_nsec; /* nanoseconds */ -}; - -/* - * HDR Metadata - * These are defined as per EDID spec and shall be used by the sink - * to set the HDR metadata for playback from userspace. - */ - -#define HDR_PRIMARIES_COUNT 3 - -/* HDR EOTF */ -#define HDR_EOTF_SDR_LUM_RANGE 0x0 -#define HDR_EOTF_HDR_LUM_RANGE 0x1 -#define HDR_EOTF_SMTPE_ST2084 0x2 -#define HDR_EOTF_HLG 0x3 - -#define DRM_MSM_EXT_HDR_METADATA -struct drm_msm_ext_hdr_metadata { - __u32 hdr_state; /* HDR state */ - __u32 eotf; /* electro optical transfer function */ - __u32 hdr_supported; /* HDR supported */ - __u32 display_primaries_x[HDR_PRIMARIES_COUNT]; /* Primaries x */ - __u32 display_primaries_y[HDR_PRIMARIES_COUNT]; /* Primaries y */ - __u32 white_point_x; /* white_point_x */ - __u32 white_point_y; /* white_point_y */ - __u32 max_luminance; /* Max luminance */ - __u32 min_luminance; /* Min Luminance */ - __u32 max_content_light_level; /* max content light level */ - __u32 max_average_light_level; /* max average light level */ -}; - -/** - * HDR sink properties - * These are defined as per EDID spec and shall be used by the userspace - * to determine the HDR properties to be set to the sink. - */ -#define DRM_MSM_EXT_HDR_PROPERTIES -struct drm_msm_ext_hdr_properties { - __u8 hdr_metadata_type_one; /* static metadata type one */ - __u32 hdr_supported; /* HDR supported */ - __u32 hdr_eotf; /* electro optical transfer function */ - __u32 hdr_max_luminance; /* Max luminance */ - __u32 hdr_avg_luminance; /* Avg luminance */ - __u32 hdr_min_luminance; /* Min Luminance */ -}; - -#define MSM_PARAM_GPU_ID 0x01 -#define MSM_PARAM_GMEM_SIZE 0x02 -#define MSM_PARAM_CHIP_ID 0x03 -#define MSM_PARAM_MAX_FREQ 0x04 -#define MSM_PARAM_TIMESTAMP 0x05 - -struct drm_msm_param { - __u32 pipe; /* in, MSM_PIPE_x */ - __u32 param; /* in, MSM_PARAM_x */ - __u64 value; /* out (get_param) or in (set_param) */ -}; - -/* - * GEM buffers: - */ - -#define MSM_BO_SCANOUT 0x00000001 /* scanout capable */ -#define MSM_BO_GPU_READONLY 0x00000002 -#define MSM_BO_CACHE_MASK 0x000f0000 -/* cache modes */ -#define MSM_BO_CACHED 0x00010000 -#define MSM_BO_WC 0x00020000 -#define MSM_BO_UNCACHED 0x00040000 - -#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ - MSM_BO_GPU_READONLY | \ - MSM_BO_CACHED | \ - MSM_BO_WC | \ - MSM_BO_UNCACHED) - -struct drm_msm_gem_new { - __u64 size; /* in */ - __u32 flags; /* in, mask of MSM_BO_x */ - __u32 handle; /* out */ -}; - -struct drm_msm_gem_info { - __u32 handle; /* in */ - __u32 pad; - __u64 offset; /* out, offset to pass to mmap() */ -}; - -#define MSM_PREP_READ 0x01 -#define MSM_PREP_WRITE 0x02 -#define MSM_PREP_NOSYNC 0x04 - -#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) - -struct drm_msm_gem_cpu_prep { - __u32 handle; /* in */ - __u32 op; /* in, mask of MSM_PREP_x */ - struct drm_msm_timespec timeout; /* in */ -}; - -struct drm_msm_gem_cpu_fini { - __u32 handle; /* in */ -}; - -/* - * Cmdstream Submission: - */ - -/* The value written into the cmdstream is logically: - * - * ((relocbuf->gpuaddr + reloc_offset) << shift) | or - * - * When we have GPU's w/ >32bit ptrs, it should be possible to deal - * with this by emit'ing two reloc entries with appropriate shift - * values. Or a new MSM_SUBMIT_CMD_x type would also be an option. - * - * NOTE that reloc's must be sorted by order of increasing submit_offset, - * otherwise EINVAL. - */ -struct drm_msm_gem_submit_reloc { - __u32 submit_offset; /* in, offset from submit_bo */ - __u32 or; /* in, value OR'd with result */ - __s32 shift; /* in, amount of left shift (can be negative) */ - __u32 reloc_idx; /* in, index of reloc_bo buffer */ - __u64 reloc_offset; /* in, offset from start of reloc_bo */ -}; - -/* submit-types: - * BUF - this cmd buffer is executed normally. - * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are - * processed normally, but the kernel does not setup an IB to - * this buffer in the first-level ringbuffer - * CTX_RESTORE_BUF - only executed if there has been a GPU context - * switch since the last SUBMIT ioctl - */ -#define MSM_SUBMIT_CMD_BUF 0x0001 -#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 -#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 -struct drm_msm_gem_submit_cmd { - __u32 type; /* in, one of MSM_SUBMIT_CMD_x */ - __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */ - __u32 submit_offset; /* in, offset into submit_bo */ - __u32 size; /* in, cmdstream size */ - __u32 pad; - __u32 nr_relocs; /* in, number of submit_reloc's */ - __u64 relocs; /* in, ptr to array of submit_reloc's */ -}; - -/* Each buffer referenced elsewhere in the cmdstream submit (ie. the - * cmdstream buffer(s) themselves or reloc entries) has one (and only - * one) entry in the submit->bos[] table. - * - * As a optimization, the current buffer (gpu virtual address) can be - * passed back through the 'presumed' field. If on a subsequent reloc, - * userspace passes back a 'presumed' address that is still valid, - * then patching the cmdstream for this entry is skipped. This can - * avoid kernel needing to map/access the cmdstream bo in the common - * case. - */ -#define MSM_SUBMIT_BO_READ 0x0001 -#define MSM_SUBMIT_BO_WRITE 0x0002 - -#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) - -struct drm_msm_gem_submit_bo { - __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */ - __u32 handle; /* in, GEM handle */ - __u64 presumed; /* in/out, presumed buffer address */ -}; - -/* Valid submit ioctl flags: */ -#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */ -#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */ -#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */ -#define MSM_SUBMIT_FLAGS ( \ - MSM_SUBMIT_NO_IMPLICIT | \ - MSM_SUBMIT_FENCE_FD_IN | \ - MSM_SUBMIT_FENCE_FD_OUT | \ - 0) - -/* Each cmdstream submit consists of a table of buffers involved, and - * one or more cmdstream buffers. This allows for conditional execution - * (context-restore), and IB buffers needed for per tile/bin draw cmds. - */ -struct drm_msm_gem_submit { - __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ - __u32 fence; /* out */ - __u32 nr_bos; /* in, number of submit_bo's */ - __u32 nr_cmds; /* in, number of submit_cmd's */ - __u64 bos; /* in, ptr to array of submit_bo's */ - __u64 cmds; /* in, ptr to array of submit_cmd's */ - __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ -}; - -/* The normal way to synchronize with the GPU is just to CPU_PREP on - * a buffer if you need to access it from the CPU (other cmdstream - * submission from same or other contexts, PAGE_FLIP ioctl, etc, all - * handle the required synchronization under the hood). This ioctl - * mainly just exists as a way to implement the gallium pipe_fence - * APIs without requiring a dummy bo to synchronize on. - */ -struct drm_msm_wait_fence { - __u32 fence; /* in */ - __u32 pad; - struct drm_msm_timespec timeout; /* in */ -}; - -/* madvise provides a way to tell the kernel in case a buffers contents - * can be discarded under memory pressure, which is useful for userspace - * bo cache where we want to optimistically hold on to buffer allocate - * and potential mmap, but allow the pages to be discarded under memory - * pressure. - * - * Typical usage would involve madvise(DONTNEED) when buffer enters BO - * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache. - * In the WILLNEED case, 'retained' indicates to userspace whether the - * backing pages still exist. - */ -#define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */ -#define MSM_MADV_DONTNEED 1 /* backing pages not needed */ -#define __MSM_MADV_PURGED 2 /* internal state */ - -struct drm_msm_gem_madvise { - __u32 handle; /* in, GEM handle */ - __u32 madv; /* in, MSM_MADV_x */ - __u32 retained; /* out, whether backing store still exists */ -}; - -/* HDR WRGB x and y index */ -#define DISPLAY_PRIMARIES_WX 0 -#define DISPLAY_PRIMARIES_WY 1 -#define DISPLAY_PRIMARIES_RX 2 -#define DISPLAY_PRIMARIES_RY 3 -#define DISPLAY_PRIMARIES_GX 4 -#define DISPLAY_PRIMARIES_GY 5 -#define DISPLAY_PRIMARIES_BX 6 -#define DISPLAY_PRIMARIES_BY 7 -#define DISPLAY_PRIMARIES_MAX 8 - -struct drm_panel_hdr_properties { - __u32 hdr_enabled; - - /* WRGB X and y values arrayed in format */ - /* [WX, WY, RX, RY, GX, GY, BX, BY] */ - __u32 display_primaries[DISPLAY_PRIMARIES_MAX]; - - /* peak brightness supported by panel */ - __u32 peak_brightness; - /* Blackness level supported by panel */ - __u32 blackness_level; -}; - -/** - * struct drm_msm_event_req - Payload to event enable/disable ioctls. - * @object_id: DRM object id. e.g.: for crtc pass crtc id. - * @object_type: DRM object type. e.g.: for crtc set it to DRM_MODE_OBJECT_CRTC. - * @event: Event for which notification is being enabled/disabled. - * e.g.: for Histogram set - DRM_EVENT_HISTOGRAM. - * @client_context: Opaque pointer that will be returned during event response - * notification. - * @index: Object index(e.g.: crtc index), optional for user-space to set. - * Driver will override value based on object_id and object_type. - */ -struct drm_msm_event_req { - __u32 object_id; - __u32 object_type; - __u32 event; - __u64 client_context; - __u32 index; -}; - -/** - * struct drm_msm_event_resp - payload returned when read is called for - * custom notifications. - * @base: Event type and length of complete notification payload. - * @info: Contains information about DRM that which raised this event. - * @data: Custom payload that driver returns for event type. - * size of data = base.length - (sizeof(base) + sizeof(info)) - */ -struct drm_msm_event_resp { - struct drm_event base; - struct drm_msm_event_req info; - __u8 data[]; -}; - -#define DRM_MSM_GET_PARAM 0x00 -/* placeholder: -#define DRM_MSM_SET_PARAM 0x01 - */ -#define DRM_MSM_GEM_NEW 0x02 -#define DRM_MSM_GEM_INFO 0x03 -#define DRM_MSM_GEM_CPU_PREP 0x04 -#define DRM_MSM_GEM_CPU_FINI 0x05 -#define DRM_MSM_GEM_SUBMIT 0x06 -#define DRM_MSM_WAIT_FENCE 0x07 -#define DRM_MSM_GEM_MADVISE 0x08 - -#define DRM_SDE_WB_CONFIG 0x40 -#define DRM_MSM_REGISTER_EVENT 0x41 -#define DRM_MSM_DEREGISTER_EVENT 0x42 -#define DRM_MSM_RMFB2 0x43 - -/* sde custom events */ -#define DRM_EVENT_HISTOGRAM 0x80000000 -#define DRM_EVENT_AD_BACKLIGHT 0x80000001 -#define DRM_EVENT_CRTC_POWER 0x80000002 -#define DRM_EVENT_SYS_BACKLIGHT 0x80000003 -#define DRM_EVENT_SDE_POWER 0x80000004 -#define DRM_EVENT_IDLE_NOTIFY 0x80000005 -#define DRM_EVENT_PANEL_DEAD 0x80000006 /* ESD event */ - -#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) -#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) -#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) -#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) -#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) -#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) -#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) -#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) -#define DRM_IOCTL_SDE_WB_CONFIG \ - DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg) -#define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \ - DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req) -#define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \ - DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req) -#define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + \ - DRM_MSM_RMFB2), unsigned int) - -#if defined(__cplusplus) -} -#endif - -#endif /* __MSM_DRM_H__ */ diff --git a/sdm710/original-kernel-headers/drm/msm_drm_pp.h b/sdm710/original-kernel-headers/drm/msm_drm_pp.h deleted file mode 100644 index 38f710ec..00000000 --- a/sdm710/original-kernel-headers/drm/msm_drm_pp.h +++ /dev/null @@ -1,439 +0,0 @@ -#ifndef _MSM_DRM_PP_H_ -#define _MSM_DRM_PP_H_ - -#include <linux/types.h> -/** - * struct drm_msm_pcc_coeff - PCC coefficient structure for each color - * component. - * @c: constant coefficient. - * @r: red coefficient. - * @g: green coefficient. - * @b: blue coefficient. - * @rg: red green coefficient. - * @gb: green blue coefficient. - * @rb: red blue coefficient. - * @rgb: red blue green coefficient. - */ - -struct drm_msm_pcc_coeff { - __u32 c; - __u32 r; - __u32 g; - __u32 b; - __u32 rg; - __u32 gb; - __u32 rb; - __u32 rgb; -}; - -/** - * struct drm_msm_pcc - pcc feature structure - * @flags: for customizing operations - * @r: red coefficients. - * @g: green coefficients. - * @b: blue coefficients. - * @r_rr: second order coefficients - * @r_gg: second order coefficients - * @r_bb: second order coefficients - * @g_rr: second order coefficients - * @g_gg: second order coefficients - * @g_bb: second order coefficients - * @b_rr: second order coefficients - * @b_gg: second order coefficients - * @b_bb: second order coefficients - */ -#define DRM_MSM_PCC3 -struct drm_msm_pcc { - __u64 flags; - struct drm_msm_pcc_coeff r; - struct drm_msm_pcc_coeff g; - struct drm_msm_pcc_coeff b; - __u32 r_rr; - __u32 r_gg; - __u32 r_bb; - __u32 g_rr; - __u32 g_gg; - __u32 g_bb; - __u32 b_rr; - __u32 b_gg; - __u32 b_bb; -}; - -/* struct drm_msm_pa_vlut - picture adjustment vLUT structure - * flags: for customizing vlut operation - * val: vLUT values - */ -#define PA_VLUT_SIZE 256 -struct drm_msm_pa_vlut { - __u64 flags; - __u32 val[PA_VLUT_SIZE]; -}; - -#define PA_HSIC_HUE_ENABLE (1 << 0) -#define PA_HSIC_SAT_ENABLE (1 << 1) -#define PA_HSIC_VAL_ENABLE (1 << 2) -#define PA_HSIC_CONT_ENABLE (1 << 3) -/** - * struct drm_msm_pa_hsic - pa hsic feature structure - * @flags: flags for the feature customization, values can be: - * - PA_HSIC_HUE_ENABLE: Enable hue adjustment - * - PA_HSIC_SAT_ENABLE: Enable saturation adjustment - * - PA_HSIC_VAL_ENABLE: Enable value adjustment - * - PA_HSIC_CONT_ENABLE: Enable contrast adjustment - * - * @hue: hue setting - * @saturation: saturation setting - * @value: value setting - * @contrast: contrast setting - */ -#define DRM_MSM_PA_HSIC -struct drm_msm_pa_hsic { - __u64 flags; - __u32 hue; - __u32 saturation; - __u32 value; - __u32 contrast; -}; - -#define MEMCOL_PROT_HUE (1 << 0) -#define MEMCOL_PROT_SAT (1 << 1) -#define MEMCOL_PROT_VAL (1 << 2) -#define MEMCOL_PROT_CONT (1 << 3) -#define MEMCOL_PROT_SIXZONE (1 << 4) -#define MEMCOL_PROT_BLEND (1 << 5) -/* struct drm_msm_memcol - Memory color feature structure. - * Skin, sky, foliage features are supported. - * @prot_flags: Bit mask for enabling protection feature. - * @color_adjust_p0: Adjustment curve. - * @color_adjust_p1: Adjustment curve. - * @color_adjust_p2: Adjustment curve. - * @blend_gain: Blend gain weightage from othe PA features. - * @sat_hold: Saturation hold value. - * @val_hold: Value hold info. - * @hue_region: Hue qualifier. - * @sat_region: Saturation qualifier. - * @val_region: Value qualifier. - */ -#define DRM_MSM_MEMCOL -struct drm_msm_memcol { - __u64 prot_flags; - __u32 color_adjust_p0; - __u32 color_adjust_p1; - __u32 color_adjust_p2; - __u32 blend_gain; - __u32 sat_hold; - __u32 val_hold; - __u32 hue_region; - __u32 sat_region; - __u32 val_region; -}; - -#define DRM_MSM_SIXZONE -#define SIXZONE_LUT_SIZE 384 -#define SIXZONE_HUE_ENABLE (1 << 0) -#define SIXZONE_SAT_ENABLE (1 << 1) -#define SIXZONE_VAL_ENABLE (1 << 2) -/* struct drm_msm_sixzone_curve - Sixzone HSV adjustment curve structure. - * @p0: Hue adjustment. - * @p1: Saturation/Value adjustment. - */ -struct drm_msm_sixzone_curve { - __u32 p1; - __u32 p0; -}; - -/* struct drm_msm_sixzone - Sixzone feature structure. - * @flags: for feature customization, values can be: - * - SIXZONE_HUE_ENABLE: Enable hue adjustment - * - SIXZONE_SAT_ENABLE: Enable saturation adjustment - * - SIXZONE_VAL_ENABLE: Enable value adjustment - * @threshold: threshold qualifier. - * @adjust_p0: Adjustment curve. - * @adjust_p1: Adjustment curve. - * @sat_hold: Saturation hold info. - * @val_hold: Value hold info. - * @curve: HSV adjustment curve lut. - */ -struct drm_msm_sixzone { - __u64 flags; - __u32 threshold; - __u32 adjust_p0; - __u32 adjust_p1; - __u32 sat_hold; - __u32 val_hold; - struct drm_msm_sixzone_curve curve[SIXZONE_LUT_SIZE]; -}; - -#define GAMUT_3D_MODE_17 1 -#define GAMUT_3D_MODE_5 2 -#define GAMUT_3D_MODE_13 3 - -#define GAMUT_3D_MODE17_TBL_SZ 1229 -#define GAMUT_3D_MODE5_TBL_SZ 32 -#define GAMUT_3D_MODE13_TBL_SZ 550 -#define GAMUT_3D_SCALE_OFF_SZ 16 -#define GAMUT_3D_SCALEB_OFF_SZ 12 -#define GAMUT_3D_TBL_NUM 4 -#define GAMUT_3D_SCALE_OFF_TBL_NUM 3 -#define GAMUT_3D_MAP_EN (1 << 0) - -/** - * struct drm_msm_3d_col - 3d gamut color component structure - * @c0: Holds c0 value - * @c2_c1: Holds c2/c1 values - */ -struct drm_msm_3d_col { - __u32 c2_c1; - __u32 c0; -}; -/** - * struct drm_msm_3d_gamut - 3d gamut feature structure - * @flags: flags for the feature values are: - * 0 - no map - * GAMUT_3D_MAP_EN - enable map - * @mode: lut mode can take following values: - * - GAMUT_3D_MODE_17 - * - GAMUT_3D_MODE_5 - * - GAMUT_3D_MODE_13 - * @scale_off: Scale offset table - * @col: Color component tables - */ -struct drm_msm_3d_gamut { - __u64 flags; - __u32 mode; - __u32 scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ]; - struct drm_msm_3d_col col[GAMUT_3D_TBL_NUM][GAMUT_3D_MODE17_TBL_SZ]; -}; - -#define PGC_TBL_LEN 512 -#define PGC_8B_ROUND (1 << 0) -/** - * struct drm_msm_pgc_lut - pgc lut feature structure - * @flags: flags for the featue values can be: - * - PGC_8B_ROUND - * @c0: color0 component lut - * @c1: color1 component lut - * @c2: color2 component lut - */ -struct drm_msm_pgc_lut { - __u64 flags; - __u32 c0[PGC_TBL_LEN]; - __u32 c1[PGC_TBL_LEN]; - __u32 c2[PGC_TBL_LEN]; -}; - -#define IGC_TBL_LEN 256 -#define IGC_DITHER_ENABLE (1 << 0) -/** - * struct drm_msm_igc_lut - igc lut feature structure - * @flags: flags for the feature customization, values can be: - * - IGC_DITHER_ENABLE: Enable dither functionality - * @c0: color0 component lut - * @c1: color1 component lut - * @c2: color2 component lut - * @strength: dither strength, considered valid when IGC_DITHER_ENABLE - * is set in flags. Strength value based on source bit width. - */ -struct drm_msm_igc_lut { - __u64 flags; - __u32 c0[IGC_TBL_LEN]; - __u32 c1[IGC_TBL_LEN]; - __u32 c2[IGC_TBL_LEN]; - __u32 strength; -}; - -#define HIST_V_SIZE 256 -/** - * struct drm_msm_hist - histogram feature structure - * @flags: for customizing operations - * @data: histogram data - */ -struct drm_msm_hist { - __u64 flags; - __u32 data[HIST_V_SIZE]; -}; - -#define AD4_LUT_GRP0_SIZE 33 -#define AD4_LUT_GRP1_SIZE 32 -/* - * struct drm_msm_ad4_init - ad4 init structure set by user-space client. - * Init param values can change based on tuning - * hence it is passed by user-space clients. - */ -struct drm_msm_ad4_init { - __u32 init_param_001[AD4_LUT_GRP0_SIZE]; - __u32 init_param_002[AD4_LUT_GRP0_SIZE]; - __u32 init_param_003[AD4_LUT_GRP0_SIZE]; - __u32 init_param_004[AD4_LUT_GRP0_SIZE]; - __u32 init_param_005[AD4_LUT_GRP1_SIZE]; - __u32 init_param_006[AD4_LUT_GRP1_SIZE]; - __u32 init_param_007[AD4_LUT_GRP0_SIZE]; - __u32 init_param_008[AD4_LUT_GRP0_SIZE]; - __u32 init_param_009; - __u32 init_param_010; - __u32 init_param_011; - __u32 init_param_012; - __u32 init_param_013; - __u32 init_param_014; - __u32 init_param_015; - __u32 init_param_016; - __u32 init_param_017; - __u32 init_param_018; - __u32 init_param_019; - __u32 init_param_020; - __u32 init_param_021; - __u32 init_param_022; - __u32 init_param_023; - __u32 init_param_024; - __u32 init_param_025; - __u32 init_param_026; - __u32 init_param_027; - __u32 init_param_028; - __u32 init_param_029; - __u32 init_param_030; - __u32 init_param_031; - __u32 init_param_032; - __u32 init_param_033; - __u32 init_param_034; - __u32 init_param_035; - __u32 init_param_036; - __u32 init_param_037; - __u32 init_param_038; - __u32 init_param_039; - __u32 init_param_040; - __u32 init_param_041; - __u32 init_param_042; - __u32 init_param_043; - __u32 init_param_044; - __u32 init_param_045; - __u32 init_param_046; - __u32 init_param_047; - __u32 init_param_048; - __u32 init_param_049; - __u32 init_param_050; - __u32 init_param_051; - __u32 init_param_052; - __u32 init_param_053; - __u32 init_param_054; - __u32 init_param_055; - __u32 init_param_056; - __u32 init_param_057; - __u32 init_param_058; - __u32 init_param_059; - __u32 init_param_060; - __u32 init_param_061; - __u32 init_param_062; - __u32 init_param_063; - __u32 init_param_064; - __u32 init_param_065; - __u32 init_param_066; - __u32 init_param_067; - __u32 init_param_068; - __u32 init_param_069; - __u32 init_param_070; - __u32 init_param_071; - __u32 init_param_072; - __u32 init_param_073; - __u32 init_param_074; - __u32 init_param_075; -}; - -/* - * struct drm_msm_ad4_cfg - ad4 config structure set by user-space client. - * Config param values can vary based on tuning, - * hence it is passed by user-space clients. - */ -struct drm_msm_ad4_cfg { - __u32 cfg_param_001; - __u32 cfg_param_002; - __u32 cfg_param_003; - __u32 cfg_param_004; - __u32 cfg_param_005; - __u32 cfg_param_006; - __u32 cfg_param_007; - __u32 cfg_param_008; - __u32 cfg_param_009; - __u32 cfg_param_010; - __u32 cfg_param_011; - __u32 cfg_param_012; - __u32 cfg_param_013; - __u32 cfg_param_014; - __u32 cfg_param_015; - __u32 cfg_param_016; - __u32 cfg_param_017; - __u32 cfg_param_018; - __u32 cfg_param_019; - __u32 cfg_param_020; - __u32 cfg_param_021; - __u32 cfg_param_022; - __u32 cfg_param_023; - __u32 cfg_param_024; - __u32 cfg_param_025; - __u32 cfg_param_026; - __u32 cfg_param_027; - __u32 cfg_param_028; - __u32 cfg_param_029; - __u32 cfg_param_030; - __u32 cfg_param_031; - __u32 cfg_param_032; - __u32 cfg_param_033; - __u32 cfg_param_034; - __u32 cfg_param_035; - __u32 cfg_param_036; - __u32 cfg_param_037; - __u32 cfg_param_038; - __u32 cfg_param_039; - __u32 cfg_param_040; - __u32 cfg_param_041; - __u32 cfg_param_042; - __u32 cfg_param_043; - __u32 cfg_param_044; - __u32 cfg_param_045; - __u32 cfg_param_046; - __u32 cfg_param_047; - __u32 cfg_param_048; - __u32 cfg_param_049; - __u32 cfg_param_050; - __u32 cfg_param_051; - __u32 cfg_param_052; - __u32 cfg_param_053; -}; - -#define DITHER_MATRIX_SZ 16 - -/** - * struct drm_msm_dither - dither feature structure - * @flags: for customizing operations - * @temporal_en: temperal dither enable - * @c0_bitdepth: c0 component bit depth - * @c1_bitdepth: c1 component bit depth - * @c2_bitdepth: c2 component bit depth - * @c3_bitdepth: c2 component bit depth - * @matrix: dither strength matrix - */ -struct drm_msm_dither { - __u64 flags; - __u32 temporal_en; - __u32 c0_bitdepth; - __u32 c1_bitdepth; - __u32 c2_bitdepth; - __u32 c3_bitdepth; - __u32 matrix[DITHER_MATRIX_SZ]; -}; - -/** - * struct drm_msm_pa_dither - dspp dither feature structure - * @flags: for customizing operations - * @strength: dither strength - * @offset_en: offset enable bit - * @matrix: dither data matrix - */ -#define DRM_MSM_PA_DITHER -struct drm_msm_pa_dither { - __u64 flags; - __u32 strength; - __u32 offset_en; - __u32 matrix[DITHER_MATRIX_SZ]; -}; - -#endif /* _MSM_DRM_PP_H_ */ diff --git a/sdm710/original-kernel-headers/drm/sde_drm.h b/sdm710/original-kernel-headers/drm/sde_drm.h deleted file mode 100644 index 1a43659a..00000000 --- a/sdm710/original-kernel-headers/drm/sde_drm.h +++ /dev/null @@ -1,449 +0,0 @@ -#ifndef _SDE_DRM_H_ -#define _SDE_DRM_H_ - -#include "drm.h" - -/* Total number of supported color planes */ -#define SDE_MAX_PLANES 4 - -/* Total number of parameterized detail enhancer mapping curves */ -#define SDE_MAX_DE_CURVES 3 - - /* Y/RGB and UV filter configuration */ -#define FILTER_EDGE_DIRECTED_2D 0x0 -#define FILTER_CIRCULAR_2D 0x1 -#define FILTER_SEPARABLE_1D 0x2 -#define FILTER_BILINEAR 0x3 - -/* Alpha filters */ -#define FILTER_ALPHA_DROP_REPEAT 0x0 -#define FILTER_ALPHA_BILINEAR 0x1 -#define FILTER_ALPHA_2D 0x3 - -/* Blend filters */ -#define FILTER_BLEND_CIRCULAR_2D 0x0 -#define FILTER_BLEND_SEPARABLE_1D 0x1 - -/* LUT configuration flags */ -#define SCALER_LUT_SWAP 0x1 -#define SCALER_LUT_DIR_WR 0x2 -#define SCALER_LUT_Y_CIR_WR 0x4 -#define SCALER_LUT_UV_CIR_WR 0x8 -#define SCALER_LUT_Y_SEP_WR 0x10 -#define SCALER_LUT_UV_SEP_WR 0x20 - -/** - * Blend operations for "blend_op" property - * - * @SDE_DRM_BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. - * @SDE_DRM_BLEND_OP_OPAQUE: Apply a constant blend operation. The layer - * would appear opaque in case fg plane alpha - * is 0xff. - * @SDE_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already - * has alpha pre-multiplication done. If the fg - * plane alpha is less than 0xff, apply - * modulation as well. This operation is - * intended on layers having alpha channel. - * @SDE_DRM_BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not - * alpha pre-multiplied. Apply - * pre-multiplication. If fg plane alpha is - * less than 0xff, apply modulation as well. - * @SDE_DRM_BLEND_OP_MAX: Used to track maximum blend operation - * possible by mdp. - */ -#define SDE_DRM_BLEND_OP_NOT_DEFINED 0 -#define SDE_DRM_BLEND_OP_OPAQUE 1 -#define SDE_DRM_BLEND_OP_PREMULTIPLIED 2 -#define SDE_DRM_BLEND_OP_COVERAGE 3 -#define SDE_DRM_BLEND_OP_MAX 4 - -/** - * Bit masks for "src_config" property - * construct bitmask via (1UL << SDE_DRM_<flag>) - */ -#define SDE_DRM_DEINTERLACE 0 /* Specifies interlaced input */ - -/* DRM bitmasks are restricted to 0..63 */ -#define SDE_DRM_BITMASK_COUNT 64 - -/** - * Framebuffer modes for "fb_translation_mode" PLANE and CONNECTOR property - * - * @SDE_DRM_FB_NON_SEC: IOMMU configuration for this framebuffer mode - * is non-secure domain and requires - * both stage I and stage II translations when - * this buffer is accessed by the display HW. - * This is the default mode of all frambuffers. - * @SDE_DRM_FB_SEC: IOMMU configuration for this framebuffer mode - * is secure domain and requires - * both stage I and stage II translations when - * this buffer is accessed by the display HW. - * @SDE_DRM_FB_NON_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode - * is non-secure domain and requires - * only stage II translation when - * this buffer is accessed by the display HW. - * @SDE_DRM_FB_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode - * is secure domain and requires - * only stage II translation when - * this buffer is accessed by the display HW. - */ - -#define SDE_DRM_FB_NON_SEC 0 -#define SDE_DRM_FB_SEC 1 -#define SDE_DRM_FB_NON_SEC_DIR_TRANS 2 -#define SDE_DRM_FB_SEC_DIR_TRANS 3 - -/** - * Secure levels for "security_level" CRTC property. - * CRTC property which specifies what plane types - * can be attached to this CRTC. Plane component - * derives the plane type based on the FB_MODE. - * @ SDE_DRM_SEC_NON_SEC: Both Secure and non-secure plane types can be - * attached to this CRTC. This is the default state of - * the CRTC. - * @ SDE_DRM_SEC_ONLY: Only secure planes can be added to this CRTC. If a - * CRTC is instructed to be in this mode it follows the - * platform dependent restrictions. - */ -#define SDE_DRM_SEC_NON_SEC 0 -#define SDE_DRM_SEC_ONLY 1 - -/** - * struct sde_drm_pix_ext_v1 - version 1 of pixel ext structure - * @num_ext_pxls_lr: Number of total horizontal pixels - * @num_ext_pxls_tb: Number of total vertical lines - * @left_ftch: Number of extra pixels to overfetch from left - * @right_ftch: Number of extra pixels to overfetch from right - * @top_ftch: Number of extra lines to overfetch from top - * @btm_ftch: Number of extra lines to overfetch from bottom - * @left_rpt: Number of extra pixels to repeat from left - * @right_rpt: Number of extra pixels to repeat from right - * @top_rpt: Number of extra lines to repeat from top - * @btm_rpt: Number of extra lines to repeat from bottom - */ -struct sde_drm_pix_ext_v1 { - /* - * Number of pixels ext in left, right, top and bottom direction - * for all color components. - */ - int32_t num_ext_pxls_lr[SDE_MAX_PLANES]; - int32_t num_ext_pxls_tb[SDE_MAX_PLANES]; - - /* - * Number of pixels needs to be overfetched in left, right, top - * and bottom directions from source image for scaling. - */ - int32_t left_ftch[SDE_MAX_PLANES]; - int32_t right_ftch[SDE_MAX_PLANES]; - int32_t top_ftch[SDE_MAX_PLANES]; - int32_t btm_ftch[SDE_MAX_PLANES]; - /* - * Number of pixels needs to be repeated in left, right, top and - * bottom directions for scaling. - */ - int32_t left_rpt[SDE_MAX_PLANES]; - int32_t right_rpt[SDE_MAX_PLANES]; - int32_t top_rpt[SDE_MAX_PLANES]; - int32_t btm_rpt[SDE_MAX_PLANES]; - -}; - -/** - * struct sde_drm_scaler_v1 - version 1 of struct sde_drm_scaler - * @lr: Pixel extension settings for left/right - * @tb: Pixel extension settings for top/botton - * @init_phase_x: Initial scaler phase values for x - * @phase_step_x: Phase step values for x - * @init_phase_y: Initial scaler phase values for y - * @phase_step_y: Phase step values for y - * @horz_filter: Horizontal filter array - * @vert_filter: Vertical filter array - */ -struct sde_drm_scaler_v1 { - /* - * Pix ext settings - */ - struct sde_drm_pix_ext_v1 pe; - /* - * Phase settings - */ - int32_t init_phase_x[SDE_MAX_PLANES]; - int32_t phase_step_x[SDE_MAX_PLANES]; - int32_t init_phase_y[SDE_MAX_PLANES]; - int32_t phase_step_y[SDE_MAX_PLANES]; - - /* - * Filter type to be used for scaling in horizontal and vertical - * directions - */ - uint32_t horz_filter[SDE_MAX_PLANES]; - uint32_t vert_filter[SDE_MAX_PLANES]; -}; - -/** - * struct sde_drm_de_v1 - version 1 of detail enhancer structure - * @enable: Enables/disables detail enhancer - * @sharpen_level1: Sharpening strength for noise - * @sharpen_level2: Sharpening strength for context - * @clip: Clip coefficient - * @limit: Detail enhancer limit factor - * @thr_quiet: Quite zone threshold - * @thr_dieout: Die-out zone threshold - * @thr_low: Linear zone left threshold - * @thr_high: Linear zone right threshold - * @prec_shift: Detail enhancer precision - * @adjust_a: Mapping curves A coefficients - * @adjust_b: Mapping curves B coefficients - * @adjust_c: Mapping curves C coefficients - */ -struct sde_drm_de_v1 { - uint32_t enable; - int16_t sharpen_level1; - int16_t sharpen_level2; - uint16_t clip; - uint16_t limit; - uint16_t thr_quiet; - uint16_t thr_dieout; - uint16_t thr_low; - uint16_t thr_high; - uint16_t prec_shift; - int16_t adjust_a[SDE_MAX_DE_CURVES]; - int16_t adjust_b[SDE_MAX_DE_CURVES]; - int16_t adjust_c[SDE_MAX_DE_CURVES]; -}; - -/** - * struct sde_drm_scaler_v2 - version 2 of struct sde_drm_scaler - * @enable: Scaler enable - * @dir_en: Detail enhancer enable - * @pe: Pixel extension settings - * @horz_decimate: Horizontal decimation factor - * @vert_decimate: Vertical decimation factor - * @init_phase_x: Initial scaler phase values for x - * @phase_step_x: Phase step values for x - * @init_phase_y: Initial scaler phase values for y - * @phase_step_y: Phase step values for y - * @preload_x: Horizontal preload value - * @preload_y: Vertical preload value - * @src_width: Source width - * @src_height: Source height - * @dst_width: Destination width - * @dst_height: Destination height - * @y_rgb_filter_cfg: Y/RGB plane filter configuration - * @uv_filter_cfg: UV plane filter configuration - * @alpha_filter_cfg: Alpha filter configuration - * @blend_cfg: Selection of blend coefficients - * @lut_flag: LUT configuration flags - * @dir_lut_idx: 2d 4x4 LUT index - * @y_rgb_cir_lut_idx: Y/RGB circular LUT index - * @uv_cir_lut_idx: UV circular LUT index - * @y_rgb_sep_lut_idx: Y/RGB separable LUT index - * @uv_sep_lut_idx: UV separable LUT index - * @de: Detail enhancer settings - */ -struct sde_drm_scaler_v2 { - /* - * General definitions - */ - uint32_t enable; - uint32_t dir_en; - - /* - * Pix ext settings - */ - struct sde_drm_pix_ext_v1 pe; - - /* - * Decimation settings - */ - uint32_t horz_decimate; - uint32_t vert_decimate; - - /* - * Phase settings - */ - int32_t init_phase_x[SDE_MAX_PLANES]; - int32_t phase_step_x[SDE_MAX_PLANES]; - int32_t init_phase_y[SDE_MAX_PLANES]; - int32_t phase_step_y[SDE_MAX_PLANES]; - - uint32_t preload_x[SDE_MAX_PLANES]; - uint32_t preload_y[SDE_MAX_PLANES]; - uint32_t src_width[SDE_MAX_PLANES]; - uint32_t src_height[SDE_MAX_PLANES]; - - uint32_t dst_width; - uint32_t dst_height; - - uint32_t y_rgb_filter_cfg; - uint32_t uv_filter_cfg; - uint32_t alpha_filter_cfg; - uint32_t blend_cfg; - - uint32_t lut_flag; - uint32_t dir_lut_idx; - - /* for Y(RGB) and UV planes*/ - uint32_t y_rgb_cir_lut_idx; - uint32_t uv_cir_lut_idx; - uint32_t y_rgb_sep_lut_idx; - uint32_t uv_sep_lut_idx; - - /* - * Detail enhancer settings - */ - struct sde_drm_de_v1 de; -}; - -/* Number of dest scalers supported */ -#define SDE_MAX_DS_COUNT 2 - -/* - * Destination scaler flag config - */ -#define SDE_DRM_DESTSCALER_ENABLE 0x1 -#define SDE_DRM_DESTSCALER_SCALE_UPDATE 0x2 -#define SDE_DRM_DESTSCALER_ENHANCER_UPDATE 0x4 -#define SDE_DRM_DESTSCALER_PU_ENABLE 0x8 - -/** - * struct sde_drm_dest_scaler_cfg - destination scaler config structure - * @flags: Flag to switch between mode for destination scaler - * refer to destination scaler flag config - * @index: Destination scaler selection index - * @lm_width: Layer mixer width configuration - * @lm_height: Layer mixer height configuration - * @scaler_cfg: The scaling parameters for all the mode except disable - * Userspace pointer to struct sde_drm_scaler_v2 - */ -struct sde_drm_dest_scaler_cfg { - uint32_t flags; - uint32_t index; - uint32_t lm_width; - uint32_t lm_height; - uint64_t scaler_cfg; -}; - -/** - * struct sde_drm_dest_scaler_data - destination scaler data struct - * @num_dest_scaler: Number of dest scalers to be configured - * @ds_cfg: Destination scaler block configuration - */ -struct sde_drm_dest_scaler_data { - uint32_t num_dest_scaler; - struct sde_drm_dest_scaler_cfg ds_cfg[SDE_MAX_DS_COUNT]; -}; - -/* - * Define constants for struct sde_drm_csc - */ -#define SDE_CSC_MATRIX_COEFF_SIZE 9 -#define SDE_CSC_CLAMP_SIZE 6 -#define SDE_CSC_BIAS_SIZE 3 - -/** - * struct sde_drm_csc_v1 - version 1 of struct sde_drm_csc - * @ctm_coeff: Matrix coefficients, in S31.32 format - * @pre_bias: Pre-bias array values - * @post_bias: Post-bias array values - * @pre_clamp: Pre-clamp array values - * @post_clamp: Post-clamp array values - */ -struct sde_drm_csc_v1 { - int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE]; - uint32_t pre_bias[SDE_CSC_BIAS_SIZE]; - uint32_t post_bias[SDE_CSC_BIAS_SIZE]; - uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE]; - uint32_t post_clamp[SDE_CSC_CLAMP_SIZE]; -}; - -/** - * struct sde_drm_color - struct to store the color and alpha values - * @color_0: Color 0 value - * @color_1: Color 1 value - * @color_2: Color 2 value - * @color_3: Color 3 value - */ -struct sde_drm_color { - uint32_t color_0; - uint32_t color_1; - uint32_t color_2; - uint32_t color_3; -}; - -/* Total number of supported dim layers */ -#define SDE_MAX_DIM_LAYERS 7 - -/* SDE_DRM_DIM_LAYER_CONFIG_FLAG - flags for Dim Layer */ -/* Color fill inside of the rect, including border */ -#define SDE_DRM_DIM_LAYER_INCLUSIVE 0x1 -/* Color fill outside of the rect, excluding border */ -#define SDE_DRM_DIM_LAYER_EXCLUSIVE 0x2 - -/** - * struct sde_drm_dim_layer - dim layer cfg struct - * @flags: Refer SDE_DRM_DIM_LAYER_CONFIG_FLAG for possible values - * @stage: Blending stage of the dim layer - * @color_fill: Color fill for dim layer - * @rect: Dim layer coordinates - */ -struct sde_drm_dim_layer_cfg { - uint32_t flags; - uint32_t stage; - struct sde_drm_color color_fill; - struct drm_clip_rect rect; -}; - -/** - * struct sde_drm_dim_layer_v1 - version 1 of dim layer struct - * @num_layers: Numer of Dim Layers - * @layer: Dim layer user cfgs ptr for the num_layers - */ -struct sde_drm_dim_layer_v1 { - uint32_t num_layers; - struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS]; -}; - -/* Writeback Config version definition */ -#define SDE_DRM_WB_CFG 0x1 - -/* SDE_DRM_WB_CONFIG_FLAGS - Writeback configuration flags */ -#define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1<<0) - -/** - * struct sde_drm_wb_cfg - Writeback configuration structure - * @flags: see DRM_MSM_WB_CONFIG_FLAGS - * @connector_id: writeback connector identifier - * @count_modes: Count of modes in modes_ptr - * @modes: Pointer to struct drm_mode_modeinfo - */ -struct sde_drm_wb_cfg { - uint32_t flags; - uint32_t connector_id; - uint32_t count_modes; - uint64_t modes; -}; - -#define SDE_MAX_ROI_V1 4 - -/** - * struct sde_drm_roi_v1 - list of regions of interest for a drm object - * @num_rects: number of valid rectangles in the roi array - * @roi: list of roi rectangles - */ -struct sde_drm_roi_v1 { - uint32_t num_rects; - struct drm_clip_rect roi[SDE_MAX_ROI_V1]; -}; - -/** - * Define extended power modes supported by the SDE connectors. - */ -#define SDE_MODE_DPMS_ON 0 -#define SDE_MODE_DPMS_LP1 1 -#define SDE_MODE_DPMS_LP2 2 -#define SDE_MODE_DPMS_STANDBY 3 -#define SDE_MODE_DPMS_SUSPEND 4 -#define SDE_MODE_DPMS_OFF 5 - -#endif /* _SDE_DRM_H_ */ diff --git a/sdm710/original-kernel-headers/linux/avtimer.h b/sdm710/original-kernel-headers/linux/avtimer.h deleted file mode 100644 index cbcd8247..00000000 --- a/sdm710/original-kernel-headers/linux/avtimer.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _AVTIMER_H -#define _AVTIMER_H - -#include <linux/ioctl.h> - -#define MAJOR_NUM 100 - -#define IOCTL_GET_AVTIMER_TICK _IOR(MAJOR_NUM, 0, uint64_t) - -#endif diff --git a/sdm710/original-kernel-headers/linux/ion.h b/sdm710/original-kernel-headers/linux/ion.h deleted file mode 100644 index a042797d..00000000 --- a/sdm710/original-kernel-headers/linux/ion.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * drivers/staging/android/uapi/ion.h - * - * Copyright (C) 2011 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _LINUX_ION_H -#define _LINUX_ION_H - -#include <linux/ioctl.h> -#include <linux/types.h> - -typedef int ion_user_handle_t; - -/** - * enum ion_heap_types - list of all possible types of heaps - * @ION_HEAP_TYPE_SYSTEM: memory allocated via vmalloc - * @ION_HEAP_TYPE_SYSTEM_CONTIG: memory allocated via kmalloc - * @ION_HEAP_TYPE_CARVEOUT: memory allocated from a prereserved - * carveout heap, allocations are physically - * contiguous - * @ION_HEAP_TYPE_DMA: memory allocated via DMA API - * @ION_NUM_HEAPS: helper for iterating over heaps, a bit mask - * is used to identify the heaps, so only 32 - * total heap types are supported - */ -enum ion_heap_type { - ION_HEAP_TYPE_SYSTEM, - ION_HEAP_TYPE_SYSTEM_CONTIG, - ION_HEAP_TYPE_CARVEOUT, - ION_HEAP_TYPE_CHUNK, - ION_HEAP_TYPE_DMA, - ION_HEAP_TYPE_CUSTOM, /* - * must be last so device specific heaps always - * are at the end of this enum - */ - ION_NUM_HEAPS = 16, -}; - -#define ION_HEAP_SYSTEM_MASK ((1 << ION_HEAP_TYPE_SYSTEM)) -#define ION_HEAP_SYSTEM_CONTIG_MASK ((1 << ION_HEAP_TYPE_SYSTEM_CONTIG)) -#define ION_HEAP_CARVEOUT_MASK ((1 << ION_HEAP_TYPE_CARVEOUT)) -#define ION_HEAP_TYPE_DMA_MASK ((1 << ION_HEAP_TYPE_DMA)) - -#define ION_NUM_HEAP_IDS (sizeof(unsigned int) * 8) - -/** - * allocation flags - the lower 16 bits are used by core ion, the upper 16 - * bits are reserved for use by the heaps themselves. - */ -#define ION_FLAG_CACHED 1 /* - * mappings of this buffer should be - * cached, ion will do cache - * maintenance when the buffer is - * mapped for dma - */ -#define ION_FLAG_CACHED_NEEDS_SYNC 2 /* - * mappings of this buffer will created - * at mmap time, if this is set - * caches must be managed - * manually - */ - -/** - * DOC: Ion Userspace API - * - * create a client by opening /dev/ion - * most operations handled via following ioctls - * - */ - -/** - * struct ion_allocation_data - metadata passed from userspace for allocations - * @len: size of the allocation - * @align: required alignment of the allocation - * @heap_id_mask: mask of heap ids to allocate from - * @flags: flags passed to heap - * @handle: pointer that will be populated with a cookie to use to - * refer to this allocation - * - * Provided by userspace as an argument to the ioctl - */ -struct ion_allocation_data { - size_t len; - size_t align; - unsigned int heap_id_mask; - unsigned int flags; - ion_user_handle_t handle; -}; - -/** - * struct ion_fd_data - metadata passed to/from userspace for a handle/fd pair - * @handle: a handle - * @fd: a file descriptor representing that handle - * - * For ION_IOC_SHARE or ION_IOC_MAP userspace populates the handle field with - * the handle returned from ion alloc, and the kernel returns the file - * descriptor to share or map in the fd field. For ION_IOC_IMPORT, userspace - * provides the file descriptor and the kernel returns the handle. - */ -struct ion_fd_data { - ion_user_handle_t handle; - int fd; -}; - -/** - * struct ion_handle_data - a handle passed to/from the kernel - * @handle: a handle - */ -struct ion_handle_data { - ion_user_handle_t handle; -}; - -/** - * struct ion_custom_data - metadata passed to/from userspace for a custom ioctl - * @cmd: the custom ioctl function to call - * @arg: additional data to pass to the custom ioctl, typically a user - * pointer to a predefined structure - * - * This works just like the regular cmd and arg fields of an ioctl. - */ -struct ion_custom_data { - unsigned int cmd; - unsigned long arg; -}; - -#define ION_IOC_MAGIC 'I' - -/** - * DOC: ION_IOC_ALLOC - allocate memory - * - * Takes an ion_allocation_data struct and returns it with the handle field - * populated with the opaque handle for the allocation. - */ -#define ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, \ - struct ion_allocation_data) - -/** - * DOC: ION_IOC_FREE - free memory - * - * Takes an ion_handle_data struct and frees the handle. - */ -#define ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data) - -/** - * DOC: ION_IOC_MAP - get a file descriptor to mmap - * - * Takes an ion_fd_data struct with the handle field populated with a valid - * opaque handle. Returns the struct with the fd field set to a file - * descriptor open in the current address space. This file descriptor - * can then be used as an argument to mmap. - */ -#define ION_IOC_MAP _IOWR(ION_IOC_MAGIC, 2, struct ion_fd_data) - -/** - * DOC: ION_IOC_SHARE - creates a file descriptor to use to share an allocation - * - * Takes an ion_fd_data struct with the handle field populated with a valid - * opaque handle. Returns the struct with the fd field set to a file - * descriptor open in the current address space. This file descriptor - * can then be passed to another process. The corresponding opaque handle can - * be retrieved via ION_IOC_IMPORT. - */ -#define ION_IOC_SHARE _IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data) - -/** - * DOC: ION_IOC_IMPORT - imports a shared file descriptor - * - * Takes an ion_fd_data struct with the fd field populated with a valid file - * descriptor obtained from ION_IOC_SHARE and returns the struct with the handle - * filed set to the corresponding opaque handle. - */ -#define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data) - -/** - * DOC: ION_IOC_SYNC - syncs a shared file descriptors to memory - * - * Deprecated in favor of using the dma_buf api's correctly (syncing - * will happen automatically when the buffer is mapped to a device). - * If necessary should be used after touching a cached buffer from the cpu, - * this will make the buffer in memory coherent. - */ -#define ION_IOC_SYNC _IOWR(ION_IOC_MAGIC, 7, struct ion_fd_data) - -/** - * DOC: ION_IOC_CUSTOM - call architecture specific ion ioctl - * - * Takes the argument of the architecture specific ioctl to call and - * passes appropriate userdata for that ioctl - */ -#define ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data) - -#endif /* _LINUX_ION_H */ diff --git a/sdm710/original-kernel-headers/linux/ipa_qmi_service_v01.h b/sdm710/original-kernel-headers/linux/ipa_qmi_service_v01.h deleted file mode 100644 index 72efc860..00000000 --- a/sdm710/original-kernel-headers/linux/ipa_qmi_service_v01.h +++ /dev/null @@ -1,2041 +0,0 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * This header file defines the types and structures that were defined in - * ipa. It contains the constant values defined, enums, structures, - * messages, and service message IDs (in that order) Structures that were - * defined in the IDL as messages contain mandatory elements, optional - * elements, a combination of mandatory and optional elements (mandatory - * always come before optionals in the structure), or nothing (null message) - - * An optional element in a message is preceded by a uint8_t value that must be - * set to true if the element is going to be included. When decoding a received - * message, the uint8_t values will be set to true or false by the decode - * routine, and should be checked before accessing the values that they - * correspond to. - - * Variable sized arrays are defined as static sized arrays with an unsigned - * integer (32 bit) preceding it that must be set to the number of elements - * in the array that are valid. For Example: - - * uint32_t test_opaque_len; - * uint8_t test_opaque[16]; - - * If only 4 elements are added to test_opaque[] then test_opaque_len must be - * set to 4 before sending the message. When decoding, the _len value is set - * by the decode routine and should be checked so that the correct number of - * elements in the array will be accessed. - */ -#ifndef IPA_QMI_SERVICE_V01_H -#define IPA_QMI_SERVICE_V01_H - -#define QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01 2 -#define QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01 2 -#define QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01 2 -#define QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01 2 -#define QMI_IPA_MAX_FILTERS_V01 64 -#define QMI_IPA_MAX_FILTERS_EX_V01 128 -#define QMI_IPA_MAX_PIPES_V01 20 -#define QMI_IPA_MAX_APN_V01 8 -#define QMI_IPA_MAX_PER_CLIENTS_V01 64 -/* Currently max we can use is only 1. But for scalability purpose - * we are having max value as 8. - */ -#define QMI_IPA_MAX_CLIENT_DST_PIPES_V01 8 -#define QMI_IPA_MAX_UL_FIREWALL_RULES_V01 64 - -/* - * Indicates presence of newly added member to support HW stats. - */ -#define IPA_QMI_SUPPORTS_STATS - -#define IPA_INT_MAX ((int)(~0U>>1)) -#define IPA_INT_MIN (-IPA_INT_MAX - 1) - -/* IPA definition as msm_qmi_interface.h */ - -enum ipa_qmi_result_type_v01 { - /* To force a 32 bit signed enum. Do not change or use*/ - IPA_QMI_RESULT_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, - IPA_QMI_RESULT_SUCCESS_V01 = 0, - IPA_QMI_RESULT_FAILURE_V01 = 1, - IPA_QMI_RESULT_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, -}; - -enum ipa_qmi_error_type_v01 { - /* To force a 32 bit signed enum. Do not change or use*/ - IPA_QMI_ERROR_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, - IPA_QMI_ERR_NONE_V01 = 0x0000, - IPA_QMI_ERR_MALFORMED_MSG_V01 = 0x0001, - IPA_QMI_ERR_NO_MEMORY_V01 = 0x0002, - IPA_QMI_ERR_INTERNAL_V01 = 0x0003, - IPA_QMI_ERR_CLIENT_IDS_EXHAUSTED_V01 = 0x0005, - IPA_QMI_ERR_INVALID_ID_V01 = 0x0029, - IPA_QMI_ERR_ENCODING_V01 = 0x003A, - IPA_QMI_ERR_INCOMPATIBLE_STATE_V01 = 0x005A, - IPA_QMI_ERR_NOT_SUPPORTED_V01 = 0x005E, - IPA_QMI_ERROR_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, -}; - -struct ipa_qmi_response_type_v01 { - enum ipa_qmi_result_type_v01 result; - enum ipa_qmi_error_type_v01 error; -}; - -enum ipa_platform_type_enum_v01 { - IPA_PLATFORM_TYPE_ENUM_MIN_ENUM_VAL_V01 = - -2147483647, /* To force a 32 bit signed enum. Do not change or use */ - QMI_IPA_PLATFORM_TYPE_INVALID_V01 = 0, - /* Invalid platform identifier */ - QMI_IPA_PLATFORM_TYPE_TN_V01 = 1, - /* Platform identifier - Data card device */ - QMI_IPA_PLATFORM_TYPE_LE_V01 = 2, - /* Platform identifier - Data router device */ - QMI_IPA_PLATFORM_TYPE_MSM_ANDROID_V01 = 3, - /* Platform identifier - MSM device with Android HLOS */ - QMI_IPA_PLATFORM_TYPE_MSM_WINDOWS_V01 = 4, - /* Platform identifier - MSM device with Windows HLOS */ - QMI_IPA_PLATFORM_TYPE_MSM_QNX_V01 = 5, - /* Platform identifier - MSM device with QNX HLOS */ - IPA_PLATFORM_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 - /* To force a 32 bit signed enum. Do not change or use */ -}; - -struct ipa_hdr_tbl_info_type_v01 { - uint32_t modem_offset_start; - /* Offset from the start of IPA Shared memory from which - * modem driver may insert header table entries. - */ - uint32_t modem_offset_end; - /* Offset from the start of IPA shared mem beyond which modem - * driver shall not insert header table entries. The space - * available for the modem driver shall include the - * modem_offset_start and modem_offset_end. - */ -}; /* Type */ - -struct ipa_route_tbl_info_type_v01 { - uint32_t route_tbl_start_addr; - /* Identifies the start of the routing table. Denotes the offset - * from the start of the IPA Shared Mem - */ - - uint32_t num_indices; - /* Number of indices (starting from 0) that is being allocated to - * the modem. The number indicated here is also included in the - * allocation. The value of num_indices shall not exceed 31 - * (5 bits used to specify the routing table index), unless there - * is a change in the hardware. - */ -}; /* Type */ - -struct ipa_modem_mem_info_type_v01 { - - uint32_t block_start_addr; - /* Identifies the start of the memory block allocated for the - * modem. Denotes the offset from the start of the IPA Shared Mem - */ - - uint32_t size; - /* Size of the block allocated for the modem driver */ -}; /* Type */ - -struct ipa_hdr_proc_ctx_tbl_info_type_v01 { - - uint32_t modem_offset_start; - /* Offset from the start of IPA shared memory from which the modem - * driver may insert header processing context table entries. - */ - - uint32_t modem_offset_end; - /* Offset from the start of IPA shared memory beyond which the modem - * driver may not insert header proc table entries. The space - * available for the modem driver includes modem_offset_start and - * modem_offset_end. - */ -}; /* Type */ - -struct ipa_zip_tbl_info_type_v01 { - - uint32_t modem_offset_start; - /* Offset from the start of IPA shared memory from which the modem - * driver may insert compression/decompression command entries. - */ - - uint32_t modem_offset_end; - /* Offset from the start of IPA shared memory beyond which the modem - * driver may not insert compression/decompression command entries. - * The space available for the modem driver includes - * modem_offset_start and modem_offset_end. - */ -}; /* Type */ - -/** - * Request Message; Requests the modem IPA driver - * to perform initialization - */ -struct ipa_init_modem_driver_req_msg_v01 { - - /* Optional */ - /* Platform info */ - uint8_t platform_type_valid; - /* Must be set to true if platform_type is being passed */ - enum ipa_platform_type_enum_v01 platform_type; - /* Provides information about the platform (ex. TN/MN/LE/MSM,etc) */ - - /* Optional */ - /* Header table info */ - uint8_t hdr_tbl_info_valid; - /* Must be set to true if hdr_tbl_info is being passed */ - struct ipa_hdr_tbl_info_type_v01 hdr_tbl_info; - /* Provides information about the header table */ - - /* Optional */ - /* IPV4 Routing table info */ - uint8_t v4_route_tbl_info_valid; - /* Must be set to true if v4_route_tbl_info is being passed */ - struct ipa_route_tbl_info_type_v01 v4_route_tbl_info; - /* Provides information about the IPV4 routing table */ - - /* Optional */ - /* IPV6 Routing table info */ - uint8_t v6_route_tbl_info_valid; - /* Must be set to true if v6_route_tbl_info is being passed */ - struct ipa_route_tbl_info_type_v01 v6_route_tbl_info; - /* Provides information about the IPV6 routing table */ - - /* Optional */ - /* IPV4 Filter table start address */ - uint8_t v4_filter_tbl_start_addr_valid; - /* Must be set to true if v4_filter_tbl_start_addr is being passed */ - uint32_t v4_filter_tbl_start_addr; - /* Provides information about the starting address of IPV4 filter - * table in IPAv2 or non-hashable IPv4 filter table in IPAv3. - * Denotes the offset from the start of the IPA Shared Mem - */ - - /* Optional */ - /* IPV6 Filter table start address */ - uint8_t v6_filter_tbl_start_addr_valid; - /* Must be set to true if v6_filter_tbl_start_addr is being passed */ - uint32_t v6_filter_tbl_start_addr; - /* Provides information about the starting address of IPV6 filter - * table in IPAv2 or non-hashable IPv6 filter table in IPAv3. - * Denotes the offset from the start of the IPA Shared Mem - */ - - /* Optional */ - /* Modem memory block */ - uint8_t modem_mem_info_valid; - /* Must be set to true if modem_mem_info is being passed */ - struct ipa_modem_mem_info_type_v01 modem_mem_info; - /* Provides information about the start address and the size of - * the memory block that is being allocated to the modem driver. - * Denotes the physical address - */ - - /* Optional */ - /* Destination end point for control commands from modem */ - uint8_t ctrl_comm_dest_end_pt_valid; - /* Must be set to true if ctrl_comm_dest_end_pt is being passed */ - uint32_t ctrl_comm_dest_end_pt; - /* Provides information about the destination end point on the - * application processor to which the modem driver can send - * control commands. The value of this parameter cannot exceed - * 19 since IPA only supports 20 end points. - */ - - /* Optional */ - /* Modem Bootup Information */ - uint8_t is_ssr_bootup_valid; - /* Must be set to true if is_ssr_bootup is being passed */ - uint8_t is_ssr_bootup; - /* Specifies whether the modem is booting up after a modem only - * sub-system restart or not. This will let the modem driver - * know that it doesn't have to reinitialize some of the HW - * blocks because IPA has not been reset since the previous - * initialization. - */ - - /* Optional */ - /* Header Processing Context Table Information */ - uint8_t hdr_proc_ctx_tbl_info_valid; - /* Must be set to true if hdr_proc_ctx_tbl_info is being passed */ - struct ipa_hdr_proc_ctx_tbl_info_type_v01 hdr_proc_ctx_tbl_info; - /* Provides information about the header processing context table. - */ - - /* Optional */ - /* Compression Decompression Table Information */ - uint8_t zip_tbl_info_valid; - /* Must be set to true if zip_tbl_info is being passed */ - struct ipa_zip_tbl_info_type_v01 zip_tbl_info; - /* Provides information about the zip table. - */ - - /* Optional */ - /* IPv4 Hashable Routing Table Information */ - /** Must be set to true if v4_hash_route_tbl_info is being passed */ - uint8_t v4_hash_route_tbl_info_valid; - struct ipa_route_tbl_info_type_v01 v4_hash_route_tbl_info; - - /* Optional */ - /* IPv6 Hashable Routing Table Information */ - /** Must be set to true if v6_hash_route_tbl_info is being passed */ - uint8_t v6_hash_route_tbl_info_valid; - struct ipa_route_tbl_info_type_v01 v6_hash_route_tbl_info; - - /* - * Optional - * IPv4 Hashable Filter Table Start Address - * Must be set to true if v4_hash_filter_tbl_start_addr - * is being passed - */ - uint8_t v4_hash_filter_tbl_start_addr_valid; - uint32_t v4_hash_filter_tbl_start_addr; - /* Identifies the starting address of the IPv4 hashable filter - * table in IPAv3 onwards. Denotes the offset from the start of - * the IPA shared memory. - */ - - /* Optional - * IPv6 Hashable Filter Table Start Address - * Must be set to true if v6_hash_filter_tbl_start_addr - * is being passed - */ - uint8_t v6_hash_filter_tbl_start_addr_valid; - uint32_t v6_hash_filter_tbl_start_addr; - /* Identifies the starting address of the IPv6 hashable filter - * table in IPAv3 onwards. Denotes the offset from the start of - * the IPA shared memory. - */ - - /* Optional - * Modem HW Stats Quota Base address - * Must be set to true if hw_stats_quota_base_addr - * is being passed - */ - uint8_t hw_stats_quota_base_addr_valid; - uint32_t hw_stats_quota_base_addr; - - /* Optional - * Modem HW Stats Quota Size - * Must be set to true if hw_stats_quota_size - * is being passed - */ - uint8_t hw_stats_quota_size_valid; - uint32_t hw_stats_quota_size; - - /* Optional - * Modem HW Drop Stats Table Start Address - * Must be set to true if hw_drop_stats_base_addr - * is being passed - */ - uint8_t hw_drop_stats_base_addr_valid; - uint32_t hw_drop_stats_base_addr; - - /* Optional - * Modem HW Drop Stats Table size - * Must be set to true if hw_drop_stats_table_size - * is being passed - */ - uint8_t hw_drop_stats_table_size_valid; - uint32_t hw_drop_stats_table_size; -}; /* Message */ - -/* Response Message; Requests the modem IPA driver about initialization */ -struct ipa_init_modem_driver_resp_msg_v01 { - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /* Standard response type.*/ - - /* Optional */ - /* Destination end point for control commands from master driver */ - uint8_t ctrl_comm_dest_end_pt_valid; - /* Must be set to true if ctrl_comm_dest_ep is being passed */ - uint32_t ctrl_comm_dest_end_pt; - /* Provides information about the destination end point on the - * modem processor to which the master driver can send control - * commands. The value of this parameter cannot exceed 19 since - * IPA only supports 20 end points. This field is looked at only - * if the result in TLV RESULT_CODE is QMI_RESULT_SUCCESS - */ - - /* Optional */ - /* Default end point */ - uint8_t default_end_pt_valid; - /* Must be set to true if default_end_pt is being passed */ - uint32_t default_end_pt; - /* Provides information about the default end point. The master - * driver may or may not set the register in the hardware with - * this value. The value of this parameter cannot exceed 19 - * since IPA only supports 20 end points. This field is looked - * at only if the result in TLV RESULT_CODE is QMI_RESULT_SUCCESS - */ - - /* Optional */ - /* Modem Driver Initialization Pending */ - uint8_t modem_driver_init_pending_valid; - /* Must be set to true if modem_driver_init_pending is being passed */ - uint8_t modem_driver_init_pending; - /* - * Identifies if second level message handshake is needed - * between drivers to indicate when IPA HWP loading is completed. - * If this is set by modem driver, AP driver will need to wait - * for a INIT_MODEM_DRIVER_CMPLT message before communicating with - * IPA HWP. - */ -}; /* Message */ - -/* - * Request Message; Request from Modem IPA driver to indicate - * modem driver init completion - */ -struct ipa_init_modem_driver_cmplt_req_msg_v01 { - /* Mandatory */ - /* Modem Driver init complete status; */ - uint8_t status; - /* - * Specifies whether the modem driver initialization is complete - * including the micro controller image loading. - */ -}; /* Message */ - -/* - * Response Message; Request from Modem IPA driver to indicate - * modem driver init completion - */ -struct ipa_init_modem_driver_cmplt_resp_msg_v01 { - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /**< Standard response type.*/ -}; /* Message */ - -/* Request Message; This is the message that is exchanged between the - * control point and the service in order to register for indications. - */ -struct ipa_indication_reg_req_msg_v01 { - /* Optional */ - /* Master driver initialization completion */ - uint8_t master_driver_init_complete_valid; - /* Must be set to true if master_driver_init_complete is being passed */ - uint8_t master_driver_init_complete; - /* If set to TRUE, this field indicates that the client is - * interested in getting indications about the completion - * of the initialization sequence of the master driver. - * Setting this field in the request message makes sense - * only when the QMI_IPA_INDICATION_REGISTER_REQ is being - * originated from the modem driver - */ - - /* Optional */ - /* Data Usage Quota Reached */ - uint8_t data_usage_quota_reached_valid; - /* Must be set to true if data_usage_quota_reached is being passed */ - uint8_t data_usage_quota_reached; - /* If set to TRUE, this field indicates that the client wants to - * receive indications about reaching the data usage quota that - * previously set via QMI_IPA_SET_DATA_USAGE_QUOTA. Setting this field - * in the request message makes sense only when the - * QMI_IPA_INDICATION_REGISTER_REQ is being originated from the Master - * driver - */ -}; /* Message */ - - -/* Response Message; This is the message that is exchanged between the - * control point and the service in order to register for indications. - */ -struct ipa_indication_reg_resp_msg_v01 { - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /**< Standard response type.*/ -}; /* Message */ - - -/* Indication Message; Indication sent to the Modem IPA driver from - * master IPA driver about initialization being complete. - */ -struct ipa_master_driver_init_complt_ind_msg_v01 { - /* Mandatory */ - /* Master driver initialization completion status */ - struct ipa_qmi_response_type_v01 master_driver_init_status; - /* Indicates the status of initialization. If everything went - * as expected, this field is set to SUCCESS. ERROR is set - * otherwise. Extended error info may be used to convey - * additional information about the error - */ -}; /* Message */ - -struct ipa_ipfltr_range_eq_16_type_v01 { - uint8_t offset; - /* Specifies the offset from the IHL (Internet Header length) */ - - uint16_t range_low; - /* Specifies the lower bound of the range */ - - uint16_t range_high; - /* Specifies the upper bound of the range */ -}; /* Type */ - -struct ipa_ipfltr_mask_eq_32_type_v01 { - uint8_t offset; - /* Specifies the offset either from IHL or from the start of - * the IP packet. This depends on the equation that this structure - * is used in. - */ - - uint32_t mask; - /* Specifies the mask that has to be used in the comparison. - * The field is ANDed with the mask and compared against the value. - */ - - uint32_t value; - /* Specifies the 32 bit value that used in the comparison. */ -}; /* Type */ - -struct ipa_ipfltr_eq_16_type_v01 { - uint8_t offset; - /* Specifies the offset into the packet */ - - uint16_t value; - /* Specifies the 16 bit value that should be used in the comparison. */ -}; /* Type */ - -struct ipa_ipfltr_eq_32_type_v01 { - uint8_t offset; - /* Specifies the offset into the packet */ - - uint32_t value; - /* Specifies the 32 bit value that should be used in the comparison. */ -}; /* Type */ - -struct ipa_ipfltr_mask_eq_128_type_v01 { - uint8_t offset; - /* Specifies the offset into the packet */ - - uint8_t mask[16]; - /* Specifies the mask that has to be used in the comparison. - * The field is ANDed with the mask and compared against the value. - */ - - uint8_t value[16]; - /* Specifies the 128 bit value that should be used in the comparison. */ -}; /* Type */ - - -struct ipa_filter_rule_type_v01 { - uint16_t rule_eq_bitmap; - /* 16-bit Bitmask to indicate how many eqs are valid in this rule */ - - uint8_t tos_eq_present; - /* Specifies if a type of service check rule is present */ - - uint8_t tos_eq; - /* The value to check against the type of service (ipv4) field */ - - uint8_t protocol_eq_present; - /* Specifies if a protocol check rule is present */ - - uint8_t protocol_eq; - /* The value to check against the protocol field */ - - uint8_t num_ihl_offset_range_16; - /* The number of 16 bit range check rules at the location - * determined by IP header length plus a given offset offset - * in this rule. See the definition of the ipa_filter_range_eq_16 - * for better understanding. The value of this field cannot exceed - * IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS which is set as 2 - */ - - struct ipa_ipfltr_range_eq_16_type_v01 - ihl_offset_range_16[QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01]; - /* Array of the registered IP header length offset 16 bit range - * check rules. - */ - - uint8_t num_offset_meq_32; - /* The number of 32 bit masked comparison rules present - * in this rule - */ - - struct ipa_ipfltr_mask_eq_32_type_v01 - offset_meq_32[QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01]; - /* An array of all the possible 32bit masked comparison rules - * in this rule - */ - - uint8_t tc_eq_present; - /* Specifies if the traffic class rule is present in this rule */ - - uint8_t tc_eq; - /* The value against which the IPV4 traffic class field has to - * be checked - */ - - uint8_t flow_eq_present; - /* Specifies if the "flow equals" rule is present in this rule */ - - uint32_t flow_eq; - /* The value against which the IPV6 flow field has to be checked */ - - uint8_t ihl_offset_eq_16_present; - /* Specifies if there is a 16 bit comparison required at the - * location in the packet determined by "Intenet Header length - * + specified offset" - */ - - struct ipa_ipfltr_eq_16_type_v01 ihl_offset_eq_16; - /* The 16 bit comparison equation */ - - uint8_t ihl_offset_eq_32_present; - /* Specifies if there is a 32 bit comparison required at the - * location in the packet determined by "Intenet Header length - * + specified offset" - */ - - struct ipa_ipfltr_eq_32_type_v01 ihl_offset_eq_32; - /* The 32 bit comparison equation */ - - uint8_t num_ihl_offset_meq_32; - /* The number of 32 bit masked comparison equations in this - * rule. The location of the packet to be compared is - * determined by the IP Header length + the give offset - */ - - struct ipa_ipfltr_mask_eq_32_type_v01 - ihl_offset_meq_32[QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01]; - /* Array of 32 bit masked comparison equations. - */ - - uint8_t num_offset_meq_128; - /* The number of 128 bit comparison equations in this rule */ - - struct ipa_ipfltr_mask_eq_128_type_v01 - offset_meq_128[QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01]; - /* Array of 128 bit comparison equations. The location in the - * packet is determined by the specified offset - */ - - uint8_t metadata_meq32_present; - /* Boolean indicating if the 32 bit masked comparison equation - * is present or not. Comparison is done against the metadata - * in IPA. Metadata can either be extracted from the packet - * header or from the "metadata" register. - */ - - struct ipa_ipfltr_mask_eq_32_type_v01 - metadata_meq32; - /* The metadata 32 bit masked comparison equation */ - - uint8_t ipv4_frag_eq_present; - /* Specifies if the IPv4 Fragment equation is present in this rule */ -}; /* Type */ - - -enum ipa_ip_type_enum_v01 { - IPA_IP_TYPE_ENUM_MIN_ENUM_VAL_V01 = -2147483647, - /* To force a 32 bit signed enum. Do not change or use*/ - QMI_IPA_IP_TYPE_INVALID_V01 = 0, - /* Invalid IP type identifier */ - QMI_IPA_IP_TYPE_V4_V01 = 1, - /* IP V4 type */ - QMI_IPA_IP_TYPE_V6_V01 = 2, - /* IP V6 type */ - QMI_IPA_IP_TYPE_V4V6_V01 = 3, - /* Applies to both IP types */ - IPA_IP_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 - /* To force a 32 bit signed enum. Do not change or use*/ -}; - - -enum ipa_filter_action_enum_v01 { - IPA_FILTER_ACTION_ENUM_MIN_ENUM_VAL_V01 = -2147483647, - /* To force a 32 bit signed enum. Do not change or use */ - QMI_IPA_FILTER_ACTION_INVALID_V01 = 0, - /* Invalid action on filter hit */ - QMI_IPA_FILTER_ACTION_SRC_NAT_V01 = 1, - /* Pass packet to NAT block for Source NAT */ - QMI_IPA_FILTER_ACTION_DST_NAT_V01 = 2, - /* Pass packet to NAT block for Destination NAT */ - QMI_IPA_FILTER_ACTION_ROUTING_V01 = 3, - /* Pass packet to Routing block */ - QMI_IPA_FILTER_ACTION_EXCEPTION_V01 = 4, - /* Treat packet as exception and send to exception pipe */ - IPA_FILTER_ACTION_ENUM_MAX_ENUM_VAL_V01 = 2147483647 - /* To force a 32 bit signed enum. Do not change or use*/ -}; - -struct ipa_filter_spec_type_v01 { - uint32_t filter_spec_identifier; - /* This field is used to identify a filter spec in the list - * of filter specs being sent from the client. This field - * is applicable only in the filter install request and response. - */ - - enum ipa_ip_type_enum_v01 ip_type; - /* This field identifies the IP type for which this rule is - * applicable. The driver needs to identify the filter table - * (V6 or V4) and this field is essential for that - */ - - struct ipa_filter_rule_type_v01 filter_rule; - /* This field specifies the rules in the filter spec. These rules - * are the ones that are matched against fields in the packet. - */ - - enum ipa_filter_action_enum_v01 filter_action; - /* This field specifies the action to be taken when a filter match - * occurs. The remote side should install this information into the - * hardware along with the filter equations. - */ - - uint8_t is_routing_table_index_valid; - /* Specifies whether the routing table index is present or not. - * If the action is "QMI_IPA_FILTER_ACTION_EXCEPTION", this - * parameter need not be provided. - */ - - uint32_t route_table_index; - /* This is the index in the routing table that should be used - * to route the packets if the filter rule is hit - */ - - uint8_t is_mux_id_valid; - /* Specifies whether the mux_id is valid */ - - uint32_t mux_id; - /* This field identifies the QMAP MUX ID. As a part of QMAP - * protocol, several data calls may be multiplexed over the - * same physical transport channel. This identifier is used to - * identify one such data call. The maximum value for this - * identifier is 255. - */ -}; /* Type */ - -struct ipa_filter_spec_ex_type_v01 { - enum ipa_ip_type_enum_v01 ip_type; - /* This field identifies the IP type for which this rule is - * applicable. The driver needs to identify the filter table - * (V6 or V4) and this field is essential for that - */ - - struct ipa_filter_rule_type_v01 filter_rule; - /* This field specifies the rules in the filter spec. These rules - * are the ones that are matched against fields in the packet. - */ - - enum ipa_filter_action_enum_v01 filter_action; - /* This field specifies the action to be taken when a filter match - * occurs. The remote side should install this information into the - * hardware along with the filter equations. - */ - - uint8_t is_routing_table_index_valid; - /* Specifies whether the routing table index is present or not. - * If the action is "QMI_IPA_FILTER_ACTION_EXCEPTION", this - * parameter need not be provided. - */ - - uint32_t route_table_index; - /* This is the index in the routing table that should be used - * to route the packets if the filter rule is hit - */ - - uint8_t is_mux_id_valid; - /* Specifies whether the mux_id is valid */ - - uint32_t mux_id; - /* This field identifies the QMAP MUX ID. As a part of QMAP - * protocol, several data calls may be multiplexed over the - * same physical transport channel. This identifier is used to - * identify one such data call. The maximum value for this - * identifier is 255. - */ - - uint32_t rule_id; - /* Rule Id of the given filter. The Rule Id is populated in the rule - * header when installing the rule in IPA. - */ - - uint8_t is_rule_hashable; - /** Specifies whether the given rule is hashable. - */ -}; /* Type */ - - -/* Request Message; This is the message that is exchanged between the - * control point and the service in order to request the installation - * of filtering rules in the hardware block by the remote side. - */ -struct ipa_install_fltr_rule_req_msg_v01 { - /* Optional - * IP type that this rule applies to - * Filter specification to be installed in the hardware - */ - uint8_t filter_spec_list_valid; - /* Must be set to true if filter_spec_list is being passed */ - uint32_t filter_spec_list_len; - /* Must be set to # of elements in filter_spec_list */ - struct ipa_filter_spec_type_v01 - filter_spec_list[QMI_IPA_MAX_FILTERS_V01]; - /* This structure defines the list of filters that have - * to be installed in the hardware. The driver installing - * these rules shall do so in the same order as specified - * in this list. - */ - - /* Optional */ - /* Pipe index to intall rule */ - uint8_t source_pipe_index_valid; - /* Must be set to true if source_pipe_index is being passed */ - uint32_t source_pipe_index; - /* This is the source pipe on which the filter rule is to be - * installed. The requestor may always not know the pipe - * indices. If not specified, the receiver shall install - * this rule on all the pipes that it controls through - * which data may be fed into IPA. - */ - - /* Optional */ - /* Total number of IPv4 filters in the filter spec list */ - uint8_t num_ipv4_filters_valid; - /* Must be set to true if num_ipv4_filters is being passed */ - uint32_t num_ipv4_filters; - /* Number of IPv4 rules included in filter spec list */ - - /* Optional */ - /* Total number of IPv6 filters in the filter spec list */ - uint8_t num_ipv6_filters_valid; - /* Must be set to true if num_ipv6_filters is being passed */ - uint32_t num_ipv6_filters; - /* Number of IPv6 rules included in filter spec list */ - - /* Optional */ - /* List of XLAT filter indices in the filter spec list */ - uint8_t xlat_filter_indices_list_valid; - /* Must be set to true if xlat_filter_indices_list - * is being passed - */ - uint32_t xlat_filter_indices_list_len; - /* Must be set to # of elements in xlat_filter_indices_list */ - uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_V01]; - /* List of XLAT filter indices. Filter rules at specified indices - * will need to be modified by the receiver if the PDN is XLAT - * before installing them on the associated IPA consumer pipe. - */ - - /* Optional */ - /* Extended Filter Specification */ - uint8_t filter_spec_ex_list_valid; - /* Must be set to true if filter_spec_ex_list is being passed */ - uint32_t filter_spec_ex_list_len; - /* Must be set to # of elements in filter_spec_ex_list */ - struct ipa_filter_spec_ex_type_v01 - filter_spec_ex_list[QMI_IPA_MAX_FILTERS_V01]; - /* - * List of filter specifications of filters that must be installed in - * the IPAv3.x hardware. - * The driver installing these rules must do so in the same - * order as specified in this list. - */ -}; /* Message */ - -struct ipa_filter_rule_identifier_to_handle_map_v01 { - uint32_t filter_spec_identifier; - /* This field is used to identify a filter spec in the list of - * filter specs being sent from the client. This field is - * applicable only in the filter install request and response. - */ - uint32_t filter_handle; - /* This field is used to identify a rule in any subsequent message. - * This is a value that is provided by the server to the control - * point - */ -}; /* Type */ - -/* Response Message; This is the message that is exchanged between the - * control point and the service in order to request the - * installation of filtering rules in the hardware block by - * the remote side. - */ -struct ipa_install_fltr_rule_resp_msg_v01 { - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /* Standard response type. - * Standard response type. Contains the following data members: - * - qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE - * - qmi_error_type -- Error code. Possible error code values are - * described in the error codes section of each message definition. - */ - - /* Optional */ - /* Filter Handle List */ - uint8_t filter_handle_list_valid; - /* Must be set to true if filter_handle_list is being passed */ - uint32_t filter_handle_list_len; - /* Must be set to # of elements in filter_handle_list */ - struct ipa_filter_rule_identifier_to_handle_map_v01 - filter_handle_list[QMI_IPA_MAX_FILTERS_V01]; - /* - * List of handles returned to the control point. Each handle is - * mapped to the rule identifier that was specified in the - * request message. Any further reference to the rule is done - * using the filter handle. - */ - - /* Optional */ - /* Rule id List */ - uint8_t rule_id_valid; - /* Must be set to true if rule_id is being passed */ - uint32_t rule_id_len; - /* Must be set to # of elements in rule_id */ - uint32_t rule_id[QMI_IPA_MAX_FILTERS_V01]; - /* - * List of rule ids returned to the control point. - * Any further reference to the rule is done using the - * filter rule id specified in this list. - */ -}; /* Message */ - -struct ipa_filter_handle_to_index_map_v01 { - uint32_t filter_handle; - /* This is a handle that was given to the remote client that - * requested the rule addition. - */ - uint32_t filter_index; - /* This index denotes the location in a filter table, where the - * filter rule has been installed. The maximum value of this - * field is 64. - */ -}; /* Type */ - -/* Request Message; This is the message that is exchanged between the - * control point and the service in order to notify the remote driver - * of the installation of the filter rule supplied earlier by the - * remote driver. - */ -struct ipa_fltr_installed_notif_req_msg_v01 { - /* Mandatory */ - /* Pipe index */ - uint32_t source_pipe_index; - /* This is the source pipe on which the filter rule has been - * installed or was attempted to be installed - */ - - /* Mandatory */ - /* Installation Status */ - enum ipa_qmi_result_type_v01 install_status; - /* This is the status of installation. If this indicates - * SUCCESS, other optional fields carry additional - * information - */ - - /* Mandatory */ - /* List of Filter Indices */ - uint32_t filter_index_list_len; - /* Must be set to # of elements in filter_index_list */ - struct ipa_filter_handle_to_index_map_v01 - filter_index_list[QMI_IPA_MAX_FILTERS_V01]; - /* - * Provides the list of filter indices and the corresponding - * filter handle. If the installation_status indicates a - * failure, the filter indices must be set to a reserve - * index (255). - */ - - /* Optional */ - /* Embedded pipe index */ - uint8_t embedded_pipe_index_valid; - /* Must be set to true if embedded_pipe_index is being passed */ - uint32_t embedded_pipe_index; - /* This index denotes the embedded pipe number on which a call to - * the same PDN has been made. If this field is set, it denotes - * that this is a use case where PDN sharing is happening. The - * embedded pipe is used to send data from the embedded client - * in the device - */ - - /* Optional */ - /* Retain Header Configuration */ - uint8_t retain_header_valid; - /* Must be set to true if retain_header is being passed */ - uint8_t retain_header; - /* This field indicates if the driver installing the rule has - * turned on the "retain header" bit. If this is true, the - * header that is removed by IPA is reinserted after the - * packet processing is completed. - */ - - /* Optional */ - /* Embedded call Mux Id */ - uint8_t embedded_call_mux_id_valid; - /**< Must be set to true if embedded_call_mux_id is being passed */ - uint32_t embedded_call_mux_id; - /* This identifies one of the many calls that have been originated - * on the embedded pipe. This is how we identify the PDN gateway - * to which traffic from the source pipe has to flow. - */ - - /* Optional */ - /* Total number of IPv4 filters in the filter index list */ - uint8_t num_ipv4_filters_valid; - /* Must be set to true if num_ipv4_filters is being passed */ - uint32_t num_ipv4_filters; - /* Number of IPv4 rules included in filter index list */ - - /* Optional */ - /* Total number of IPv6 filters in the filter index list */ - uint8_t num_ipv6_filters_valid; - /* Must be set to true if num_ipv6_filters is being passed */ - uint32_t num_ipv6_filters; - /* Number of IPv6 rules included in filter index list */ - - /* Optional */ - /* Start index on IPv4 filters installed on source pipe */ - uint8_t start_ipv4_filter_idx_valid; - /* Must be set to true if start_ipv4_filter_idx is being passed */ - uint32_t start_ipv4_filter_idx; - /* Start index of IPv4 rules in filter index list */ - - /* Optional */ - /* Start index on IPv6 filters installed on source pipe */ - uint8_t start_ipv6_filter_idx_valid; - /* Must be set to true if start_ipv6_filter_idx is being passed */ - uint32_t start_ipv6_filter_idx; - /* Start index of IPv6 rules in filter index list */ - - /* Optional */ - /* List of Rule Ids */ - uint8_t rule_id_valid; - /* Must be set to true if rule_id is being passed */ - uint32_t rule_id_len; - /* Must be set to # of elements in rule_id */ - uint32_t rule_id[QMI_IPA_MAX_FILTERS_V01]; - /* - * Provides the list of Rule Ids of rules added in IPA on the given - * source pipe index. If the install_status TLV indicates a - * failure, the Rule Ids in this list must be set to a reserved - * index (255). - */ - - /* Optional */ - /* List of destination pipe IDs. */ - uint8_t dst_pipe_id_valid; - /* Must be set to true if dst_pipe_id is being passed. */ - uint32_t dst_pipe_id_len; - /* Must be set to # of elements in dst_pipe_id. */ - uint32_t dst_pipe_id[QMI_IPA_MAX_CLIENT_DST_PIPES_V01]; - /* Provides the list of destination pipe IDs for a source pipe. */ - -}; /* Message */ - -/* Response Message; This is the message that is exchanged between the - * control point and the service in order to notify the remote driver - * of the installation of the filter rule supplied earlier by the - * remote driver. - */ -struct ipa_fltr_installed_notif_resp_msg_v01 { - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /* Standard response type */ -}; /* Message */ - -/* Request Message; Notifies the remote driver of the need to clear the data - * path to prevent the IPA from being blocked at the head of the processing - * pipeline - */ -struct ipa_enable_force_clear_datapath_req_msg_v01 { - /* Mandatory */ - /* Pipe Mask */ - uint32_t source_pipe_bitmask; - /* Set of consumer (source) pipes that must be clear of - * active data transfers. - */ - - /* Mandatory */ - /* Request ID */ - uint32_t request_id; - /* Identifies the ID of the request that is sent to the server - * The same request ID is used in the message to remove the force_clear - * request. The server is expected to keep track of the request ID and - * the source_pipe_bitmask so that it can revert as needed - */ - - /* Optional */ - /* Source Throttle State */ - uint8_t throttle_source_valid; - /* Must be set to true if throttle_source is being passed */ - uint8_t throttle_source; - /* Specifies whether the server is to throttle the data from - * these consumer (source) pipes after clearing the exisiting - * data present in the IPA that were pulled from these pipes - * The server is expected to put all the source pipes in the - * source_pipe_bitmask in the same state - */ -}; /* Message */ - -/* Response Message; Notifies the remote driver of the need to clear the - * data path to prevent the IPA from being blocked at the head of the - * processing pipeline - */ -struct ipa_enable_force_clear_datapath_resp_msg_v01 { - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /* Standard response type */ -}; /* Message */ - -/* Request Message; Notifies the remote driver that the forceful clearing - * of the data path can be lifted - */ -struct ipa_disable_force_clear_datapath_req_msg_v01 { - /* Mandatory */ - /* Request ID */ - uint32_t request_id; - /* Identifies the request that was sent to the server to - * forcibly clear the data path. This request simply undoes - * the operation done in that request - */ -}; /* Message */ - -/* Response Message; Notifies the remote driver that the forceful clearing - * of the data path can be lifted - */ -struct ipa_disable_force_clear_datapath_resp_msg_v01 { - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /* Standard response type */ -}; /* Message */ - -enum ipa_peripheral_speed_enum_v01 { - IPA_PERIPHERAL_SPEED_ENUM_MIN_ENUM_VAL_V01 = -2147483647, - /* To force a 32 bit signed enum. Do not change or use */ - QMI_IPA_PER_USB_FS_V01 = 1, - /* Full-speed USB connection */ - QMI_IPA_PER_USB_HS_V01 = 2, - /* High-speed USB connection */ - QMI_IPA_PER_USB_SS_V01 = 3, - /* Super-speed USB connection */ - QMI_IPA_PER_WLAN_V01 = 4, - /* WLAN connection */ - IPA_PERIPHERAL_SPEED_ENUM_MAX_ENUM_VAL_V01 = 2147483647 - /* To force a 32 bit signed enum. Do not change or use*/ -}; - -enum ipa_pipe_mode_enum_v01 { - IPA_PIPE_MODE_ENUM_MIN_ENUM_VAL_V01 = -2147483647, - /* To force a 32 bit signed enum. Do not change or use */ - QMI_IPA_PIPE_MODE_HW_V01 = 1, - /* Pipe is connected with a hardware block */ - QMI_IPA_PIPE_MODE_SW_V01 = 2, - /* Pipe is controlled by the software */ - IPA_PIPE_MODE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 - /* To force a 32 bit signed enum. Do not change or use */ -}; - -enum ipa_peripheral_type_enum_v01 { - IPA_PERIPHERAL_TYPE_ENUM_MIN_ENUM_VAL_V01 = -2147483647, - /* To force a 32 bit signed enum. Do not change or use */ - QMI_IPA_PERIPHERAL_USB_V01 = 1, - /* Specifies a USB peripheral */ - QMI_IPA_PERIPHERAL_HSIC_V01 = 2, - /* Specifies an HSIC peripheral */ - QMI_IPA_PERIPHERAL_PCIE_V01 = 3, - /* Specifies a PCIe peripheral */ - IPA_PERIPHERAL_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 - /* To force a 32 bit signed enum. Do not change or use */ -}; - -struct ipa_config_req_msg_v01 { - /* Optional */ - /* Peripheral Type */ - uint8_t peripheral_type_valid; - /* Must be set to true if peripheral_type is being passed */ - enum ipa_peripheral_type_enum_v01 peripheral_type; - /* Informs the remote driver about the perhipheral for - * which this configuration information is relevant. Values: - * - QMI_IPA_PERIPHERAL_USB (1) -- Specifies a USB peripheral - * - QMI_IPA_PERIPHERAL_HSIC(2) -- Specifies an HSIC peripheral - * - QMI_IPA_PERIPHERAL_PCIE(3) -- Specifies a PCIe peripheral - */ - - /* Optional */ - /* HW Deaggregation Support */ - uint8_t hw_deaggr_supported_valid; - /* Must be set to true if hw_deaggr_supported is being passed */ - uint8_t hw_deaggr_supported; - /* Informs the remote driver whether the local IPA driver - * allows de-aggregation to be performed in the hardware - */ - - /* Optional */ - /* Maximum Aggregation Frame Size */ - uint8_t max_aggr_frame_size_valid; - /* Must be set to true if max_aggr_frame_size is being passed */ - uint32_t max_aggr_frame_size; - /* Specifies the maximum size of the aggregated frame that - * the remote driver can expect from this execution environment - * - Valid range: 128 bytes to 32768 bytes - */ - - /* Optional */ - /* IPA Ingress Pipe Mode */ - uint8_t ipa_ingress_pipe_mode_valid; - /* Must be set to true if ipa_ingress_pipe_mode is being passed */ - - enum ipa_pipe_mode_enum_v01 ipa_ingress_pipe_mode; - /* Indicates to the remote driver if the ingress pipe into the - * IPA is in direct connection with another hardware block or - * if the producer of data to this ingress pipe is a software - * module. Values: - * -QMI_IPA_PIPE_MODE_HW(1) --Pipe is connected with hardware block - * -QMI_IPA_PIPE_MODE_SW(2) --Pipe is controlled by the software - */ - - /* Optional */ - /* Peripheral Speed Info */ - uint8_t peripheral_speed_info_valid; - /* Must be set to true if peripheral_speed_info is being passed */ - - enum ipa_peripheral_speed_enum_v01 peripheral_speed_info; - /* Indicates the speed that the peripheral connected to the IPA supports - * Values: - * - QMI_IPA_PER_USB_FS (1) -- Full-speed USB connection - * - QMI_IPA_PER_USB_HS (2) -- High-speed USB connection - * - QMI_IPA_PER_USB_SS (3) -- Super-speed USB connection - * - QMI_IPA_PER_WLAN (4) -- WLAN connection - */ - - /* Optional */ - /* Downlink Accumulation Time limit */ - uint8_t dl_accumulation_time_limit_valid; - /* Must be set to true if dl_accumulation_time_limit is being passed */ - uint32_t dl_accumulation_time_limit; - /* Informs the remote driver about the time for which data - * is accumulated in the downlink direction before it is pushed into the - * IPA (downlink is with respect to the WWAN air interface) - * - Units: milliseconds - * - Maximum value: 255 - */ - - /* Optional */ - /* Downlink Accumulation Packet limit */ - uint8_t dl_accumulation_pkt_limit_valid; - /* Must be set to true if dl_accumulation_pkt_limit is being passed */ - uint32_t dl_accumulation_pkt_limit; - /* Informs the remote driver about the number of packets - * that are to be accumulated in the downlink direction before it is - * pushed into the IPA - Maximum value: 1023 - */ - - /* Optional */ - /* Downlink Accumulation Byte Limit */ - uint8_t dl_accumulation_byte_limit_valid; - /* Must be set to true if dl_accumulation_byte_limit is being passed */ - uint32_t dl_accumulation_byte_limit; - /* Inform the remote driver about the number of bytes - * that are to be accumulated in the downlink direction before it - * is pushed into the IPA - Maximum value: TBD - */ - - /* Optional */ - /* Uplink Accumulation Time Limit */ - uint8_t ul_accumulation_time_limit_valid; - /* Must be set to true if ul_accumulation_time_limit is being passed */ - uint32_t ul_accumulation_time_limit; - /* Inform thes remote driver about the time for which data - * is to be accumulated in the uplink direction before it is pushed into - * the IPA (downlink is with respect to the WWAN air interface). - * - Units: milliseconds - * - Maximum value: 255 - */ - - /* Optional */ - /* HW Control Flags */ - uint8_t hw_control_flags_valid; - /* Must be set to true if hw_control_flags is being passed */ - uint32_t hw_control_flags; - /* Informs the remote driver about the hardware control flags: - * - Bit 0: IPA_HW_FLAG_HALT_SYSTEM_ON_NON_TERMINAL_FAILURE -- - * Indicates to the hardware that it must not continue with - * any subsequent operation even if the failure is not terminal - * - Bit 1: IPA_HW_FLAG_NO_REPORT_MHI_CHANNEL_ERORR -- - * Indicates to the hardware that it is not required to report - * channel errors to the host. - * - Bit 2: IPA_HW_FLAG_NO_REPORT_MHI_CHANNEL_WAKE_UP -- - * Indicates to the hardware that it is not required to generate - * wake-up events to the host. - * - Bit 4: IPA_HW_FLAG_WORK_OVER_DDR -- - * Indicates to the hardware that it is accessing addresses in - * the DDR and not over PCIe - * - Bit 5: IPA_HW_FLAG_INTERRUPT_MODE_CTRL_FLAG -- - * Indicates whether the device must - * raise an event to let the host know that it is going into an - * interrupt mode (no longer polling for data/buffer availability) - */ - - /* Optional */ - /* Uplink MSI Event Threshold */ - uint8_t ul_msi_event_threshold_valid; - /* Must be set to true if ul_msi_event_threshold is being passed */ - uint32_t ul_msi_event_threshold; - /* Informs the remote driver about the threshold that will - * cause an interrupt (MSI) to be fired to the host. This ensures - * that the remote driver does not accumulate an excesive number of - * events before firing an interrupt. - * This threshold is applicable for data moved in the UL direction. - * - Maximum value: 65535 - */ - - /* Optional */ - /* Downlink MSI Event Threshold */ - uint8_t dl_msi_event_threshold_valid; - /* Must be set to true if dl_msi_event_threshold is being passed */ - uint32_t dl_msi_event_threshold; - /* Informs the remote driver about the threshold that will - * cause an interrupt (MSI) to be fired to the host. This ensures - * that the remote driver does not accumulate an excesive number of - * events before firing an interrupt - * This threshold is applicable for data that is moved in the - * DL direction - Maximum value: 65535 - */ - - /* Optional */ - /* Uplink Fifo Size */ - uint8_t ul_fifo_size_valid; - /* Must be set to true if ul_fifo_size is being passed */ - uint32_t ul_fifo_size; - /* - * Informs the remote driver about the total Uplink xDCI - * buffer size that holds the complete aggregated frame - * or BAM data fifo size of the peripheral channel/pipe(in Bytes). - * This deprecates the max_aggr_frame_size field. This TLV - * deprecates max_aggr_frame_size TLV from version 1.9 onwards - * and the max_aggr_frame_size TLV will be ignored in the presence - * of this TLV. - */ - - /* Optional */ - /* Downlink Fifo Size */ - uint8_t dl_fifo_size_valid; - /* Must be set to true if dl_fifo_size is being passed */ - uint32_t dl_fifo_size; - /* - * Informs the remote driver about the total Downlink xDCI buffering - * capacity or BAM data fifo size of the peripheral channel/pipe. - * (In Bytes). dl_fifo_size = n * dl_buf_size. This deprecates the - * max_aggr_frame_size field. If this value is set - * max_aggr_frame_size is ignored. - */ - - /* Optional */ - /* Downlink Buffer Size */ - uint8_t dl_buf_size_valid; - /* Must be set to true if dl_buf_size is being passed */ - uint32_t dl_buf_size; - /* Informs the remote driver about the single xDCI buffer size. - * This is applicable only in GSI mode(in Bytes).\n - */ -}; /* Message */ - -/* Response Message; Notifies the remote driver of the configuration - * information - */ -struct ipa_config_resp_msg_v01 { - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /**< Standard response type.*/ -}; /* Message */ - -enum ipa_stats_type_enum_v01 { - IPA_STATS_TYPE_ENUM_MIN_ENUM_VAL_V01 = -2147483647, - /* To force a 32 bit signed enum. Do not change or use */ - QMI_IPA_STATS_TYPE_INVALID_V01 = 0, - /* Invalid stats type identifier */ - QMI_IPA_STATS_TYPE_PIPE_V01 = 1, - /* Pipe stats type */ - QMI_IPA_STATS_TYPE_FILTER_RULES_V01 = 2, - /* Filter rule stats type */ - IPA_STATS_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 - /* To force a 32 bit signed enum. Do not change or use */ -}; - -struct ipa_pipe_stats_info_type_v01 { - uint32_t pipe_index; - /* Pipe index for statistics to be retrieved. */ - - uint64_t num_ipv4_packets; - /* Accumulated number of IPv4 packets over this pipe. */ - - uint64_t num_ipv4_bytes; - /* Accumulated number of IPv4 bytes over this pipe. */ - - uint64_t num_ipv6_packets; - /* Accumulated number of IPv6 packets over this pipe. */ - - uint64_t num_ipv6_bytes; - /* Accumulated number of IPv6 bytes over this pipe. */ -}; - -struct ipa_stats_type_filter_rule_v01 { - uint32_t filter_rule_index; - /* Filter rule index for statistics to be retrieved. */ - - uint64_t num_packets; - /* Accumulated number of packets over this filter rule. */ -}; - -/* Request Message; Retrieve the data statistics collected on modem - * IPA driver. - */ -struct ipa_get_data_stats_req_msg_v01 { - /* Mandatory */ - /* Stats Type */ - enum ipa_stats_type_enum_v01 ipa_stats_type; - /* Indicates the type of statistics to be retrieved. */ - - /* Optional */ - /* Reset Statistics */ - uint8_t reset_stats_valid; - /* Must be set to true if reset_stats is being passed */ - uint8_t reset_stats; - /* Option to reset the specific type of data statistics - * currently collected. - */ -}; /* Message */ - -/* Response Message; Retrieve the data statistics collected - * on modem IPA driver. - */ -struct ipa_get_data_stats_resp_msg_v01 { - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /* Standard response type. */ - - /* Optional */ - /* Stats Type */ - uint8_t ipa_stats_type_valid; - /* Must be set to true if ipa_stats_type is passed */ - enum ipa_stats_type_enum_v01 ipa_stats_type; - /* Indicates the type of statistics that are retrieved. */ - - /* Optional */ - /* Uplink Source Pipe Statistics List */ - uint8_t ul_src_pipe_stats_list_valid; - /* Must be set to true if ul_src_pipe_stats_list is being passed */ - uint32_t ul_src_pipe_stats_list_len; - /* Must be set to # of elements in ul_src_pipe_stats_list */ - struct ipa_pipe_stats_info_type_v01 - ul_src_pipe_stats_list[QMI_IPA_MAX_PIPES_V01]; - /* List of all Uplink pipe statistics that are retrieved. */ - - /* Optional */ - /* Downlink Destination Pipe Statistics List */ - uint8_t dl_dst_pipe_stats_list_valid; - /* Must be set to true if dl_dst_pipe_stats_list is being passed */ - uint32_t dl_dst_pipe_stats_list_len; - /* Must be set to # of elements in dl_dst_pipe_stats_list */ - struct ipa_pipe_stats_info_type_v01 - dl_dst_pipe_stats_list[QMI_IPA_MAX_PIPES_V01]; - /* List of all Downlink pipe statistics that are retrieved. */ - - /* Optional */ - /* Downlink Filter Rule Stats List */ - uint8_t dl_filter_rule_stats_list_valid; - /* Must be set to true if dl_filter_rule_stats_list is being passed */ - uint32_t dl_filter_rule_stats_list_len; - /* Must be set to # of elements in dl_filter_rule_stats_list */ - struct ipa_stats_type_filter_rule_v01 - dl_filter_rule_stats_list[QMI_IPA_MAX_FILTERS_V01]; - /* List of all Downlink filter rule statistics retrieved. */ -}; /* Message */ - -struct ipa_apn_data_stats_info_type_v01 { - uint32_t mux_id; - /* Indicates the MUX ID associated with the APN for which the data - * usage statistics is queried - */ - - uint64_t num_ul_packets; - /* Accumulated number of uplink packets corresponding to - * this Mux ID - */ - - uint64_t num_ul_bytes; - /* Accumulated number of uplink bytes corresponding to - * this Mux ID - */ - - uint64_t num_dl_packets; - /* Accumulated number of downlink packets corresponding - * to this Mux ID - */ - - uint64_t num_dl_bytes; - /* Accumulated number of downlink bytes corresponding to - * this Mux ID - */ -}; /* Type */ - -/* Request Message; Retrieve the APN data statistics collected from modem */ -struct ipa_get_apn_data_stats_req_msg_v01 { - /* Optional */ - /* Mux ID List */ - uint8_t mux_id_list_valid; - /* Must be set to true if mux_id_list is being passed */ - uint32_t mux_id_list_len; - /* Must be set to # of elements in mux_id_list */ - uint32_t mux_id_list[QMI_IPA_MAX_APN_V01]; - /* The list of MUX IDs associated with APNs for which the data usage - * statistics is being retrieved - */ -}; /* Message */ - -/* Response Message; Retrieve the APN data statistics collected from modem */ -struct ipa_get_apn_data_stats_resp_msg_v01 { - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /* Standard response type.*/ - - /* Optional */ - /* APN Data Statistics List */ - uint8_t apn_data_stats_list_valid; - /* Must be set to true if apn_data_stats_list is being passed */ - uint32_t apn_data_stats_list_len; - /* Must be set to # of elements in apn_data_stats_list */ - struct ipa_apn_data_stats_info_type_v01 - apn_data_stats_list[QMI_IPA_MAX_APN_V01]; - /* List of APN data retrieved as per request on mux_id. - * For now, only one APN monitoring is supported on modem driver. - * Making this as list for expandability to support more APNs in future. - */ -}; /* Message */ - -struct ipa_data_usage_quota_info_type_v01 { - uint32_t mux_id; - /* Indicates the MUX ID associated with the APN for which the data usage - * quota needs to be set - */ - - uint64_t num_Mbytes; - /* Number of Mega-bytes of quota value to be set on this APN associated - * with this Mux ID. - */ -}; /* Type */ - -/* Request Message; Master driver sets a data usage quota value on - * modem driver - */ -struct ipa_set_data_usage_quota_req_msg_v01 { - /* Optional */ - /* APN Quota List */ - uint8_t apn_quota_list_valid; - /* Must be set to true if apn_quota_list is being passed */ - uint32_t apn_quota_list_len; - /* Must be set to # of elements in apn_quota_list */ - struct ipa_data_usage_quota_info_type_v01 - apn_quota_list[QMI_IPA_MAX_APN_V01]; - /* The list of APNs on which a data usage quota to be set on modem - * driver. For now, only one APN monitoring is supported on modem - * driver. Making this as list for expandability to support more - * APNs in future. - */ -}; /* Message */ - -/* Response Message; Master driver sets a data usage on modem driver. */ -struct ipa_set_data_usage_quota_resp_msg_v01 { - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /* Standard response type.*/ -}; /* Message */ - -/* Indication Message; Modem driver sends this indication to master - * driver when the data usage quota is reached - */ -struct ipa_data_usage_quota_reached_ind_msg_v01 { - /* Mandatory */ - /* APN Quota List */ - struct ipa_data_usage_quota_info_type_v01 apn; - /* This message indicates which APN has the previously set quota - * reached. For now, only one APN monitoring is supported on modem - * driver. - */ -}; /* Message */ - -/* Request Message; Master driver request modem driver to terminate - * the current data usage quota monitoring session. - */ -struct ipa_stop_data_usage_quota_req_msg_v01 { - /* This element is a placeholder to prevent the declaration of - * an empty struct. DO NOT USE THIS FIELD UNDER ANY CIRCUMSTANCE - */ - char __placeholder; -}; /* Message */ - -/* Response Message; Master driver request modem driver to terminate - * the current quota monitoring session. - */ -struct ipa_stop_data_usage_quota_resp_msg_v01 { - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /**< Standard response type.*/ -}; /* Message */ - -/* Request Message; Request from Modem IPA driver to set DPL peripheral pipe */ -struct ipa_install_fltr_rule_req_ex_msg_v01 { - - /* Optional */ - /* Extended Filter Specification */ - uint8_t filter_spec_ex_list_valid; - uint32_t filter_spec_ex_list_len; - struct ipa_filter_spec_ex_type_v01 - filter_spec_ex_list[QMI_IPA_MAX_FILTERS_EX_V01]; - /* List of filter specifications of filters that must be installed in - * the IPAv3.x hardware. - * The driver installing these rules must do so in the same order as - * specified in this list. - */ - - /* Optional */ - /* Pipe Index to Install Rule */ - uint8_t source_pipe_index_valid; - uint32_t source_pipe_index; - /* Pipe index to install the filter rule. - * The requester may not always know the pipe indices. If not specified, - * the receiver must install this rule on all pipes that it controls, - * through which data may be fed into the IPA. - */ - - /* Optional */ - /* Total Number of IPv4 Filters in the Filter Spec List */ - uint8_t num_ipv4_filters_valid; - uint32_t num_ipv4_filters; - /* Number of IPv4 rules included in the filter specification list. */ - - /* Optional */ - /* Total Number of IPv6 Filters in the Filter Spec List */ - uint8_t num_ipv6_filters_valid; - uint32_t num_ipv6_filters; - /* Number of IPv6 rules included in the filter specification list. */ - - /* Optional */ - /* List of XLAT Filter Indices in the Filter Spec List */ - uint8_t xlat_filter_indices_list_valid; - uint32_t xlat_filter_indices_list_len; - uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_EX_V01]; - /* List of XLAT filter indices. - * Filter rules at specified indices must be modified by the - * receiver if the PDN is XLAT before installing them on the associated - * IPA consumer pipe. - */ -}; /* Message */ - -/* Response Message; Requests installation of filtering rules in the hardware - * block on the remote side. - */ -struct ipa_install_fltr_rule_resp_ex_msg_v01 { - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /* Standard response type. - * Standard response type. Contains the following data members: - * - qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE - * - qmi_error_type -- Error code. Possible error code values are - * described in the error codes - * section of each message - * definition. - */ - - /* Optional */ - /* Rule ID List */ - uint8_t rule_id_valid; - uint32_t rule_id_len; - uint32_t rule_id[QMI_IPA_MAX_FILTERS_EX_V01]; - /* List of rule IDs returned to the control point. - * Any further reference to the rule is done using the filter rule ID - * specified in this list. - */ -}; /* Message */ - -/* - * Request Message; Requests the modem IPA driver to enable or - * disable collection of per client statistics. - */ -struct ipa_enable_per_client_stats_req_msg_v01 { - - /* Mandatory */ - /* Collect statistics per client; */ - uint8_t enable_per_client_stats; - /* - * Indicates whether to start or stop collecting - * per client statistics. - */ -}; /* Message */ - -/* - * Response Message; Requests the modem IPA driver to enable or disable - * collection of per client statistics. - */ -struct ipa_enable_per_client_stats_resp_msg_v01 { - - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /* Standard response type. */ -}; /* Message */ - -struct ipa_per_client_stats_info_type_v01 { - - uint32_t client_id; - /* - * Id of the client on APPS processor side for which Modem processor - * needs to send uplink/downlink statistics. - */ - - uint32_t src_pipe_id; - /* - * IPA consumer pipe on which client on APPS side sent uplink - * data to modem. - */ - - uint64_t num_ul_ipv4_bytes; - /* - * Accumulated number of uplink IPv4 bytes for a client. - */ - - uint64_t num_ul_ipv6_bytes; - /* - * Accumulated number of uplink IPv6 bytes for a client. - */ - - uint64_t num_dl_ipv4_bytes; - /* - * Accumulated number of downlink IPv4 bytes for a client. - */ - - uint64_t num_dl_ipv6_bytes; - /* - * Accumulated number of downlink IPv6 byes for a client. - */ - - - uint32_t num_ul_ipv4_pkts; - /* - * Accumulated number of uplink IPv4 packets for a client. - */ - - uint32_t num_ul_ipv6_pkts; - /* - * Accumulated number of uplink IPv6 packets for a client. - */ - - uint32_t num_dl_ipv4_pkts; - /* - * Accumulated number of downlink IPv4 packets for a client. - */ - - uint32_t num_dl_ipv6_pkts; - /* - * Accumulated number of downlink IPv6 packets for a client. - */ -}; /* Type */ - -/* - * Request Message; Requests the modem IPA driver to provide statistics - * for a givenclient. - */ -struct ipa_get_stats_per_client_req_msg_v01 { - - /* Mandatory */ - /* Client id */ - uint32_t client_id; - /* - * Id of the client on APPS processor side for which Modem processor - * needs to send uplink/downlink statistics. if client id is specified - * as 0xffffffff, then Q6 will send the stats for all the clients of - * the specified source pipe. - */ - - /* Mandatory */ - /* Source pipe id */ - uint32_t src_pipe_id; - /* - * IPA consumer pipe on which client on APPS side sent uplink - * data to modem. In future, this implementation can be extended - * to provide 0xffffffff as the source pipe id, where Q6 will send - * the stats of all the clients across all different tethered-pipes. - */ - - /* Optional */ - /* Reset client statistics. */ - uint8_t reset_stats_valid; - /* Must be set to true if reset_stats is being passed. */ - uint8_t reset_stats; - /* - * Option to reset the statistics currently collected by modem for this - * particular client. - */ -}; /* Message */ - -/* - * Response Message; Requests the modem IPA driver to provide statistics - * for a given client. - */ -struct ipa_get_stats_per_client_resp_msg_v01 { - - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /* Standard response type. */ - - /* Optional */ - /* Per clients Statistics List */ - uint8_t per_client_stats_list_valid; - /* Must be set to true if per_client_stats_list is being passed. */ - uint32_t per_client_stats_list_len; - /* Must be set to # of elements in per_client_stats_list. */ - struct ipa_per_client_stats_info_type_v01 - per_client_stats_list[QMI_IPA_MAX_PER_CLIENTS_V01]; - /* - * List of all per client statistics that are retrieved. - */ -}; /* Message */ - -struct ipa_ul_firewall_rule_type_v01 { - - enum ipa_ip_type_enum_v01 ip_type; - /* - * IP type for which this rule is applicable. - * The driver must identify the filter table (v6 or v4), and this - * field is essential for that. Values: - * - QMI_IPA_IP_TYPE_INVALID (0) -- Invalid IP type identifier - * - QMI_IPA_IP_TYPE_V4 (1) -- IPv4 type - * - QMI_IPA_IP_TYPE_V6 (2) -- IPv6 type - */ - - struct ipa_filter_rule_type_v01 filter_rule; - /* - * Rules in the filter specification. These rules are the - * ones that are matched against fields in the packet. - * Currently we only send IPv6 whitelist rules to Q6. - */ -}; /* Type */ - -/* - * Request Message; Requestes remote IPA driver to install uplink - * firewall rules. - */ -struct ipa_configure_ul_firewall_rules_req_msg_v01 { - - /* Optional */ - /* Uplink Firewall Specification */ - uint32_t firewall_rules_list_len; - /* Must be set to # of elements in firewall_rules_list. */ - struct ipa_ul_firewall_rule_type_v01 - firewall_rules_list[QMI_IPA_MAX_UL_FIREWALL_RULES_V01]; - /* - * List of uplink firewall specifications of filters that must be - * installed. - */ - - uint32_t mux_id; - /* - * QMAP Mux ID. As a part of the QMAP protocol, - * several data calls may be multiplexed over the same physical - * transport channel. This identifier is used to identify one - * such data call. The maximum value for this identifier is 255. - */ - - /* Optional */ - uint8_t disable_valid; - /* Must be set to true if enable is being passed. */ - uint8_t disable; - /* - * Indicates whether uplink firewall needs to be enabled or disabled. - */ - - /* Optional */ - uint8_t are_blacklist_filters_valid; - /* Must be set to true if are_blacklist_filters is being passed. */ - uint8_t are_blacklist_filters; - /* - * Indicates whether the filters received as part of this message are - * blacklist filters. i.e. drop uplink packets matching these rules. - */ -}; /* Message */ - -/* - * Response Message; Requestes remote IPA driver to install - * uplink firewall rules. - */ -struct ipa_configure_ul_firewall_rules_resp_msg_v01 { - - /* Mandatory */ - /* Result Code */ - struct ipa_qmi_response_type_v01 resp; - /* - * Standard response type. - * Standard response type. Contains the following data members: - * qmi_result_type -- QMI_RESULT_SUCCESS or QMI_RESULT_FAILURE - * qmi_error_type -- Error code. Possible error code values are - * described in the error codes section of each message definition. - */ -}; /* Message */ - -enum ipa_ul_firewall_status_enum_v01 { - IPA_UL_FIREWALL_STATUS_ENUM_MIN_ENUM_VAL_V01 = -2147483647, - /* To force a 32 bit signed enum. Do not change or use*/ - QMI_IPA_UL_FIREWALL_STATUS_SUCCESS_V01 = 0, - /* Indicates that the uplink firewall rules - * are configured successfully. - */ - QMI_IPA_UL_FIREWALL_STATUS_FAILURE_V01 = 1, - /* Indicates that the uplink firewall rules - * are not configured successfully. - */ - IPA_UL_FIREWALL_STATUS_ENUM_MAX_ENUM_VAL_V01 = 2147483647 - /* To force a 32 bit signed enum. Do not change or use*/ -}; - -struct ipa_ul_firewall_config_result_type_v01 { - - enum ipa_ul_firewall_status_enum_v01 is_success; - /* - * Indicates whether the uplink firewall rules are configured - * successfully. - */ - - uint32_t mux_id; - /* - * QMAP Mux ID. As a part of the QMAP protocol, - * several data calls may be multiplexed over the same physical - * transport channel. This identifier is used to identify one - * such data call. The maximum value for this identifier is 255. - */ -}; - -/* - * Indication Message; Requestes remote IPA driver to install - * uplink firewall rules. - */ -struct ipa_configure_ul_firewall_rules_ind_msg_v01 { - - struct ipa_ul_firewall_config_result_type_v01 result; -}; /* Message */ - - -/*Service Message Definition*/ -#define QMI_IPA_INDICATION_REGISTER_REQ_V01 0x0020 -#define QMI_IPA_INDICATION_REGISTER_RESP_V01 0x0020 -#define QMI_IPA_INIT_MODEM_DRIVER_REQ_V01 0x0021 -#define QMI_IPA_INIT_MODEM_DRIVER_RESP_V01 0x0021 -#define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_V01 0x0022 -#define QMI_IPA_INSTALL_FILTER_RULE_REQ_V01 0x0023 -#define QMI_IPA_INSTALL_FILTER_RULE_RESP_V01 0x0023 -#define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_V01 0x0024 -#define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_V01 0x0024 -#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0025 -#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0025 -#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0026 -#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0026 -#define QMI_IPA_CONFIG_REQ_V01 0x0027 -#define QMI_IPA_CONFIG_RESP_V01 0x0027 -#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0028 -#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0028 -#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0029 -#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0029 -#define QMI_IPA_GET_DATA_STATS_REQ_V01 0x0030 -#define QMI_IPA_GET_DATA_STATS_RESP_V01 0x0030 -#define QMI_IPA_GET_APN_DATA_STATS_REQ_V01 0x0031 -#define QMI_IPA_GET_APN_DATA_STATS_RESP_V01 0x0031 -#define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01 0x0032 -#define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_V01 0x0032 -#define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_V01 0x0033 -#define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01 0x0034 -#define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_V01 0x0034 -#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_V01 0x0035 -#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_V01 0x0035 -#define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_V01 0x0037 -#define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_V01 0x0037 -#define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_V01 0x0038 -#define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_V01 0x0038 -#define QMI_IPA_GET_STATS_PER_CLIENT_REQ_V01 0x0039 -#define QMI_IPA_GET_STATS_PER_CLIENT_RESP_V01 0x0039 -#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_V01 0x003A -#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_V01 0x003A -#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_V01 0x003A - -/* add for max length*/ -#define QMI_IPA_INIT_MODEM_DRIVER_REQ_MAX_MSG_LEN_V01 162 -#define QMI_IPA_INIT_MODEM_DRIVER_RESP_MAX_MSG_LEN_V01 25 -#define QMI_IPA_INDICATION_REGISTER_REQ_MAX_MSG_LEN_V01 8 -#define QMI_IPA_INDICATION_REGISTER_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_INSTALL_FILTER_RULE_REQ_MAX_MSG_LEN_V01 22369 -#define QMI_IPA_INSTALL_FILTER_RULE_RESP_MAX_MSG_LEN_V01 783 -#define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_MAX_MSG_LEN_V01 870 -#define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_MAX_MSG_LEN_V01 7 -#define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_MAX_MSG_LEN_V01 15 - - -#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 18 -#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 7 -#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 - - -#define QMI_IPA_CONFIG_REQ_MAX_MSG_LEN_V01 102 -#define QMI_IPA_CONFIG_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 18 -#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 7 -#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_GET_DATA_STATS_REQ_MAX_MSG_LEN_V01 11 -#define QMI_IPA_GET_DATA_STATS_RESP_MAX_MSG_LEN_V01 2234 -#define QMI_IPA_GET_APN_DATA_STATS_REQ_MAX_MSG_LEN_V01 36 -#define QMI_IPA_GET_APN_DATA_STATS_RESP_MAX_MSG_LEN_V01 299 -#define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 100 -#define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 0 -#define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7 - -#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_MAX_MSG_LEN_V01 4 -#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_MAX_MSG_LEN_V01 7 - -#define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_MAX_MSG_LEN_V01 22685 -#define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_MAX_MSG_LEN_V01 523 - -#define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_MAX_MSG_LEN_V01 4 -#define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_MAX_MSG_LEN_V01 7 - -#define QMI_IPA_GET_STATS_PER_CLIENT_REQ_MAX_MSG_LEN_V01 18 -#define QMI_IPA_GET_STATS_PER_CLIENT_RESP_MAX_MSG_LEN_V01 3595 - -#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_MAX_MSG_LEN_V01 9875 -#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_MAX_MSG_LEN_V01 7 -#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_MAX_MSG_LEN_V01 11 -/* Service Object Accessor */ - -#endif/* IPA_QMI_SERVICE_V01_H */ diff --git a/sdm710/original-kernel-headers/linux/mdss_rotator.h b/sdm710/original-kernel-headers/linux/mdss_rotator.h deleted file mode 100644 index 23f0ff48..00000000 --- a/sdm710/original-kernel-headers/linux/mdss_rotator.h +++ /dev/null @@ -1,144 +0,0 @@ -#ifndef _MDSS_ROTATOR_H_ -#define _MDSS_ROTATOR_H_ - -#include <linux/msm_mdp_ext.h> - -#define MDSS_ROTATOR_IOCTL_MAGIC 'w' - -/* open a rotation session */ -#define MDSS_ROTATION_OPEN \ - _IOWR(MDSS_ROTATOR_IOCTL_MAGIC, 1, struct mdp_rotation_config *) - -/* change the rotation session configuration */ -#define MDSS_ROTATION_CONFIG \ - _IOWR(MDSS_ROTATOR_IOCTL_MAGIC, 2, struct mdp_rotation_config *) - -/* queue the rotation request */ -#define MDSS_ROTATION_REQUEST \ - _IOWR(MDSS_ROTATOR_IOCTL_MAGIC, 3, struct mdp_rotation_request *) - -/* close a rotation session with the specified rotation session ID */ -#define MDSS_ROTATION_CLOSE _IOW(MDSS_ROTATOR_IOCTL_MAGIC, 4, unsigned int) - -/* - * Rotation request flag - */ -/* no rotation flag, i.e. color space conversion */ -#define MDP_ROTATION_NOP 0x01 - -/* left/right flip */ -#define MDP_ROTATION_FLIP_LR 0x02 - -/* up/down flip */ -#define MDP_ROTATION_FLIP_UD 0x04 - -/* rotate 90 degree */ -#define MDP_ROTATION_90 0x08 - -/* rotate 180 degre */ -#define MDP_ROTATION_180 (MDP_ROTATION_FLIP_LR | MDP_ROTATION_FLIP_UD) - -/* rotate 270 degree */ -#define MDP_ROTATION_270 (MDP_ROTATION_90 | MDP_ROTATION_180) - -/* format is interlaced */ -#define MDP_ROTATION_DEINTERLACE 0x10 - -/* enable bwc */ -#define MDP_ROTATION_BWC_EN 0x40 - -/* secure data */ -#define MDP_ROTATION_SECURE 0x80 - -/* - * Rotation commit flag - */ -/* Flag indicates to validate the rotation request */ -#define MDSS_ROTATION_REQUEST_VALIDATE 0x01 - -#define MDP_ROTATION_REQUEST_VERSION_1_0 0x00010000 - -/* - * Client can let driver to allocate the hardware resources with - * this particular hw resource id. - */ -#define MDSS_ROTATION_HW_ANY 0xFFFFFFFF - -/* - * Configuration Structures - */ -struct mdp_rotation_buf_info { - uint32_t width; - uint32_t height; - uint32_t format; - struct mult_factor comp_ratio; -}; - -struct mdp_rotation_config { - uint32_t version; - uint32_t session_id; - struct mdp_rotation_buf_info input; - struct mdp_rotation_buf_info output; - uint32_t frame_rate; - uint32_t flags; - uint32_t reserved[6]; -}; - -struct mdp_rotation_item { - /* rotation request flag */ - uint32_t flags; - - /* Source crop rectangle */ - struct mdp_rect src_rect; - - /* Destination rectangle */ - struct mdp_rect dst_rect; - - /* Input buffer for the request */ - struct mdp_layer_buffer input; - - /* The output buffer for the request */ - struct mdp_layer_buffer output; - - /* - * DMA pipe selection for this request by client: - * 0: DMA pipe 0 - * 1: DMA pipe 1 - * or MDSS_ROTATION_HW_ANY if client wants - * driver to allocate any that is available - */ - uint32_t pipe_idx; - - /* - * Write-back block selection for this request by client: - * 0: Write-back block 0 - * 1: Write-back block 1 - * or MDSS_ROTATION_HW_ANY if client wants - * driver to allocate any that is available - */ - uint32_t wb_idx; - - /* Which session ID is this request scheduled on */ - uint32_t session_id; - - /* 32bits reserved value for future usage */ - uint32_t reserved[6]; -}; - -struct mdp_rotation_request { - /* 32bit version indicates the request structure */ - uint32_t version; - - uint32_t flags; - - /* Number of rotation request items in the list */ - uint32_t count; - - /* Pointer to a list of rotation request items */ - struct mdp_rotation_item *list; - - /* 32bits reserved value for future usage*/ - uint32_t reserved[6]; -}; - -#endif /* _MDSS_ROTATOR_H_*/ diff --git a/sdm710/original-kernel-headers/linux/mfd/msm-adie-codec.h b/sdm710/original-kernel-headers/linux/mfd/msm-adie-codec.h deleted file mode 100644 index 3f523c00..00000000 --- a/sdm710/original-kernel-headers/linux/mfd/msm-adie-codec.h +++ /dev/null @@ -1,147 +0,0 @@ -#ifndef __UAPI_MFD_MSM_ADIE_CODEC_H -#define __UAPI_MFD_MSM_ADIE_CODEC_H - -#include <linux/types.h> - -/* Value Represents a entry */ -#define ADIE_CODEC_ACTION_ENTRY 0x1 -/* Value representing a delay wait */ -#define ADIE_CODEC_ACTION_DELAY_WAIT 0x2 -/* Value representing a stage reached */ -#define ADIE_CODEC_ACTION_STAGE_REACHED 0x3 - -/* This value is the state after the client sets the path */ -#define ADIE_CODEC_PATH_OFF 0x0050 - -/* State to which client asks the drv to proceed to where it can - * set up the clocks and 0-fill PCM buffers - */ -#define ADIE_CODEC_DIGITAL_READY 0x0100 - -/* State to which client asks the drv to proceed to where it can - * start sending data after internal steady state delay - */ -#define ADIE_CODEC_DIGITAL_ANALOG_READY 0x1000 - - -/* Client Asks adie to switch off the Analog portion of the - * the internal codec. After the use of this path - */ -#define ADIE_CODEC_ANALOG_OFF 0x0750 - - -/* Client Asks adie to switch off the digital portion of the - * the internal codec. After switching off the analog portion. - * - * 0-fill PCM may or maynot be sent at this point - * - */ -#define ADIE_CODEC_DIGITAL_OFF 0x0600 - -/* State to which client asks the drv to write the default values - * to the registers - */ -#define ADIE_CODEC_FLASH_IMAGE 0x0001 - -/* Path type */ -#define ADIE_CODEC_RX 0 -#define ADIE_CODEC_TX 1 -#define ADIE_CODEC_LB 3 -#define ADIE_CODEC_MAX 4 - -#define ADIE_CODEC_PACK_ENTRY(reg, mask, val) ((val)|(mask << 8)|(reg << 16)) - -#define ADIE_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \ - do { \ - ((reg) = ((packed >> 16) & (0xff))); \ - ((mask) = ((packed >> 8) & (0xff))); \ - ((val) = ((packed) & (0xff))); \ - } while (0); - -struct adie_codec_action_unit { - u32 type; - u32 action; -}; - -struct adie_codec_hwsetting_entry { - struct adie_codec_action_unit *actions; - u32 action_sz; - u32 freq_plan; - u32 osr; - /* u32 VolMask; - * u32 SidetoneMask; - */ -}; - -struct adie_codec_dev_profile { - u32 path_type; /* RX or TX */ - u32 setting_sz; - struct adie_codec_hwsetting_entry *settings; -}; - -struct adie_codec_register { - u8 reg; - u8 mask; - u8 val; -}; - -struct adie_codec_register_image { - struct adie_codec_register *regs; - u32 img_sz; -}; - -struct adie_codec_path; - -struct adie_codec_anc_data { - u32 size; - u32 writes[]; -}; - -struct adie_codec_operations { - int codec_id; - int (*codec_open)(struct adie_codec_dev_profile *profile, - struct adie_codec_path **path_pptr); - int (*codec_close)(struct adie_codec_path *path_ptr); - int (*codec_setpath)(struct adie_codec_path *path_ptr, - u32 freq_plan, u32 osr); - int (*codec_proceed_stage)(struct adie_codec_path *path_ptr, - u32 state); - u32 (*codec_freq_supported)(struct adie_codec_dev_profile *profile, - u32 requested_freq); - int (*codec_enable_sidetone)(struct adie_codec_path *rx_path_ptr, - u32 enable); - int (*codec_enable_anc)(struct adie_codec_path *rx_path_ptr, - u32 enable, struct adie_codec_anc_data *calibration_writes); - int (*codec_set_device_digital_volume)( - struct adie_codec_path *path_ptr, - u32 num_channels, - u32 vol_percentage); - - int (*codec_set_device_analog_volume)(struct adie_codec_path *path_ptr, - u32 num_channels, - u32 volume); - int (*codec_set_master_mode)(struct adie_codec_path *path_ptr, - u8 master); -}; - -int adie_codec_register_codec_operations( - const struct adie_codec_operations *codec_ops); -int adie_codec_open(struct adie_codec_dev_profile *profile, - struct adie_codec_path **path_pptr); -int adie_codec_setpath(struct adie_codec_path *path_ptr, - u32 freq_plan, u32 osr); -int adie_codec_proceed_stage(struct adie_codec_path *path_ptr, u32 state); -int adie_codec_close(struct adie_codec_path *path_ptr); -u32 adie_codec_freq_supported(struct adie_codec_dev_profile *profile, - u32 requested_freq); -int adie_codec_enable_sidetone(struct adie_codec_path *rx_path_ptr, u32 enable); -int adie_codec_enable_anc(struct adie_codec_path *rx_path_ptr, u32 enable, - struct adie_codec_anc_data *calibration_writes); -int adie_codec_set_device_digital_volume(struct adie_codec_path *path_ptr, - u32 num_channels, u32 vol_percentage /* in percentage */); - -int adie_codec_set_device_analog_volume(struct adie_codec_path *path_ptr, - u32 num_channels, u32 volume /* in percentage */); - -int adie_codec_set_master_mode(struct adie_codec_path *path_ptr, u8 master); -#endif diff --git a/sdm710/original-kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h b/sdm710/original-kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h deleted file mode 100644 index 63ab6241..00000000 --- a/sdm710/original-kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h +++ /dev/null @@ -1,1399 +0,0 @@ -#ifndef WCD9320_REGISTERS_H -#define WCD9320_REGISTERS_H - -#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h> - -#define TAIKO_A_CHIP_CTL WCD9XXX_A_CHIP_CTL -#define TAIKO_A_CHIP_CTL__POR WCD9XXX_A_CHIP_CTL__POR -#define TAIKO_A_CHIP_STATUS WCD9XXX_A_CHIP_STATUS -#define TAIKO_A_CHIP_STATUS__POR WCD9XXX_A_CHIP_STATUS__POR -#define TAIKO_A_CHIP_ID_BYTE_0 WCD9XXX_A_CHIP_ID_BYTE_0 -#define TAIKO_A_CHIP_ID_BYTE_0__POR WCD9XXX_A_CHIP_ID_BYTE_0__POR -#define TAIKO_A_CHIP_ID_BYTE_1 WCD9XXX_A_CHIP_ID_BYTE_1 -#define TAIKO_A_CHIP_ID_BYTE_1__POR WCD9XXX_A_CHIP_ID_BYTE_1__POR -#define TAIKO_A_CHIP_ID_BYTE_2 WCD9XXX_A_CHIP_ID_BYTE_2 -#define TAIKO_A_CHIP_ID_BYTE_2__POR WCD9XXX_A_CHIP_ID_BYTE_2__POR -#define TAIKO_A_CHIP_ID_BYTE_3 WCD9XXX_A_CHIP_ID_BYTE_3 -#define TAIKO_A_CHIP_ID_BYTE_3__POR WCD9XXX_A_CHIP_ID_BYTE_3__POR -#define TAIKO_A_CHIP_VERSION WCD9XXX_A_CHIP_VERSION -#define TAIKO_A_CHIP_VERSION__POR WCD9XXX_A_CHIP_VERSION__POR -#define TAIKO_A_SB_VERSION WCD9XXX_A_SB_VERSION -#define TAIKO_A_SB_VERSION__POR WCD9XXX_A_SB_VERSION__POR -#define TAIKO_A_SLAVE_ID_1 WCD9XXX_A_SLAVE_ID_1 -#define TAIKO_A_SLAVE_ID_1__POR WCD9XXX_A_SLAVE_ID_1__POR -#define TAIKO_A_SLAVE_ID_2 WCD9XXX_A_SLAVE_ID_2 -#define TAIKO_A_SLAVE_ID_2__POR WCD9XXX_A_SLAVE_ID_2__POR -#define TAIKO_A_SLAVE_ID_3 WCD9XXX_A_SLAVE_ID_3 -#define TAIKO_A_SLAVE_ID_3__POR WCD9XXX_A_SLAVE_ID_3__POR -#define TAIKO_A_PIN_CTL_OE0 (0x010) -#define TAIKO_A_PIN_CTL_OE0__POR (0x00) -#define TAIKO_A_PIN_CTL_OE1 (0x011) -#define TAIKO_A_PIN_CTL_OE1__POR (0x00) -#define TAIKO_A_PIN_CTL_DATA0 (0x012) -#define TAIKO_A_PIN_CTL_DATA0__POR (0x00) -#define TAIKO_A_PIN_CTL_DATA1 (0x013) -#define TAIKO_A_PIN_CTL_DATA1__POR (0x00) -#define TAIKO_A_HDRIVE_GENERIC (0x018) -#define TAIKO_A_HDRIVE_GENERIC__POR (0x00) -#define TAIKO_A_HDRIVE_OVERRIDE (0x019) -#define TAIKO_A_HDRIVE_OVERRIDE__POR (0x08) -#define TAIKO_A_ANA_CSR_WAIT_STATE (0x020) -#define TAIKO_A_ANA_CSR_WAIT_STATE__POR (0x44) -#define TAIKO_A_PROCESS_MONITOR_CTL0 (0x040) -#define TAIKO_A_PROCESS_MONITOR_CTL0__POR (0x80) -#define TAIKO_A_PROCESS_MONITOR_CTL1 (0x041) -#define TAIKO_A_PROCESS_MONITOR_CTL1__POR (0x00) -#define TAIKO_A_PROCESS_MONITOR_CTL2 (0x042) -#define TAIKO_A_PROCESS_MONITOR_CTL2__POR (0x00) -#define TAIKO_A_PROCESS_MONITOR_CTL3 (0x043) -#define TAIKO_A_PROCESS_MONITOR_CTL3__POR (0x01) -#define TAIKO_A_QFUSE_CTL (0x048) -#define TAIKO_A_QFUSE_CTL__POR (0x00) -#define TAIKO_A_QFUSE_STATUS (0x049) -#define TAIKO_A_QFUSE_STATUS__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT0 (0x04A) -#define TAIKO_A_QFUSE_DATA_OUT0__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT1 (0x04B) -#define TAIKO_A_QFUSE_DATA_OUT1__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT2 (0x04C) -#define TAIKO_A_QFUSE_DATA_OUT2__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT3 (0x04D) -#define TAIKO_A_QFUSE_DATA_OUT3__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT4 (0x04E) -#define TAIKO_A_QFUSE_DATA_OUT4__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT5 (0x04F) -#define TAIKO_A_QFUSE_DATA_OUT5__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT6 (0x050) -#define TAIKO_A_QFUSE_DATA_OUT6__POR (0x00) -#define TAIKO_A_QFUSE_DATA_OUT7 (0x051) -#define TAIKO_A_QFUSE_DATA_OUT7__POR (0x00) -#define TAIKO_A_CDC_CTL WCD9XXX_A_CDC_CTL -#define TAIKO_A_CDC_CTL__POR WCD9XXX_A_CDC_CTL__POR -#define TAIKO_A_LEAKAGE_CTL WCD9XXX_A_LEAKAGE_CTL -#define TAIKO_A_LEAKAGE_CTL__POR WCD9XXX_A_LEAKAGE_CTL__POR -#define TAIKO_A_INTR_MODE (0x090) -#define TAIKO_A_INTR_MODE__POR (0x00) -#define TAIKO_A_INTR_MASK0 (0x094) -#define TAIKO_A_INTR_MASK0__POR (0xFF) -#define TAIKO_A_INTR_MASK1 (0x095) -#define TAIKO_A_INTR_MASK1__POR (0xFF) -#define TAIKO_A_INTR_MASK2 (0x096) -#define TAIKO_A_INTR_MASK2__POR (0x3F) -#define TAIKO_A_INTR_MASK3 (0x097) -#define TAIKO_A_INTR_MASK3__POR (0x3F) -#define TAIKO_A_INTR_STATUS0 (0x098) -#define TAIKO_A_INTR_STATUS0__POR (0x00) -#define TAIKO_A_INTR_STATUS1 (0x099) -#define TAIKO_A_INTR_STATUS1__POR (0x00) -#define TAIKO_A_INTR_STATUS2 (0x09A) -#define TAIKO_A_INTR_STATUS2__POR (0x00) -#define TAIKO_A_INTR_STATUS3 (0x09B) -#define TAIKO_A_INTR_STATUS3__POR (0x00) -#define TAIKO_A_INTR_CLEAR0 (0x09C) -#define TAIKO_A_INTR_CLEAR0__POR (0x00) -#define TAIKO_A_INTR_CLEAR1 (0x09D) -#define TAIKO_A_INTR_CLEAR1__POR (0x00) -#define TAIKO_A_INTR_CLEAR2 (0x09E) -#define TAIKO_A_INTR_CLEAR2__POR (0x00) -#define TAIKO_A_INTR_CLEAR3 (0x09F) -#define TAIKO_A_INTR_CLEAR3__POR (0x00) -#define TAIKO_A_INTR_LEVEL0 (0x0A0) -#define TAIKO_A_INTR_LEVEL0__POR (0x01) -#define TAIKO_A_INTR_LEVEL1 (0x0A1) -#define TAIKO_A_INTR_LEVEL1__POR (0x00) -#define TAIKO_A_INTR_LEVEL2 (0x0A2) -#define TAIKO_A_INTR_LEVEL2__POR (0x00) -#define TAIKO_A_INTR_LEVEL3 (0x0A3) -#define TAIKO_A_INTR_LEVEL3__POR (0x00) -#define TAIKO_A_INTR_TEST0 (0x0A4) -#define TAIKO_A_INTR_TEST0__POR (0x00) -#define TAIKO_A_INTR_TEST1 (0x0A5) -#define TAIKO_A_INTR_TEST1__POR (0x00) -#define TAIKO_A_INTR_TEST2 (0x0A6) -#define TAIKO_A_INTR_TEST2__POR (0x00) -#define TAIKO_A_INTR_TEST3 (0x0A7) -#define TAIKO_A_INTR_TEST3__POR (0x00) -#define TAIKO_A_INTR_SET0 (0x0A8) -#define TAIKO_A_INTR_SET0__POR (0x00) -#define TAIKO_A_INTR_SET1 (0x0A9) -#define TAIKO_A_INTR_SET1__POR (0x00) -#define TAIKO_A_INTR_SET2 (0x0AA) -#define TAIKO_A_INTR_SET2__POR (0x00) -#define TAIKO_A_INTR_SET3 (0x0AB) -#define TAIKO_A_INTR_SET3__POR (0x00) -#define TAIKO_A_INTR_DESTN0 (0x0AC) -#define TAIKO_A_INTR_DESTN0__POR (0x00) -#define TAIKO_A_INTR_DESTN1 (0x0AD) -#define TAIKO_A_INTR_DESTN1__POR (0x00) -#define TAIKO_A_INTR_DESTN2 (0x0AE) -#define TAIKO_A_INTR_DESTN2__POR (0x00) -#define TAIKO_A_INTR_DESTN3 (0x0AF) -#define TAIKO_A_INTR_DESTN3__POR (0x00) -#define TAIKO_A_CDC_TX_I2S_SCK_MODE (0x0C0) -#define TAIKO_A_CDC_TX_I2S_SCK_MODE__POR (0x00) -#define TAIKO_A_CDC_TX_I2S_WS_MODE (0x0C1) -#define TAIKO_A_CDC_TX_I2S_WS_MODE__POR (0x00) -#define TAIKO_A_CDC_DMIC_DATA0_MODE (0x0C4) -#define TAIKO_A_CDC_DMIC_DATA0_MODE__POR (0x00) -#define TAIKO_A_CDC_DMIC_CLK0_MODE (0x0C5) -#define TAIKO_A_CDC_DMIC_CLK0_MODE__POR (0x00) -#define TAIKO_A_CDC_DMIC_DATA1_MODE (0x0C6) -#define TAIKO_A_CDC_DMIC_DATA1_MODE__POR (0x00) -#define TAIKO_A_CDC_DMIC_CLK1_MODE (0x0C7) -#define TAIKO_A_CDC_DMIC_CLK1_MODE__POR (0x00) -#define TAIKO_A_CDC_RX_I2S_SCK_MODE (0x0C8) -#define TAIKO_A_CDC_RX_I2S_SCK_MODE__POR (0x00) -#define TAIKO_A_CDC_RX_I2S_WS_MODE (0x0C9) -#define TAIKO_A_CDC_RX_I2S_WS_MODE__POR (0x00) -#define TAIKO_A_CDC_DMIC_DATA2_MODE (0x0CA) -#define TAIKO_A_CDC_DMIC_DATA2_MODE__POR (0x00) -#define TAIKO_A_CDC_DMIC_CLK2_MODE (0x0CB) -#define TAIKO_A_CDC_DMIC_CLK2_MODE__POR (0x00) -#define TAIKO_A_CDC_INTR1_MODE (0x0CC) -#define TAIKO_A_CDC_INTR1_MODE__POR (0x00) -#define TAIKO_A_CDC_SB_NRZ_SEL_MODE (0x0CD) -#define TAIKO_A_CDC_SB_NRZ_SEL_MODE__POR (0x00) -#define TAIKO_A_CDC_INTR2_MODE (0x0CE) -#define TAIKO_A_CDC_INTR2_MODE__POR (0x00) -#define TAIKO_A_CDC_RF_PA_ON_MODE (0x0CF) -#define TAIKO_A_CDC_RF_PA_ON_MODE__POR (0x00) -#define TAIKO_A_BIAS_REF_CTL (0x100) -#define TAIKO_A_BIAS_REF_CTL__POR (0x1C) -#define TAIKO_A_BIAS_CENTRAL_BG_CTL (0x101) -#define TAIKO_A_BIAS_CENTRAL_BG_CTL__POR (0x50) -#define TAIKO_A_BIAS_PRECHRG_CTL (0x102) -#define TAIKO_A_BIAS_PRECHRG_CTL__POR (0x07) -#define TAIKO_A_BIAS_CURR_CTL_1 (0x103) -#define TAIKO_A_BIAS_CURR_CTL_1__POR (0x52) -#define TAIKO_A_BIAS_CURR_CTL_2 (0x104) -#define TAIKO_A_BIAS_CURR_CTL_2__POR (0x00) -#define TAIKO_A_BIAS_OSC_BG_CTL (0x105) -#define TAIKO_A_BIAS_OSC_BG_CTL__POR (0x16) -#define TAIKO_A_CLK_BUFF_EN1 (0x108) -#define TAIKO_A_CLK_BUFF_EN1__POR (0x04) -#define TAIKO_A_CLK_BUFF_EN2 (0x109) -#define TAIKO_A_CLK_BUFF_EN2__POR (0x02) -#define TAIKO_A_LDO_H_MODE_1 (0x110) -#define TAIKO_A_LDO_H_MODE_1__POR (0x65) -#define TAIKO_A_LDO_H_MODE_2 (0x111) -#define TAIKO_A_LDO_H_MODE_2__POR (0xA8) -#define TAIKO_A_LDO_H_LOOP_CTL (0x112) -#define TAIKO_A_LDO_H_LOOP_CTL__POR (0x6B) -#define TAIKO_A_LDO_H_COMP_1 (0x113) -#define TAIKO_A_LDO_H_COMP_1__POR (0x84) -#define TAIKO_A_LDO_H_COMP_2 (0x114) -#define TAIKO_A_LDO_H_COMP_2__POR (0xE0) -#define TAIKO_A_LDO_H_BIAS_1 (0x115) -#define TAIKO_A_LDO_H_BIAS_1__POR (0x6D) -#define TAIKO_A_LDO_H_BIAS_2 (0x116) -#define TAIKO_A_LDO_H_BIAS_2__POR (0xA5) -#define TAIKO_A_LDO_H_BIAS_3 (0x117) -#define TAIKO_A_LDO_H_BIAS_3__POR (0x60) -#define TAIKO_A_VBAT_CLK (0x118) -#define TAIKO_A_VBAT_CLK__POR (0x03) -#define TAIKO_A_VBAT_LOOP (0x119) -#define TAIKO_A_VBAT_LOOP__POR (0x02) -#define TAIKO_A_VBAT_REF (0x11A) -#define TAIKO_A_VBAT_REF__POR (0x20) -#define TAIKO_A_VBAT_ADC_TEST (0x11B) -#define TAIKO_A_VBAT_ADC_TEST__POR (0x00) -#define TAIKO_A_VBAT_FE (0x11C) -#define TAIKO_A_VBAT_FE__POR (0x48) -#define TAIKO_A_VBAT_BIAS_1 (0x11D) -#define TAIKO_A_VBAT_BIAS_1__POR (0x03) -#define TAIKO_A_VBAT_BIAS_2 (0x11E) -#define TAIKO_A_VBAT_BIAS_2__POR (0x00) -#define TAIKO_A_VBAT_ADC_DATA_MSB (0x11F) -#define TAIKO_A_VBAT_ADC_DATA_MSB__POR (0x00) -#define TAIKO_A_VBAT_ADC_DATA_LSB (0x120) -#define TAIKO_A_VBAT_ADC_DATA_LSB__POR (0x00) -#define TAIKO_A_MICB_CFILT_1_CTL (0x128) -#define TAIKO_A_MICB_CFILT_1_CTL__POR (0x40) -#define TAIKO_A_MICB_CFILT_1_VAL (0x129) -#define TAIKO_A_MICB_CFILT_1_VAL__POR (0x80) -#define TAIKO_A_MICB_CFILT_1_PRECHRG (0x12A) -#define TAIKO_A_MICB_CFILT_1_PRECHRG__POR (0x38) -#define TAIKO_A_MICB_1_CTL (0x12B) -#define TAIKO_A_MICB_1_CTL__POR (0x16) -#define TAIKO_A_MICB_1_INT_RBIAS (0x12C) -#define TAIKO_A_MICB_1_INT_RBIAS__POR (0x24) -#define TAIKO_A_MICB_1_MBHC (0x12D) -#define TAIKO_A_MICB_1_MBHC__POR (0x01) -#define TAIKO_A_MICB_CFILT_2_CTL (0x12E) -#define TAIKO_A_MICB_CFILT_2_CTL__POR (0x40) -#define TAIKO_A_MICB_CFILT_2_VAL (0x12F) -#define TAIKO_A_MICB_CFILT_2_VAL__POR (0x80) -#define TAIKO_A_MICB_CFILT_2_PRECHRG (0x130) -#define TAIKO_A_MICB_CFILT_2_PRECHRG__POR (0x38) -#define TAIKO_A_MICB_2_CTL (0x131) -#define TAIKO_A_MICB_2_CTL__POR (0x16) -#define TAIKO_A_MICB_2_INT_RBIAS (0x132) -#define TAIKO_A_MICB_2_INT_RBIAS__POR (0x24) -#define TAIKO_A_MICB_2_MBHC (0x133) -#define TAIKO_A_MICB_2_MBHC__POR (0x02) -#define TAIKO_A_MICB_CFILT_3_CTL (0x134) -#define TAIKO_A_MICB_CFILT_3_CTL__POR (0x40) -#define TAIKO_A_MICB_CFILT_3_VAL (0x135) -#define TAIKO_A_MICB_CFILT_3_VAL__POR (0x80) -#define TAIKO_A_MICB_CFILT_3_PRECHRG (0x136) -#define TAIKO_A_MICB_CFILT_3_PRECHRG__POR (0x38) -#define TAIKO_A_MICB_3_CTL (0x137) -#define TAIKO_A_MICB_3_CTL__POR (0x16) -#define TAIKO_A_MICB_3_INT_RBIAS (0x138) -#define TAIKO_A_MICB_3_INT_RBIAS__POR (0x24) -#define TAIKO_A_MICB_3_MBHC (0x139) -#define TAIKO_A_MICB_3_MBHC__POR (0x00) -#define TAIKO_A_MICB_4_CTL (0x13D) -#define TAIKO_A_MICB_4_CTL__POR (0x16) -#define TAIKO_A_MICB_4_INT_RBIAS (0x13E) -#define TAIKO_A_MICB_4_INT_RBIAS__POR (0x24) -#define TAIKO_A_MICB_4_MBHC (0x13F) -#define TAIKO_A_MICB_4_MBHC__POR (0x01) -#define TAIKO_A_MBHC_INSERT_DETECT (0x14A) -#define TAIKO_A_MBHC_INSERT_DETECT__POR (0x00) -#define TAIKO_A_MBHC_INSERT_DET_STATUS (0x14B) -#define TAIKO_A_MBHC_INSERT_DET_STATUS__POR (0x00) -#define TAIKO_A_TX_COM_BIAS (0x14C) -#define TAIKO_A_TX_COM_BIAS__POR (0xF0) -#define TAIKO_A_MBHC_SCALING_MUX_1 (0x14E) -#define TAIKO_A_MBHC_SCALING_MUX_1__POR (0x00) -#define TAIKO_A_MBHC_SCALING_MUX_2 (0x14F) -#define TAIKO_A_MBHC_SCALING_MUX_2__POR (0x80) -#define TAIKO_A_MAD_ANA_CTRL (0x150) -#define TAIKO_A_MAD_ANA_CTRL__POR (0xF1) -#define TAIKO_A_TX_SUP_SWITCH_CTRL_1 (0x151) -#define TAIKO_A_TX_SUP_SWITCH_CTRL_1__POR (0x00) -#define TAIKO_A_TX_SUP_SWITCH_CTRL_2 (0x152) -#define TAIKO_A_TX_SUP_SWITCH_CTRL_2__POR (0x80) -#define TAIKO_A_TX_1_2_EN (0x153) -#define TAIKO_A_TX_1_2_EN__POR (0x00) -#define TAIKO_A_TX_1_2_TEST_EN (0x154) -#define TAIKO_A_TX_1_2_TEST_EN__POR (0xCC) -#define TAIKO_A_TX_1_2_ADC_CH1 (0x155) -#define TAIKO_A_TX_1_2_ADC_CH1__POR (0x44) -#define TAIKO_A_TX_1_2_ADC_CH2 (0x156) -#define TAIKO_A_TX_1_2_ADC_CH2__POR (0x44) -#define TAIKO_A_TX_1_2_ATEST_REFCTRL (0x157) -#define TAIKO_A_TX_1_2_ATEST_REFCTRL__POR (0x00) -#define TAIKO_A_TX_1_2_TEST_CTL (0x158) -#define TAIKO_A_TX_1_2_TEST_CTL__POR (0x38) -#define TAIKO_A_TX_1_2_TEST_BLOCK_EN (0x159) -#define TAIKO_A_TX_1_2_TEST_BLOCK_EN__POR (0xFC) -#define TAIKO_A_TX_1_2_TXFE_CLKDIV (0x15A) -#define TAIKO_A_TX_1_2_TXFE_CLKDIV__POR (0x55) -#define TAIKO_A_TX_1_2_SAR_ERR_CH1 (0x15B) -#define TAIKO_A_TX_1_2_SAR_ERR_CH1__POR (0x00) -#define TAIKO_A_TX_1_2_SAR_ERR_CH2 (0x15C) -#define TAIKO_A_TX_1_2_SAR_ERR_CH2__POR (0x00) -#define TAIKO_A_TX_3_4_EN (0x15D) -#define TAIKO_A_TX_3_4_EN__POR (0x00) -#define TAIKO_A_TX_3_4_TEST_EN (0x15E) -#define TAIKO_A_TX_3_4_TEST_EN__POR (0xCC) -#define TAIKO_A_TX_3_4_ADC_CH3 (0x15F) -#define TAIKO_A_TX_3_4_ADC_CH3__POR (0x44) -#define TAIKO_A_TX_3_4_ADC_CH4 (0x160) -#define TAIKO_A_TX_3_4_ADC_CH4__POR (0x44) -#define TAIKO_A_TX_3_4_ATEST_REFCTRL (0x161) -#define TAIKO_A_TX_3_4_ATEST_REFCTRL__POR (0x00) -#define TAIKO_A_TX_3_4_TEST_CTL (0x162) -#define TAIKO_A_TX_3_4_TEST_CTL__POR (0x38) -#define TAIKO_A_TX_3_4_TEST_BLOCK_EN (0x163) -#define TAIKO_A_TX_3_4_TEST_BLOCK_EN__POR (0xFC) -#define TAIKO_A_TX_3_4_TXFE_CKDIV (0x164) -#define TAIKO_A_TX_3_4_TXFE_CKDIV__POR (0x55) -#define TAIKO_A_TX_3_4_SAR_ERR_CH3 (0x165) -#define TAIKO_A_TX_3_4_SAR_ERR_CH3__POR (0x00) -#define TAIKO_A_TX_3_4_SAR_ERR_CH4 (0x166) -#define TAIKO_A_TX_3_4_SAR_ERR_CH4__POR (0x00) -#define TAIKO_A_TX_5_6_EN (0x167) -#define TAIKO_A_TX_5_6_EN__POR (0x11) -#define TAIKO_A_TX_5_6_TEST_EN (0x168) -#define TAIKO_A_TX_5_6_TEST_EN__POR (0xCC) -#define TAIKO_A_TX_5_6_ADC_CH5 (0x169) -#define TAIKO_A_TX_5_6_ADC_CH5__POR (0x44) -#define TAIKO_A_TX_5_6_ADC_CH6 (0x16A) -#define TAIKO_A_TX_5_6_ADC_CH6__POR (0x44) -#define TAIKO_A_TX_5_6_ATEST_REFCTRL (0x16B) -#define TAIKO_A_TX_5_6_ATEST_REFCTRL__POR (0x00) -#define TAIKO_A_TX_5_6_TEST_CTL (0x16C) -#define TAIKO_A_TX_5_6_TEST_CTL__POR (0x38) -#define TAIKO_A_TX_5_6_TEST_BLOCK_EN (0x16D) -#define TAIKO_A_TX_5_6_TEST_BLOCK_EN__POR (0xFC) -#define TAIKO_A_TX_5_6_TXFE_CKDIV (0x16E) -#define TAIKO_A_TX_5_6_TXFE_CKDIV__POR (0x55) -#define TAIKO_A_TX_5_6_SAR_ERR_CH5 (0x16F) -#define TAIKO_A_TX_5_6_SAR_ERR_CH5__POR (0x00) -#define TAIKO_A_TX_5_6_SAR_ERR_CH6 (0x170) -#define TAIKO_A_TX_5_6_SAR_ERR_CH6__POR (0x00) -#define TAIKO_A_TX_7_MBHC_EN (0x171) -#define TAIKO_A_TX_7_MBHC_EN__POR (0x0C) -#define TAIKO_A_TX_7_MBHC_ATEST_REFCTRL (0x172) -#define TAIKO_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00) -#define TAIKO_A_TX_7_MBHC_ADC (0x173) -#define TAIKO_A_TX_7_MBHC_ADC__POR (0x44) -#define TAIKO_A_TX_7_MBHC_TEST_CTL (0x174) -#define TAIKO_A_TX_7_MBHC_TEST_CTL__POR (0x38) -#define TAIKO_A_TX_7_MBHC_SAR_ERR (0x175) -#define TAIKO_A_TX_7_MBHC_SAR_ERR__POR (0x00) -#define TAIKO_A_TX_7_TXFE_CLKDIV (0x176) -#define TAIKO_A_TX_7_TXFE_CLKDIV__POR (0x0B) -#define TAIKO_A_BUCK_MODE_1 (0x181) -#define TAIKO_A_BUCK_MODE_1__POR (0x21) -#define TAIKO_A_BUCK_MODE_2 (0x182) -#define TAIKO_A_BUCK_MODE_2__POR (0xFF) -#define TAIKO_A_BUCK_MODE_3 (0x183) -#define TAIKO_A_BUCK_MODE_3__POR (0xCC) -#define TAIKO_A_BUCK_MODE_4 (0x184) -#define TAIKO_A_BUCK_MODE_4__POR (0x3A) -#define TAIKO_A_BUCK_MODE_5 (0x185) -#define TAIKO_A_BUCK_MODE_5__POR (0x00) -#define TAIKO_A_BUCK_CTRL_VCL_1 (0x186) -#define TAIKO_A_BUCK_CTRL_VCL_1__POR (0x48) -#define TAIKO_A_BUCK_CTRL_VCL_2 (0x187) -#define TAIKO_A_BUCK_CTRL_VCL_2__POR (0xA3) -#define TAIKO_A_BUCK_CTRL_VCL_3 (0x188) -#define TAIKO_A_BUCK_CTRL_VCL_3__POR (0x82) -#define TAIKO_A_BUCK_CTRL_CCL_1 (0x189) -#define TAIKO_A_BUCK_CTRL_CCL_1__POR (0xAB) -#define TAIKO_A_BUCK_CTRL_CCL_2 (0x18A) -#define TAIKO_A_BUCK_CTRL_CCL_2__POR (0xDC) -#define TAIKO_A_BUCK_CTRL_CCL_3 (0x18B) -#define TAIKO_A_BUCK_CTRL_CCL_3__POR (0x6A) -#define TAIKO_A_BUCK_CTRL_CCL_4 (0x18C) -#define TAIKO_A_BUCK_CTRL_CCL_4__POR (0x58) -#define TAIKO_A_BUCK_CTRL_PWM_DRVR_1 (0x18D) -#define TAIKO_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50) -#define TAIKO_A_BUCK_CTRL_PWM_DRVR_2 (0x18E) -#define TAIKO_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64) -#define TAIKO_A_BUCK_CTRL_PWM_DRVR_3 (0x18F) -#define TAIKO_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77) -#define TAIKO_A_BUCK_TMUX_A_D (0x190) -#define TAIKO_A_BUCK_TMUX_A_D__POR (0x00) -#define TAIKO_A_NCP_BUCKREF (0x191) -#define TAIKO_A_NCP_BUCKREF__POR (0x00) -#define TAIKO_A_NCP_EN (0x192) -#define TAIKO_A_NCP_EN__POR (0xFE) -#define TAIKO_A_NCP_CLK (0x193) -#define TAIKO_A_NCP_CLK__POR (0x94) -#define TAIKO_A_NCP_STATIC (0x194) -#define TAIKO_A_NCP_STATIC__POR (0x28) -#define TAIKO_A_NCP_VTH_LOW (0x195) -#define TAIKO_A_NCP_VTH_LOW__POR (0x88) -#define TAIKO_A_NCP_VTH_HIGH (0x196) -#define TAIKO_A_NCP_VTH_HIGH__POR (0xA0) -#define TAIKO_A_NCP_ATEST (0x197) -#define TAIKO_A_NCP_ATEST__POR (0x00) -#define TAIKO_A_NCP_DTEST (0x198) -#define TAIKO_A_NCP_DTEST__POR (0x00) -#define TAIKO_A_NCP_DLY1 (0x199) -#define TAIKO_A_NCP_DLY1__POR (0x06) -#define TAIKO_A_NCP_DLY2 (0x19A) -#define TAIKO_A_NCP_DLY2__POR (0x06) -#define TAIKO_A_RX_AUX_SW_CTL (0x19B) -#define TAIKO_A_RX_AUX_SW_CTL__POR (0x00) -#define TAIKO_A_RX_PA_AUX_IN_CONN (0x19C) -#define TAIKO_A_RX_PA_AUX_IN_CONN__POR (0x00) -#define TAIKO_A_RX_COM_TIMER_DIV (0x19E) -#define TAIKO_A_RX_COM_TIMER_DIV__POR (0xE8) -#define TAIKO_A_RX_COM_OCP_CTL (0x19F) -#define TAIKO_A_RX_COM_OCP_CTL__POR (0x1F) -#define TAIKO_A_RX_COM_OCP_COUNT (0x1A0) -#define TAIKO_A_RX_COM_OCP_COUNT__POR (0x77) -#define TAIKO_A_RX_COM_DAC_CTL (0x1A1) -#define TAIKO_A_RX_COM_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_COM_BIAS (0x1A2) -#define TAIKO_A_RX_COM_BIAS__POR (0x00) -#define TAIKO_A_RX_HPH_AUTO_CHOP (0x1A4) -#define TAIKO_A_RX_HPH_AUTO_CHOP__POR (0x38) -#define TAIKO_A_RX_HPH_CHOP_CTL (0x1A5) -#define TAIKO_A_RX_HPH_CHOP_CTL__POR (0xB4) -#define TAIKO_A_RX_HPH_BIAS_PA (0x1A6) -#define TAIKO_A_RX_HPH_BIAS_PA__POR (0xAA) -#define TAIKO_A_RX_HPH_BIAS_LDO (0x1A7) -#define TAIKO_A_RX_HPH_BIAS_LDO__POR (0x87) -#define TAIKO_A_RX_HPH_BIAS_CNP (0x1A8) -#define TAIKO_A_RX_HPH_BIAS_CNP__POR (0x8A) -#define TAIKO_A_RX_HPH_BIAS_WG_OCP (0x1A9) -#define TAIKO_A_RX_HPH_BIAS_WG_OCP__POR (0x2A) -#define TAIKO_A_RX_HPH_OCP_CTL (0x1AA) -#define TAIKO_A_RX_HPH_OCP_CTL__POR (0x68) -#define TAIKO_A_RX_HPH_CNP_EN (0x1AB) -#define TAIKO_A_RX_HPH_CNP_EN__POR (0x80) -#define TAIKO_A_RX_HPH_CNP_WG_CTL (0x1AC) -#define TAIKO_A_RX_HPH_CNP_WG_CTL__POR (0xDE) -#define TAIKO_A_RX_HPH_CNP_WG_TIME (0x1AD) -#define TAIKO_A_RX_HPH_CNP_WG_TIME__POR (0x2A) -#define TAIKO_A_RX_HPH_L_GAIN (0x1AE) -#define TAIKO_A_RX_HPH_L_GAIN__POR (0x00) -#define TAIKO_A_RX_HPH_L_TEST (0x1AF) -#define TAIKO_A_RX_HPH_L_TEST__POR (0x00) -#define TAIKO_A_RX_HPH_L_PA_CTL (0x1B0) -#define TAIKO_A_RX_HPH_L_PA_CTL__POR (0x40) -#define TAIKO_A_RX_HPH_L_DAC_CTL (0x1B1) -#define TAIKO_A_RX_HPH_L_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_HPH_L_ATEST (0x1B2) -#define TAIKO_A_RX_HPH_L_ATEST__POR (0x00) -#define TAIKO_A_RX_HPH_L_STATUS (0x1B3) -#define TAIKO_A_RX_HPH_L_STATUS__POR (0x00) -#define TAIKO_A_RX_HPH_R_GAIN (0x1B4) -#define TAIKO_A_RX_HPH_R_GAIN__POR (0x00) -#define TAIKO_A_RX_HPH_R_TEST (0x1B5) -#define TAIKO_A_RX_HPH_R_TEST__POR (0x00) -#define TAIKO_A_RX_HPH_R_PA_CTL (0x1B6) -#define TAIKO_A_RX_HPH_R_PA_CTL__POR (0x40) -#define TAIKO_A_RX_HPH_R_DAC_CTL (0x1B7) -#define TAIKO_A_RX_HPH_R_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_HPH_R_ATEST (0x1B8) -#define TAIKO_A_RX_HPH_R_ATEST__POR (0x00) -#define TAIKO_A_RX_HPH_R_STATUS (0x1B9) -#define TAIKO_A_RX_HPH_R_STATUS__POR (0x00) -#define TAIKO_A_RX_EAR_BIAS_PA (0x1BA) -#define TAIKO_A_RX_EAR_BIAS_PA__POR (0xA6) -#define TAIKO_A_RX_EAR_BIAS_CMBUFF (0x1BB) -#define TAIKO_A_RX_EAR_BIAS_CMBUFF__POR (0xA0) -#define TAIKO_A_RX_EAR_EN (0x1BC) -#define TAIKO_A_RX_EAR_EN__POR (0x00) -#define TAIKO_A_RX_EAR_GAIN (0x1BD) -#define TAIKO_A_RX_EAR_GAIN__POR (0x02) -#define TAIKO_A_RX_EAR_CMBUFF (0x1BE) -#define TAIKO_A_RX_EAR_CMBUFF__POR (0x04) -#define TAIKO_A_RX_EAR_ICTL (0x1BF) -#define TAIKO_A_RX_EAR_ICTL__POR (0x40) -#define TAIKO_A_RX_EAR_CCOMP (0x1C0) -#define TAIKO_A_RX_EAR_CCOMP__POR (0x08) -#define TAIKO_A_RX_EAR_VCM (0x1C1) -#define TAIKO_A_RX_EAR_VCM__POR (0x03) -#define TAIKO_A_RX_EAR_CNP (0x1C2) -#define TAIKO_A_RX_EAR_CNP__POR (0xF2) -#define TAIKO_A_RX_EAR_DAC_CTL_ATEST (0x1C3) -#define TAIKO_A_RX_EAR_DAC_CTL_ATEST__POR (0x00) -#define TAIKO_A_RX_EAR_STATUS (0x1C5) -#define TAIKO_A_RX_EAR_STATUS__POR (0x04) -#define TAIKO_A_RX_LINE_BIAS_PA (0x1C6) -#define TAIKO_A_RX_LINE_BIAS_PA__POR (0xA8) -#define TAIKO_A_RX_BUCK_BIAS1 (0x1C7) -#define TAIKO_A_RX_BUCK_BIAS1__POR (0x42) -#define TAIKO_A_RX_BUCK_BIAS2 (0x1C8) -#define TAIKO_A_RX_BUCK_BIAS2__POR (0x84) -#define TAIKO_A_RX_LINE_COM (0x1C9) -#define TAIKO_A_RX_LINE_COM__POR (0x80) -#define TAIKO_A_RX_LINE_CNP_EN (0x1CA) -#define TAIKO_A_RX_LINE_CNP_EN__POR (0x00) -#define TAIKO_A_RX_LINE_CNP_WG_CTL (0x1CB) -#define TAIKO_A_RX_LINE_CNP_WG_CTL__POR (0x00) -#define TAIKO_A_RX_LINE_CNP_WG_TIME (0x1CC) -#define TAIKO_A_RX_LINE_CNP_WG_TIME__POR (0x04) -#define TAIKO_A_RX_LINE_1_GAIN (0x1CD) -#define TAIKO_A_RX_LINE_1_GAIN__POR (0x00) -#define TAIKO_A_RX_LINE_1_TEST (0x1CE) -#define TAIKO_A_RX_LINE_1_TEST__POR (0x00) -#define TAIKO_A_RX_LINE_1_DAC_CTL (0x1CF) -#define TAIKO_A_RX_LINE_1_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_LINE_1_STATUS (0x1D0) -#define TAIKO_A_RX_LINE_1_STATUS__POR (0x00) -#define TAIKO_A_RX_LINE_2_GAIN (0x1D1) -#define TAIKO_A_RX_LINE_2_GAIN__POR (0x00) -#define TAIKO_A_RX_LINE_2_TEST (0x1D2) -#define TAIKO_A_RX_LINE_2_TEST__POR (0x00) -#define TAIKO_A_RX_LINE_2_DAC_CTL (0x1D3) -#define TAIKO_A_RX_LINE_2_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_LINE_2_STATUS (0x1D4) -#define TAIKO_A_RX_LINE_2_STATUS__POR (0x00) -#define TAIKO_A_RX_LINE_3_GAIN (0x1D5) -#define TAIKO_A_RX_LINE_3_GAIN__POR (0x00) -#define TAIKO_A_RX_LINE_3_TEST (0x1D6) -#define TAIKO_A_RX_LINE_3_TEST__POR (0x00) -#define TAIKO_A_RX_LINE_3_DAC_CTL (0x1D7) -#define TAIKO_A_RX_LINE_3_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_LINE_3_STATUS (0x1D8) -#define TAIKO_A_RX_LINE_3_STATUS__POR (0x00) -#define TAIKO_A_RX_LINE_4_GAIN (0x1D9) -#define TAIKO_A_RX_LINE_4_GAIN__POR (0x00) -#define TAIKO_A_RX_LINE_4_TEST (0x1DA) -#define TAIKO_A_RX_LINE_4_TEST__POR (0x00) -#define TAIKO_A_RX_LINE_4_DAC_CTL (0x1DB) -#define TAIKO_A_RX_LINE_4_DAC_CTL__POR (0x00) -#define TAIKO_A_RX_LINE_4_STATUS (0x1DC) -#define TAIKO_A_RX_LINE_4_STATUS__POR (0x00) -#define TAIKO_A_RX_LINE_CNP_DBG (0x1DD) -#define TAIKO_A_RX_LINE_CNP_DBG__POR (0x00) -#define TAIKO_A_SPKR_DRV_EN (0x1DF) -#define TAIKO_A_SPKR_DRV_EN__POR (0x6F) -#define TAIKO_A_SPKR_DRV_GAIN (0x1E0) -#define TAIKO_A_SPKR_DRV_GAIN__POR (0x00) -#define TAIKO_A_SPKR_DRV_DAC_CTL (0x1E1) -#define TAIKO_A_SPKR_DRV_DAC_CTL__POR (0x04) -#define TAIKO_A_SPKR_DRV_OCP_CTL (0x1E2) -#define TAIKO_A_SPKR_DRV_OCP_CTL__POR (0x98) -#define TAIKO_A_SPKR_DRV_CLIP_DET (0x1E3) -#define TAIKO_A_SPKR_DRV_CLIP_DET__POR (0x48) -#define TAIKO_A_SPKR_DRV_IEC (0x1E4) -#define TAIKO_A_SPKR_DRV_IEC__POR (0x20) -#define TAIKO_A_SPKR_DRV_DBG_DAC (0x1E5) -#define TAIKO_A_SPKR_DRV_DBG_DAC__POR (0x05) -#define TAIKO_A_SPKR_DRV_DBG_PA (0x1E6) -#define TAIKO_A_SPKR_DRV_DBG_PA__POR (0x18) -#define TAIKO_A_SPKR_DRV_DBG_PWRSTG (0x1E7) -#define TAIKO_A_SPKR_DRV_DBG_PWRSTG__POR (0x00) -#define TAIKO_A_SPKR_DRV_BIAS_LDO (0x1E8) -#define TAIKO_A_SPKR_DRV_BIAS_LDO__POR (0x45) -#define TAIKO_A_SPKR_DRV_BIAS_INT (0x1E9) -#define TAIKO_A_SPKR_DRV_BIAS_INT__POR (0xA5) -#define TAIKO_A_SPKR_DRV_BIAS_PA (0x1EA) -#define TAIKO_A_SPKR_DRV_BIAS_PA__POR (0x55) -#define TAIKO_A_SPKR_DRV_STATUS_OCP (0x1EB) -#define TAIKO_A_SPKR_DRV_STATUS_OCP__POR (0x00) -#define TAIKO_A_SPKR_DRV_STATUS_PA (0x1EC) -#define TAIKO_A_SPKR_DRV_STATUS_PA__POR (0x00) -#define TAIKO_A_SPKR_PROT_EN (0x1ED) -#define TAIKO_A_SPKR_PROT_EN__POR (0x00) -#define TAIKO_A_SPKR_PROT_ADC_EN (0x1EE) -#define TAIKO_A_SPKR_PROT_ADC_EN__POR (0x44) -#define TAIKO_A_SPKR_PROT_ISENSE_BIAS (0x1EF) -#define TAIKO_A_SPKR_PROT_ISENSE_BIAS__POR (0x44) -#define TAIKO_A_SPKR_PROT_VSENSE_BIAS (0x1F0) -#define TAIKO_A_SPKR_PROT_VSENSE_BIAS__POR (0x44) -#define TAIKO_A_SPKR_PROT_ADC_ATEST_REFCTRL (0x1F1) -#define TAIKO_A_SPKR_PROT_ADC_ATEST_REFCTRL__POR (0x00) -#define TAIKO_A_SPKR_PROT_ADC_TEST_CTL (0x1F2) -#define TAIKO_A_SPKR_PROT_ADC_TEST_CTL__POR (0x38) -#define TAIKO_A_SPKR_PROT_TEST_BLOCK_EN (0x1F3) -#define TAIKO_A_SPKR_PROT_TEST_BLOCK_EN__POR (0xFC) -#define TAIKO_A_SPKR_PROT_ATEST (0x1F4) -#define TAIKO_A_SPKR_PROT_ATEST__POR (0x00) -#define TAIKO_A_SPKR_PROT_V_SAR_ERR (0x1F5) -#define TAIKO_A_SPKR_PROT_V_SAR_ERR__POR (0x00) -#define TAIKO_A_SPKR_PROT_I_SAR_ERR (0x1F6) -#define TAIKO_A_SPKR_PROT_I_SAR_ERR__POR (0x00) -#define TAIKO_A_SPKR_PROT_LDO_CTRL (0x1F7) -#define TAIKO_A_SPKR_PROT_LDO_CTRL__POR (0x00) -#define TAIKO_A_SPKR_PROT_ISENSE_CTRL (0x1F8) -#define TAIKO_A_SPKR_PROT_ISENSE_CTRL__POR (0x00) -#define TAIKO_A_SPKR_PROT_VSENSE_CTRL (0x1F9) -#define TAIKO_A_SPKR_PROT_VSENSE_CTRL__POR (0x00) -#define TAIKO_A_RC_OSC_FREQ (0x1FA) -#define TAIKO_A_RC_OSC_FREQ__POR (0x46) -#define TAIKO_A_RC_OSC_TEST (0x1FB) -#define TAIKO_A_RC_OSC_TEST__POR (0x0A) -#define TAIKO_A_RC_OSC_STATUS (0x1FC) -#define TAIKO_A_RC_OSC_STATUS__POR (0x18) -#define TAIKO_A_RC_OSC_TUNER (0x1FD) -#define TAIKO_A_RC_OSC_TUNER__POR (0x00) -#define TAIKO_A_MBHC_HPH (0x1FE) -#define TAIKO_A_MBHC_HPH__POR (0x44) -#define TAIKO_A_CDC_ANC1_B1_CTL (0x200) -#define TAIKO_A_CDC_ANC1_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_B1_CTL (0x280) -#define TAIKO_A_CDC_ANC2_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_SHIFT (0x201) -#define TAIKO_A_CDC_ANC1_SHIFT__POR (0x00) -#define TAIKO_A_CDC_ANC2_SHIFT (0x281) -#define TAIKO_A_CDC_ANC2_SHIFT__POR (0x00) -#define TAIKO_A_CDC_ANC1_IIR_B1_CTL (0x202) -#define TAIKO_A_CDC_ANC1_IIR_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_IIR_B1_CTL (0x282) -#define TAIKO_A_CDC_ANC2_IIR_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_IIR_B2_CTL (0x203) -#define TAIKO_A_CDC_ANC1_IIR_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_IIR_B2_CTL (0x283) -#define TAIKO_A_CDC_ANC2_IIR_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_IIR_B3_CTL (0x204) -#define TAIKO_A_CDC_ANC1_IIR_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_IIR_B3_CTL (0x284) -#define TAIKO_A_CDC_ANC2_IIR_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_LPF_B1_CTL (0x206) -#define TAIKO_A_CDC_ANC1_LPF_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_LPF_B1_CTL (0x286) -#define TAIKO_A_CDC_ANC2_LPF_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_LPF_B2_CTL (0x207) -#define TAIKO_A_CDC_ANC1_LPF_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_LPF_B2_CTL (0x287) -#define TAIKO_A_CDC_ANC2_LPF_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_SPARE (0x209) -#define TAIKO_A_CDC_ANC1_SPARE__POR (0x00) -#define TAIKO_A_CDC_ANC2_SPARE (0x289) -#define TAIKO_A_CDC_ANC2_SPARE__POR (0x00) -#define TAIKO_A_CDC_ANC1_SMLPF_CTL (0x20A) -#define TAIKO_A_CDC_ANC1_SMLPF_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_SMLPF_CTL (0x28A) -#define TAIKO_A_CDC_ANC2_SMLPF_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_DCFLT_CTL (0x20B) -#define TAIKO_A_CDC_ANC1_DCFLT_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_DCFLT_CTL (0x28B) -#define TAIKO_A_CDC_ANC2_DCFLT_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_GAIN_CTL (0x20C) -#define TAIKO_A_CDC_ANC1_GAIN_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_GAIN_CTL (0x28C) -#define TAIKO_A_CDC_ANC2_GAIN_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC1_B2_CTL (0x20D) -#define TAIKO_A_CDC_ANC1_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_ANC2_B2_CTL (0x28D) -#define TAIKO_A_CDC_ANC2_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_TX1_VOL_CTL_TIMER (0x220) -#define TAIKO_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX2_VOL_CTL_TIMER (0x228) -#define TAIKO_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX3_VOL_CTL_TIMER (0x230) -#define TAIKO_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX4_VOL_CTL_TIMER (0x238) -#define TAIKO_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX5_VOL_CTL_TIMER (0x240) -#define TAIKO_A_CDC_TX5_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX6_VOL_CTL_TIMER (0x248) -#define TAIKO_A_CDC_TX6_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX7_VOL_CTL_TIMER (0x250) -#define TAIKO_A_CDC_TX7_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX8_VOL_CTL_TIMER (0x258) -#define TAIKO_A_CDC_TX8_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX9_VOL_CTL_TIMER (0x260) -#define TAIKO_A_CDC_TX9_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX10_VOL_CTL_TIMER (0x268) -#define TAIKO_A_CDC_TX10_VOL_CTL_TIMER__POR (0x00) -#define TAIKO_A_CDC_TX1_VOL_CTL_GAIN (0x221) -#define TAIKO_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX2_VOL_CTL_GAIN (0x229) -#define TAIKO_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX3_VOL_CTL_GAIN (0x231) -#define TAIKO_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX4_VOL_CTL_GAIN (0x239) -#define TAIKO_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX5_VOL_CTL_GAIN (0x241) -#define TAIKO_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX6_VOL_CTL_GAIN (0x249) -#define TAIKO_A_CDC_TX6_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX7_VOL_CTL_GAIN (0x251) -#define TAIKO_A_CDC_TX7_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX8_VOL_CTL_GAIN (0x259) -#define TAIKO_A_CDC_TX8_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX9_VOL_CTL_GAIN (0x261) -#define TAIKO_A_CDC_TX9_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX10_VOL_CTL_GAIN (0x269) -#define TAIKO_A_CDC_TX10_VOL_CTL_GAIN__POR (0x00) -#define TAIKO_A_CDC_TX1_VOL_CTL_CFG (0x222) -#define TAIKO_A_CDC_TX1_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX2_VOL_CTL_CFG (0x22A) -#define TAIKO_A_CDC_TX2_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX3_VOL_CTL_CFG (0x232) -#define TAIKO_A_CDC_TX3_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX4_VOL_CTL_CFG (0x23A) -#define TAIKO_A_CDC_TX4_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX5_VOL_CTL_CFG (0x242) -#define TAIKO_A_CDC_TX5_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX6_VOL_CTL_CFG (0x24A) -#define TAIKO_A_CDC_TX6_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX7_VOL_CTL_CFG (0x252) -#define TAIKO_A_CDC_TX7_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX8_VOL_CTL_CFG (0x25A) -#define TAIKO_A_CDC_TX8_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX9_VOL_CTL_CFG (0x262) -#define TAIKO_A_CDC_TX9_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX10_VOL_CTL_CFG (0x26A) -#define TAIKO_A_CDC_TX10_VOL_CTL_CFG__POR (0x00) -#define TAIKO_A_CDC_TX1_MUX_CTL (0x223) -#define TAIKO_A_CDC_TX1_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX2_MUX_CTL (0x22B) -#define TAIKO_A_CDC_TX2_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX3_MUX_CTL (0x233) -#define TAIKO_A_CDC_TX3_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX4_MUX_CTL (0x23B) -#define TAIKO_A_CDC_TX4_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX5_MUX_CTL (0x243) -#define TAIKO_A_CDC_TX5_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX6_MUX_CTL (0x24B) -#define TAIKO_A_CDC_TX6_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX7_MUX_CTL (0x253) -#define TAIKO_A_CDC_TX7_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX8_MUX_CTL (0x25B) -#define TAIKO_A_CDC_TX8_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX9_MUX_CTL (0x263) -#define TAIKO_A_CDC_TX9_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX10_MUX_CTL (0x26B) -#define TAIKO_A_CDC_TX10_MUX_CTL__POR (0x08) -#define TAIKO_A_CDC_TX1_CLK_FS_CTL (0x224) -#define TAIKO_A_CDC_TX1_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX2_CLK_FS_CTL (0x22C) -#define TAIKO_A_CDC_TX2_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX3_CLK_FS_CTL (0x234) -#define TAIKO_A_CDC_TX3_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX4_CLK_FS_CTL (0x23C) -#define TAIKO_A_CDC_TX4_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX5_CLK_FS_CTL (0x244) -#define TAIKO_A_CDC_TX5_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX6_CLK_FS_CTL (0x24C) -#define TAIKO_A_CDC_TX6_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX7_CLK_FS_CTL (0x254) -#define TAIKO_A_CDC_TX7_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX8_CLK_FS_CTL (0x25C) -#define TAIKO_A_CDC_TX8_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX9_CLK_FS_CTL (0x264) -#define TAIKO_A_CDC_TX9_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX10_CLK_FS_CTL (0x26C) -#define TAIKO_A_CDC_TX10_CLK_FS_CTL__POR (0x03) -#define TAIKO_A_CDC_TX1_DMIC_CTL (0x225) -#define TAIKO_A_CDC_TX1_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX2_DMIC_CTL (0x22D) -#define TAIKO_A_CDC_TX2_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX3_DMIC_CTL (0x235) -#define TAIKO_A_CDC_TX3_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX4_DMIC_CTL (0x23D) -#define TAIKO_A_CDC_TX4_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX5_DMIC_CTL (0x245) -#define TAIKO_A_CDC_TX5_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX6_DMIC_CTL (0x24D) -#define TAIKO_A_CDC_TX6_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX7_DMIC_CTL (0x255) -#define TAIKO_A_CDC_TX7_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX8_DMIC_CTL (0x25D) -#define TAIKO_A_CDC_TX8_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX9_DMIC_CTL (0x265) -#define TAIKO_A_CDC_TX9_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_TX10_DMIC_CTL (0x26D) -#define TAIKO_A_CDC_TX10_DMIC_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B1_CTL (0x278) -#define TAIKO_A_CDC_DEBUG_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B2_CTL (0x279) -#define TAIKO_A_CDC_DEBUG_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B3_CTL (0x27A) -#define TAIKO_A_CDC_DEBUG_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B4_CTL (0x27B) -#define TAIKO_A_CDC_DEBUG_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B5_CTL (0x27C) -#define TAIKO_A_CDC_DEBUG_B5_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B6_CTL (0x27D) -#define TAIKO_A_CDC_DEBUG_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_DEBUG_B7_CTL (0x27E) -#define TAIKO_A_CDC_DEBUG_B7_CTL__POR (0x00) -#define TAIKO_A_CDC_SRC1_PDA_CFG (0x2A0) -#define TAIKO_A_CDC_SRC1_PDA_CFG__POR (0x00) -#define TAIKO_A_CDC_SRC2_PDA_CFG (0x2A8) -#define TAIKO_A_CDC_SRC2_PDA_CFG__POR (0x00) -#define TAIKO_A_CDC_SRC1_FS_CTL (0x2A1) -#define TAIKO_A_CDC_SRC1_FS_CTL__POR (0x1B) -#define TAIKO_A_CDC_SRC2_FS_CTL (0x2A9) -#define TAIKO_A_CDC_SRC2_FS_CTL__POR (0x1B) -#define TAIKO_A_CDC_RX1_B1_CTL (0x2B0) -#define TAIKO_A_CDC_RX1_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX2_B1_CTL (0x2B8) -#define TAIKO_A_CDC_RX2_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX3_B1_CTL (0x2C0) -#define TAIKO_A_CDC_RX3_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX4_B1_CTL (0x2C8) -#define TAIKO_A_CDC_RX4_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX5_B1_CTL (0x2D0) -#define TAIKO_A_CDC_RX5_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX6_B1_CTL (0x2D8) -#define TAIKO_A_CDC_RX6_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX7_B1_CTL (0x2E0) -#define TAIKO_A_CDC_RX7_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX1_B2_CTL (0x2B1) -#define TAIKO_A_CDC_RX1_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX2_B2_CTL (0x2B9) -#define TAIKO_A_CDC_RX2_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX3_B2_CTL (0x2C1) -#define TAIKO_A_CDC_RX3_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX4_B2_CTL (0x2C9) -#define TAIKO_A_CDC_RX4_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX5_B2_CTL (0x2D1) -#define TAIKO_A_CDC_RX5_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX6_B2_CTL (0x2D9) -#define TAIKO_A_CDC_RX6_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX7_B2_CTL (0x2E1) -#define TAIKO_A_CDC_RX7_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX1_B3_CTL (0x2B2) -#define TAIKO_A_CDC_RX1_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX2_B3_CTL (0x2BA) -#define TAIKO_A_CDC_RX2_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX3_B3_CTL (0x2C2) -#define TAIKO_A_CDC_RX3_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX4_B3_CTL (0x2CA) -#define TAIKO_A_CDC_RX4_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX5_B3_CTL (0x2D2) -#define TAIKO_A_CDC_RX5_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX6_B3_CTL (0x2DA) -#define TAIKO_A_CDC_RX6_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX7_B3_CTL (0x2E2) -#define TAIKO_A_CDC_RX7_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_RX1_B4_CTL (0x2B3) -#define TAIKO_A_CDC_RX1_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX2_B4_CTL (0x2BB) -#define TAIKO_A_CDC_RX2_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX3_B4_CTL (0x2C3) -#define TAIKO_A_CDC_RX3_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX4_B4_CTL (0x2CB) -#define TAIKO_A_CDC_RX4_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX5_B4_CTL (0x2D3) -#define TAIKO_A_CDC_RX5_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX6_B4_CTL (0x2DB) -#define TAIKO_A_CDC_RX6_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX7_B4_CTL (0x2E3) -#define TAIKO_A_CDC_RX7_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_RX1_B5_CTL (0x2B4) -#define TAIKO_A_CDC_RX1_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX2_B5_CTL (0x2BC) -#define TAIKO_A_CDC_RX2_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX3_B5_CTL (0x2C4) -#define TAIKO_A_CDC_RX3_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX4_B5_CTL (0x2CC) -#define TAIKO_A_CDC_RX4_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX5_B5_CTL (0x2D4) -#define TAIKO_A_CDC_RX5_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX6_B5_CTL (0x2DC) -#define TAIKO_A_CDC_RX6_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX7_B5_CTL (0x2E4) -#define TAIKO_A_CDC_RX7_B5_CTL__POR (0x78) -#define TAIKO_A_CDC_RX1_B6_CTL (0x2B5) -#define TAIKO_A_CDC_RX1_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX2_B6_CTL (0x2BD) -#define TAIKO_A_CDC_RX2_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX3_B6_CTL (0x2C5) -#define TAIKO_A_CDC_RX3_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX4_B6_CTL (0x2CD) -#define TAIKO_A_CDC_RX4_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX5_B6_CTL (0x2D5) -#define TAIKO_A_CDC_RX5_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX6_B6_CTL (0x2DD) -#define TAIKO_A_CDC_RX6_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX7_B6_CTL (0x2E5) -#define TAIKO_A_CDC_RX7_B6_CTL__POR (0x80) -#define TAIKO_A_CDC_RX1_VOL_CTL_B1_CTL (0x2B6) -#define TAIKO_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX2_VOL_CTL_B1_CTL (0x2BE) -#define TAIKO_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX3_VOL_CTL_B1_CTL (0x2C6) -#define TAIKO_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX4_VOL_CTL_B1_CTL (0x2CE) -#define TAIKO_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX5_VOL_CTL_B1_CTL (0x2D6) -#define TAIKO_A_CDC_RX5_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX6_VOL_CTL_B1_CTL (0x2DE) -#define TAIKO_A_CDC_RX6_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX7_VOL_CTL_B1_CTL (0x2E6) -#define TAIKO_A_CDC_RX7_VOL_CTL_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL (0x2B7) -#define TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL (0x2BF) -#define TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL (0x2C7) -#define TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL (0x2CF) -#define TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL (0x2D7) -#define TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL (0x2DF) -#define TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL (0x2E7) -#define TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_VBAT_CFG (0x2E8) -#define TAIKO_A_CDC_VBAT_CFG__POR (0x1A) -#define TAIKO_A_CDC_VBAT_ADC_CAL1 (0x2E9) -#define TAIKO_A_CDC_VBAT_ADC_CAL1__POR (0x00) -#define TAIKO_A_CDC_VBAT_ADC_CAL2 (0x2EA) -#define TAIKO_A_CDC_VBAT_ADC_CAL2__POR (0x00) -#define TAIKO_A_CDC_VBAT_ADC_CAL3 (0x2EB) -#define TAIKO_A_CDC_VBAT_ADC_CAL3__POR (0x04) -#define TAIKO_A_CDC_VBAT_PK_EST1 (0x2EC) -#define TAIKO_A_CDC_VBAT_PK_EST1__POR (0xE0) -#define TAIKO_A_CDC_VBAT_PK_EST2 (0x2ED) -#define TAIKO_A_CDC_VBAT_PK_EST2__POR (0x01) -#define TAIKO_A_CDC_VBAT_PK_EST3 (0x2EE) -#define TAIKO_A_CDC_VBAT_PK_EST3__POR (0x40) -#define TAIKO_A_CDC_VBAT_RF_PROC1 (0x2EF) -#define TAIKO_A_CDC_VBAT_RF_PROC1__POR (0x2A) -#define TAIKO_A_CDC_VBAT_RF_PROC2 (0x2F0) -#define TAIKO_A_CDC_VBAT_RF_PROC2__POR (0x86) -#define TAIKO_A_CDC_VBAT_TAC1 (0x2F1) -#define TAIKO_A_CDC_VBAT_TAC1__POR (0x70) -#define TAIKO_A_CDC_VBAT_TAC2 (0x2F2) -#define TAIKO_A_CDC_VBAT_TAC2__POR (0x18) -#define TAIKO_A_CDC_VBAT_TAC3 (0x2F3) -#define TAIKO_A_CDC_VBAT_TAC3__POR (0x18) -#define TAIKO_A_CDC_VBAT_TAC4 (0x2F4) -#define TAIKO_A_CDC_VBAT_TAC4__POR (0x03) -#define TAIKO_A_CDC_VBAT_GAIN_UPD1 (0x2F5) -#define TAIKO_A_CDC_VBAT_GAIN_UPD1__POR (0x01) -#define TAIKO_A_CDC_VBAT_GAIN_UPD2 (0x2F6) -#define TAIKO_A_CDC_VBAT_GAIN_UPD2__POR (0x00) -#define TAIKO_A_CDC_VBAT_GAIN_UPD3 (0x2F7) -#define TAIKO_A_CDC_VBAT_GAIN_UPD3__POR (0x64) -#define TAIKO_A_CDC_VBAT_GAIN_UPD4 (0x2F8) -#define TAIKO_A_CDC_VBAT_GAIN_UPD4__POR (0x01) -#define TAIKO_A_CDC_VBAT_DEBUG1 (0x2F9) -#define TAIKO_A_CDC_VBAT_DEBUG1__POR (0x00) -#define TAIKO_A_CDC_CLK_ANC_RESET_CTL (0x300) -#define TAIKO_A_CDC_CLK_ANC_RESET_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_RX_RESET_CTL (0x301) -#define TAIKO_A_CDC_CLK_RX_RESET_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_TX_RESET_B1_CTL (0x302) -#define TAIKO_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_TX_RESET_B2_CTL (0x303) -#define TAIKO_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_DMIC_B1_CTL (0x304) -#define TAIKO_A_CDC_CLK_DMIC_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_DMIC_B2_CTL (0x305) -#define TAIKO_A_CDC_CLK_DMIC_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_RX_I2S_CTL (0x306) -#define TAIKO_A_CDC_CLK_RX_I2S_CTL__POR (0x03) -#define TAIKO_A_CDC_CLK_TX_I2S_CTL (0x307) -#define TAIKO_A_CDC_CLK_TX_I2S_CTL__POR (0x03) -#define TAIKO_A_CDC_CLK_OTHR_RESET_B1_CTL (0x308) -#define TAIKO_A_CDC_CLK_OTHR_RESET_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL (0x309) -#define TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x30A) -#define TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x30B) -#define TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_OTHR_CTL (0x30C) -#define TAIKO_A_CDC_CLK_OTHR_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL (0x30D) -#define TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_ANC_CLK_EN_CTL (0x30E) -#define TAIKO_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_RX_B1_CTL (0x30F) -#define TAIKO_A_CDC_CLK_RX_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_RX_B2_CTL (0x310) -#define TAIKO_A_CDC_CLK_RX_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_MCLK_CTL (0x311) -#define TAIKO_A_CDC_CLK_MCLK_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_PDM_CTL (0x312) -#define TAIKO_A_CDC_CLK_PDM_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_SD_CTL (0x313) -#define TAIKO_A_CDC_CLK_SD_CTL__POR (0x00) -#define TAIKO_A_CDC_CLK_POWER_CTL (0x314) -#define TAIKO_A_CDC_CLK_POWER_CTL__POR (0x00) -#define TAIKO_A_CDC_CLSH_B1_CTL (0x320) -#define TAIKO_A_CDC_CLSH_B1_CTL__POR (0xE4) -#define TAIKO_A_CDC_CLSH_B2_CTL (0x321) -#define TAIKO_A_CDC_CLSH_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CLSH_B3_CTL (0x322) -#define TAIKO_A_CDC_CLSH_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CLSH_BUCK_NCP_VARS (0x323) -#define TAIKO_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00) -#define TAIKO_A_CDC_CLSH_IDLE_HPH_THSD (0x324) -#define TAIKO_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12) -#define TAIKO_A_CDC_CLSH_IDLE_EAR_THSD (0x325) -#define TAIKO_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C) -#define TAIKO_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326) -#define TAIKO_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18) -#define TAIKO_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327) -#define TAIKO_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23) -#define TAIKO_A_CDC_CLSH_K_ADDR (0x328) -#define TAIKO_A_CDC_CLSH_K_ADDR__POR (0x00) -#define TAIKO_A_CDC_CLSH_K_DATA (0x329) -#define TAIKO_A_CDC_CLSH_K_DATA__POR (0xA4) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D) -#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09) -#define TAIKO_A_CDC_CLSH_V_PA_HD_EAR (0x32E) -#define TAIKO_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00) -#define TAIKO_A_CDC_CLSH_V_PA_HD_HPH (0x32F) -#define TAIKO_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00) -#define TAIKO_A_CDC_CLSH_V_PA_MIN_EAR (0x330) -#define TAIKO_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00) -#define TAIKO_A_CDC_CLSH_V_PA_MIN_HPH (0x331) -#define TAIKO_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B1_CTL (0x340) -#define TAIKO_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B1_CTL (0x350) -#define TAIKO_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B2_CTL (0x341) -#define TAIKO_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B2_CTL (0x351) -#define TAIKO_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B3_CTL (0x342) -#define TAIKO_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B3_CTL (0x352) -#define TAIKO_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B4_CTL (0x343) -#define TAIKO_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B4_CTL (0x353) -#define TAIKO_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B5_CTL (0x344) -#define TAIKO_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B5_CTL (0x354) -#define TAIKO_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B6_CTL (0x345) -#define TAIKO_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B6_CTL (0x355) -#define TAIKO_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B7_CTL (0x346) -#define TAIKO_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B7_CTL (0x356) -#define TAIKO_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_GAIN_B8_CTL (0x347) -#define TAIKO_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_B8_CTL (0x357) -#define TAIKO_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_CTL (0x348) -#define TAIKO_A_CDC_IIR1_CTL__POR (0x40) -#define TAIKO_A_CDC_IIR2_CTL (0x358) -#define TAIKO_A_CDC_IIR2_CTL__POR (0x40) -#define TAIKO_A_CDC_IIR1_GAIN_TIMER_CTL (0x349) -#define TAIKO_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_GAIN_TIMER_CTL (0x359) -#define TAIKO_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_COEF_B1_CTL (0x34A) -#define TAIKO_A_CDC_IIR1_COEF_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_COEF_B1_CTL (0x35A) -#define TAIKO_A_CDC_IIR2_COEF_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR1_COEF_B2_CTL (0x34B) -#define TAIKO_A_CDC_IIR1_COEF_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_IIR2_COEF_B2_CTL (0x35B) -#define TAIKO_A_CDC_IIR2_COEF_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_TOP_GAIN_UPDATE (0x360) -#define TAIKO_A_CDC_TOP_GAIN_UPDATE__POR (0x00) -#define TAIKO_A_CDC_COMP0_B1_CTL (0x368) -#define TAIKO_A_CDC_COMP0_B1_CTL__POR (0x30) -#define TAIKO_A_CDC_COMP1_B1_CTL (0x370) -#define TAIKO_A_CDC_COMP1_B1_CTL__POR (0x30) -#define TAIKO_A_CDC_COMP2_B1_CTL (0x378) -#define TAIKO_A_CDC_COMP2_B1_CTL__POR (0x30) -#define TAIKO_A_CDC_COMP0_B2_CTL (0x369) -#define TAIKO_A_CDC_COMP0_B2_CTL__POR (0xB5) -#define TAIKO_A_CDC_COMP1_B2_CTL (0x371) -#define TAIKO_A_CDC_COMP1_B2_CTL__POR (0xB5) -#define TAIKO_A_CDC_COMP2_B2_CTL (0x379) -#define TAIKO_A_CDC_COMP2_B2_CTL__POR (0xB5) -#define TAIKO_A_CDC_COMP0_B3_CTL (0x36A) -#define TAIKO_A_CDC_COMP0_B3_CTL__POR (0x28) -#define TAIKO_A_CDC_COMP1_B3_CTL (0x372) -#define TAIKO_A_CDC_COMP1_B3_CTL__POR (0x28) -#define TAIKO_A_CDC_COMP2_B3_CTL (0x37A) -#define TAIKO_A_CDC_COMP2_B3_CTL__POR (0x28) -#define TAIKO_A_CDC_COMP0_B4_CTL (0x36B) -#define TAIKO_A_CDC_COMP0_B4_CTL__POR (0x3C) -#define TAIKO_A_CDC_COMP1_B4_CTL (0x373) -#define TAIKO_A_CDC_COMP1_B4_CTL__POR (0x3C) -#define TAIKO_A_CDC_COMP2_B4_CTL (0x37B) -#define TAIKO_A_CDC_COMP2_B4_CTL__POR (0x3C) -#define TAIKO_A_CDC_COMP0_B5_CTL (0x36C) -#define TAIKO_A_CDC_COMP0_B5_CTL__POR (0x1F) -#define TAIKO_A_CDC_COMP1_B5_CTL (0x374) -#define TAIKO_A_CDC_COMP1_B5_CTL__POR (0x1F) -#define TAIKO_A_CDC_COMP2_B5_CTL (0x37C) -#define TAIKO_A_CDC_COMP2_B5_CTL__POR (0x1F) -#define TAIKO_A_CDC_COMP0_B6_CTL (0x36D) -#define TAIKO_A_CDC_COMP0_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_COMP1_B6_CTL (0x375) -#define TAIKO_A_CDC_COMP1_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_COMP2_B6_CTL (0x37D) -#define TAIKO_A_CDC_COMP2_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_COMP0_SHUT_DOWN_STATUS (0x36E) -#define TAIKO_A_CDC_COMP0_SHUT_DOWN_STATUS__POR (0x03) -#define TAIKO_A_CDC_COMP1_SHUT_DOWN_STATUS (0x376) -#define TAIKO_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x03) -#define TAIKO_A_CDC_COMP2_SHUT_DOWN_STATUS (0x37E) -#define TAIKO_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x03) -#define TAIKO_A_CDC_COMP0_FS_CFG (0x36F) -#define TAIKO_A_CDC_COMP0_FS_CFG__POR (0x03) -#define TAIKO_A_CDC_COMP1_FS_CFG (0x377) -#define TAIKO_A_CDC_COMP1_FS_CFG__POR (0x03) -#define TAIKO_A_CDC_COMP2_FS_CFG (0x37F) -#define TAIKO_A_CDC_COMP2_FS_CFG__POR (0x03) -#define TAIKO_A_CDC_CONN_RX1_B1_CTL (0x380) -#define TAIKO_A_CDC_CONN_RX1_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX1_B2_CTL (0x381) -#define TAIKO_A_CDC_CONN_RX1_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX1_B3_CTL (0x382) -#define TAIKO_A_CDC_CONN_RX1_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX2_B1_CTL (0x383) -#define TAIKO_A_CDC_CONN_RX2_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX2_B2_CTL (0x384) -#define TAIKO_A_CDC_CONN_RX2_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX2_B3_CTL (0x385) -#define TAIKO_A_CDC_CONN_RX2_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX3_B1_CTL (0x386) -#define TAIKO_A_CDC_CONN_RX3_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX3_B2_CTL (0x387) -#define TAIKO_A_CDC_CONN_RX3_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX4_B1_CTL (0x388) -#define TAIKO_A_CDC_CONN_RX4_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX4_B2_CTL (0x389) -#define TAIKO_A_CDC_CONN_RX4_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX5_B1_CTL (0x38A) -#define TAIKO_A_CDC_CONN_RX5_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX5_B2_CTL (0x38B) -#define TAIKO_A_CDC_CONN_RX5_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX6_B1_CTL (0x38C) -#define TAIKO_A_CDC_CONN_RX6_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX6_B2_CTL (0x38D) -#define TAIKO_A_CDC_CONN_RX6_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX7_B1_CTL (0x38E) -#define TAIKO_A_CDC_CONN_RX7_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX7_B2_CTL (0x38F) -#define TAIKO_A_CDC_CONN_RX7_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX7_B3_CTL (0x390) -#define TAIKO_A_CDC_CONN_RX7_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_ANC_B1_CTL (0x391) -#define TAIKO_A_CDC_CONN_ANC_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_ANC_B2_CTL (0x392) -#define TAIKO_A_CDC_CONN_ANC_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_B1_CTL (0x393) -#define TAIKO_A_CDC_CONN_TX_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_B2_CTL (0x394) -#define TAIKO_A_CDC_CONN_TX_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_B3_CTL (0x395) -#define TAIKO_A_CDC_CONN_TX_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_B4_CTL (0x396) -#define TAIKO_A_CDC_CONN_TX_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ1_B1_CTL (0x397) -#define TAIKO_A_CDC_CONN_EQ1_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ1_B2_CTL (0x398) -#define TAIKO_A_CDC_CONN_EQ1_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ1_B3_CTL (0x399) -#define TAIKO_A_CDC_CONN_EQ1_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ1_B4_CTL (0x39A) -#define TAIKO_A_CDC_CONN_EQ1_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ2_B1_CTL (0x39B) -#define TAIKO_A_CDC_CONN_EQ2_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ2_B2_CTL (0x39C) -#define TAIKO_A_CDC_CONN_EQ2_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ2_B3_CTL (0x39D) -#define TAIKO_A_CDC_CONN_EQ2_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_EQ2_B4_CTL (0x39E) -#define TAIKO_A_CDC_CONN_EQ2_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_SRC1_B1_CTL (0x39F) -#define TAIKO_A_CDC_CONN_SRC1_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_SRC1_B2_CTL (0x3A0) -#define TAIKO_A_CDC_CONN_SRC1_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_SRC2_B1_CTL (0x3A1) -#define TAIKO_A_CDC_CONN_SRC2_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_SRC2_B2_CTL (0x3A2) -#define TAIKO_A_CDC_CONN_SRC2_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B1_CTL (0x3A3) -#define TAIKO_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B2_CTL (0x3A4) -#define TAIKO_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B3_CTL (0x3A5) -#define TAIKO_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B4_CTL (0x3A6) -#define TAIKO_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B5_CTL (0x3A7) -#define TAIKO_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B6_CTL (0x3A8) -#define TAIKO_A_CDC_CONN_TX_SB_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B7_CTL (0x3A9) -#define TAIKO_A_CDC_CONN_TX_SB_B7_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B8_CTL (0x3AA) -#define TAIKO_A_CDC_CONN_TX_SB_B8_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B9_CTL (0x3AB) -#define TAIKO_A_CDC_CONN_TX_SB_B9_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B10_CTL (0x3AC) -#define TAIKO_A_CDC_CONN_TX_SB_B10_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_TX_SB_B11_CTL (0x3AD) -#define TAIKO_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX_SB_B1_CTL (0x3AE) -#define TAIKO_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_RX_SB_B2_CTL (0x3AF) -#define TAIKO_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_CLSH_CTL (0x3B0) -#define TAIKO_A_CDC_CONN_CLSH_CTL__POR (0x00) -#define TAIKO_A_CDC_CONN_MISC (0x3B1) -#define TAIKO_A_CDC_CONN_MISC__POR (0x01) -#define TAIKO_A_CDC_CONN_MAD (0x3B2) -#define TAIKO_A_CDC_CONN_MAD__POR (0x01) -#define TAIKO_A_CDC_MBHC_EN_CTL (0x3C0) -#define TAIKO_A_CDC_MBHC_EN_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_FIR_B1_CFG (0x3C1) -#define TAIKO_A_CDC_MBHC_FIR_B1_CFG__POR (0x00) -#define TAIKO_A_CDC_MBHC_FIR_B2_CFG (0x3C2) -#define TAIKO_A_CDC_MBHC_FIR_B2_CFG__POR (0x06) -#define TAIKO_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) -#define TAIKO_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03) -#define TAIKO_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) -#define TAIKO_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09) -#define TAIKO_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) -#define TAIKO_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E) -#define TAIKO_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) -#define TAIKO_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45) -#define TAIKO_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) -#define TAIKO_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04) -#define TAIKO_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) -#define TAIKO_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78) -#define TAIKO_A_CDC_MBHC_B1_STATUS (0x3C9) -#define TAIKO_A_CDC_MBHC_B1_STATUS__POR (0x00) -#define TAIKO_A_CDC_MBHC_B2_STATUS (0x3CA) -#define TAIKO_A_CDC_MBHC_B2_STATUS__POR (0x00) -#define TAIKO_A_CDC_MBHC_B3_STATUS (0x3CB) -#define TAIKO_A_CDC_MBHC_B3_STATUS__POR (0x00) -#define TAIKO_A_CDC_MBHC_B4_STATUS (0x3CC) -#define TAIKO_A_CDC_MBHC_B4_STATUS__POR (0x00) -#define TAIKO_A_CDC_MBHC_B5_STATUS (0x3CD) -#define TAIKO_A_CDC_MBHC_B5_STATUS__POR (0x00) -#define TAIKO_A_CDC_MBHC_B1_CTL (0x3CE) -#define TAIKO_A_CDC_MBHC_B1_CTL__POR (0xC0) -#define TAIKO_A_CDC_MBHC_B2_CTL (0x3CF) -#define TAIKO_A_CDC_MBHC_B2_CTL__POR (0x5D) -#define TAIKO_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) -#define TAIKO_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) -#define TAIKO_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) -#define TAIKO_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) -#define TAIKO_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) -#define TAIKO_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) -#define TAIKO_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) -#define TAIKO_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF) -#define TAIKO_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) -#define TAIKO_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07) -#define TAIKO_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) -#define TAIKO_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF) -#define TAIKO_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) -#define TAIKO_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F) -#define TAIKO_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) -#define TAIKO_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) -#define TAIKO_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80) -#define TAIKO_A_CDC_MBHC_CLK_CTL (0x3DC) -#define TAIKO_A_CDC_MBHC_CLK_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_INT_CTL (0x3DD) -#define TAIKO_A_CDC_MBHC_INT_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_DEBUG_CTL (0x3DE) -#define TAIKO_A_CDC_MBHC_DEBUG_CTL__POR (0x00) -#define TAIKO_A_CDC_MBHC_SPARE (0x3DF) -#define TAIKO_A_CDC_MBHC_SPARE__POR (0x00) -#define TAIKO_A_CDC_MAD_MAIN_CTL_1 (0x3E0) -#define TAIKO_A_CDC_MAD_MAIN_CTL_1__POR (0x00) -#define TAIKO_A_CDC_MAD_MAIN_CTL_2 (0x3E1) -#define TAIKO_A_CDC_MAD_MAIN_CTL_2__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_1 (0x3E2) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_1__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_2 (0x3E3) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_2__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_3 (0x3E4) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_3__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_4 (0x3E5) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_4__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_5 (0x3E6) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_5__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_6 (0x3E7) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_6__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_7 (0x3E8) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_7__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_8 (0x3E9) -#define TAIKO_A_CDC_MAD_AUDIO_CTL_8__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_PTR (0x3EA) -#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_PTR__POR (0x00) -#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_VAL (0x3EB) -#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_VAL__POR (0x40) -#define TAIKO_A_CDC_MAD_ULTR_CTL_1 (0x3EC) -#define TAIKO_A_CDC_MAD_ULTR_CTL_1__POR (0x00) -#define TAIKO_A_CDC_MAD_ULTR_CTL_2 (0x3ED) -#define TAIKO_A_CDC_MAD_ULTR_CTL_2__POR (0x00) -#define TAIKO_A_CDC_MAD_ULTR_CTL_3 (0x3EE) -#define TAIKO_A_CDC_MAD_ULTR_CTL_3__POR (0x00) -#define TAIKO_A_CDC_MAD_ULTR_CTL_4 (0x3EF) -#define TAIKO_A_CDC_MAD_ULTR_CTL_4__POR (0x00) -#define TAIKO_A_CDC_MAD_ULTR_CTL_5 (0x3F0) -#define TAIKO_A_CDC_MAD_ULTR_CTL_5__POR (0x00) -#define TAIKO_A_CDC_MAD_ULTR_CTL_6 (0x3F1) -#define TAIKO_A_CDC_MAD_ULTR_CTL_6__POR (0x00) -#define TAIKO_A_CDC_MAD_ULTR_CTL_7 (0x3F2) -#define TAIKO_A_CDC_MAD_ULTR_CTL_7__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_1 (0x3F3) -#define TAIKO_A_CDC_MAD_BEACON_CTL_1__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_2 (0x3F4) -#define TAIKO_A_CDC_MAD_BEACON_CTL_2__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_3 (0x3F5) -#define TAIKO_A_CDC_MAD_BEACON_CTL_3__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_4 (0x3F6) -#define TAIKO_A_CDC_MAD_BEACON_CTL_4__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_5 (0x3F7) -#define TAIKO_A_CDC_MAD_BEACON_CTL_5__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_6 (0x3F8) -#define TAIKO_A_CDC_MAD_BEACON_CTL_6__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_7 (0x3F9) -#define TAIKO_A_CDC_MAD_BEACON_CTL_7__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_CTL_8 (0x3FA) -#define TAIKO_A_CDC_MAD_BEACON_CTL_8__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_PTR (0x3FB) -#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_PTR__POR (0x00) -#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_VAL (0x3FC) -#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_VAL__POR (0x00) - -/* Taiko v2+ registers */ -#define TAIKO_A_CDC_TX_1_GAIN (0x153) -#define TAIKO_A_CDC_TX_1_GAIN__POR (0x02) -#define TAIKO_A_CDC_TX_2_GAIN (0x155) -#define TAIKO_A_CDC_TX_2_GAIN__POR (0x02) -#define TAIKO_A_CDC_TX_1_2_ADC_IB (0x156) -#define TAIKO_A_CDC_TX_1_2_ADC_IB__POR (0x44) -#define TAIKO_A_CDC_TX_3_GAIN (0x15D) -#define TAIKO_A_CDC_TX_3_GAIN__POR (0x02) -#define TAIKO_A_CDC_TX_4_GAIN (0x15F) -#define TAIKO_A_CDC_TX_4_GAIN__POR (0x02) -#define TAIKO_A_CDC_TX_3_4_ADC_IB (0x160) -#define TAIKO_A_CDC_TX_3_4_ADC_IB__POR (0x44) -#define TAIKO_A_CDC_TX_5_GAIN (0x167) -#define TAIKO_A_CDC_TX_5_GAIN__POR (0x02) -#define TAIKO_A_CDC_TX_6_GAIN (0x169) -#define TAIKO_A_CDC_TX_6_GAIN__POR (0x02) -#define TAIKO_A_CDC_TX_5_6_ADC_IB (0x16A) -#define TAIKO_A_CDC_TX_5_6_ADC_IB__POR (0x44) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL0 (0x270) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL0__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL1 (0x271) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL1__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL2 (0x272) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL2__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL3 (0x273) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL3__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL4 (0x274) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL4__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL5 (0x275) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL5__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL6 (0x276) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL6__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL7 (0x277) -#define TAIKO_A_CDC_SPKR_CLIPDET_VAL7__POR (0x00) -#define TAIKO_A_CDC_VBAT_GAIN_UPD_MON (0x2FA) -#define TAIKO_A_CDC_VBAT_GAIN_UPD_MON__POR (0x00) -#define TAIKO_A_CDC_VBAT_GAIN_MON_VAL (0x2FB) -#define TAIKO_A_CDC_VBAT_GAIN_MON_VAL__POR (0x00) -#define TAIKO_A_CDC_PA_RAMP_B1_CTL (0x361) -#define TAIKO_A_CDC_PA_RAMP_B1_CTL__POR (0x00) -#define TAIKO_A_CDC_PA_RAMP_B2_CTL (0x362) -#define TAIKO_A_CDC_PA_RAMP_B2_CTL__POR (0x00) -#define TAIKO_A_CDC_PA_RAMP_B3_CTL (0x363) -#define TAIKO_A_CDC_PA_RAMP_B3_CTL__POR (0x00) -#define TAIKO_A_CDC_PA_RAMP_B4_CTL (0x364) -#define TAIKO_A_CDC_PA_RAMP_B4_CTL__POR (0x00) -#define TAIKO_A_CDC_SPKR_CLIPDET_B1_CTL (0x365) -#define TAIKO_A_CDC_SPKR_CLIPDET_B1_CTL__POR (0x00) - -/* SLIMBUS Slave Registers */ -#define TAIKO_SLIM_PGD_PORT_INT_EN0 (0x30) -#define TAIKO_SLIM_PGD_PORT_INT_STATUS_RX_0 (0x34) -#define TAIKO_SLIM_PGD_PORT_INT_STATUS_RX_1 (0x35) -#define TAIKO_SLIM_PGD_PORT_INT_STATUS_TX_0 (0x36) -#define TAIKO_SLIM_PGD_PORT_INT_STATUS_TX_1 (0x37) -#define TAIKO_SLIM_PGD_PORT_INT_CLR_RX_0 (0x38) -#define TAIKO_SLIM_PGD_PORT_INT_CLR_RX_1 (0x39) -#define TAIKO_SLIM_PGD_PORT_INT_CLR_TX_0 (0x3A) -#define TAIKO_SLIM_PGD_PORT_INT_CLR_TX_1 (0x3B) -#define TAIKO_SLIM_PGD_PORT_INT_RX_SOURCE0 (0x60) -#define TAIKO_SLIM_PGD_PORT_INT_TX_SOURCE0 (0x70) - -/* Macros for Packing Register Writes into a U32 */ -#define TAIKO_PACKED_REG_SIZE sizeof(u32) - -#define TAIKO_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)|\ - ((mask & 0xff) << 8)|((reg & 0xffff) << 16)) - -#define TAIKO_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \ - do { \ - ((reg) = ((packed >> 16) & (0xffff))); \ - ((mask) = ((packed >> 8) & (0xff))); \ - ((val) = ((packed) & (0xff))); \ - } while (0); - -#endif diff --git a/sdm710/original-kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h b/sdm710/original-kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h deleted file mode 100644 index 7902cfba..00000000 --- a/sdm710/original-kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h +++ /dev/null @@ -1,361 +0,0 @@ -#ifndef WCD9XXX_CODEC_DIGITAL_H - -#define WCD9XXX_CODEC_DIGITAL_H - -#define WCD9XXX_A_CHIP_CTL (0x00) -#define WCD9XXX_A_CHIP_CTL__POR (0x00000000) -#define WCD9XXX_A_CHIP_STATUS (0x01) -#define WCD9XXX_A_CHIP_STATUS__POR (0x00000000) -#define WCD9XXX_A_CHIP_ID_BYTE_0 (0x04) -#define WCD9XXX_A_CHIP_ID_BYTE_0__POR (0x00000000) -#define WCD9XXX_A_CHIP_ID_BYTE_1 (0x05) -#define WCD9XXX_A_CHIP_ID_BYTE_1__POR (0x00000000) -#define WCD9XXX_A_CHIP_ID_BYTE_2 (0x06) -#define WCD9XXX_A_CHIP_ID_BYTE_2__POR (0x00000000) -#define WCD9XXX_A_CHIP_ID_BYTE_3 (0x07) -#define WCD9XXX_A_CHIP_ID_BYTE_3__POR (0x00000001) -#define WCD9XXX_A_CHIP_VERSION (0x08) -#define WCD9XXX_A_CHIP_VERSION__POR (0x00000020) -#define WCD9XXX_A_SB_VERSION (0x09) -#define WCD9XXX_A_SB_VERSION__POR (0x00000010) -#define WCD9XXX_A_SLAVE_ID_1 (0x0C) -#define WCD9XXX_A_SLAVE_ID_1__POR (0x00000077) -#define WCD9XXX_A_SLAVE_ID_2 (0x0D) -#define WCD9XXX_A_SLAVE_ID_2__POR (0x00000066) -#define WCD9XXX_A_SLAVE_ID_3 (0x0E) -#define WCD9XXX_A_SLAVE_ID_3__POR (0x00000055) -#define WCD9XXX_A_CDC_CTL (0x80) -#define WCD9XXX_A_CDC_CTL__POR (0x00000000) -#define WCD9XXX_A_LEAKAGE_CTL (0x88) -#define WCD9XXX_A_LEAKAGE_CTL__POR (0x00000004) -#define WCD9XXX_A_INTR_MODE (0x90) -#define WCD9XXX_A_INTR_MASK0 (0x94) -#define WCD9XXX_A_INTR_STATUS0 (0x98) -#define WCD9XXX_A_INTR_CLEAR0 (0x9C) -#define WCD9XXX_A_INTR_LEVEL0 (0xA0) -#define WCD9XXX_A_INTR_LEVEL1 (0xA1) -#define WCD9XXX_A_INTR_LEVEL2 (0xA2) -#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB) -#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80) -#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB) -#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80) -#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL (0x101) -#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL__POR (0x50) -#define WCD9XXX_A_CLK_BUFF_EN1 (0x108) -#define WCD9XXX_A_CLK_BUFF_EN1__POR (0x04) -#define WCD9XXX_A_CLK_BUFF_EN2 (0x109) -#define WCD9XXX_A_CLK_BUFF_EN2__POR (0x02) -#define WCD9XXX_A_RX_COM_BIAS (0x1A2) -#define WCD9XXX_A_RX_COM_BIAS__POR (0x00) -#define WCD9XXX_A_RC_OSC_FREQ (0x1FA) -#define WCD9XXX_A_RC_OSC_FREQ__POR (0x46) -#define WCD9XXX_A_BIAS_OSC_BG_CTL (0x105) -#define WCD9XXX_A_BIAS_OSC_BG_CTL__POR (0x16) -#define WCD9XXX_A_RC_OSC_TEST (0x1FB) -#define WCD9XXX_A_RC_OSC_TEST__POR (0x0A) -#define WCD9XXX_A_CDC_CLK_MCLK_CTL (0x311) -#define WCD9XXX_A_CDC_CLK_MCLK_CTL__POR (0x00) - -#define WCD9XXX_A_CDC_MBHC_EN_CTL (0x3C0) -#define WCD9XXX_A_CDC_MBHC_EN_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG (0x3C1) -#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG (0x3C2) -#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG__POR (0x06) -#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) -#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03) -#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) -#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09) -#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) -#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E) -#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) -#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45) -#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) -#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04) -#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) -#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78) -#define WCD9XXX_A_CDC_MBHC_B1_STATUS (0x3C9) -#define WCD9XXX_A_CDC_MBHC_B1_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B2_STATUS (0x3CA) -#define WCD9XXX_A_CDC_MBHC_B2_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B3_STATUS (0x3CB) -#define WCD9XXX_A_CDC_MBHC_B3_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B4_STATUS (0x3CC) -#define WCD9XXX_A_CDC_MBHC_B4_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B5_STATUS (0x3CD) -#define WCD9XXX_A_CDC_MBHC_B5_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B1_CTL (0x3CE) -#define WCD9XXX_A_CDC_MBHC_B1_CTL__POR (0xC0) -#define WCD9XXX_A_CDC_MBHC_B2_CTL (0x3CF) -#define WCD9XXX_A_CDC_MBHC_B2_CTL__POR (0x5D) -#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) -#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) -#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) -#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) -#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) -#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) -#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) -#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF) -#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) -#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07) -#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) -#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF) -#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) -#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F) -#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) -#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) -#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80) -#define WCD9XXX_A_CDC_MBHC_CLK_CTL (0x3DC) -#define WCD9XXX_A_CDC_MBHC_CLK_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_INT_CTL (0x3DD) -#define WCD9XXX_A_CDC_MBHC_INT_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL (0x3DE) -#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_SPARE (0x3DF) -#define WCD9XXX_A_CDC_MBHC_SPARE__POR (0x00) -#define WCD9XXX_A_MBHC_SCALING_MUX_1 (0x14E) -#define WCD9XXX_A_MBHC_SCALING_MUX_1__POR (0x00) -#define WCD9XXX_A_RX_HPH_OCP_CTL (0x1AA) -#define WCD9XXX_A_RX_HPH_OCP_CTL__POR (0x68) -#define WCD9XXX_A_MICB_1_CTL (0x12B) -#define WCD9XXX_A_MICB_1_CTL__POR (0x16) -#define WCD9XXX_A_MICB_1_INT_RBIAS (0x12C) -#define WCD9XXX_A_MICB_1_INT_RBIAS__POR (0x24) -#define WCD9XXX_A_MICB_1_MBHC (0x12D) -#define WCD9XXX_A_MICB_1_MBHC__POR (0x01) -#define WCD9XXX_A_MICB_CFILT_2_CTL (0x12E) -#define WCD9XXX_A_MICB_CFILT_2_CTL__POR (0x40) -#define WCD9XXX_A_MICB_CFILT_2_VAL (0x12F) -#define WCD9XXX_A_MICB_CFILT_2_VAL__POR (0x80) -#define WCD9XXX_A_MICB_CFILT_2_PRECHRG (0x130) -#define WCD9XXX_A_MICB_CFILT_2_PRECHRG__POR (0x38) -#define WCD9XXX_A_MICB_2_CTL (0x131) -#define WCD9XXX_A_MICB_2_CTL__POR (0x16) -#define WCD9XXX_A_MICB_2_INT_RBIAS (0x132) -#define WCD9XXX_A_MICB_2_INT_RBIAS__POR (0x24) -#define WCD9XXX_A_MICB_2_MBHC (0x133) -#define WCD9XXX_A_MICB_2_MBHC__POR (0x02) -#define WCD9XXX_A_MICB_CFILT_3_CTL (0x134) -#define WCD9XXX_A_MICB_CFILT_3_CTL__POR (0x40) -#define WCD9XXX_A_MICB_CFILT_3_VAL (0x135) -#define WCD9XXX_A_MICB_CFILT_3_VAL__POR (0x80) -#define WCD9XXX_A_MICB_CFILT_3_PRECHRG (0x136) -#define WCD9XXX_A_MICB_CFILT_3_PRECHRG__POR (0x38) -#define WCD9XXX_A_MICB_3_CTL (0x137) -#define WCD9XXX_A_MICB_3_CTL__POR (0x16) -#define WCD9XXX_A_MICB_3_INT_RBIAS (0x138) -#define WCD9XXX_A_MICB_3_INT_RBIAS__POR (0x24) -#define WCD9XXX_A_MICB_3_MBHC (0x139) -#define WCD9XXX_A_MICB_3_MBHC__POR (0x00) -#define WCD9XXX_A_MICB_4_CTL (0x13D) -#define WCD9XXX_A_MICB_4_CTL__POR (0x16) -#define WCD9XXX_A_MICB_4_INT_RBIAS (0x13E) -#define WCD9XXX_A_MICB_4_INT_RBIAS__POR (0x24) -#define WCD9XXX_A_MICB_4_MBHC (0x13F) -#define WCD9XXX_A_MICB_4_MBHC__POR (0x01) -#define WCD9XXX_A_MICB_CFILT_1_VAL (0x129) -#define WCD9XXX_A_MICB_CFILT_1_VAL__POR (0x80) -#define WCD9XXX_A_RX_HPH_L_STATUS (0x1B3) -#define WCD9XXX_A_RX_HPH_L_STATUS__POR (0x00) -#define WCD9XXX_A_MBHC_HPH (0x1FE) -#define WCD9XXX_A_MBHC_HPH__POR (0x44) -#define WCD9XXX_A_RX_HPH_CNP_WG_TIME (0x1AD) -#define WCD9XXX_A_RX_HPH_CNP_WG_TIME__POR (0x2A) -#define WCD9XXX_A_RX_HPH_R_DAC_CTL (0x1B7) -#define WCD9XXX_A_RX_HPH_R_DAC_CTL__POR (0x00) -#define WCD9XXX_A_RX_HPH_L_DAC_CTL (0x1B1) -#define WCD9XXX_A_RX_HPH_L_DAC_CTL__POR (0x00) -#define WCD9XXX_A_TX_7_MBHC_EN (0x171) -#define WCD9XXX_A_TX_7_MBHC_EN__POR (0x0C) -#define WCD9XXX_A_PIN_CTL_OE0 (0x010) -#define WCD9XXX_A_PIN_CTL_OE0__POR (0x00) -#define WCD9XXX_A_PIN_CTL_OE1 (0x011) -#define WCD9XXX_A_PIN_CTL_OE1__POR (0x00) -#define WCD9XXX_A_MICB_CFILT_1_CTL (0x128) -#define WCD9XXX_A_LDO_H_MODE_1 (0x110) -#define WCD9XXX_A_LDO_H_MODE_1__POR (0x65) -#define WCD9XXX_A_MICB_CFILT_1_CTL__POR (0x40) -#define WCD9XXX_A_TX_7_MBHC_TEST_CTL (0x174) -#define WCD9XXX_A_TX_7_MBHC_TEST_CTL__POR (0x38) -#define WCD9XXX_A_MBHC_SCALING_MUX_2 (0x14F) -#define WCD9XXX_A_MBHC_SCALING_MUX_2__POR (0x80) -#define WCD9XXX_A_TX_COM_BIAS (0x14C) -#define WCD9XXX_A_TX_COM_BIAS__POR (0xF0) - -#define WCD9XXX_A_MBHC_INSERT_DETECT (0x14A) /* TAIKO and later */ -#define WCD9XXX_A_MBHC_INSERT_DETECT__POR (0x00) -#define WCD9XXX_A_MBHC_INSERT_DET_STATUS (0x14B) /* TAIKO and later */ -#define WCD9XXX_A_MBHC_INSERT_DET_STATUS__POR (0x00) -#define WCD9XXX_A_MAD_ANA_CTRL (0x150) -#define WCD9XXX_A_MAD_ANA_CTRL__POR (0xF1) - - -#define WCD9XXX_A_CDC_CLK_OTHR_CTL (0x30C) -#define WCD9XXX_A_CDC_CLK_OTHR_CTL__POR (0x00) - -/* Class H related common registers */ -#define WCD9XXX_A_BUCK_MODE_1 (0x181) -#define WCD9XXX_A_BUCK_MODE_1__POR (0x21) -#define WCD9XXX_A_BUCK_MODE_2 (0x182) -#define WCD9XXX_A_BUCK_MODE_2__POR (0xFF) -#define WCD9XXX_A_BUCK_MODE_3 (0x183) -#define WCD9XXX_A_BUCK_MODE_3__POR (0xCC) -#define WCD9XXX_A_BUCK_MODE_4 (0x184) -#define WCD9XXX_A_BUCK_MODE_4__POR (0x3A) -#define WCD9XXX_A_BUCK_MODE_5 (0x185) -#define WCD9XXX_A_BUCK_MODE_5__POR (0x00) -#define WCD9XXX_A_BUCK_CTRL_VCL_1 (0x186) -#define WCD9XXX_A_BUCK_CTRL_VCL_1__POR (0x48) -#define WCD9XXX_A_BUCK_CTRL_VCL_2 (0x187) -#define WCD9XXX_A_BUCK_CTRL_VCL_2__POR (0xA3) -#define WCD9XXX_A_BUCK_CTRL_VCL_3 (0x188) -#define WCD9XXX_A_BUCK_CTRL_VCL_3__POR (0x82) -#define WCD9XXX_A_BUCK_CTRL_CCL_1 (0x189) -#define WCD9XXX_A_BUCK_CTRL_CCL_1__POR (0xAB) -#define WCD9XXX_A_BUCK_CTRL_CCL_2 (0x18A) -#define WCD9XXX_A_BUCK_CTRL_CCL_2__POR (0xDC) -#define WCD9XXX_A_BUCK_CTRL_CCL_3 (0x18B) -#define WCD9XXX_A_BUCK_CTRL_CCL_3__POR (0x6A) -#define WCD9XXX_A_BUCK_CTRL_CCL_4 (0x18C) -#define WCD9XXX_A_BUCK_CTRL_CCL_4__POR (0x58) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1 (0x18D) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2 (0x18E) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3 (0x18F) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77) -#define WCD9XXX_A_BUCK_TMUX_A_D (0x190) -#define WCD9XXX_A_BUCK_TMUX_A_D__POR (0x00) -#define WCD9XXX_A_NCP_EN (0x192) -#define WCD9XXX_A_NCP_EN__POR (0xFE) -#define WCD9XXX_A_NCP_STATIC (0x194) -#define WCD9XXX_A_NCP_STATIC__POR (0x28) -#define WCD9XXX_A_NCP_BUCKREF (0x191) -#define WCD9XXX_A_NCP_BUCKREF__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_B1_CTL (0x320) -#define WCD9XXX_A_CDC_CLSH_B1_CTL__POR (0xE4) -#define WCD9XXX_A_CDC_CLSH_B2_CTL (0x321) -#define WCD9XXX_A_CDC_CLSH_B2_CTL__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_B3_CTL (0x322) -#define WCD9XXX_A_CDC_CLSH_B3_CTL__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS (0x323) -#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD (0x324) -#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12) -#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD (0x325) -#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C) -#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326) -#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18) -#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327) -#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23) -#define WCD9XXX_A_CDC_CLSH_K_ADDR (0x328) -#define WCD9XXX_A_CDC_CLSH_K_ADDR__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_K_DATA (0x329) -#define WCD9XXX_A_CDC_CLSH_K_DATA__POR (0xA4) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09) -#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR (0x32E) -#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH (0x32F) -#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR (0x330) -#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH (0x331) -#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00) - -#define WCD9XXX_A_CDC_RX1_B6_CTL (0x2B5) -#define WCD9XXX_A_CDC_RX1_B6_CTL__POR (0x80) -#define WCD9XXX_A_CDC_RX2_B6_CTL (0x2BD) -#define WCD9XXX_A_CDC_RX2_B6_CTL__POR (0x80) -#define WCD9XXX_A_RX_HPH_L_GAIN (0x1AE) -#define WCD9XXX_A_RX_HPH_L_GAIN__POR (0x00) -#define WCD9XXX_A_RX_HPH_R_GAIN (0x1B4) -#define WCD9XXX_A_RX_HPH_R_GAIN__POR (0x00) -#define WCD9XXX_A_RX_HPH_CHOP_CTL (0x1A5) -#define WCD9XXX_A_RX_HPH_CHOP_CTL__POR (0xB4) -#define WCD9XXX_A_RX_HPH_BIAS_PA (0x1A6) -#define WCD9XXX_A_RX_HPH_BIAS_PA__POR (0x7A) -#define WCD9XXX_A_RX_HPH_L_TEST (0x1AF) -#define WCD9XXX_A_RX_HPH_L_TEST__POR (0x00) -#define WCD9XXX_A_RX_HPH_R_TEST (0x1B5) -#define WCD9XXX_A_RX_HPH_R_TEST__POR (0x00) -#define WCD9XXX_A_CDC_CLK_RX_B1_CTL (0x30F) -#define WCD9XXX_A_CDC_CLK_RX_B1_CTL__POR (0x00) -#define WCD9XXX_A_NCP_CLK (0x193) -#define WCD9XXX_A_NCP_CLK__POR (0x94) -#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP (0x1A9) -#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP__POR (0x2A) -#define WCD9XXX_A_RX_HPH_CNP_WG_CTL (0x1AC) -#define WCD9XXX_A_RX_HPH_CNP_WG_CTL__POR (0xDE) -#define WCD9XXX_A_RX_HPH_L_PA_CTL (0x1B0) -#define WCD9XXX_A_RX_HPH_L_PA_CTL__POR (0x42) -#define WCD9XXX_A_RX_HPH_R_PA_CTL (0x1B6) -#define WCD9XXX_A_RX_HPH_R_PA_CTL__POR (0x42) -#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL (0x383) -#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL__POR (0x00) -#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL (0x361) -#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL__POR (0x00) -#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL (0x362) -#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL__POR (0x00) -#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL (0x363) -#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL__POR (0x00) -#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL (0x364) -#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL__POR (0x00) - -#define WCD9330_A_LEAKAGE_CTL (0x03C) -#define WCD9330_A_LEAKAGE_CTL__POR (0x04) -#define WCD9330_A_CDC_CTL (0x034) -#define WCD9330_A_CDC_CTL__POR (0x00) - -/* Class-H registers for codecs from and above WCD9335 */ -#define WCD9XXX_A_CDC_RX0_RX_PATH_CFG0 (0xB42) -#define WCD9XXX_A_CDC_RX1_RX_PATH_CFG0 (0xB56) -#define WCD9XXX_A_CDC_RX2_RX_PATH_CFG0 (0xB6A) -#define WCD9XXX_A_CDC_CLSH_K1_MSB (0xC08) -#define WCD9XXX_A_CDC_CLSH_K1_LSB (0xC09) -#define WCD9XXX_A_ANA_RX_SUPPLIES (0x608) -#define WCD9XXX_A_ANA_HPH (0x609) -#define WCD9XXX_A_CDC_CLSH_CRC (0xC01) -#define WCD9XXX_FLYBACK_EN (0x6A4) -#define WCD9XXX_FLYBACK_VNEG_CTRL_1 (0x6A5) -#define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2 (0x6AF) -#define WCD9XXX_RX_BIAS_FLYB_BUFF (0x6C7) -#define WCD9XXX_HPH_L_EN (0x6D3) -#define WCD9XXX_HPH_R_EN (0x6D6) -#define WCD9XXX_HPH_REFBUFF_UHQA_CTL (0x6DD) -#define WCD9XXX_CLASSH_CTRL_VCL_2 (0x69B) -#define WCD9XXX_CDC_CLSH_HPH_V_PA (0xC04) -#define WCD9XXX_CDC_RX0_RX_PATH_SEC0 (0xB49) -#define WCD9XXX_CDC_RX1_RX_PATH_CTL (0xB55) -#define WCD9XXX_CDC_RX2_RX_PATH_CTL (0xB69) -#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_CONTROL (0xD41) -#define WCD9XXX_CLASSH_CTRL_CCL_1 (0x69C) - -/* RX Gain control registers of codecs from and above WCD9335 */ -#define WCD9XXX_CDC_RX1_RX_VOL_CTL (0xB59) -#define WCD9XXX_CDC_RX1_RX_VOL_MIX_CTL (0xB5C) -#define WCD9XXX_CDC_RX1_RX_PATH_SEC1 (0xB5E) -#define WCD9XXX_CDC_RX2_RX_VOL_CTL (0xB6D) -#define WCD9XXX_CDC_RX2_RX_VOL_MIX_CTL (0xB70) -#define WCD9XXX_CDC_RX2_RX_PATH_SEC1 (0xB72) - -/* Class-H registers for codecs from and above WCD934X */ -#define WCD9XXX_HPH_CNP_WG_CTL (0x06cc) -#define WCD9XXX_FLYBACK_VNEG_CTRL_4 (0x06a8) -#define WCD9XXX_HPH_NEW_INT_PA_MISC2 (0x0738) -#define WCD9XXX_RX_BIAS_HPH_LOWPOWER (0x06bf) -#define WCD9XXX_HPH_PA_CTL1 (0x06d1) -#endif diff --git a/sdm710/original-kernel-headers/linux/msm-core-interface.h b/sdm710/original-kernel-headers/linux/msm-core-interface.h deleted file mode 100644 index 6c0dae46..00000000 --- a/sdm710/original-kernel-headers/linux/msm-core-interface.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __MSM_CORE_LIB_H__ -#define __MSM_CORE_LIB_H__ - -#include <linux/ioctl.h> - -#define TEMP_DATA_POINTS 13 -#define MAX_NUM_FREQ 200 - -enum msm_core_ioctl_params { - MSM_CORE_LEAKAGE, - MSM_CORE_VOLTAGE, -}; - -#define MSM_CORE_MAGIC 0x9D - -struct sched_params { - uint32_t cpumask; - uint32_t cluster; - uint32_t power[TEMP_DATA_POINTS][MAX_NUM_FREQ]; - uint32_t voltage[MAX_NUM_FREQ]; - uint32_t freq[MAX_NUM_FREQ]; -}; - - -#define EA_LEAKAGE _IOWR(MSM_CORE_MAGIC, MSM_CORE_LEAKAGE,\ - struct sched_params) -#define EA_VOLT _IOWR(MSM_CORE_MAGIC, MSM_CORE_VOLTAGE,\ - struct sched_params) -#endif diff --git a/sdm710/original-kernel-headers/linux/msm_adsp.h b/sdm710/original-kernel-headers/linux/msm_adsp.h deleted file mode 100644 index 12731698..00000000 --- a/sdm710/original-kernel-headers/linux/msm_adsp.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (C) 2007 Google, Inc. - * Author: Iliyan Malchev <ibm@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef _LINUX_MSM_ADSP_H -#define _LINUX_MSM_ADSP_H - -#include <linux/types.h> -#include <linux/ioctl.h> - -#define ADSP_IOCTL_MAGIC 'q' - -/* ADSP_IOCTL_WRITE_COMMAND */ -struct adsp_command_t { - uint16_t queue; - uint32_t len; /* bytes */ - uint8_t *data; -}; - -/* ADSP_IOCTL_GET_EVENT */ -struct adsp_event_t { - uint16_t type; /* 1 == event (RPC), 0 == message (adsp) */ - uint32_t timeout_ms; /* -1 for infinite, 0 for immediate return */ - uint16_t msg_id; - uint16_t flags; /* 1 == 16--bit event, 0 == 32-bit event */ - uint32_t len; /* size in, number of bytes out */ - uint8_t *data; -}; - -#define ADSP_IOCTL_ENABLE \ - _IOR(ADSP_IOCTL_MAGIC, 1, unsigned) - -#define ADSP_IOCTL_DISABLE \ - _IOR(ADSP_IOCTL_MAGIC, 2, unsigned) - -#define ADSP_IOCTL_DISABLE_ACK \ - _IOR(ADSP_IOCTL_MAGIC, 3, unsigned) - -#define ADSP_IOCTL_WRITE_COMMAND \ - _IOR(ADSP_IOCTL_MAGIC, 4, struct adsp_command_t *) - -#define ADSP_IOCTL_GET_EVENT \ - _IOWR(ADSP_IOCTL_MAGIC, 5, struct adsp_event_data_t *) - -#define ADSP_IOCTL_SET_CLKRATE \ - _IOR(ADSP_IOCTL_MAGIC, 6, unsigned) - -#define ADSP_IOCTL_DISABLE_EVENT_RSP \ - _IOR(ADSP_IOCTL_MAGIC, 10, unsigned) - -#define ADSP_IOCTL_REGISTER_PMEM \ - _IOW(ADSP_IOCTL_MAGIC, 13, unsigned) - -#define ADSP_IOCTL_UNREGISTER_PMEM \ - _IOW(ADSP_IOCTL_MAGIC, 14, unsigned) - -/* Cause any further GET_EVENT ioctls to fail (-ENODEV) - * until the device is closed and reopened. Useful for - * terminating event dispatch threads - */ -#define ADSP_IOCTL_ABORT_EVENT_READ \ - _IOW(ADSP_IOCTL_MAGIC, 15, unsigned) - -#define ADSP_IOCTL_LINK_TASK \ - _IOW(ADSP_IOCTL_MAGIC, 16, unsigned) - -#endif diff --git a/sdm710/original-kernel-headers/linux/msm_audio.h b/sdm710/original-kernel-headers/linux/msm_audio.h deleted file mode 100644 index 95d39602..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio.h +++ /dev/null @@ -1,480 +0,0 @@ -/* include/linux/msm_audio.h - * - * Copyright (C) 2008 Google, Inc. - * Copyright (c) 2012, 2014, 2017 The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _LINUX_MSM_AUDIO_H -#define _LINUX_MSM_AUDIO_H - -#include <linux/types.h> -#include <linux/ioctl.h> - -/* PCM Audio */ - -#define AUDIO_IOCTL_MAGIC 'a' - -#define AUDIO_START _IOW(AUDIO_IOCTL_MAGIC, 0, unsigned int) -#define AUDIO_STOP _IOW(AUDIO_IOCTL_MAGIC, 1, unsigned int) -#define AUDIO_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 2, unsigned int) -#define AUDIO_GET_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 3, \ - struct msm_audio_config) -#define AUDIO_SET_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 4, \ - struct msm_audio_config) -#define AUDIO_GET_STATS _IOR(AUDIO_IOCTL_MAGIC, 5, \ - struct msm_audio_stats) -#define AUDIO_ENABLE_AUDPP _IOW(AUDIO_IOCTL_MAGIC, 6, unsigned int) -#define AUDIO_SET_ADRC _IOW(AUDIO_IOCTL_MAGIC, 7, unsigned int) -#define AUDIO_SET_EQ _IOW(AUDIO_IOCTL_MAGIC, 8, unsigned int) -#define AUDIO_SET_RX_IIR _IOW(AUDIO_IOCTL_MAGIC, 9, unsigned int) -#define AUDIO_SET_VOLUME _IOW(AUDIO_IOCTL_MAGIC, 10, unsigned int) -#define AUDIO_PAUSE _IOW(AUDIO_IOCTL_MAGIC, 11, unsigned int) -#define AUDIO_PLAY_DTMF _IOW(AUDIO_IOCTL_MAGIC, 12, unsigned int) -#define AUDIO_GET_EVENT _IOR(AUDIO_IOCTL_MAGIC, 13, \ - struct msm_audio_event) -#define AUDIO_ABORT_GET_EVENT _IOW(AUDIO_IOCTL_MAGIC, 14, unsigned int) -#define AUDIO_REGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 15, unsigned int) -#define AUDIO_DEREGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 16, unsigned int) -#define AUDIO_ASYNC_WRITE _IOW(AUDIO_IOCTL_MAGIC, 17, \ - struct msm_audio_aio_buf) -#define AUDIO_ASYNC_READ _IOW(AUDIO_IOCTL_MAGIC, 18, \ - struct msm_audio_aio_buf) -#define AUDIO_SET_INCALL _IOW(AUDIO_IOCTL_MAGIC, 19, struct msm_voicerec_mode) -#define AUDIO_GET_NUM_SND_DEVICE _IOR(AUDIO_IOCTL_MAGIC, 20, unsigned int) -#define AUDIO_GET_SND_DEVICES _IOWR(AUDIO_IOCTL_MAGIC, 21, \ - struct msm_snd_device_list) -#define AUDIO_ENABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 22, unsigned int) -#define AUDIO_DISABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 23, unsigned int) -#define AUDIO_ROUTE_STREAM _IOW(AUDIO_IOCTL_MAGIC, 24, \ - struct msm_audio_route_config) -#define AUDIO_GET_PCM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 30, unsigned int) -#define AUDIO_SET_PCM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 31, unsigned int) -#define AUDIO_SWITCH_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 32, unsigned int) -#define AUDIO_SET_MUTE _IOW(AUDIO_IOCTL_MAGIC, 33, unsigned int) -#define AUDIO_UPDATE_ACDB _IOW(AUDIO_IOCTL_MAGIC, 34, unsigned int) -#define AUDIO_START_VOICE _IOW(AUDIO_IOCTL_MAGIC, 35, unsigned int) -#define AUDIO_STOP_VOICE _IOW(AUDIO_IOCTL_MAGIC, 36, unsigned int) -#define AUDIO_REINIT_ACDB _IOW(AUDIO_IOCTL_MAGIC, 39, unsigned int) -#define AUDIO_OUTPORT_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 40, unsigned short) -#define AUDIO_SET_ERR_THRESHOLD_VALUE _IOW(AUDIO_IOCTL_MAGIC, 41, \ - unsigned short) -#define AUDIO_GET_BITSTREAM_ERROR_INFO _IOR(AUDIO_IOCTL_MAGIC, 42, \ - struct msm_audio_bitstream_error_info) - -#define AUDIO_SET_SRS_TRUMEDIA_PARAM _IOW(AUDIO_IOCTL_MAGIC, 43, unsigned int) - -/* Qualcomm technologies inc extensions */ -#define AUDIO_SET_STREAM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 80, \ - struct msm_audio_stream_config) -#define AUDIO_GET_STREAM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 81, \ - struct msm_audio_stream_config) -#define AUDIO_GET_SESSION_ID _IOR(AUDIO_IOCTL_MAGIC, 82, unsigned short) -#define AUDIO_GET_STREAM_INFO _IOR(AUDIO_IOCTL_MAGIC, 83, \ - struct msm_audio_bitstream_info) -#define AUDIO_SET_PAN _IOW(AUDIO_IOCTL_MAGIC, 84, unsigned int) -#define AUDIO_SET_QCONCERT_PLUS _IOW(AUDIO_IOCTL_MAGIC, 85, unsigned int) -#define AUDIO_SET_MBADRC _IOW(AUDIO_IOCTL_MAGIC, 86, unsigned int) -#define AUDIO_SET_VOLUME_PATH _IOW(AUDIO_IOCTL_MAGIC, 87, \ - struct msm_vol_info) -#define AUDIO_SET_MAX_VOL_ALL _IOW(AUDIO_IOCTL_MAGIC, 88, unsigned int) -#define AUDIO_ENABLE_AUDPRE _IOW(AUDIO_IOCTL_MAGIC, 89, unsigned int) -#define AUDIO_SET_AGC _IOW(AUDIO_IOCTL_MAGIC, 90, unsigned int) -#define AUDIO_SET_NS _IOW(AUDIO_IOCTL_MAGIC, 91, unsigned int) -#define AUDIO_SET_TX_IIR _IOW(AUDIO_IOCTL_MAGIC, 92, unsigned int) -#define AUDIO_GET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 93, \ - struct msm_audio_buf_cfg) -#define AUDIO_SET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 94, \ - struct msm_audio_buf_cfg) -#define AUDIO_SET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 95, \ - struct msm_acdb_cmd_device) -#define AUDIO_GET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 96, \ - struct msm_acdb_cmd_device) - -#define AUDIO_REGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 97, \ - struct msm_audio_ion_info) -#define AUDIO_DEREGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 98, \ - struct msm_audio_ion_info) -#define AUDIO_SET_EFFECTS_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 99, \ - struct msm_hwacc_effects_config) -#define AUDIO_EFFECTS_SET_BUF_LEN _IOW(AUDIO_IOCTL_MAGIC, 100, \ - struct msm_hwacc_buf_cfg) -#define AUDIO_EFFECTS_GET_BUF_AVAIL _IOW(AUDIO_IOCTL_MAGIC, 101, \ - struct msm_hwacc_buf_avail) -#define AUDIO_EFFECTS_WRITE _IOW(AUDIO_IOCTL_MAGIC, 102, void *) -#define AUDIO_EFFECTS_READ _IOWR(AUDIO_IOCTL_MAGIC, 103, void *) -#define AUDIO_EFFECTS_SET_PP_PARAMS _IOW(AUDIO_IOCTL_MAGIC, 104, void *) - -#define AUDIO_PM_AWAKE _IOW(AUDIO_IOCTL_MAGIC, 105, unsigned int) -#define AUDIO_PM_RELAX _IOW(AUDIO_IOCTL_MAGIC, 106, unsigned int) - -#define AUDIO_MAX_COMMON_IOCTL_NUM 107 - - -#define HANDSET_MIC 0x01 -#define HANDSET_SPKR 0x02 -#define HEADSET_MIC 0x03 -#define HEADSET_SPKR_MONO 0x04 -#define HEADSET_SPKR_STEREO 0x05 -#define SPKR_PHONE_MIC 0x06 -#define SPKR_PHONE_MONO 0x07 -#define SPKR_PHONE_STEREO 0x08 -#define BT_SCO_MIC 0x09 -#define BT_SCO_SPKR 0x0A -#define BT_A2DP_SPKR 0x0B -#define TTY_HEADSET_MIC 0x0C -#define TTY_HEADSET_SPKR 0x0D - -/* Default devices are not supported in a */ -/* device switching context. Only supported */ -/* for stream devices. */ -/* DO NOT USE */ -#define DEFAULT_TX 0x0E -#define DEFAULT_RX 0x0F - -#define BT_A2DP_TX 0x10 - -#define HEADSET_MONO_PLUS_SPKR_MONO_RX 0x11 -#define HEADSET_MONO_PLUS_SPKR_STEREO_RX 0x12 -#define HEADSET_STEREO_PLUS_SPKR_MONO_RX 0x13 -#define HEADSET_STEREO_PLUS_SPKR_STEREO_RX 0x14 - -#define I2S_RX 0x20 -#define I2S_TX 0x21 - -#define ADRC_ENABLE 0x0001 -#define EQUALIZER_ENABLE 0x0002 -#define IIR_ENABLE 0x0004 -#define QCONCERT_PLUS_ENABLE 0x0008 -#define MBADRC_ENABLE 0x0010 -#define SRS_ENABLE 0x0020 -#define SRS_DISABLE 0x0040 - -#define AGC_ENABLE 0x0001 -#define NS_ENABLE 0x0002 -#define TX_IIR_ENABLE 0x0004 -#define FLUENCE_ENABLE 0x0008 - -#define VOC_REC_UPLINK 0x00 -#define VOC_REC_DOWNLINK 0x01 -#define VOC_REC_BOTH 0x02 - -struct msm_audio_config { - uint32_t buffer_size; - uint32_t buffer_count; - uint32_t channel_count; - uint32_t sample_rate; - uint32_t type; - uint32_t meta_field; - uint32_t bits; - uint32_t unused[3]; -}; - -struct msm_audio_stream_config { - uint32_t buffer_size; - uint32_t buffer_count; -}; - -struct msm_audio_buf_cfg { - uint32_t meta_info_enable; - uint32_t frames_per_buf; -}; - -struct msm_audio_stats { - uint32_t byte_count; - uint32_t sample_count; - uint32_t unused[2]; -}; - -struct msm_audio_ion_info { - int fd; - void *vaddr; -}; - -struct msm_audio_pmem_info { - int fd; - void *vaddr; -}; - -struct msm_audio_aio_buf { - void *buf_addr; - uint32_t buf_len; - uint32_t data_len; - void *private_data; - unsigned short mfield_sz; /*only useful for data has meta field */ -}; - -/* Audio routing */ - -#define SND_IOCTL_MAGIC 's' - -#define SND_MUTE_UNMUTED 0 -#define SND_MUTE_MUTED 1 - -struct msm_mute_info { - uint32_t mute; - uint32_t path; -}; - -struct msm_vol_info { - uint32_t vol; - uint32_t path; -}; - -struct msm_voicerec_mode { - uint32_t rec_mode; -}; - -struct msm_snd_device_config { - uint32_t device; - uint32_t ear_mute; - uint32_t mic_mute; -}; - -#define SND_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_device_config *) - -enum cad_device_path_type { - CAD_DEVICE_PATH_RX, /*For Decoding session*/ - CAD_DEVICE_PATH_TX, /* For Encoding session*/ - CAD_DEVICE_PATH_RX_TX, /* For Voice call */ - CAD_DEVICE_PATH_LB, /* For loopback (FM Analog)*/ - CAD_DEVICE_PATH_MAX -}; - -struct cad_devices_type { - uint32_t rx_device; - uint32_t tx_device; - enum cad_device_path_type pathtype; -}; - -struct msm_cad_device_config { - struct cad_devices_type device; - uint32_t ear_mute; - uint32_t mic_mute; -}; - -#define CAD_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_cad_device_config *) - -#define SND_METHOD_VOICE 0 -#define SND_METHOD_MIDI 4 - -struct msm_snd_volume_config { - uint32_t device; - uint32_t method; - uint32_t volume; -}; - -#define SND_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_snd_volume_config *) - -struct msm_cad_volume_config { - struct cad_devices_type device; - uint32_t method; - uint32_t volume; -}; - -#define CAD_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_cad_volume_config *) - -/* Returns the number of SND endpoints supported. */ - -#define SND_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned int *) - -struct msm_snd_endpoint { - int id; /* input and output */ - char name[64]; /* output only */ -}; - -/* Takes an index between 0 and one less than the number returned by - * SND_GET_NUM_ENDPOINTS, and returns the SND index and name of a - * SND endpoint. On input, the .id field contains the number of the - * endpoint, and on exit it contains the SND index, while .name contains - * the description of the endpoint. - */ - -#define SND_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_snd_endpoint *) - - -#define SND_AVC_CTL _IOW(SND_IOCTL_MAGIC, 6, unsigned int *) -#define SND_AGC_CTL _IOW(SND_IOCTL_MAGIC, 7, unsigned int *) - -/*return the number of CAD endpoints supported. */ - -#define CAD_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned int *) - -struct msm_cad_endpoint { - int id; /* input and output */ - char name[64]; /* output only */ -}; - -/* Takes an index between 0 and one less than the number returned by - * SND_GET_NUM_ENDPOINTS, and returns the CAD index and name of a - * CAD endpoint. On input, the .id field contains the number of the - * endpoint, and on exit it contains the SND index, while .name contains - * the description of the endpoint. - */ - -#define CAD_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_cad_endpoint *) - -struct msm_audio_pcm_config { - uint32_t pcm_feedback; /* 0 - disable > 0 - enable */ - uint32_t buffer_count; /* Number of buffers to allocate */ - uint32_t buffer_size; /* Size of buffer for capturing of - * PCM samples - */ -}; - -#define AUDIO_EVENT_SUSPEND 0 -#define AUDIO_EVENT_RESUME 1 -#define AUDIO_EVENT_WRITE_DONE 2 -#define AUDIO_EVENT_READ_DONE 3 -#define AUDIO_EVENT_STREAM_INFO 4 -#define AUDIO_EVENT_BITSTREAM_ERROR_INFO 5 - -#define AUDIO_CODEC_TYPE_MP3 0 -#define AUDIO_CODEC_TYPE_AAC 1 - -struct msm_audio_bitstream_info { - uint32_t codec_type; - uint32_t chan_info; - uint32_t sample_rate; - uint32_t bit_stream_info; - uint32_t bit_rate; - uint32_t unused[3]; -}; - -struct msm_audio_bitstream_error_info { - uint32_t dec_id; - uint32_t err_msg_indicator; - uint32_t err_type; -}; - -union msm_audio_event_payload { - struct msm_audio_aio_buf aio_buf; - struct msm_audio_bitstream_info stream_info; - struct msm_audio_bitstream_error_info error_info; - int reserved; -}; - -struct msm_audio_event { - int event_type; - int timeout_ms; - union msm_audio_event_payload event_payload; -}; - -#define MSM_SNDDEV_CAP_RX 0x1 -#define MSM_SNDDEV_CAP_TX 0x2 -#define MSM_SNDDEV_CAP_VOICE 0x4 - -struct msm_snd_device_info { - uint32_t dev_id; - uint32_t dev_cap; /* bitmask describe capability of device */ - char dev_name[64]; -}; - -struct msm_snd_device_list { - uint32_t num_dev; /* Indicate number of device info to be retrieved */ - struct msm_snd_device_info *list; -}; - -struct msm_dtmf_config { - uint16_t path; - uint16_t dtmf_hi; - uint16_t dtmf_low; - uint16_t duration; - uint16_t tx_gain; - uint16_t rx_gain; - uint16_t mixing; -}; - -#define AUDIO_ROUTE_STREAM_VOICE_RX 0 -#define AUDIO_ROUTE_STREAM_VOICE_TX 1 -#define AUDIO_ROUTE_STREAM_PLAYBACK 2 -#define AUDIO_ROUTE_STREAM_REC 3 - -struct msm_audio_route_config { - uint32_t stream_type; - uint32_t stream_id; - uint32_t dev_id; -}; - -#define AUDIO_MAX_EQ_BANDS 12 - -struct msm_audio_eq_band { - uint16_t band_idx; /* The band index, 0 .. 11 */ - uint32_t filter_type; /* Filter band type */ - uint32_t center_freq_hz; /* Filter band center frequency */ - uint32_t filter_gain; /* Filter band initial gain (dB) */ - /* Range is +12 dB to -12 dB with 1dB increments. */ - uint32_t q_factor; -} __attribute__ ((packed)); - -struct msm_audio_eq_stream_config { - uint32_t enable; /* Number of consequtive bands specified */ - uint32_t num_bands; - struct msm_audio_eq_band eq_bands[AUDIO_MAX_EQ_BANDS]; -} __attribute__ ((packed)); - -struct msm_acdb_cmd_device { - uint32_t command_id; - uint32_t device_id; - uint32_t network_id; - uint32_t sample_rate_id; /* Actual sample rate value */ - uint32_t interface_id; /* See interface id's above */ - uint32_t algorithm_block_id; /* See enumerations above */ - uint32_t total_bytes; /* Length in bytes used by buffer */ - uint32_t *phys_buf; /* Physical Address of data */ -}; - -struct msm_hwacc_data_config { - __u32 buf_size; - __u32 num_buf; - __u32 num_channels; - __u8 channel_map[8]; - __u32 sample_rate; - __u32 bits_per_sample; -}; - -struct msm_hwacc_buf_cfg { - __u32 input_len; - __u32 output_len; -}; - -struct msm_hwacc_buf_avail { - __u32 input_num_avail; - __u32 output_num_avail; -}; - -struct msm_hwacc_effects_config { - struct msm_hwacc_data_config input; - struct msm_hwacc_data_config output; - struct msm_hwacc_buf_cfg buf_cfg; - __u32 meta_mode_enabled; - __u32 overwrite_topology; - __s32 topology; -}; - -#define ADSP_STREAM_PP_EVENT 0 -#define ADSP_STREAM_ENCDEC_EVENT 1 -#define ADSP_STREAM_IEC_61937_FMT_UPDATE_EVENT 2 -#define ADSP_STREAM_EVENT_MAX 3 - -struct msm_adsp_event_data { - __u32 event_type; - __u32 payload_len; - __u8 payload[0]; -}; - -#if defined(CONFIG_CIRRUS_SPKR_PROTECTION) -struct msm_pcm_drv_data { - const char *config_name; -}; -#endif -#endif diff --git a/sdm710/original-kernel-headers/linux/msm_audio_aac.h b/sdm710/original-kernel-headers/linux/msm_audio_aac.h deleted file mode 100644 index 8499ac48..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_aac.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef _MSM_AUDIO_AAC_H -#define _MSM_AUDIO_AAC_H - -#include <linux/msm_audio.h> - -#define AUDIO_SET_AAC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_aac_config) -#define AUDIO_GET_AAC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_aac_config) - -#define AUDIO_SET_AAC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_aac_enc_config) - -#define AUDIO_GET_AAC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+4), struct msm_audio_aac_enc_config) - -#define AUDIO_SET_AAC_MIX_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+5), uint32_t) - -#define AUDIO_AAC_FORMAT_ADTS -1 -#define AUDIO_AAC_FORMAT_RAW 0x0000 -#define AUDIO_AAC_FORMAT_PSUEDO_RAW 0x0001 -#define AUDIO_AAC_FORMAT_LOAS 0x0002 -#define AUDIO_AAC_FORMAT_ADIF 0x0003 - -#define AUDIO_AAC_OBJECT_LC 0x0002 -#define AUDIO_AAC_OBJECT_LTP 0x0004 -#define AUDIO_AAC_OBJECT_ERLC 0x0011 -#define AUDIO_AAC_OBJECT_BSAC 0x0016 - -#define AUDIO_AAC_SEC_DATA_RES_ON 0x0001 -#define AUDIO_AAC_SEC_DATA_RES_OFF 0x0000 - -#define AUDIO_AAC_SCA_DATA_RES_ON 0x0001 -#define AUDIO_AAC_SCA_DATA_RES_OFF 0x0000 - -#define AUDIO_AAC_SPEC_DATA_RES_ON 0x0001 -#define AUDIO_AAC_SPEC_DATA_RES_OFF 0x0000 - -#define AUDIO_AAC_SBR_ON_FLAG_ON 0x0001 -#define AUDIO_AAC_SBR_ON_FLAG_OFF 0x0000 - -#define AUDIO_AAC_SBR_PS_ON_FLAG_ON 0x0001 -#define AUDIO_AAC_SBR_PS_ON_FLAG_OFF 0x0000 - -/* Primary channel on both left and right channels */ -#define AUDIO_AAC_DUAL_MONO_PL_PR 0 -/* Secondary channel on both left and right channels */ -#define AUDIO_AAC_DUAL_MONO_SL_SR 1 -/* Primary channel on right channel and 2nd on left channel */ -#define AUDIO_AAC_DUAL_MONO_SL_PR 2 -/* 2nd channel on right channel and primary on left channel */ -#define AUDIO_AAC_DUAL_MONO_PL_SR 3 - -struct msm_audio_aac_config { - signed short format; - unsigned short audio_object; - unsigned short ep_config; /* 0 ~ 3 useful only obj = ERLC */ - unsigned short aac_section_data_resilience_flag; - unsigned short aac_scalefactor_data_resilience_flag; - unsigned short aac_spectral_data_resilience_flag; - unsigned short sbr_on_flag; - unsigned short sbr_ps_on_flag; - unsigned short dual_mono_mode; - unsigned short channel_configuration; - unsigned short sample_rate; -}; - -struct msm_audio_aac_enc_config { - uint32_t channels; - uint32_t sample_rate; - uint32_t bit_rate; - uint32_t stream_format; -}; - -#endif /* _MSM_AUDIO_AAC_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_audio_ac3.h b/sdm710/original-kernel-headers/linux/msm_audio_ac3.h deleted file mode 100644 index 2203d9e4..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_ac3.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _MSM_AUDIO_AC3_H -#define _MSM_AUDIO_AC3_H - -#include <linux/msm_audio.h> - -#define AUDIO_SET_AC3_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned int) -#define AUDIO_GET_AC3_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned int) - -#define AUDAC3_DEF_WORDSIZE 0 -#define AUDAC3_DEF_USER_DOWNMIX_FLAG 0x0 -#define AUDAC3_DEF_USER_KARAOKE_FLAG 0x0 -#define AUDAC3_DEF_ERROR_CONCEALMENT 0 -#define AUDAC3_DEF_MAX_REPEAT_COUNT 0 - -struct msm_audio_ac3_config { - unsigned short numChans; - unsigned short wordSize; - unsigned short kCapableMode; - unsigned short compMode; - unsigned short outLfeOn; - unsigned short outputMode; - unsigned short stereoMode; - unsigned short dualMonoMode; - unsigned short fsCod; - unsigned short pcmScaleFac; - unsigned short dynRngScaleHi; - unsigned short dynRngScaleLow; - unsigned short user_downmix_flag; - unsigned short user_karaoke_flag; - unsigned short dm_address_high; - unsigned short dm_address_low; - unsigned short ko_address_high; - unsigned short ko_address_low; - unsigned short error_concealment; - unsigned short max_rep_count; - unsigned short channel_routing_mode[6]; -}; - -#endif /* _MSM_AUDIO_AC3_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_audio_alac.h b/sdm710/original-kernel-headers/linux/msm_audio_alac.h deleted file mode 100644 index 36b96567..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_alac.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef _MSM_AUDIO_ALAC_H -#define _MSM_AUDIO_ALAC_H - -#define AUDIO_GET_ALAC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_alac_config) -#define AUDIO_SET_ALAC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_alac_config) - -struct msm_audio_alac_config { - uint32_t frameLength; - uint8_t compatVersion; - uint8_t bitDepth; - uint8_t pb; /* currently unused */ - uint8_t mb; /* currently unused */ - uint8_t kb; /* currently unused */ - uint8_t channelCount; - uint16_t maxRun; /* currently unused */ - uint32_t maxSize; - uint32_t averageBitRate; - uint32_t sampleRate; - uint32_t channelLayout; -}; - -#endif /* _MSM_AUDIO_ALAC_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_audio_amrnb.h b/sdm710/original-kernel-headers/linux/msm_audio_amrnb.h deleted file mode 100644 index 04099835..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_amrnb.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef _MSM_AUDIO_AMRNB_H -#define _MSM_AUDIO_AMRNB_H - -#include <linux/msm_audio.h> - -#define AUDIO_GET_AMRNB_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned int) -#define AUDIO_SET_AMRNB_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned int) -#define AUDIO_GET_AMRNB_ENC_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+2), \ - struct msm_audio_amrnb_enc_config_v2) -#define AUDIO_SET_AMRNB_ENC_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+3), \ - struct msm_audio_amrnb_enc_config_v2) - -struct msm_audio_amrnb_enc_config { - unsigned short voicememoencweight1; - unsigned short voicememoencweight2; - unsigned short voicememoencweight3; - unsigned short voicememoencweight4; - unsigned short dtx_mode_enable; /* 0xFFFF - enable, 0- disable */ - unsigned short test_mode_enable; /* 0xFFFF - enable, 0- disable */ - unsigned short enc_mode; /* 0-MR475,1-MR515,2-MR59,3-MR67,4-MR74 - * 5-MR795, 6- MR102, 7- MR122(default) - */ -}; - -struct msm_audio_amrnb_enc_config_v2 { - uint32_t band_mode; - uint32_t dtx_enable; - uint32_t frame_format; -}; -#endif /* _MSM_AUDIO_AMRNB_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_audio_amrwb.h b/sdm710/original-kernel-headers/linux/msm_audio_amrwb.h deleted file mode 100644 index 0d55397d..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_amrwb.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _MSM_AUDIO_AMRWB_H -#define _MSM_AUDIO_AMRWB_H - -#include <linux/msm_audio.h> - -#define AUDIO_GET_AMRWB_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), \ - struct msm_audio_amrwb_enc_config) -#define AUDIO_SET_AMRWB_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), \ - struct msm_audio_amrwb_enc_config) - -struct msm_audio_amrwb_enc_config { - uint32_t band_mode; - uint32_t dtx_enable; - uint32_t frame_format; -}; -#endif /* _MSM_AUDIO_AMRWB_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_audio_amrwbplus.h b/sdm710/original-kernel-headers/linux/msm_audio_amrwbplus.h deleted file mode 100644 index 5b8a980a..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_amrwbplus.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _MSM_AUDIO_AMR_WB_PLUS_H -#define _MSM_AUDIO_AMR_WB_PLUS_H - -#define AUDIO_GET_AMRWBPLUS_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+2), struct msm_audio_amrwbplus_config_v2) -#define AUDIO_SET_AMRWBPLUS_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_amrwbplus_config_v2) - -struct msm_audio_amrwbplus_config_v2 { - unsigned int size_bytes; - unsigned int version; - unsigned int num_channels; - unsigned int amr_band_mode; - unsigned int amr_dtx_mode; - unsigned int amr_frame_fmt; - unsigned int amr_lsf_idx; -}; -#endif /* _MSM_AUDIO_AMR_WB_PLUS_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_audio_ape.h b/sdm710/original-kernel-headers/linux/msm_audio_ape.h deleted file mode 100644 index b14f6852..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_ape.h +++ /dev/null @@ -1,26 +0,0 @@ -/* The following structure has been taken - * from Monkey's Audio SDK with permission - */ - -#ifndef _MSM_AUDIO_APE_H -#define _MSM_AUDIO_APE_H - -#define AUDIO_GET_APE_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_ape_config) -#define AUDIO_SET_APE_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_ape_config) - -struct msm_audio_ape_config { - uint16_t compatibleVersion; - uint16_t compressionLevel; - uint32_t formatFlags; - uint32_t blocksPerFrame; - uint32_t finalFrameBlocks; - uint32_t totalFrames; - uint16_t bitsPerSample; - uint16_t numChannels; - uint32_t sampleRate; - uint32_t seekTablePresent; -}; - -#endif /* _MSM_AUDIO_APE_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_audio_calibration.h b/sdm710/original-kernel-headers/linux/msm_audio_calibration.h deleted file mode 100644 index 42800d7b..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_calibration.h +++ /dev/null @@ -1,742 +0,0 @@ -#ifndef _MSM_AUDIO_CALIBRATION_H -#define _MSM_AUDIO_CALIBRATION_H - -#include <linux/types.h> -#include <linux/ioctl.h> - -#define CAL_IOCTL_MAGIC 'a' - -#define AUDIO_ALLOCATE_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \ - 200, void *) -#define AUDIO_DEALLOCATE_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \ - 201, void *) -#define AUDIO_PREPARE_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \ - 202, void *) -#define AUDIO_SET_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \ - 203, void *) -#define AUDIO_GET_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \ - 204, void *) -#define AUDIO_POST_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \ - 205, void *) - -/* For Real-Time Audio Calibration */ -#define AUDIO_GET_RTAC_ADM_INFO _IOR(CAL_IOCTL_MAGIC, \ - 207, void *) -#define AUDIO_GET_RTAC_VOICE_INFO _IOR(CAL_IOCTL_MAGIC, \ - 208, void *) -#define AUDIO_GET_RTAC_ADM_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 209, void *) -#define AUDIO_SET_RTAC_ADM_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 210, void *) -#define AUDIO_GET_RTAC_ASM_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 211, void *) -#define AUDIO_SET_RTAC_ASM_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 212, void *) -#define AUDIO_GET_RTAC_CVS_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 213, void *) -#define AUDIO_SET_RTAC_CVS_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 214, void *) -#define AUDIO_GET_RTAC_CVP_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 215, void *) -#define AUDIO_SET_RTAC_CVP_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 216, void *) -#define AUDIO_GET_RTAC_AFE_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 217, void *) -#define AUDIO_SET_RTAC_AFE_CAL _IOWR(CAL_IOCTL_MAGIC, \ - 218, void *) -enum { - CVP_VOC_RX_TOPOLOGY_CAL_TYPE = 0, - CVP_VOC_TX_TOPOLOGY_CAL_TYPE, - CVP_VOCPROC_STATIC_CAL_TYPE, - CVP_VOCPROC_DYNAMIC_CAL_TYPE, - CVS_VOCSTRM_STATIC_CAL_TYPE, - CVP_VOCDEV_CFG_CAL_TYPE, - CVP_VOCPROC_STATIC_COL_CAL_TYPE, - CVP_VOCPROC_DYNAMIC_COL_CAL_TYPE, - CVS_VOCSTRM_STATIC_COL_CAL_TYPE, - - ADM_TOPOLOGY_CAL_TYPE, - ADM_CUST_TOPOLOGY_CAL_TYPE, - ADM_AUDPROC_CAL_TYPE, - ADM_AUDVOL_CAL_TYPE, - - ASM_TOPOLOGY_CAL_TYPE, - ASM_CUST_TOPOLOGY_CAL_TYPE, - ASM_AUDSTRM_CAL_TYPE, - - AFE_COMMON_RX_CAL_TYPE, - AFE_COMMON_TX_CAL_TYPE, - AFE_ANC_CAL_TYPE, - AFE_AANC_CAL_TYPE, - AFE_FB_SPKR_PROT_CAL_TYPE, - AFE_HW_DELAY_CAL_TYPE, - AFE_SIDETONE_CAL_TYPE, - AFE_TOPOLOGY_CAL_TYPE, - AFE_CUST_TOPOLOGY_CAL_TYPE, - - LSM_CUST_TOPOLOGY_CAL_TYPE, - LSM_TOPOLOGY_CAL_TYPE, - LSM_CAL_TYPE, - - ADM_RTAC_INFO_CAL_TYPE, - VOICE_RTAC_INFO_CAL_TYPE, - ADM_RTAC_APR_CAL_TYPE, - ASM_RTAC_APR_CAL_TYPE, - VOICE_RTAC_APR_CAL_TYPE, - - MAD_CAL_TYPE, - ULP_AFE_CAL_TYPE, - ULP_LSM_CAL_TYPE, - - DTS_EAGLE_CAL_TYPE, - AUDIO_CORE_METAINFO_CAL_TYPE, - SRS_TRUMEDIA_CAL_TYPE, - - CORE_CUSTOM_TOPOLOGIES_CAL_TYPE, - ADM_RTAC_AUDVOL_CAL_TYPE, - - ULP_LSM_TOPOLOGY_ID_CAL_TYPE, - AFE_FB_SPKR_PROT_TH_VI_CAL_TYPE, - AFE_FB_SPKR_PROT_EX_VI_CAL_TYPE, - AFE_SIDETONE_IIR_CAL_TYPE, - AFE_LSM_TOPOLOGY_CAL_TYPE, - AFE_LSM_TX_CAL_TYPE, - ADM_LSM_TOPOLOGY_CAL_TYPE, - ADM_LSM_AUDPROC_CAL_TYPE, - MAX_CAL_TYPES, -}; - -#define AFE_FB_SPKR_PROT_TH_VI_CAL_TYPE AFE_FB_SPKR_PROT_TH_VI_CAL_TYPE -#define AFE_FB_SPKR_PROT_EX_VI_CAL_TYPE AFE_FB_SPKR_PROT_EX_VI_CAL_TYPE - -#define AFE_SIDETONE_IIR_CAL_TYPE AFE_SIDETONE_IIR_CAL_TYPE - -#define AFE_LSM_TOPOLOGY_CAL_TYPE AFE_LSM_TOPOLOGY_CAL_TYPE -#define AFE_LSM_TX_CAL_TYPE AFE_LSM_TX_CAL_TYPE -#define ADM_LSM_TOPOLOGY_CAL_TYPE ADM_LSM_TOPOLOGY_CAL_TYPE -#define ADM_LSM_AUDPROC_CAL_TYPE ADM_LSM_AUDPROC_CAL_TYPE -#define LSM_CAL_TYPES - -#define TOPOLOGY_SPECIFIC_CHANNEL_INFO -#define MSM_SPKR_PROT_SPV3 - -enum { - VERSION_0_0, -}; - -enum { - PER_VOCODER_CAL_BIT_MASK = 0x10000, -}; - -#define MAX_IOCTL_CMD_SIZE 512 - -/* common structures */ - -struct audio_cal_header { - int32_t data_size; - int32_t version; - int32_t cal_type; - int32_t cal_type_size; -}; - -struct audio_cal_type_header { - int32_t version; - int32_t buffer_number; -}; - -struct audio_cal_data { - /* Size of cal data at mem_handle allocation or at vaddr */ - int32_t cal_size; - /* If mem_handle if shared memory is used*/ - int32_t mem_handle; - /* size of virtual memory if shared memory not used */ -}; - - -/* AUDIO_ALLOCATE_CALIBRATION */ -struct audio_cal_type_alloc { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; -}; - -struct audio_cal_alloc { - struct audio_cal_header hdr; - struct audio_cal_type_alloc cal_type; -}; - - -/* AUDIO_DEALLOCATE_CALIBRATION */ -struct audio_cal_type_dealloc { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; -}; - -struct audio_cal_dealloc { - struct audio_cal_header hdr; - struct audio_cal_type_dealloc cal_type; -}; - - -/* AUDIO_PREPARE_CALIBRATION */ -struct audio_cal_type_prepare { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; -}; - -struct audio_cal_prepare { - struct audio_cal_header hdr; - struct audio_cal_type_prepare cal_type; -}; - - -/* AUDIO_POST_CALIBRATION */ -struct audio_cal_type_post { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; -}; - -struct audio_cal_post { - struct audio_cal_header hdr; - struct audio_cal_type_post cal_type; -}; - -/*AUDIO_CORE_META_INFO */ - -struct audio_cal_info_metainfo { - uint32_t nKey; -}; - -/* Cal info types */ -enum { - RX_DEVICE, - TX_DEVICE, - MAX_PATH_TYPE -}; - -struct audio_cal_info_adm_top { - int32_t topology; - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t app_type; - int32_t sample_rate; -}; - -struct audio_cal_info_audproc { - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t app_type; - int32_t sample_rate; -}; - -struct audio_cal_info_audvol { - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t app_type; - int32_t vol_index; -}; - -struct audio_cal_info_afe { - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t sample_rate; -}; - -struct audio_cal_info_afe_top { - int32_t topology; - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t sample_rate; -}; - -struct audio_cal_info_asm_top { - int32_t topology; - int32_t app_type; -}; - -struct audio_cal_info_audstrm { - int32_t app_type; -}; - -struct audio_cal_info_aanc { - int32_t acdb_id; -}; - -#define MAX_HW_DELAY_ENTRIES 25 - -struct audio_cal_hw_delay_entry { - uint32_t sample_rate; - uint32_t delay_usec; -}; - -struct audio_cal_hw_delay_data { - uint32_t num_entries; - struct audio_cal_hw_delay_entry entry[MAX_HW_DELAY_ENTRIES]; -}; - -struct audio_cal_info_hw_delay { - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t property_type; - struct audio_cal_hw_delay_data data; -}; - -enum msm_spkr_prot_states { - MSM_SPKR_PROT_CALIBRATED, - MSM_SPKR_PROT_CALIBRATION_IN_PROGRESS, - MSM_SPKR_PROT_DISABLED, - MSM_SPKR_PROT_NOT_CALIBRATED, - MSM_SPKR_PROT_PRE_CALIBRATED, - MSM_SPKR_PROT_IN_FTM_MODE -}; -#define MSM_SPKR_PROT_IN_FTM_MODE MSM_SPKR_PROT_IN_FTM_MODE - -enum msm_spkr_count { - SP_V2_SPKR_1, - SP_V2_SPKR_2, - SP_V2_NUM_MAX_SPKRS -}; - -struct audio_cal_info_spk_prot_cfg { - int32_t r0[SP_V2_NUM_MAX_SPKRS]; - int32_t t0[SP_V2_NUM_MAX_SPKRS]; - uint32_t quick_calib_flag; - uint32_t mode; - /* - * 0 - Start spk prot - * 1 - Start calib - * 2 - Disable spk prot - */ -#ifdef MSM_SPKR_PROT_SPV3 - uint32_t sp_version; - int32_t limiter_th[SP_V2_NUM_MAX_SPKRS]; -#endif -}; - -struct audio_cal_info_sp_th_vi_ftm_cfg { - uint32_t wait_time[SP_V2_NUM_MAX_SPKRS]; - uint32_t ftm_time[SP_V2_NUM_MAX_SPKRS]; - uint32_t mode; - /* - * 0 - normal running mode - * 1 - Calibration - * 2 - FTM mode - */ -}; - -struct audio_cal_info_sp_ex_vi_ftm_cfg { - uint32_t wait_time[SP_V2_NUM_MAX_SPKRS]; - uint32_t ftm_time[SP_V2_NUM_MAX_SPKRS]; - uint32_t mode; - /* - * 0 - normal running mode - * 2 - FTM mode - */ -}; - -struct audio_cal_info_sp_ex_vi_param { - int32_t freq_q20[SP_V2_NUM_MAX_SPKRS]; - int32_t resis_q24[SP_V2_NUM_MAX_SPKRS]; - int32_t qmct_q24[SP_V2_NUM_MAX_SPKRS]; - int32_t status[SP_V2_NUM_MAX_SPKRS]; -}; - -struct audio_cal_info_sp_th_vi_param { - int32_t r_dc_q24[SP_V2_NUM_MAX_SPKRS]; - int32_t temp_q22[SP_V2_NUM_MAX_SPKRS]; - int32_t status[SP_V2_NUM_MAX_SPKRS]; -}; - -struct audio_cal_info_msm_spk_prot_status { - int32_t r0[SP_V2_NUM_MAX_SPKRS]; - int32_t status; -}; - -struct audio_cal_info_sidetone { - uint16_t enable; - uint16_t gain; - int32_t tx_acdb_id; - int32_t rx_acdb_id; - int32_t mid; - int32_t pid; -}; - -#define MAX_SIDETONE_IIR_DATA_SIZE 224 -#define MAX_NO_IIR_FILTER_STAGE 10 - -struct audio_cal_info_sidetone_iir { - uint16_t iir_enable; - uint16_t num_biquad_stages; - uint16_t pregain; - int32_t tx_acdb_id; - int32_t rx_acdb_id; - int32_t mid; - int32_t pid; - uint8_t iir_config[MAX_SIDETONE_IIR_DATA_SIZE]; -}; -struct audio_cal_info_lsm_top { - int32_t topology; - int32_t acdb_id; - int32_t app_type; -}; - - -struct audio_cal_info_lsm { - int32_t acdb_id; - /* RX_DEVICE or TX_DEVICE */ - int32_t path; - int32_t app_type; -}; - -#define VSS_NUM_CHANNELS_MAX 8 - -struct audio_cal_info_voc_top { - int32_t topology; - int32_t acdb_id; -#ifdef TOPOLOGY_SPECIFIC_CHANNEL_INFO - uint32_t num_channels; - uint8_t channel_mapping[VSS_NUM_CHANNELS_MAX]; -#endif -}; - -struct audio_cal_info_vocproc { - int32_t tx_acdb_id; - int32_t rx_acdb_id; - int32_t tx_sample_rate; - int32_t rx_sample_rate; -}; - -enum { - DEFAULT_FEATURE_SET, - VOL_BOOST_FEATURE_SET, -}; - -struct audio_cal_info_vocvol { - int32_t tx_acdb_id; - int32_t rx_acdb_id; - /* DEFAULT_ or VOL_BOOST_FEATURE_SET */ - int32_t feature_set; -}; - -struct audio_cal_info_vocdev_cfg { - int32_t tx_acdb_id; - int32_t rx_acdb_id; -}; - -#define MAX_VOICE_COLUMNS 20 - -union audio_cal_col_na { - uint8_t val8; - uint16_t val16; - uint32_t val32; - uint64_t val64; -} __attribute__((packed)); - -struct audio_cal_col { - uint32_t id; - uint32_t type; - union audio_cal_col_na na_value; -} __attribute__((packed)); - -struct audio_cal_col_data { - uint32_t num_columns; - struct audio_cal_col column[MAX_VOICE_COLUMNS]; -} __attribute__((packed)); - -struct audio_cal_info_voc_col { - int32_t table_id; - int32_t tx_acdb_id; - int32_t rx_acdb_id; - struct audio_cal_col_data data; -}; - -/* AUDIO_SET_CALIBRATION & */ -struct audio_cal_type_basic { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; -}; - -struct audio_cal_basic { - struct audio_cal_header hdr; - struct audio_cal_type_basic cal_type; -}; - -struct audio_cal_type_adm_top { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_adm_top cal_info; -}; - -struct audio_cal_adm_top { - struct audio_cal_header hdr; - struct audio_cal_type_adm_top cal_type; -}; - -struct audio_cal_type_metainfo { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_metainfo cal_info; -}; - -struct audio_core_metainfo { - struct audio_cal_header hdr; - struct audio_cal_type_metainfo cal_type; -}; - -struct audio_cal_type_audproc { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_audproc cal_info; -}; - -struct audio_cal_audproc { - struct audio_cal_header hdr; - struct audio_cal_type_audproc cal_type; -}; - -struct audio_cal_type_audvol { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_audvol cal_info; -}; - -struct audio_cal_audvol { - struct audio_cal_header hdr; - struct audio_cal_type_audvol cal_type; -}; - -struct audio_cal_type_asm_top { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_asm_top cal_info; -}; - -struct audio_cal_asm_top { - struct audio_cal_header hdr; - struct audio_cal_type_asm_top cal_type; -}; - -struct audio_cal_type_audstrm { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_audstrm cal_info; -}; - -struct audio_cal_audstrm { - struct audio_cal_header hdr; - struct audio_cal_type_audstrm cal_type; -}; - -struct audio_cal_type_afe { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_afe cal_info; -}; - -struct audio_cal_afe { - struct audio_cal_header hdr; - struct audio_cal_type_afe cal_type; -}; - -struct audio_cal_type_afe_top { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_afe_top cal_info; -}; - -struct audio_cal_afe_top { - struct audio_cal_header hdr; - struct audio_cal_type_afe_top cal_type; -}; - -struct audio_cal_type_aanc { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_aanc cal_info; -}; - -struct audio_cal_aanc { - struct audio_cal_header hdr; - struct audio_cal_type_aanc cal_type; -}; - -struct audio_cal_type_fb_spk_prot_cfg { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_spk_prot_cfg cal_info; -}; - -struct audio_cal_fb_spk_prot_cfg { - struct audio_cal_header hdr; - struct audio_cal_type_fb_spk_prot_cfg cal_type; -}; - -struct audio_cal_type_sp_th_vi_ftm_cfg { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_sp_th_vi_ftm_cfg cal_info; -}; - -struct audio_cal_sp_th_vi_ftm_cfg { - struct audio_cal_header hdr; - struct audio_cal_type_sp_th_vi_ftm_cfg cal_type; -}; - -struct audio_cal_type_sp_ex_vi_ftm_cfg { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_sp_ex_vi_ftm_cfg cal_info; -}; - -struct audio_cal_sp_ex_vi_ftm_cfg { - struct audio_cal_header hdr; - struct audio_cal_type_sp_ex_vi_ftm_cfg cal_type; -}; -struct audio_cal_type_hw_delay { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_hw_delay cal_info; -}; - -struct audio_cal_hw_delay { - struct audio_cal_header hdr; - struct audio_cal_type_hw_delay cal_type; -}; - -struct audio_cal_type_sidetone { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_sidetone cal_info; -}; - -struct audio_cal_sidetone { - struct audio_cal_header hdr; - struct audio_cal_type_sidetone cal_type; -}; - -struct audio_cal_type_sidetone_iir { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_sidetone_iir cal_info; -}; - -struct audio_cal_sidetone_iir { - struct audio_cal_header hdr; - struct audio_cal_type_sidetone_iir cal_type; -}; - -struct audio_cal_type_lsm_top { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_lsm_top cal_info; -}; - -struct audio_cal_lsm_top { - struct audio_cal_header hdr; - struct audio_cal_type_lsm_top cal_type; -}; - -struct audio_cal_type_lsm { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_lsm cal_info; -}; - -struct audio_cal_lsm { - struct audio_cal_header hdr; - struct audio_cal_type_lsm cal_type; -}; - -struct audio_cal_type_voc_top { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_voc_top cal_info; -}; - -struct audio_cal_voc_top { - struct audio_cal_header hdr; - struct audio_cal_type_voc_top cal_type; -}; - -struct audio_cal_type_vocproc { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_vocproc cal_info; -}; - -struct audio_cal_vocproc { - struct audio_cal_header hdr; - struct audio_cal_type_vocproc cal_type; -}; - -struct audio_cal_type_vocvol { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_vocvol cal_info; -}; - -struct audio_cal_vocvol { - struct audio_cal_header hdr; - struct audio_cal_type_vocvol cal_type; -}; - -struct audio_cal_type_vocdev_cfg { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_vocdev_cfg cal_info; -}; - -struct audio_cal_vocdev_cfg { - struct audio_cal_header hdr; - struct audio_cal_type_vocdev_cfg cal_type; -}; - -struct audio_cal_type_voc_col { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_voc_col cal_info; -}; - -struct audio_cal_voc_col { - struct audio_cal_header hdr; - struct audio_cal_type_voc_col cal_type; -}; - -/* AUDIO_GET_CALIBRATION */ -struct audio_cal_type_fb_spk_prot_status { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_msm_spk_prot_status cal_info; -}; - -struct audio_cal_fb_spk_prot_status { - struct audio_cal_header hdr; - struct audio_cal_type_fb_spk_prot_status cal_type; -}; - -struct audio_cal_type_sp_th_vi_param { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_sp_th_vi_param cal_info; -}; - -struct audio_cal_sp_th_vi_param { - struct audio_cal_header hdr; - struct audio_cal_type_sp_th_vi_param cal_type; -}; -struct audio_cal_type_sp_ex_vi_param { - struct audio_cal_type_header cal_hdr; - struct audio_cal_data cal_data; - struct audio_cal_info_sp_ex_vi_param cal_info; -}; - -struct audio_cal_sp_ex_vi_param { - struct audio_cal_header hdr; - struct audio_cal_type_sp_ex_vi_param cal_type; -}; -#endif /* _MSM_AUDIO_CALIBRATION_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_audio_mvs.h b/sdm710/original-kernel-headers/linux/msm_audio_mvs.h deleted file mode 100644 index 36d3b55b..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_mvs.h +++ /dev/null @@ -1,155 +0,0 @@ -#ifndef _MSM_AUDIO_MVS_H -#define _MSM_AUDIO_MVS_H - -#include <linux/msm_audio.h> - -#define AUDIO_GET_MVS_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM + 0), unsigned int) -#define AUDIO_SET_MVS_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM + 1), unsigned int) - -/* MVS modes */ -#define MVS_MODE_IS733 0x1 /*QCELP 13K*/ -#define MVS_MODE_IS127 0x2 /*EVRC-8k*/ -#define MVS_MODE_4GV_NB 0x3 /*EVRC-B*/ -#define MVS_MODE_4GV_WB 0x4 /*EVRC-WB*/ -#define MVS_MODE_AMR 0x5 -#define MVS_MODE_EFR 0x6 -#define MVS_MODE_FR 0x7 -#define MVS_MODE_HR 0x8 -#define MVS_MODE_LINEAR_PCM 0x9 -#define MVS_MODE_G711 0xA -#define MVS_MODE_PCM 0xC -#define MVS_MODE_AMR_WB 0xD -#define MVS_MODE_G729A 0xE -#define MVS_MODE_G711A 0xF -#define MVS_MODE_G722 0x10 -#define MVS_MODE_PCM_WB 0x12 - -enum msm_audio_amr_mode { - MVS_AMR_MODE_0475, /* AMR 4.75 kbps */ - MVS_AMR_MODE_0515, /* AMR 5.15 kbps */ - MVS_AMR_MODE_0590, /* AMR 5.90 kbps */ - MVS_AMR_MODE_0670, /* AMR 6.70 kbps */ - MVS_AMR_MODE_0740, /* AMR 7.40 kbps */ - MVS_AMR_MODE_0795, /* AMR 7.95 kbps */ - MVS_AMR_MODE_1020, /* AMR 10.20 kbps */ - MVS_AMR_MODE_1220, /* AMR 12.20 kbps */ - MVS_AMR_MODE_0660, /* AMR-WB 6.60 kbps */ - MVS_AMR_MODE_0885, /* AMR-WB 8.85 kbps */ - MVS_AMR_MODE_1265, /* AMR-WB 12.65 kbps */ - MVS_AMR_MODE_1425, /* AMR-WB 14.25 kbps */ - MVS_AMR_MODE_1585, /* AMR-WB 15.85 kbps */ - MVS_AMR_MODE_1825, /* AMR-WB 18.25 kbps */ - MVS_AMR_MODE_1985, /* AMR-WB 19.85 kbps */ - MVS_AMR_MODE_2305, /* AMR-WB 23.05 kbps */ - MVS_AMR_MODE_2385, /* AMR-WB 23.85 kbps */ - MVS_AMR_MODE_UNDEF -}; - -/* The MVS VOC rate type is used to identify the rate of QCELP 13K(IS733), - * EVRC(IS127), 4GV, or 4GV-WB frame. - */ -enum msm_audio_voc_rate { - MVS_VOC_0_RATE, /* Blank frame */ - MVS_VOC_8_RATE, /* 1/8 rate */ - MVS_VOC_4_RATE, /* 1/4 rate */ - MVS_VOC_2_RATE, /* 1/2 rate */ - MVS_VOC_1_RATE, /* Full rate */ - MVS_VOC_ERASURE, /* erasure frame */ - MVS_VOC_RATE_MAX, - MVS_VOC_RATE_UNDEF = MVS_VOC_RATE_MAX -}; - -enum msm_audio_amr_frame_type { - MVS_AMR_SPEECH_GOOD, /* Good speech frame */ - MVS_AMR_SPEECH_DEGRADED, /* Speech degraded */ - MVS_AMR_ONSET, /* Onset */ - MVS_AMR_SPEECH_BAD, /* Corrupt speech frame (bad CRC) */ - MVS_AMR_SID_FIRST, /* First silence descriptor */ - MVS_AMR_SID_UPDATE, /* Comfort noise frame */ - MVS_AMR_SID_BAD, /* Corrupt SID frame (bad CRC) */ - MVS_AMR_NO_DATA, /* Nothing to transmit */ - MVS_AMR_SPEECH_LOST /* Downlink speech lost */ -}; - -enum msm_audio_g711a_mode { - MVS_G711A_MODE_MULAW, - MVS_G711A_MODE_ALAW -}; - -enum msm_audio_g711_mode { - MVS_G711_MODE_MULAW, - MVS_G711_MODE_ALAW -}; - -enum mvs_g722_mode_type { - MVS_G722_MODE_01, - MVS_G722_MODE_02, - MVS_G722_MODE_03, - MVS_G722_MODE_MAX, - MVS_G722_MODE_UNDEF -}; - -enum msm_audio_g711a_frame_type { - MVS_G711A_SPEECH_GOOD, - MVS_G711A_SID, - MVS_G711A_NO_DATA, - MVS_G711A_ERASURE -}; - -enum msm_audio_g729a_frame_type { - MVS_G729A_NO_DATA, - MVS_G729A_SPEECH_GOOD, - MVS_G729A_SID, - MVS_G729A_ERASURE -}; - -struct min_max_rate { - uint32_t min_rate; - uint32_t max_rate; -}; - -struct msm_audio_mvs_config { - uint32_t mvs_mode; - uint32_t rate_type; - struct min_max_rate min_max_rate; - uint32_t dtx_mode; -}; - -#define MVS_MAX_VOC_PKT_SIZE 640 - -struct gsm_header { - uint8_t bfi; - uint8_t sid; - uint8_t taf; - uint8_t ufi; -}; - -struct q6_msm_audio_mvs_frame { - union { - uint32_t frame_type; - uint32_t packet_rate; - struct gsm_header gsm_frame_type; - } header; - uint32_t len; - uint8_t voc_pkt[MVS_MAX_VOC_PKT_SIZE]; - -}; - -struct msm_audio_mvs_frame { - uint32_t frame_type; - uint32_t len; - uint8_t voc_pkt[MVS_MAX_VOC_PKT_SIZE]; - -}; - -#define Q5V2_MVS_MAX_VOC_PKT_SIZE 320 - -struct q5v2_msm_audio_mvs_frame { - uint32_t frame_type; - uint32_t len; - uint8_t voc_pkt[Q5V2_MVS_MAX_VOC_PKT_SIZE]; - -}; -#endif /* _MSM_AUDIO_MVS_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_audio_qcp.h b/sdm710/original-kernel-headers/linux/msm_audio_qcp.h deleted file mode 100644 index de8552a2..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_qcp.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef _MSM_AUDIO_QCP_H -#define _MSM_AUDIO_QCP_H - -#include <linux/msm_audio.h> - -#define AUDIO_SET_QCELP_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - 0, struct msm_audio_qcelp_enc_config) - -#define AUDIO_GET_QCELP_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - 1, struct msm_audio_qcelp_enc_config) - -#define AUDIO_SET_EVRC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - 2, struct msm_audio_evrc_enc_config) - -#define AUDIO_GET_EVRC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - 3, struct msm_audio_evrc_enc_config) - -#define CDMA_RATE_BLANK 0x00 -#define CDMA_RATE_EIGHTH 0x01 -#define CDMA_RATE_QUARTER 0x02 -#define CDMA_RATE_HALF 0x03 -#define CDMA_RATE_FULL 0x04 -#define CDMA_RATE_ERASURE 0x05 - -struct msm_audio_qcelp_enc_config { - uint32_t cdma_rate; - uint32_t min_bit_rate; - uint32_t max_bit_rate; -}; - -struct msm_audio_evrc_enc_config { - uint32_t cdma_rate; - uint32_t min_bit_rate; - uint32_t max_bit_rate; -}; - -#endif /* _MSM_AUDIO_QCP_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_audio_sbc.h b/sdm710/original-kernel-headers/linux/msm_audio_sbc.h deleted file mode 100644 index 206b183c..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_sbc.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef _MSM_AUDIO_SBC_H -#define _MSM_AUDIO_SBC_H - -#include <linux/msm_audio.h> - -#define AUDIO_SET_SBC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_sbc_enc_config) - -#define AUDIO_GET_SBC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_sbc_enc_config) - -#define AUDIO_SBC_BA_LOUDNESS 0x0 -#define AUDIO_SBC_BA_SNR 0x1 - -#define AUDIO_SBC_MODE_MONO 0x0 -#define AUDIO_SBC_MODE_DUAL 0x1 -#define AUDIO_SBC_MODE_STEREO 0x2 -#define AUDIO_SBC_MODE_JSTEREO 0x3 - -#define AUDIO_SBC_BANDS_8 0x1 - -#define AUDIO_SBC_BLOCKS_4 0x0 -#define AUDIO_SBC_BLOCKS_8 0x1 -#define AUDIO_SBC_BLOCKS_12 0x2 -#define AUDIO_SBC_BLOCKS_16 0x3 - -struct msm_audio_sbc_enc_config { - uint32_t channels; - uint32_t sample_rate; - uint32_t bit_allocation; - uint32_t number_of_subbands; - uint32_t number_of_blocks; - uint32_t bit_rate; - uint32_t mode; -}; -#endif /* _MSM_AUDIO_SBC_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_audio_voicememo.h b/sdm710/original-kernel-headers/linux/msm_audio_voicememo.h deleted file mode 100644 index 50e1696f..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_voicememo.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef _MSM_AUDIO_VOICEMEMO_H -#define _MSM_AUDIO_VOICEMEMO_H - -#include <linux/msm_audio.h> - -#define AUDIO_GET_VOICEMEMO_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned int) -#define AUDIO_SET_VOICEMEMO_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned int) - -/* rec_type */ -enum rpc_voc_rec_dir_type { - RPC_VOC_REC_NONE, - RPC_VOC_REC_FORWARD, - RPC_VOC_REC_REVERSE, - RPC_VOC_REC_BOTH, - RPC_VOC_MAX_REC_TYPE -}; - -/* capability */ -enum rpc_voc_capability_type { - RPC_VOC_CAP_IS733 = 4, - RPC_VOC_CAP_IS127 = 8, - RPC_VOC_CAP_AMR = 64, - RPC_VOC_CAP_32BIT_DUMMY = 2147483647 -}; - -/* Rate */ -enum rpc_voc_rate_type { - RPC_VOC_0_RATE = 0, - RPC_VOC_8_RATE, - RPC_VOC_4_RATE, - RPC_VOC_2_RATE, - RPC_VOC_1_RATE, - RPC_VOC_ERASURE, - RPC_VOC_ERR_RATE, - RPC_VOC_AMR_RATE_475 = 0, - RPC_VOC_AMR_RATE_515 = 1, - RPC_VOC_AMR_RATE_590 = 2, - RPC_VOC_AMR_RATE_670 = 3, - RPC_VOC_AMR_RATE_740 = 4, - RPC_VOC_AMR_RATE_795 = 5, - RPC_VOC_AMR_RATE_1020 = 6, - RPC_VOC_AMR_RATE_1220 = 7, -}; - -/* frame_format */ -enum rpc_voc_pb_len_rate_var_type { - RPC_VOC_PB_NATIVE_QCP = 3, - RPC_VOC_PB_AMR, - RPC_VOC_PB_EVB -}; - -struct msm_audio_voicememo_config { - uint32_t rec_type; - uint32_t rec_interval_ms; - uint32_t auto_stop_ms; - uint32_t capability; - uint32_t max_rate; - uint32_t min_rate; - uint32_t frame_format; - uint32_t dtx_enable; - uint32_t data_req_ms; -}; - -#endif /* _MSM_AUDIO_VOICEMEMO_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_audio_wma.h b/sdm710/original-kernel-headers/linux/msm_audio_wma.h deleted file mode 100644 index 8f46f2c6..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_wma.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef _MSM_AUDIO_WMA_H -#define _MSM_AUDIO_WMA_H - -#define AUDIO_GET_WMA_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned int) -#define AUDIO_SET_WMA_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned int) - -#define AUDIO_GET_WMA_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+2), struct msm_audio_wma_config_v2) -#define AUDIO_SET_WMA_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_wma_config_v2) - -struct msm_audio_wma_config { - unsigned short armdatareqthr; - unsigned short channelsdecoded; - unsigned short wmabytespersec; - unsigned short wmasamplingfreq; - unsigned short wmaencoderopts; -}; - -struct msm_audio_wma_config_v2 { - unsigned short format_tag; - unsigned short numchannels; - uint32_t samplingrate; - uint32_t avgbytespersecond; - unsigned short block_align; - unsigned short validbitspersample; - uint32_t channelmask; - unsigned short encodeopt; -}; - -#endif /* _MSM_AUDIO_WMA_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_audio_wmapro.h b/sdm710/original-kernel-headers/linux/msm_audio_wmapro.h deleted file mode 100644 index 7559a877..00000000 --- a/sdm710/original-kernel-headers/linux/msm_audio_wmapro.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef _MSM_AUDIO_WMAPRO_H -#define _MSM_AUDIO_WMAPRO_H - -#define AUDIO_GET_WMAPRO_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_wmapro_config) -#define AUDIO_SET_WMAPRO_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \ - (AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_wmapro_config) - -struct msm_audio_wmapro_config { - unsigned short armdatareqthr; - uint8_t validbitspersample; - uint8_t numchannels; - unsigned short formattag; - uint32_t samplingrate; - uint32_t avgbytespersecond; - unsigned short asfpacketlength; - uint32_t channelmask; - unsigned short encodeopt; - unsigned short advancedencodeopt; - uint32_t advancedencodeopt2; -}; -#endif /* _MSM_AUDIO_WMAPRO_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_dsps.h b/sdm710/original-kernel-headers/linux/msm_dsps.h deleted file mode 100644 index e3da5769..00000000 --- a/sdm710/original-kernel-headers/linux/msm_dsps.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _DSPS_H_ -#define _DSPS_H_ - -#include <linux/ioctl.h> - -#define DSPS_IOCTL_MAGIC 'd' - -#define DSPS_IOCTL_ON _IO(DSPS_IOCTL_MAGIC, 1) -#define DSPS_IOCTL_OFF _IO(DSPS_IOCTL_MAGIC, 2) - -#define DSPS_IOCTL_READ_SLOW_TIMER _IOR(DSPS_IOCTL_MAGIC, 3, unsigned int*) -#define DSPS_IOCTL_READ_FAST_TIMER _IOR(DSPS_IOCTL_MAGIC, 4, unsigned int*) - -#define DSPS_IOCTL_RESET _IO(DSPS_IOCTL_MAGIC, 5) - -#endif /* _DSPS_H_ */ diff --git a/sdm710/original-kernel-headers/linux/msm_ion.h b/sdm710/original-kernel-headers/linux/msm_ion.h deleted file mode 100644 index b7918c8b..00000000 --- a/sdm710/original-kernel-headers/linux/msm_ion.h +++ /dev/null @@ -1,218 +0,0 @@ -#ifndef _MSM_ION_H -#define _MSM_ION_H - -#include "ion.h" - -#define ION_BIT(nr) (1UL << (nr)) - -enum msm_ion_heap_types { - ION_HEAP_TYPE_MSM_START = ION_HEAP_TYPE_CUSTOM + 1, - ION_HEAP_TYPE_SECURE_DMA = ION_HEAP_TYPE_MSM_START, - ION_HEAP_TYPE_SYSTEM_SECURE, - ION_HEAP_TYPE_HYP_CMA, - ION_HEAP_TYPE_SECURE_CARVEOUT, - /* - * if you add a heap type here you should also add it to - * heap_types_info[] in msm_ion.c - */ -}; - -/** - * These are the only ids that should be used for Ion heap ids. - * The ids listed are the order in which allocation will be attempted - * if specified. Don't swap the order of heap ids unless you know what - * you are doing! - * Id's are spaced by purpose to allow new Id's to be inserted in-between (for - * possible fallbacks) - */ - -enum ion_heap_ids { - INVALID_HEAP_ID = -1, - ION_CP_MM_HEAP_ID = 8, - ION_SECURE_HEAP_ID = 9, - ION_SECURE_DISPLAY_HEAP_ID = 10, - ION_CP_MFC_HEAP_ID = 12, - ION_SPSS_HEAP_ID = 13, /* Secure Processor ION heap */ - ION_SECURE_CARVEOUT_HEAP_ID = 14, - ION_CP_WB_HEAP_ID = 16, /* 8660 only */ - ION_QSECOM_TA_HEAP_ID = 19, - ION_CAMERA_HEAP_ID = 20, /* 8660 only */ - ION_SYSTEM_CONTIG_HEAP_ID = 21, - ION_ADSP_HEAP_ID = 22, - ION_PIL1_HEAP_ID = 23, /* Currently used for other PIL images */ - ION_SF_HEAP_ID = 24, - ION_SYSTEM_HEAP_ID = 25, - ION_PIL2_HEAP_ID = 26, /* Currently used for modem firmware images */ - ION_QSECOM_HEAP_ID = 27, - ION_AUDIO_HEAP_ID = 28, - - ION_MM_FIRMWARE_HEAP_ID = 29, - ION_GOOGLE_HEAP_ID = 30, - - ION_HEAP_ID_RESERVED = 31 /** Bit reserved for ION_FLAG_SECURE flag */ -}; - -/* - * The IOMMU heap is deprecated! Here are some aliases for backwards - * compatibility: - */ -#define ION_IOMMU_HEAP_ID ION_SYSTEM_HEAP_ID -#define ION_HEAP_TYPE_IOMMU ION_HEAP_TYPE_SYSTEM - -#define ION_SPSS_HEAP_ID ION_SPSS_HEAP_ID - -enum ion_fixed_position { - NOT_FIXED, - FIXED_LOW, - FIXED_MIDDLE, - FIXED_HIGH, -}; - -enum cp_mem_usage { - VIDEO_BITSTREAM = 0x1, - VIDEO_PIXEL = 0x2, - VIDEO_NONPIXEL = 0x3, - DISPLAY_SECURE_CP_USAGE = 0x4, - CAMERA_SECURE_CP_USAGE = 0x5, - MAX_USAGE = 0x6, - UNKNOWN = 0x7FFFFFFF, -}; - -/** - * Flags to be used when allocating from the secure heap for - * content protection - */ -#define ION_FLAG_CP_TOUCH ION_BIT(17) -#define ION_FLAG_CP_BITSTREAM ION_BIT(18) -#define ION_FLAG_CP_PIXEL ION_BIT(19) -#define ION_FLAG_CP_NON_PIXEL ION_BIT(20) -#define ION_FLAG_CP_CAMERA ION_BIT(21) -#define ION_FLAG_CP_HLOS ION_BIT(22) -#define ION_FLAG_CP_SPSS_SP ION_BIT(23) -#define ION_FLAG_CP_SPSS_SP_SHARED ION_BIT(24) -#define ION_FLAG_CP_SEC_DISPLAY ION_BIT(25) -#define ION_FLAG_CP_APP ION_BIT(26) -#define ION_FLAG_CP_CAMERA_PREVIEW ION_BIT(27) -/* ION_FLAG_ALLOW_NON_CONTIG uses ION_BIT(28) */ -#define ION_FLAG_CP_CDSP ION_BIT(29) -#define ION_FLAG_CP_SPSS_HLOS_SHARED ION_BIT(30) - -/** - * Flag to allow non continguous allocation of memory from secure - * heap - */ -#define ION_FLAG_ALLOW_NON_CONTIG ION_BIT(28) - -/** - * Flag to use when allocating to indicate that a heap is secure. - * Do NOT use BIT macro since it is defined in #ifdef __KERNEL__ - */ -#define ION_FLAG_SECURE ION_BIT(ION_HEAP_ID_RESERVED) - -/* - * Used in conjunction with heap which pool memory to force an allocation - * to come from the page allocator directly instead of from the pool allocation - */ -#define ION_FLAG_POOL_FORCE_ALLOC ION_BIT(16) - -/** - * Deprecated! Please use the corresponding ION_FLAG_* - */ -#define ION_SECURE ION_FLAG_SECURE - -/** - * Macro should be used with ion_heap_ids defined above. - */ -#define ION_HEAP(bit) ION_BIT(bit) - -#define ION_ADSP_HEAP_NAME "adsp" -#define ION_SYSTEM_HEAP_NAME "system" -#define ION_VMALLOC_HEAP_NAME ION_SYSTEM_HEAP_NAME -#define ION_KMALLOC_HEAP_NAME "kmalloc" -#define ION_AUDIO_HEAP_NAME "audio" -#define ION_SF_HEAP_NAME "sf" -#define ION_MM_HEAP_NAME "mm" -#define ION_CAMERA_HEAP_NAME "camera_preview" -#define ION_IOMMU_HEAP_NAME "iommu" -#define ION_MFC_HEAP_NAME "mfc" -#define ION_SPSS_HEAP_NAME "spss" -#define ION_SECURE_CARVEOUT_HEAP_NAME "secure_carveout" -#define ION_WB_HEAP_NAME "wb" -#define ION_MM_FIRMWARE_HEAP_NAME "mm_fw" -#define ION_GOOGLE_HEAP_NAME "easel_mem" -#define ION_PIL1_HEAP_NAME "pil_1" -#define ION_PIL2_HEAP_NAME "pil_2" -#define ION_QSECOM_HEAP_NAME "qsecom" -#define ION_QSECOM_TA_HEAP_NAME "qsecom_ta" -#define ION_SECURE_HEAP_NAME "secure_heap" -#define ION_SECURE_DISPLAY_HEAP_NAME "secure_display" - -#define ION_SET_CACHED(__cache) ((__cache) | ION_FLAG_CACHED) -#define ION_SET_UNCACHED(__cache) ((__cache) & ~ION_FLAG_CACHED) - -#define ION_IS_CACHED(__flags) ((__flags) & ION_FLAG_CACHED) - -/* struct ion_flush_data - data passed to ion for flushing caches - * - * @handle: handle with data to flush - * @fd: fd to flush - * @vaddr: userspace virtual address mapped with mmap - * @offset: offset into the handle to flush - * @length: length of handle to flush - * - * Performs cache operations on the handle. If p is the start address - * of the handle, p + offset through p + offset + length will have - * the cache operations performed - */ -struct ion_flush_data { - ion_user_handle_t handle; - int fd; - void *vaddr; - unsigned int offset; - unsigned int length; -}; - -struct ion_prefetch_regions { - unsigned int vmid; - size_t *sizes; - unsigned int nr_sizes; -}; - -struct ion_prefetch_data { - int heap_id; - unsigned long len; - struct ion_prefetch_regions *regions; - unsigned int nr_regions; -}; - -#define ION_IOC_MSM_MAGIC 'M' - -/** - * DOC: ION_IOC_CLEAN_CACHES - clean the caches - * - * Clean the caches of the handle specified. - */ -#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MSM_MAGIC, 0, \ - struct ion_flush_data) -/** - * DOC: ION_IOC_INV_CACHES - invalidate the caches - * - * Invalidate the caches of the handle specified. - */ -#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 1, \ - struct ion_flush_data) -/** - * DOC: ION_IOC_CLEAN_INV_CACHES - clean and invalidate the caches - * - * Clean and invalidate the caches of the handle specified. - */ -#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 2, \ - struct ion_flush_data) - -#define ION_IOC_PREFETCH _IOWR(ION_IOC_MSM_MAGIC, 3, \ - struct ion_prefetch_data) - -#define ION_IOC_DRAIN _IOWR(ION_IOC_MSM_MAGIC, 4, \ - struct ion_prefetch_data) - -#endif diff --git a/sdm710/original-kernel-headers/linux/msm_ipa.h b/sdm710/original-kernel-headers/linux/msm_ipa.h deleted file mode 100644 index 123bfca7..00000000 --- a/sdm710/original-kernel-headers/linux/msm_ipa.h +++ /dev/null @@ -1,2196 +0,0 @@ -#ifndef _MSM_IPA_H_ -#define _MSM_IPA_H_ - -#include <stdint.h> -#include <stddef.h> -#include <sys/stat.h> -#include <linux/ioctl.h> -#include <linux/types.h> -#include <linux/if_ether.h> - -/** - * unique magic number of the IPA device - */ -#define IPA_IOC_MAGIC 0xCF - -/** - * IPA device full path - */ -#define IPA_DEV_NAME "/dev/ipa" - -/** - * IPA NAT table character device name - */ -#define IPA_NAT_DEV_NAME "ipaNatTable" - -/** - * IPA IPv6CT table character device name - */ -#define IPA_IPV6CT_DEV_NAME "ipaIpv6CTTable" - - /** - * name of the default routing tables for v4 and v6 - */ -#define IPA_DFLT_RT_TBL_NAME "ipa_dflt_rt" - -/** - * commands supported by IPA driver - */ -#define IPA_IOCTL_ADD_HDR 0 -#define IPA_IOCTL_DEL_HDR 1 -#define IPA_IOCTL_ADD_RT_RULE 2 -#define IPA_IOCTL_DEL_RT_RULE 3 -#define IPA_IOCTL_ADD_FLT_RULE 4 -#define IPA_IOCTL_DEL_FLT_RULE 5 -#define IPA_IOCTL_COMMIT_HDR 6 -#define IPA_IOCTL_RESET_HDR 7 -#define IPA_IOCTL_COMMIT_RT 8 -#define IPA_IOCTL_RESET_RT 9 -#define IPA_IOCTL_COMMIT_FLT 10 -#define IPA_IOCTL_RESET_FLT 11 -#define IPA_IOCTL_DUMP 12 -#define IPA_IOCTL_GET_RT_TBL 13 -#define IPA_IOCTL_PUT_RT_TBL 14 -#define IPA_IOCTL_COPY_HDR 15 -#define IPA_IOCTL_QUERY_INTF 16 -#define IPA_IOCTL_QUERY_INTF_TX_PROPS 17 -#define IPA_IOCTL_QUERY_INTF_RX_PROPS 18 -#define IPA_IOCTL_GET_HDR 19 -#define IPA_IOCTL_PUT_HDR 20 -#define IPA_IOCTL_SET_FLT 21 -#define IPA_IOCTL_ALLOC_NAT_MEM 22 -#define IPA_IOCTL_V4_INIT_NAT 23 -#define IPA_IOCTL_TABLE_DMA_CMD 24 -#define IPA_IOCTL_NAT_DMA IPA_IOCTL_TABLE_DMA_CMD -#define IPA_IOCTL_INIT_IPV6CT_TABLE 25 -#define IPA_IOCTL_V4_DEL_NAT 26 -#define IPA_IOCTL_PULL_MSG 27 -#define IPA_IOCTL_GET_NAT_OFFSET 28 -#define IPA_IOCTL_RM_ADD_DEPENDENCY 29 -#define IPA_IOCTL_RM_DEL_DEPENDENCY 30 -#define IPA_IOCTL_GENERATE_FLT_EQ 31 -#define IPA_IOCTL_QUERY_INTF_EXT_PROPS 32 -#define IPA_IOCTL_QUERY_EP_MAPPING 33 -#define IPA_IOCTL_QUERY_RT_TBL_INDEX 34 -#define IPA_IOCTL_WRITE_QMAPID 35 -#define IPA_IOCTL_MDFY_FLT_RULE 36 -#define IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_ADD 37 -#define IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_DEL 38 -#define IPA_IOCTL_NOTIFY_WAN_EMBMS_CONNECTED 39 -#define IPA_IOCTL_ADD_HDR_PROC_CTX 40 -#define IPA_IOCTL_DEL_HDR_PROC_CTX 41 -#define IPA_IOCTL_MDFY_RT_RULE 42 -#define IPA_IOCTL_ADD_RT_RULE_AFTER 43 -#define IPA_IOCTL_ADD_FLT_RULE_AFTER 44 -#define IPA_IOCTL_GET_HW_VERSION 45 -#define IPA_IOCTL_ADD_RT_RULE_EXT 46 -#define IPA_IOCTL_ADD_VLAN_IFACE 47 -#define IPA_IOCTL_DEL_VLAN_IFACE 48 -#define IPA_IOCTL_ADD_L2TP_VLAN_MAPPING 49 -#define IPA_IOCTL_DEL_L2TP_VLAN_MAPPING 50 -#define IPA_IOCTL_NAT_MODIFY_PDN 51 -#define IPA_IOCTL_ALLOC_NAT_TABLE 52 -#define IPA_IOCTL_ALLOC_IPV6CT_TABLE 53 -#define IPA_IOCTL_DEL_NAT_TABLE 54 -#define IPA_IOCTL_DEL_IPV6CT_TABLE 55 -#define IPA_IOCTL_CLEANUP 56 -#define IPA_IOCTL_QUERY_WLAN_CLIENT 57 -#define IPA_IOCTL_GET_VLAN_MODE 58 - -/** - * max size of the header to be inserted - */ -#define IPA_HDR_MAX_SIZE 64 - -/** - * max size of the name of the resource (routing table, header) - */ -#define IPA_RESOURCE_NAME_MAX 32 - -/** - * max number of interface properties - */ -#define IPA_NUM_PROPS_MAX 35 - -/** - * size of the mac address - */ -#define IPA_MAC_ADDR_SIZE 6 - -/** - * max number of mbim streams - */ -#define IPA_MBIM_MAX_STREAM_NUM 8 - -/** - * size of the ipv6 address - */ -#define IPA_WAN_MSG_IPv6_ADDR_GW_LEN 4 - -/** - * max number of lan clients supported per device type - * for LAN stats via HW. - */ -#define IPA_MAX_NUM_HW_PATH_CLIENTS 16 - -/** - * max number of destination pipes possible for a client. - */ -#define QMI_IPA_MAX_CLIENT_DST_PIPES 4 - -/** - * the attributes of the rule (routing or filtering) - */ -#define IPA_FLT_TOS (1ul << 0) -#define IPA_FLT_PROTOCOL (1ul << 1) -#define IPA_FLT_SRC_ADDR (1ul << 2) -#define IPA_FLT_DST_ADDR (1ul << 3) -#define IPA_FLT_SRC_PORT_RANGE (1ul << 4) -#define IPA_FLT_DST_PORT_RANGE (1ul << 5) -#define IPA_FLT_TYPE (1ul << 6) -#define IPA_FLT_CODE (1ul << 7) -#define IPA_FLT_SPI (1ul << 8) -#define IPA_FLT_SRC_PORT (1ul << 9) -#define IPA_FLT_DST_PORT (1ul << 10) -#define IPA_FLT_TC (1ul << 11) -#define IPA_FLT_FLOW_LABEL (1ul << 12) -#define IPA_FLT_NEXT_HDR (1ul << 13) -#define IPA_FLT_META_DATA (1ul << 14) -#define IPA_FLT_FRAGMENT (1ul << 15) -#define IPA_FLT_TOS_MASKED (1ul << 16) -#define IPA_FLT_MAC_SRC_ADDR_ETHER_II (1ul << 17) -#define IPA_FLT_MAC_DST_ADDR_ETHER_II (1ul << 18) -#define IPA_FLT_MAC_SRC_ADDR_802_3 (1ul << 19) -#define IPA_FLT_MAC_DST_ADDR_802_3 (1ul << 20) -#define IPA_FLT_MAC_ETHER_TYPE (1ul << 21) -#define IPA_FLT_MAC_DST_ADDR_L2TP (1ul << 22) -#define IPA_FLT_TCP_SYN (1ul << 23) -#define IPA_FLT_TCP_SYN_L2TP (1ul << 24) -#define IPA_FLT_L2TP_INNER_IP_TYPE (1ul << 25) -#define IPA_FLT_L2TP_INNER_IPV4_DST_ADDR (1ul << 26) - -/** - * maximal number of NAT PDNs in the PDN config table - */ -#define IPA_MAX_PDN_NUM 5 - -/** - * enum ipa_client_type - names for the various IPA "clients" - * these are from the perspective of the clients, for e.g. - * HSIC1_PROD means HSIC client is the producer and IPA is the - * consumer. - * PROD clients are always even, and CONS clients are always odd. - * Add new clients in the end of the list and update IPA_CLIENT_MAX - */ -enum ipa_client_type { - IPA_CLIENT_HSIC1_PROD = 0, - IPA_CLIENT_HSIC1_CONS = 1, - - IPA_CLIENT_HSIC2_PROD = 2, - IPA_CLIENT_HSIC2_CONS = 3, - - IPA_CLIENT_HSIC3_PROD = 4, - IPA_CLIENT_HSIC3_CONS = 5, - - IPA_CLIENT_HSIC4_PROD = 6, - IPA_CLIENT_HSIC4_CONS = 7, - - IPA_CLIENT_HSIC5_PROD = 8, - IPA_CLIENT_HSIC5_CONS = 9, - - IPA_CLIENT_WLAN1_PROD = 10, - IPA_CLIENT_WLAN1_CONS = 11, - - IPA_CLIENT_A5_WLAN_AMPDU_PROD = 12, - IPA_CLIENT_WLAN2_CONS = 13, - - /* RESERVERD PROD = 14, */ - IPA_CLIENT_WLAN3_CONS = 15, - - /* RESERVERD PROD = 16, */ - IPA_CLIENT_WLAN4_CONS = 17, - - IPA_CLIENT_USB_PROD = 18, - IPA_CLIENT_USB_CONS = 19, - - IPA_CLIENT_USB2_PROD = 20, - IPA_CLIENT_USB2_CONS = 21, - - IPA_CLIENT_USB3_PROD = 22, - IPA_CLIENT_USB3_CONS = 23, - - IPA_CLIENT_USB4_PROD = 24, - IPA_CLIENT_USB4_CONS = 25, - - IPA_CLIENT_UC_USB_PROD = 26, - IPA_CLIENT_USB_DPL_CONS = 27, - - IPA_CLIENT_A2_EMBEDDED_PROD = 28, - IPA_CLIENT_A2_EMBEDDED_CONS = 29, - - IPA_CLIENT_A2_TETHERED_PROD = 30, - IPA_CLIENT_A2_TETHERED_CONS = 31, - - IPA_CLIENT_APPS_LAN_PROD = 32, - IPA_CLIENT_APPS_LAN_CONS = 33, - - IPA_CLIENT_APPS_WAN_PROD = 34, - IPA_CLIENT_APPS_LAN_WAN_PROD = IPA_CLIENT_APPS_WAN_PROD, - IPA_CLIENT_APPS_WAN_CONS = 35, - - IPA_CLIENT_APPS_CMD_PROD = 36, - IPA_CLIENT_A5_LAN_WAN_CONS = 37, - - IPA_CLIENT_ODU_PROD = 38, - IPA_CLIENT_ODU_EMB_CONS = 39, - - /* RESERVERD PROD = 40, */ - IPA_CLIENT_ODU_TETH_CONS = 41, - - IPA_CLIENT_MHI_PROD = 42, - IPA_CLIENT_MHI_CONS = 43, - - IPA_CLIENT_MEMCPY_DMA_SYNC_PROD = 44, - IPA_CLIENT_MEMCPY_DMA_SYNC_CONS = 45, - - IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD = 46, - IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS = 47, - - IPA_CLIENT_ETHERNET_PROD = 48, - IPA_CLIENT_ETHERNET_CONS = 49, - - IPA_CLIENT_Q6_LAN_PROD = 50, - IPA_CLIENT_Q6_LAN_CONS = 51, - - IPA_CLIENT_Q6_WAN_PROD = 52, - IPA_CLIENT_Q6_WAN_CONS = 53, - - IPA_CLIENT_Q6_CMD_PROD = 54, - IPA_CLIENT_Q6_DUN_CONS = 55, - - IPA_CLIENT_Q6_DECOMP_PROD = 56, - IPA_CLIENT_Q6_DECOMP_CONS = 57, - - IPA_CLIENT_Q6_DECOMP2_PROD = 58, - IPA_CLIENT_Q6_DECOMP2_CONS = 59, - - /* RESERVERD PROD = 60, */ - IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS = 61, - - IPA_CLIENT_TEST_PROD = 62, - IPA_CLIENT_TEST_CONS = 63, - - IPA_CLIENT_TEST1_PROD = 64, - IPA_CLIENT_TEST1_CONS = 65, - - IPA_CLIENT_TEST2_PROD = 66, - IPA_CLIENT_TEST2_CONS = 67, - - IPA_CLIENT_TEST3_PROD = 68, - IPA_CLIENT_TEST3_CONS = 69, - - IPA_CLIENT_TEST4_PROD = 70, - IPA_CLIENT_TEST4_CONS = 71, - - /* RESERVERD PROD = 72, */ - IPA_CLIENT_DUMMY_CONS = 73 -}; - -#define IPA_CLIENT_MAX (IPA_CLIENT_DUMMY_CONS + 1) - -#define IPA_CLIENT_IS_APPS_CONS(client) \ - ((client) == IPA_CLIENT_APPS_LAN_CONS || \ - (client) == IPA_CLIENT_APPS_WAN_CONS) - -#define IPA_CLIENT_IS_USB_CONS(client) \ - ((client) == IPA_CLIENT_USB_CONS || \ - (client) == IPA_CLIENT_USB2_CONS || \ - (client) == IPA_CLIENT_USB3_CONS || \ - (client) == IPA_CLIENT_USB_DPL_CONS || \ - (client) == IPA_CLIENT_USB4_CONS) - -#define IPA_CLIENT_IS_WLAN_CONS(client) \ - ((client) == IPA_CLIENT_WLAN1_CONS || \ - (client) == IPA_CLIENT_WLAN2_CONS || \ - (client) == IPA_CLIENT_WLAN3_CONS || \ - (client) == IPA_CLIENT_WLAN4_CONS) - -#define IPA_CLIENT_IS_ODU_CONS(client) \ - ((client) == IPA_CLIENT_ODU_EMB_CONS || \ - (client) == IPA_CLIENT_ODU_TETH_CONS) - -#define IPA_CLIENT_IS_Q6_CONS(client) \ - ((client) == IPA_CLIENT_Q6_LAN_CONS || \ - (client) == IPA_CLIENT_Q6_WAN_CONS || \ - (client) == IPA_CLIENT_Q6_DUN_CONS || \ - (client) == IPA_CLIENT_Q6_DECOMP_CONS || \ - (client) == IPA_CLIENT_Q6_DECOMP2_CONS || \ - (client) == IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS) - -#define IPA_CLIENT_IS_Q6_PROD(client) \ - ((client) == IPA_CLIENT_Q6_LAN_PROD || \ - (client) == IPA_CLIENT_Q6_WAN_PROD || \ - (client) == IPA_CLIENT_Q6_CMD_PROD || \ - (client) == IPA_CLIENT_Q6_DECOMP_PROD || \ - (client) == IPA_CLIENT_Q6_DECOMP2_PROD) - -#define IPA_CLIENT_IS_Q6_NON_ZIP_CONS(client) \ - ((client) == IPA_CLIENT_Q6_LAN_CONS || \ - (client) == IPA_CLIENT_Q6_WAN_CONS || \ - (client) == IPA_CLIENT_Q6_DUN_CONS || \ - (client) == IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS) - -#define IPA_CLIENT_IS_Q6_ZIP_CONS(client) \ - ((client) == IPA_CLIENT_Q6_DECOMP_CONS || \ - (client) == IPA_CLIENT_Q6_DECOMP2_CONS) - -#define IPA_CLIENT_IS_Q6_NON_ZIP_PROD(client) \ - ((client) == IPA_CLIENT_Q6_LAN_PROD || \ - (client) == IPA_CLIENT_Q6_WAN_PROD || \ - (client) == IPA_CLIENT_Q6_CMD_PROD) - -#define IPA_CLIENT_IS_Q6_ZIP_PROD(client) \ - ((client) == IPA_CLIENT_Q6_DECOMP_PROD || \ - (client) == IPA_CLIENT_Q6_DECOMP2_PROD) - -#define IPA_CLIENT_IS_MEMCPY_DMA_CONS(client) \ - ((client) == IPA_CLIENT_MEMCPY_DMA_SYNC_CONS || \ - (client) == IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS) - -#define IPA_CLIENT_IS_MEMCPY_DMA_PROD(client) \ - ((client) == IPA_CLIENT_MEMCPY_DMA_SYNC_PROD || \ - (client) == IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD) - -#define IPA_CLIENT_IS_MHI_CONS(client) \ - ((client) == IPA_CLIENT_MHI_CONS) - -#define IPA_CLIENT_IS_MHI(client) \ - ((client) == IPA_CLIENT_MHI_CONS || \ - (client) == IPA_CLIENT_MHI_PROD) - -#define IPA_CLIENT_IS_TEST_PROD(client) \ - ((client) == IPA_CLIENT_TEST_PROD || \ - (client) == IPA_CLIENT_TEST1_PROD || \ - (client) == IPA_CLIENT_TEST2_PROD || \ - (client) == IPA_CLIENT_TEST3_PROD || \ - (client) == IPA_CLIENT_TEST4_PROD) - -#define IPA_CLIENT_IS_TEST_CONS(client) \ - ((client) == IPA_CLIENT_TEST_CONS || \ - (client) == IPA_CLIENT_TEST1_CONS || \ - (client) == IPA_CLIENT_TEST2_CONS || \ - (client) == IPA_CLIENT_TEST3_CONS || \ - (client) == IPA_CLIENT_TEST4_CONS) - -#define IPA_CLIENT_IS_TEST(client) \ - (IPA_CLIENT_IS_TEST_PROD(client) || IPA_CLIENT_IS_TEST_CONS(client)) - -/** - * enum ipa_ip_type - Address family: IPv4 or IPv6 - */ -enum ipa_ip_type { - IPA_IP_v4, - IPA_IP_v6, - IPA_IP_MAX -}; - -/** - * enum ipa_rule_type - Type of routing or filtering rule - * Hashable: Rule will be located at the hashable tables - * Non_Hashable: Rule will be located at the non-hashable tables - */ -enum ipa_rule_type { - IPA_RULE_HASHABLE, - IPA_RULE_NON_HASHABLE, -}; -#define IPA_RULE_TYPE_MAX (IPA_RULE_NON_HASHABLE + 1) - -/** - * enum ipa_flt_action - action field of filtering rule - * - * Pass to routing: 5'd0 - * Pass to source NAT: 5'd1 - * Pass to destination NAT: 5'd2 - * Pass to default output pipe (e.g., Apps or Modem): 5'd3 - */ -enum ipa_flt_action { - IPA_PASS_TO_ROUTING, - IPA_PASS_TO_SRC_NAT, - IPA_PASS_TO_DST_NAT, - IPA_PASS_TO_EXCEPTION -}; - -/** - * enum ipa_wlan_event - Events for wlan client - * - * wlan client connect: New wlan client connected - * wlan client disconnect: wlan client disconnected - * wlan client power save: wlan client moved to power save - * wlan client normal: wlan client moved out of power save - * sw routing enable: ipa routing is disabled - * sw routing disable: ipa routing is enabled - * wlan ap connect: wlan AP(access point) is up - * wlan ap disconnect: wlan AP(access point) is down - * wlan sta connect: wlan STA(station) is up - * wlan sta disconnect: wlan STA(station) is down - * wlan client connect ex: new wlan client connected - * wlan scc switch: wlan interfaces in scc mode - * wlan mcc switch: wlan interfaces in mcc mode - * wlan wdi enable: wdi data path completed - * wlan wdi disable: wdi data path teardown - */ -enum ipa_wlan_event { - WLAN_CLIENT_CONNECT, - WLAN_CLIENT_DISCONNECT, - WLAN_CLIENT_POWER_SAVE_MODE, - WLAN_CLIENT_NORMAL_MODE, - SW_ROUTING_ENABLE, - SW_ROUTING_DISABLE, - WLAN_AP_CONNECT, - WLAN_AP_DISCONNECT, - WLAN_STA_CONNECT, - WLAN_STA_DISCONNECT, - WLAN_CLIENT_CONNECT_EX, - WLAN_SWITCH_TO_SCC, - WLAN_SWITCH_TO_MCC, - WLAN_WDI_ENABLE, - WLAN_WDI_DISABLE, - IPA_WLAN_EVENT_MAX -}; - -/** - * enum ipa_wan_event - Events for wan client - * - * wan default route add/del - * wan embms connect: New wan embms interface connected - */ -enum ipa_wan_event { - WAN_UPSTREAM_ROUTE_ADD = IPA_WLAN_EVENT_MAX, - WAN_UPSTREAM_ROUTE_DEL, - WAN_EMBMS_CONNECT, - WAN_XLAT_CONNECT, - IPA_WAN_EVENT_MAX -}; - -enum ipa_ecm_event { - ECM_CONNECT = IPA_WAN_EVENT_MAX, - ECM_DISCONNECT, - IPA_ECM_EVENT_MAX, -}; - -enum ipa_tethering_stats_event { - IPA_TETHERING_STATS_UPDATE_STATS = IPA_ECM_EVENT_MAX, - IPA_TETHERING_STATS_UPDATE_NETWORK_STATS, - IPA_TETHERING_STATS_EVENT_MAX, -}; - - -enum ipa_quota_event { - IPA_QUOTA_REACH = IPA_TETHERING_STATS_EVENT_MAX, - IPA_QUOTA_EVENT_MAX, -}; - -enum ipa_ssr_event { - IPA_SSR_BEFORE_SHUTDOWN = IPA_QUOTA_EVENT_MAX, - IPA_SSR_AFTER_POWERUP, - IPA_SSR_EVENT_MAX -}; - -enum ipa_vlan_l2tp_event { - ADD_VLAN_IFACE = IPA_SSR_EVENT_MAX, - DEL_VLAN_IFACE, - ADD_L2TP_VLAN_MAPPING, - DEL_L2TP_VLAN_MAPPING, - IPA_VLAN_L2TP_EVENT_MAX, -}; - -enum ipa_per_client_stats_event { - IPA_PER_CLIENT_STATS_CONNECT_EVENT = IPA_VLAN_L2TP_EVENT_MAX, - IPA_PER_CLIENT_STATS_DISCONNECT_EVENT, - IPA_PER_CLIENT_STATS_EVENT_MAX -}; - -enum ipa_wlan_fw_ssr_event { - WLAN_FWR_SSR_BEFORE_SHUTDOWN = IPA_PER_CLIENT_STATS_EVENT_MAX, - IPA_WLAN_FW_SSR_EVENT_MAX, -#define IPA_WLAN_FW_SSR_EVENT_MAX IPA_WLAN_FW_SSR_EVENT_MAX -}; - -#define IPA_EVENT_MAX_NUM (IPA_WLAN_FW_SSR_EVENT_MAX) -#define IPA_EVENT_MAX ((int)IPA_EVENT_MAX_NUM) - -/** - * enum ipa_rm_resource_name - IPA RM clients identification names - * - * PROD resources are always even, and CONS resources are always odd. - * Add new clients in the end of the list and update IPA_RM_RESOURCE_MAX - */ -enum ipa_rm_resource_name { - IPA_RM_RESOURCE_Q6_PROD = 0, - IPA_RM_RESOURCE_Q6_CONS = 1, - - IPA_RM_RESOURCE_USB_PROD = 2, - IPA_RM_RESOURCE_USB_CONS = 3, - - IPA_RM_RESOURCE_USB_DPL_DUMMY_PROD = 4, - IPA_RM_RESOURCE_USB_DPL_CONS = 5, - - IPA_RM_RESOURCE_HSIC_PROD = 6, - IPA_RM_RESOURCE_HSIC_CONS = 7, - - IPA_RM_RESOURCE_STD_ECM_PROD = 8, - IPA_RM_RESOURCE_APPS_CONS = 9, - - IPA_RM_RESOURCE_RNDIS_PROD = 10, - /* RESERVED CONS = 11, */ - - IPA_RM_RESOURCE_WWAN_0_PROD = 12, - /* RESERVED CONS = 13, */ - - IPA_RM_RESOURCE_WLAN_PROD = 14, - IPA_RM_RESOURCE_WLAN_CONS = 15, - - IPA_RM_RESOURCE_ODU_ADAPT_PROD = 16, - IPA_RM_RESOURCE_ODU_ADAPT_CONS = 17, - - IPA_RM_RESOURCE_MHI_PROD = 18, - IPA_RM_RESOURCE_MHI_CONS = 19, - - IPA_RM_RESOURCE_ETHERNET_PROD = 20, - IPA_RM_RESOURCE_ETHERNET_CONS = 21, -}; -#define IPA_RM_RESOURCE_MAX (IPA_RM_RESOURCE_ETHERNET_CONS + 1) - -/** - * enum ipa_hw_type - IPA hardware version type - * @IPA_HW_None: IPA hardware version not defined - * @IPA_HW_v1_0: IPA hardware version 1.0 - * @IPA_HW_v1_1: IPA hardware version 1.1 - * @IPA_HW_v2_0: IPA hardware version 2.0 - * @IPA_HW_v2_1: IPA hardware version 2.1 - * @IPA_HW_v2_5: IPA hardware version 2.5 - * @IPA_HW_v2_6: IPA hardware version 2.6 - * @IPA_HW_v2_6L: IPA hardware version 2.6L - * @IPA_HW_v3_0: IPA hardware version 3.0 - * @IPA_HW_v3_1: IPA hardware version 3.1 - * @IPA_HW_v3_5: IPA hardware version 3.5 - * @IPA_HW_v3_5_1: IPA hardware version 3.5.1 - * @IPA_HW_v4_0: IPA hardware version 4.0 - */ -enum ipa_hw_type { - IPA_HW_None = 0, - IPA_HW_v1_0 = 1, - IPA_HW_v1_1 = 2, - IPA_HW_v2_0 = 3, - IPA_HW_v2_1 = 4, - IPA_HW_v2_5 = 5, - IPA_HW_v2_6 = IPA_HW_v2_5, - IPA_HW_v2_6L = 6, - IPA_HW_v3_0 = 10, - IPA_HW_v3_1 = 11, - IPA_HW_v3_5 = 12, - IPA_HW_v3_5_1 = 13, - IPA_HW_v4_0 = 14, -}; -#define IPA_HW_MAX (IPA_HW_v4_0 + 1) - -#define IPA_HW_v4_0 IPA_HW_v4_0 - -/** - * struct ipa_rule_attrib - attributes of a routing/filtering - * rule, all in LE - * @attrib_mask: what attributes are valid - * @src_port_lo: low port of src port range - * @src_port_hi: high port of src port range - * @dst_port_lo: low port of dst port range - * @dst_port_hi: high port of dst port range - * @type: ICMP/IGMP type - * @code: ICMP/IGMP code - * @spi: IPSec SPI - * @src_port: exact src port - * @dst_port: exact dst port - * @meta_data: meta-data val - * @meta_data_mask: meta-data mask - * @u.v4.tos: type of service - * @u.v4.protocol: protocol - * @u.v4.src_addr: src address value - * @u.v4.src_addr_mask: src address mask - * @u.v4.dst_addr: dst address value - * @u.v4.dst_addr_mask: dst address mask - * @u.v6.tc: traffic class - * @u.v6.flow_label: flow label - * @u.v6.next_hdr: next header - * @u.v6.src_addr: src address val - * @u.v6.src_addr_mask: src address mask - * @u.v6.dst_addr: dst address val - * @u.v6.dst_addr_mask: dst address mask - */ -struct ipa_rule_attrib { - uint32_t attrib_mask; - uint16_t src_port_lo; - uint16_t src_port_hi; - uint16_t dst_port_lo; - uint16_t dst_port_hi; - uint8_t type; - uint8_t code; - uint8_t tos_value; - uint8_t tos_mask; - uint32_t spi; - uint16_t src_port; - uint16_t dst_port; - uint32_t meta_data; - uint32_t meta_data_mask; - uint8_t src_mac_addr[ETH_ALEN]; - uint8_t src_mac_addr_mask[ETH_ALEN]; - uint8_t dst_mac_addr[ETH_ALEN]; - uint8_t dst_mac_addr_mask[ETH_ALEN]; - uint16_t ether_type; - union { - struct { - uint8_t tos; - uint8_t protocol; - uint32_t src_addr; - uint32_t src_addr_mask; - uint32_t dst_addr; - uint32_t dst_addr_mask; - } v4; - struct { - uint8_t tc; - uint32_t flow_label; - uint8_t next_hdr; - uint32_t src_addr[4]; - uint32_t src_addr_mask[4]; - uint32_t dst_addr[4]; - uint32_t dst_addr_mask[4]; - } v6; - } u; -}; - -/*! @brief The maximum number of Mask Equal 32 Eqns */ -#define IPA_IPFLTR_NUM_MEQ_32_EQNS 2 - -/*! @brief The maximum number of IHL offset Mask Equal 32 Eqns */ -#define IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS 2 - -/*! @brief The maximum number of Mask Equal 128 Eqns */ -#define IPA_IPFLTR_NUM_MEQ_128_EQNS 2 - -/*! @brief The maximum number of IHL offset Range Check 16 Eqns */ -#define IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS 2 - -/*! @brief Offset and 16 bit comparison equation */ -struct ipa_ipfltr_eq_16 { - int8_t offset; - uint16_t value; -}; - -/*! @brief Offset and 32 bit comparison equation */ -struct ipa_ipfltr_eq_32 { - int8_t offset; - uint32_t value; -}; - -/*! @brief Offset and 128 bit masked comparison equation */ -struct ipa_ipfltr_mask_eq_128 { - int8_t offset; - uint8_t mask[16]; - uint8_t value[16]; -}; - -/*! @brief Offset and 32 bit masked comparison equation */ -struct ipa_ipfltr_mask_eq_32 { - int8_t offset; - uint32_t mask; - uint32_t value; -}; - -/*! @brief Equation for identifying a range. Ranges are inclusive */ -struct ipa_ipfltr_range_eq_16 { - int8_t offset; - uint16_t range_low; - uint16_t range_high; -}; - -/*! @brief Rule equations which are set according to DS filter installation */ -struct ipa_ipfltri_rule_eq { - /*! 16-bit Bitmask to indicate how many eqs are valid in this rule */ - uint16_t rule_eq_bitmap; - /*! Specifies if a type of service check rule is present */ - uint8_t tos_eq_present; - /*! The value to check against the type of service (ipv4) field */ - uint8_t tos_eq; - /*! Specifies if a protocol check rule is present */ - uint8_t protocol_eq_present; - /*! The value to check against the protocol (ipv6) field */ - uint8_t protocol_eq; - /*! The number of ip header length offset 16 bit range check - * rules in this rule - */ - uint8_t num_ihl_offset_range_16; - /*! An array of the registered ip header length offset 16 bit - * range check rules - */ - struct ipa_ipfltr_range_eq_16 - ihl_offset_range_16[IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS]; - /*! The number of mask equal 32 rules present in this rule */ - uint8_t num_offset_meq_32; - /*! An array of all the possible mask equal 32 rules in this rule */ - struct ipa_ipfltr_mask_eq_32 - offset_meq_32[IPA_IPFLTR_NUM_MEQ_32_EQNS]; - /*! Specifies if the traffic class rule is present in this rule */ - uint8_t tc_eq_present; - /*! The value to check the traffic class (ipv4) field against */ - uint8_t tc_eq; - /*! Specifies if the flow equals rule is present in this rule */ - uint8_t fl_eq_present; - /*! The value to check the flow (ipv6) field against */ - uint32_t fl_eq; - /*! The number of ip header length offset 16 bit equations in this - * rule - */ - uint8_t ihl_offset_eq_16_present; - /*! The ip header length offset 16 bit equation */ - struct ipa_ipfltr_eq_16 ihl_offset_eq_16; - /*! The number of ip header length offset 32 bit equations in this - * rule - */ - uint8_t ihl_offset_eq_32_present; - /*! The ip header length offset 32 bit equation */ - struct ipa_ipfltr_eq_32 ihl_offset_eq_32; - /*! The number of ip header length offset 32 bit mask equations in - * this rule - */ - uint8_t num_ihl_offset_meq_32; - /*! The ip header length offset 32 bit mask equation */ - struct ipa_ipfltr_mask_eq_32 - ihl_offset_meq_32[IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS]; - /*! The number of ip header length offset 128 bit equations in this - * rule - */ - uint8_t num_offset_meq_128; - /*! The ip header length offset 128 bit equation */ - struct ipa_ipfltr_mask_eq_128 - offset_meq_128[IPA_IPFLTR_NUM_MEQ_128_EQNS]; - /*! The metadata 32 bit masked comparison equation present or not */ - /* Metadata based rules are added internally by IPA driver */ - uint8_t metadata_meq32_present; - /*! The metadata 32 bit masked comparison equation */ - struct ipa_ipfltr_mask_eq_32 metadata_meq32; - /*! Specifies if the Fragment equation is present in this rule */ - uint8_t ipv4_frag_eq_present; -}; - -/** - * struct ipa_flt_rule - attributes of a filtering rule - * @retain_hdr: bool switch to instruct IPA core to add back to the packet - * the header removed as part of header removal - * @to_uc: bool switch to pass packet to micro-controller - * @action: action field - * @rt_tbl_hdl: handle of table from "get" - * @attrib: attributes of the rule - * @eq_attrib: attributes of the rule in equation form (valid when - * eq_attrib_type is true) - * @rt_tbl_idx: index of RT table referred to by filter rule (valid when - * eq_attrib_type is true and non-exception action) - * @eq_attrib_type: true if equation level form used to specify attributes - * @max_prio: bool switch. is this rule with Max priority? meaning on rule hit, - * IPA will use the rule and will not look for other rules that may have - * higher priority - * @hashable: bool switch. is this rule hashable or not? - * ipa uses hashable rules to cache their hit results to be used in - * consecutive packets - * @rule_id: rule_id to be assigned to the filter rule. In case client specifies - * rule_id as 0 the driver will assign a new rule_id - * @set_metadata: bool switch. should metadata replacement at the NAT block - * take place? - * @pdn_idx: if action is "pass to source\destination NAT" then a comparison - * against the PDN index in the matching PDN entry will take place as an - * additional condition for NAT hit. - */ -struct ipa_flt_rule { - uint8_t retain_hdr; - uint8_t to_uc; - enum ipa_flt_action action; - uint32_t rt_tbl_hdl; - struct ipa_rule_attrib attrib; - struct ipa_ipfltri_rule_eq eq_attrib; - uint32_t rt_tbl_idx; - uint8_t eq_attrib_type; - uint8_t max_prio; - uint8_t hashable; - uint16_t rule_id; - uint8_t set_metadata; - uint8_t pdn_idx; -}; - -/** - * enum ipa_hdr_l2_type - L2 header type - * IPA_HDR_L2_NONE: L2 header which isn't Ethernet II and isn't 802_3 - * IPA_HDR_L2_ETHERNET_II: L2 header of type Ethernet II - * IPA_HDR_L2_802_3: L2 header of type 802_3 - * IPA_HDR_L2_802_1Q: L2 header of type 802_1Q - */ -enum ipa_hdr_l2_type { - IPA_HDR_L2_NONE, - IPA_HDR_L2_ETHERNET_II, - IPA_HDR_L2_802_3, - IPA_HDR_L2_802_1Q, -}; -#define IPA_HDR_L2_MAX (IPA_HDR_L2_802_1Q + 1) - -#define IPA_HDR_L2_802_1Q IPA_HDR_L2_802_1Q - -/** - * enum ipa_hdr_l2_type - Processing context type - * IPA_HDR_PROC_NONE: No processing context - * IPA_HDR_PROC_ETHII_TO_ETHII: Process Ethernet II to Ethernet II - * IPA_HDR_PROC_ETHII_TO_802_3: Process Ethernet II to 802_3 - * IPA_HDR_PROC_802_3_TO_ETHII: Process 802_3 to Ethernet II - * IPA_HDR_PROC_802_3_TO_802_3: Process 802_3 to 802_3 - */ -enum ipa_hdr_proc_type { - IPA_HDR_PROC_NONE, - IPA_HDR_PROC_ETHII_TO_ETHII, - IPA_HDR_PROC_ETHII_TO_802_3, - IPA_HDR_PROC_802_3_TO_ETHII, - IPA_HDR_PROC_802_3_TO_802_3, - IPA_HDR_PROC_L2TP_HEADER_ADD, - IPA_HDR_PROC_L2TP_HEADER_REMOVE -}; -#define IPA_HDR_PROC_MAX (IPA_HDR_PROC_L2TP_HEADER_REMOVE + 1) - -/** - * struct ipa_rt_rule - attributes of a routing rule - * @dst: dst "client" - * @hdr_hdl: handle to the dynamic header - it is not an index or an offset - * @hdr_proc_ctx_hdl: handle to header processing context. if it is provided - hdr_hdl shall be 0 - * @attrib: attributes of the rule - * @max_prio: bool switch. is this rule with Max priority? meaning on rule hit, - * IPA will use the rule and will not look for other rules that may have - * higher priority - * @hashable: bool switch. is this rule hashable or not? - * ipa uses hashable rules to cache their hit results to be used in - * consecutive packets - * @retain_hdr: bool switch to instruct IPA core to add back to the packet - * the header removed as part of header removal - */ -struct ipa_rt_rule { - enum ipa_client_type dst; - uint32_t hdr_hdl; - uint32_t hdr_proc_ctx_hdl; - struct ipa_rule_attrib attrib; - uint8_t max_prio; - uint8_t hashable; - uint8_t retain_hdr; -}; - -/** - * struct ipa_hdr_add - header descriptor includes in and out - * parameters - * @name: name of the header - * @hdr: actual header to be inserted - * @hdr_len: size of above header - * @type: l2 header type - * @is_partial: header not fully specified - * @hdr_hdl: out parameter, handle to header, valid when status is 0 - * @status: out parameter, status of header add operation, - * 0 for success, - * -1 for failure - * @is_eth2_ofst_valid: is eth2_ofst field valid? - * @eth2_ofst: offset to start of Ethernet-II/802.3 header - */ -struct ipa_hdr_add { - char name[IPA_RESOURCE_NAME_MAX]; - uint8_t hdr[IPA_HDR_MAX_SIZE]; - uint8_t hdr_len; - enum ipa_hdr_l2_type type; - uint8_t is_partial; - uint32_t hdr_hdl; - int status; - uint8_t is_eth2_ofst_valid; - uint16_t eth2_ofst; -}; - -/** - * struct ipa_ioc_add_hdr - header addition parameters (support - * multiple headers and commit) - * @commit: should headers be written to IPA HW also? - * @num_hdrs: num of headers that follow - * @ipa_hdr_add hdr: all headers need to go here back to - * back, no pointers - */ -struct ipa_ioc_add_hdr { - uint8_t commit; - uint8_t num_hdrs; - struct ipa_hdr_add hdr[0]; -}; - -/** - * struct ipa_l2tp_header_add_procparams - - * @eth_hdr_retained: Specifies if Ethernet header is retained or not - * @input_ip_version: Specifies if Input header is IPV4(0) or IPV6(1) - * @output_ip_version: Specifies if template header is IPV4(0) or IPV6(1) - */ -struct ipa_l2tp_header_add_procparams { - uint32_t eth_hdr_retained:1; - uint32_t input_ip_version:1; - uint32_t output_ip_version:1; - uint32_t reserved:29; -}; - -/** - * struct ipa_l2tp_header_remove_procparams - - * @hdr_len_remove: Specifies how much of the header needs to - be removed in bytes - * @eth_hdr_retained: Specifies if Ethernet header is retained or not - * @hdr_ofst_pkt_size_valid: Specifies if the Header offset is valid - * @hdr_ofst_pkt_size: If hdr_ofst_pkt_size_valid =1, this indicates where the - packet size field (2bytes) resides - * @hdr_endianness: 0:little endian, 1:big endian - */ -struct ipa_l2tp_header_remove_procparams { - uint32_t hdr_len_remove:8; - uint32_t eth_hdr_retained:1; - /* Following fields are valid if eth_hdr_retained =1 ( bridge mode) */ - uint32_t hdr_ofst_pkt_size_valid:1; - uint32_t hdr_ofst_pkt_size:6; - uint32_t hdr_endianness:1; - uint32_t reserved:15; -}; - -/** - * struct ipa_l2tp_hdr_proc_ctx_params - - * @hdr_add_param: parameters for header add - * @hdr_remove_param: parameters for header remove - * @is_dst_pipe_valid: if dst pipe is valid - * @dst_pipe: destination pipe - */ -struct ipa_l2tp_hdr_proc_ctx_params { - struct ipa_l2tp_header_add_procparams hdr_add_param; - struct ipa_l2tp_header_remove_procparams hdr_remove_param; - uint8_t is_dst_pipe_valid; - enum ipa_client_type dst_pipe; -}; - -#define L2TP_USER_SPACE_SPECIFY_DST_PIPE - -/** - * struct ipa_hdr_proc_ctx_add - processing context descriptor includes - * in and out parameters - * @type: processing context type - * @hdr_hdl: in parameter, handle to header - * @l2tp_params: l2tp parameters - * @proc_ctx_hdl: out parameter, handle to proc_ctx, valid when status is 0 - * @status: out parameter, status of header add operation, - * 0 for success, - * -1 for failure - */ -struct ipa_hdr_proc_ctx_add { - enum ipa_hdr_proc_type type; - uint32_t hdr_hdl; - uint32_t proc_ctx_hdl; - int status; - struct ipa_l2tp_hdr_proc_ctx_params l2tp_params; -}; - -#define IPA_L2TP_HDR_PROC_SUPPORT - -/** - * struct ipa_ioc_add_hdr - processing context addition parameters (support - * multiple processing context and commit) - * @commit: should processing context be written to IPA HW also? - * @num_proc_ctxs: num of processing context that follow - * @proc_ctx: all processing context need to go here back to - * back, no pointers - */ -struct ipa_ioc_add_hdr_proc_ctx { - uint8_t commit; - uint8_t num_proc_ctxs; - struct ipa_hdr_proc_ctx_add proc_ctx[0]; -}; - -/** - * struct ipa_ioc_copy_hdr - retrieve a copy of the specified - * header - caller can then derive the complete header - * @name: name of the header resource - * @hdr: out parameter, contents of specified header, - * valid only when ioctl return val is non-negative - * @hdr_len: out parameter, size of above header - * valid only when ioctl return val is non-negative - * @type: l2 header type - * valid only when ioctl return val is non-negative - * @is_partial: out parameter, indicates whether specified header is partial - * valid only when ioctl return val is non-negative - * @is_eth2_ofst_valid: is eth2_ofst field valid? - * @eth2_ofst: offset to start of Ethernet-II/802.3 header - */ -struct ipa_ioc_copy_hdr { - char name[IPA_RESOURCE_NAME_MAX]; - uint8_t hdr[IPA_HDR_MAX_SIZE]; - uint8_t hdr_len; - enum ipa_hdr_l2_type type; - uint8_t is_partial; - uint8_t is_eth2_ofst_valid; - uint16_t eth2_ofst; -}; - -/** - * struct ipa_ioc_get_hdr - header entry lookup parameters, if lookup was - * successful caller must call put to release the reference count when done - * @name: name of the header resource - * @hdl: out parameter, handle of header entry - * valid only when ioctl return val is non-negative - */ -struct ipa_ioc_get_hdr { - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t hdl; -}; - -/** - * struct ipa_hdr_del - header descriptor includes in and out - * parameters - * - * @hdl: handle returned from header add operation - * @status: out parameter, status of header remove operation, - * 0 for success, - * -1 for failure - */ -struct ipa_hdr_del { - uint32_t hdl; - int status; -}; - -/** - * struct ipa_ioc_del_hdr - header deletion parameters (support - * multiple headers and commit) - * @commit: should headers be removed from IPA HW also? - * @num_hdls: num of headers being removed - * @ipa_hdr_del hdl: all handles need to go here back to back, no pointers - */ -struct ipa_ioc_del_hdr { - uint8_t commit; - uint8_t num_hdls; - struct ipa_hdr_del hdl[0]; -}; - -/** - * struct ipa_hdr_proc_ctx_del - processing context descriptor includes - * in and out parameters - * @hdl: handle returned from processing context add operation - * @status: out parameter, status of header remove operation, - * 0 for success, - * -1 for failure - */ -struct ipa_hdr_proc_ctx_del { - uint32_t hdl; - int status; -}; - -/** - * ipa_ioc_del_hdr_proc_ctx - processing context deletion parameters (support - * multiple headers and commit) - * @commit: should processing contexts be removed from IPA HW also? - * @num_hdls: num of processing contexts being removed - * @ipa_hdr_proc_ctx_del hdl: all handles need to go here back to back, - * no pointers - */ -struct ipa_ioc_del_hdr_proc_ctx { - uint8_t commit; - uint8_t num_hdls; - struct ipa_hdr_proc_ctx_del hdl[0]; -}; - -/** - * struct ipa_rt_rule_add - routing rule descriptor includes in - * and out parameters - * @rule: actual rule to be added - * @at_rear: add at back of routing table, it is NOT possible to add rules at - * the rear of the "default" routing tables - * @rt_rule_hdl: output parameter, handle to rule, valid when status is 0 - * @status: output parameter, status of routing rule add operation, - * 0 for success, - * -1 for failure - */ -struct ipa_rt_rule_add { - struct ipa_rt_rule rule; - uint8_t at_rear; - uint32_t rt_rule_hdl; - int status; -}; - -/** - * struct ipa_ioc_add_rt_rule - routing rule addition parameters (supports - * multiple rules and commit); - * - * all rules MUST be added to same table - * @commit: should rules be written to IPA HW also? - * @ip: IP family of rule - * @rt_tbl_name: name of routing table resource - * @num_rules: number of routing rules that follow - * @ipa_rt_rule_add rules: all rules need to go back to back here, no pointers - */ -struct ipa_ioc_add_rt_rule { - uint8_t commit; - enum ipa_ip_type ip; - char rt_tbl_name[IPA_RESOURCE_NAME_MAX]; - uint8_t num_rules; - struct ipa_rt_rule_add rules[0]; -}; - -/** - * struct ipa_ioc_add_rt_rule_after - routing rule addition after a specific - * rule parameters(supports multiple rules and commit); - * - * all rules MUST be added to same table - * @commit: should rules be written to IPA HW also? - * @ip: IP family of rule - * @rt_tbl_name: name of routing table resource - * @num_rules: number of routing rules that follow - * @add_after_hdl: the rules will be added after this specific rule - * @ipa_rt_rule_add rules: all rules need to go back to back here, no pointers - * at_rear field will be ignored when using this IOCTL - */ -struct ipa_ioc_add_rt_rule_after { - uint8_t commit; - enum ipa_ip_type ip; - char rt_tbl_name[IPA_RESOURCE_NAME_MAX]; - uint8_t num_rules; - uint32_t add_after_hdl; - struct ipa_rt_rule_add rules[0]; -}; - -/** - * struct ipa_rt_rule_mdfy - routing rule descriptor includes - * in and out parameters - * @rule: actual rule to be added - * @rt_rule_hdl: handle to rule which supposed to modify - * @status: output parameter, status of routing rule modify operation, - * 0 for success, - * -1 for failure - * - */ -struct ipa_rt_rule_mdfy { - struct ipa_rt_rule rule; - uint32_t rt_rule_hdl; - int status; -}; - -/** - * struct ipa_ioc_mdfy_rt_rule - routing rule modify parameters (supports - * multiple rules and commit) - * @commit: should rules be written to IPA HW also? - * @ip: IP family of rule - * @num_rules: number of routing rules that follow - * @rules: all rules need to go back to back here, no pointers - */ -struct ipa_ioc_mdfy_rt_rule { - uint8_t commit; - enum ipa_ip_type ip; - uint8_t num_rules; - struct ipa_rt_rule_mdfy rules[0]; -}; - -/** - * struct ipa_rt_rule_del - routing rule descriptor includes in - * and out parameters - * @hdl: handle returned from route rule add operation - * @status: output parameter, status of route rule delete operation, - * 0 for success, - * -1 for failure - */ -struct ipa_rt_rule_del { - uint32_t hdl; - int status; -}; - -/** - * struct ipa_rt_rule_add_ext - routing rule descriptor includes in - * and out parameters - * @rule: actual rule to be added - * @at_rear: add at back of routing table, it is NOT possible to add rules at - * the rear of the "default" routing tables - * @rt_rule_hdl: output parameter, handle to rule, valid when status is 0 - * @status: output parameter, status of routing rule add operation, - * @rule_id: rule_id to be assigned to the routing rule. In case client - * specifies rule_id as 0 the driver will assign a new rule_id - * 0 for success, - * -1 for failure - */ -struct ipa_rt_rule_add_ext { - struct ipa_rt_rule rule; - uint8_t at_rear; - uint32_t rt_rule_hdl; - int status; - uint16_t rule_id; -}; - -/** - * struct ipa_ioc_add_rt_rule - routing rule addition parameters (supports - * multiple rules and commit with rule_id); - * - * all rules MUST be added to same table - * @commit: should rules be written to IPA HW also? - * @ip: IP family of rule - * @rt_tbl_name: name of routing table resource - * @num_rules: number of routing rules that follow - * @ipa_rt_rule_add_ext rules: all rules need to go back to back here, - * no pointers - */ -struct ipa_ioc_add_rt_rule_ext { - uint8_t commit; - enum ipa_ip_type ip; - char rt_tbl_name[IPA_RESOURCE_NAME_MAX]; - uint8_t num_rules; - struct ipa_rt_rule_add_ext rules[0]; -}; - - -/** - * struct ipa_ioc_del_rt_rule - routing rule deletion parameters (supports - * multiple headers and commit) - * @commit: should rules be removed from IPA HW also? - * @ip: IP family of rules - * @num_hdls: num of rules being removed - * @ipa_rt_rule_del hdl: all handles need to go back to back here, no pointers - */ -struct ipa_ioc_del_rt_rule { - uint8_t commit; - enum ipa_ip_type ip; - uint8_t num_hdls; - struct ipa_rt_rule_del hdl[0]; -}; - -/** - * struct ipa_ioc_get_rt_tbl_indx - routing table index lookup parameters - * @ip: IP family of table - * @name: name of routing table resource - * @index: output parameter, routing table index, valid only when ioctl - * return val is non-negative - */ -struct ipa_ioc_get_rt_tbl_indx { - enum ipa_ip_type ip; - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t idx; -}; - -/** - * struct ipa_flt_rule_add - filtering rule descriptor includes - * in and out parameters - * @rule: actual rule to be added - * @at_rear: add at back of filtering table? - * @flt_rule_hdl: out parameter, handle to rule, valid when status is 0 - * @status: output parameter, status of filtering rule add operation, - * 0 for success, - * -1 for failure - * - */ -struct ipa_flt_rule_add { - struct ipa_flt_rule rule; - uint8_t at_rear; - uint32_t flt_rule_hdl; - int status; -}; - -/** - * struct ipa_ioc_add_flt_rule - filtering rule addition parameters (supports - * multiple rules and commit) - * all rules MUST be added to same table - * @commit: should rules be written to IPA HW also? - * @ip: IP family of rule - * @ep: which "clients" pipe does this rule apply to? - * valid only when global is 0 - * @global: does this apply to global filter table of specific IP family - * @num_rules: number of filtering rules that follow - * @rules: all rules need to go back to back here, no pointers - */ -struct ipa_ioc_add_flt_rule { - uint8_t commit; - enum ipa_ip_type ip; - enum ipa_client_type ep; - uint8_t global; - uint8_t num_rules; - struct ipa_flt_rule_add rules[0]; -}; - -/** - * struct ipa_ioc_add_flt_rule_after - filtering rule addition after specific - * rule parameters (supports multiple rules and commit) - * all rules MUST be added to same table - * @commit: should rules be written to IPA HW also? - * @ip: IP family of rule - * @ep: which "clients" pipe does this rule apply to? - * @num_rules: number of filtering rules that follow - * @add_after_hdl: rules will be added after the rule with this handle - * @rules: all rules need to go back to back here, no pointers. at rear field - * is ignored when using this IOCTL - */ -struct ipa_ioc_add_flt_rule_after { - uint8_t commit; - enum ipa_ip_type ip; - enum ipa_client_type ep; - uint8_t num_rules; - uint32_t add_after_hdl; - struct ipa_flt_rule_add rules[0]; -}; - -/** - * struct ipa_flt_rule_mdfy - filtering rule descriptor includes - * in and out parameters - * @rule: actual rule to be added - * @flt_rule_hdl: handle to rule - * @status: output parameter, status of filtering rule modify operation, - * 0 for success, - * -1 for failure - * - */ -struct ipa_flt_rule_mdfy { - struct ipa_flt_rule rule; - uint32_t rule_hdl; - int status; -}; - -/** - * struct ipa_ioc_mdfy_flt_rule - filtering rule modify parameters (supports - * multiple rules and commit) - * @commit: should rules be written to IPA HW also? - * @ip: IP family of rule - * @num_rules: number of filtering rules that follow - * @rules: all rules need to go back to back here, no pointers - */ -struct ipa_ioc_mdfy_flt_rule { - uint8_t commit; - enum ipa_ip_type ip; - uint8_t num_rules; - struct ipa_flt_rule_mdfy rules[0]; -}; - -/** - * struct ipa_flt_rule_del - filtering rule descriptor includes - * in and out parameters - * - * @hdl: handle returned from filtering rule add operation - * @status: output parameter, status of filtering rule delete operation, - * 0 for success, - * -1 for failure - */ -struct ipa_flt_rule_del { - uint32_t hdl; - int status; -}; - -/** - * struct ipa_ioc_del_flt_rule - filtering rule deletion parameters (supports - * multiple headers and commit) - * @commit: should rules be removed from IPA HW also? - * @ip: IP family of rules - * @num_hdls: num of rules being removed - * @hdl: all handles need to go back to back here, no pointers - */ -struct ipa_ioc_del_flt_rule { - uint8_t commit; - enum ipa_ip_type ip; - uint8_t num_hdls; - struct ipa_flt_rule_del hdl[0]; -}; - -/** - * struct ipa_ioc_get_rt_tbl - routing table lookup parameters, if lookup was - * successful caller must call put to release the reference - * count when done - * @ip: IP family of table - * @name: name of routing table resource - * @htl: output parameter, handle of routing table, valid only when ioctl - * return val is non-negative - */ -struct ipa_ioc_get_rt_tbl { - enum ipa_ip_type ip; - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t hdl; -}; - -/** - * struct ipa_ioc_query_intf - used to lookup number of tx and - * rx properties of interface - * @name: name of interface - * @num_tx_props: output parameter, number of tx properties - * valid only when ioctl return val is non-negative - * @num_rx_props: output parameter, number of rx properties - * valid only when ioctl return val is non-negative - * @num_ext_props: output parameter, number of ext properties - * valid only when ioctl return val is non-negative - * @excp_pipe: exception packets of this interface should be - * routed to this pipe - */ -struct ipa_ioc_query_intf { - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t num_tx_props; - uint32_t num_rx_props; - uint32_t num_ext_props; - enum ipa_client_type excp_pipe; -}; - -/** - * struct ipa_ioc_tx_intf_prop - interface tx property - * @ip: IP family of routing rule - * @attrib: routing rule - * @dst_pipe: routing output pipe - * @alt_dst_pipe: alternate routing output pipe - * @hdr_name: name of associated header if any, empty string when no header - * @hdr_l2_type: type of associated header if any, use NONE when no header - */ -struct ipa_ioc_tx_intf_prop { - enum ipa_ip_type ip; - struct ipa_rule_attrib attrib; - enum ipa_client_type dst_pipe; - enum ipa_client_type alt_dst_pipe; - char hdr_name[IPA_RESOURCE_NAME_MAX]; - enum ipa_hdr_l2_type hdr_l2_type; -}; - -/** - * struct ipa_ioc_query_intf_tx_props - interface tx propertie - * @name: name of interface - * @num_tx_props: number of TX properties - * @tx[0]: output parameter, the tx properties go here back to back - */ -struct ipa_ioc_query_intf_tx_props { - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t num_tx_props; - struct ipa_ioc_tx_intf_prop tx[0]; -}; - -/** - * struct ipa_ioc_ext_intf_prop - interface extended property - * @ip: IP family of routing rule - * @eq_attrib: attributes of the rule in equation form - * @action: action field - * @rt_tbl_idx: index of RT table referred to by filter rule - * @mux_id: MUX_ID - * @filter_hdl: handle of filter (as specified by provider of filter rule) - * @is_xlat_rule: it is xlat flt rule or not - */ -struct ipa_ioc_ext_intf_prop { - enum ipa_ip_type ip; - struct ipa_ipfltri_rule_eq eq_attrib; - enum ipa_flt_action action; - uint32_t rt_tbl_idx; - uint8_t mux_id; - uint32_t filter_hdl; - uint8_t is_xlat_rule; - uint32_t rule_id; - uint8_t is_rule_hashable; -}; - -/** - * struct ipa_ioc_query_intf_ext_props - interface ext propertie - * @name: name of interface - * @num_ext_props: number of EXT properties - * @ext[0]: output parameter, the ext properties go here back to back - */ -struct ipa_ioc_query_intf_ext_props { - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t num_ext_props; - struct ipa_ioc_ext_intf_prop ext[0]; -}; - -/** - * struct ipa_ioc_rx_intf_prop - interface rx property - * @ip: IP family of filtering rule - * @attrib: filtering rule - * @src_pipe: input pipe - * @hdr_l2_type: type of associated header if any, use NONE when no header - */ -struct ipa_ioc_rx_intf_prop { - enum ipa_ip_type ip; - struct ipa_rule_attrib attrib; - enum ipa_client_type src_pipe; - enum ipa_hdr_l2_type hdr_l2_type; -}; - -/** - * struct ipa_ioc_query_intf_rx_props - interface rx propertie - * @name: name of interface - * @num_rx_props: number of RX properties - * @rx: output parameter, the rx properties go here back to back - */ -struct ipa_ioc_query_intf_rx_props { - char name[IPA_RESOURCE_NAME_MAX]; - uint32_t num_rx_props; - struct ipa_ioc_rx_intf_prop rx[0]; -}; - -/** - * struct ipa_ioc_nat_alloc_mem - nat table memory allocation - * properties - * @dev_name: input parameter, the name of table - * @size: input parameter, size of table in bytes - * @offset: output parameter, offset into page in case of system memory - */ -struct ipa_ioc_nat_alloc_mem { - char dev_name[IPA_RESOURCE_NAME_MAX]; - size_t size; - off_t offset; -}; - -/** - * struct ipa_ioc_nat_ipv6ct_table_alloc - NAT/IPv6CT table memory allocation - * properties - * @size: input parameter, size of table in bytes - * @offset: output parameter, offset into page in case of system memory - */ -struct ipa_ioc_nat_ipv6ct_table_alloc { - size_t size; - off_t offset; -}; - -/** - * struct ipa_ioc_v4_nat_init - nat table initialization parameters - * @tbl_index: input parameter, index of the table - * @ipv4_rules_offset: input parameter, ipv4 rules address offset - * @expn_rules_offset: input parameter, ipv4 expansion rules address offset - * @index_offset: input parameter, index rules offset - * @index_expn_offset: input parameter, index expansion rules offset - * @table_entries: input parameter, ipv4 rules table number of entries - * @expn_table_entries: input parameter, ipv4 expansion rules table number of - * entries - * @ip_addr: input parameter, public ip address - */ -struct ipa_ioc_v4_nat_init { - uint8_t tbl_index; - uint32_t ipv4_rules_offset; - uint32_t expn_rules_offset; - - uint32_t index_offset; - uint32_t index_expn_offset; - - uint16_t table_entries; - uint16_t expn_table_entries; - uint32_t ip_addr; -}; - -/** - * struct ipa_ioc_ipv6ct_init - IPv6CT table initialization parameters - * @base_table_offset: input parameter, IPv6CT base table address offset - * @expn_table_offset: input parameter, IPv6CT expansion table address offset - * @table_entries: input parameter, IPv6CT table number of entries - * @expn_table_entries: input parameter, IPv6CT expansion table number of - * entries - * @tbl_index: input parameter, index of the table - */ -struct ipa_ioc_ipv6ct_init { - uint32_t base_table_offset; - uint32_t expn_table_offset; - uint16_t table_entries; - uint16_t expn_table_entries; - uint8_t tbl_index; -}; - -/** - * struct ipa_ioc_v4_nat_del - nat table delete parameter - * @table_index: input parameter, index of the table - * @public_ip_addr: input parameter, public ip address - */ -struct ipa_ioc_v4_nat_del { - uint8_t table_index; - uint32_t public_ip_addr; -}; - -/** - * struct ipa_ioc_nat_ipv6ct_table_del - NAT/IPv6CT table delete parameter - * @table_index: input parameter, index of the table - */ -struct ipa_ioc_nat_ipv6ct_table_del { - uint8_t table_index; -}; - -/** - * struct ipa_ioc_nat_dma_one - nat/ipv6ct dma command parameter - * @table_index: input parameter, index of the table - * @base_addr: type of table, from which the base address of the table - * can be inferred - * @offset: destination offset within the NAT table - * @data: data to be written. - */ -struct ipa_ioc_nat_dma_one { - uint8_t table_index; - uint8_t base_addr; - - uint32_t offset; - uint16_t data; - -}; - -/** - * struct ipa_ioc_nat_dma_cmd - To hold multiple nat/ipv6ct dma commands - * @entries: number of dma commands in use - * @dma: data pointer to the dma commands - */ -struct ipa_ioc_nat_dma_cmd { - uint8_t entries; - struct ipa_ioc_nat_dma_one dma[0]; - -}; - -/** - * struct ipa_ioc_nat_pdn_entry - PDN entry modification data - * @pdn_index: index of the entry in the PDN config table to be changed - * @public_ip: PDN's public ip - * @src_metadata: PDN's source NAT metadata for metadata replacement - * @dst_metadata: PDN's destination NAT metadata for metadata replacement - */ -struct ipa_ioc_nat_pdn_entry { - uint8_t pdn_index; - uint32_t public_ip; - uint32_t src_metadata; - uint32_t dst_metadata; -}; - -/** - * struct ipa_ioc_vlan_iface_info - add vlan interface - * @name: interface name - * @vlan_id: VLAN ID - */ -struct ipa_ioc_vlan_iface_info { - char name[IPA_RESOURCE_NAME_MAX]; - uint8_t vlan_id; -}; - -/** - * struct ipa_ioc_l2tp_vlan_mapping_info - l2tp->vlan mapping info - * @iptype: l2tp tunnel IP type - * @l2tp_iface_name: l2tp interface name - * @l2tp_session_id: l2tp session id - * @vlan_iface_name: vlan interface name - */ -struct ipa_ioc_l2tp_vlan_mapping_info { - enum ipa_ip_type iptype; - char l2tp_iface_name[IPA_RESOURCE_NAME_MAX]; - uint8_t l2tp_session_id; - char vlan_iface_name[IPA_RESOURCE_NAME_MAX]; -}; - -/** - * struct ipa_msg_meta - Format of the message meta-data. - * @msg_type: the type of the message - * @rsvd: reserved bits for future use. - * @msg_len: the length of the message in bytes - * - * For push model: - * Client in user-space should issue a read on the device (/dev/ipa) with a - * sufficiently large buffer in a continuous loop, call will block when there is - * no message to read. Upon return, client can read the ipa_msg_meta from start - * of buffer to find out type and length of message - * size of buffer supplied >= (size of largest message + size of metadata) - * - * For pull model: - * Client in user-space can also issue a pull msg IOCTL to device (/dev/ipa) - * with a payload containing space for the ipa_msg_meta and the message specific - * payload length. - * size of buffer supplied == (len of specific message + size of metadata) - */ -struct ipa_msg_meta { - uint8_t msg_type; - uint8_t rsvd; - uint16_t msg_len; -}; - -/** - * struct ipa_wlan_msg - To hold information about wlan client - * @name: name of the wlan interface - * @mac_addr: mac address of wlan client - * - * wlan drivers need to pass name of wlan iface and mac address of - * wlan client along with ipa_wlan_event, whenever a wlan client is - * connected/disconnected/moved to power save/come out of power save - */ -struct ipa_wlan_msg { - char name[IPA_RESOURCE_NAME_MAX]; - uint8_t mac_addr[IPA_MAC_ADDR_SIZE]; -}; - -/** - * enum ipa_wlan_hdr_attrib_type - attribute type - * in wlan client header - * - * WLAN_HDR_ATTRIB_MAC_ADDR: attrib type mac address - * WLAN_HDR_ATTRIB_STA_ID: attrib type station id - */ -enum ipa_wlan_hdr_attrib_type { - WLAN_HDR_ATTRIB_MAC_ADDR, - WLAN_HDR_ATTRIB_STA_ID -}; - -/** - * struct ipa_wlan_hdr_attrib_val - header attribute value - * @attrib_type: type of attribute - * @offset: offset of attribute within header - * @u.mac_addr: mac address - * @u.sta_id: station id - */ -struct ipa_wlan_hdr_attrib_val { - enum ipa_wlan_hdr_attrib_type attrib_type; - uint8_t offset; - union { - uint8_t mac_addr[IPA_MAC_ADDR_SIZE]; - uint8_t sta_id; - } u; -}; - -/** - * struct ipa_wlan_msg_ex - To hold information about wlan client - * @name: name of the wlan interface - * @num_of_attribs: number of attributes - * @attrib_val: holds attribute values - * - * wlan drivers need to pass name of wlan iface and mac address - * of wlan client or station id along with ipa_wlan_event, - * whenever a wlan client is connected/disconnected/moved to - * power save/come out of power save - */ -struct ipa_wlan_msg_ex { - char name[IPA_RESOURCE_NAME_MAX]; - uint8_t num_of_attribs; - struct ipa_wlan_hdr_attrib_val attribs[0]; -}; - -struct ipa_ecm_msg { - char name[IPA_RESOURCE_NAME_MAX]; - int ifindex; -}; - -/** - * struct ipa_wan_msg - To hold information about wan client - * @name: name of the wan interface - * - * CnE need to pass the name of default wan iface when connected/disconnected. - * CNE need to pass the gw info in wlan AP+STA mode. - * netmgr need to pass the name of wan eMBMS iface when connected. - */ -struct ipa_wan_msg { - char upstream_ifname[IPA_RESOURCE_NAME_MAX]; - char tethered_ifname[IPA_RESOURCE_NAME_MAX]; - enum ipa_ip_type ip; - uint32_t ipv4_addr_gw; - uint32_t ipv6_addr_gw[IPA_WAN_MSG_IPv6_ADDR_GW_LEN]; -}; - -/** - * struct ipa_ioc_rm_dependency - parameters for add/delete dependency - * @resource_name: name of dependent resource - * @depends_on_name: name of its dependency - */ -struct ipa_ioc_rm_dependency { - enum ipa_rm_resource_name resource_name; - enum ipa_rm_resource_name depends_on_name; -}; - -struct ipa_ioc_generate_flt_eq { - enum ipa_ip_type ip; - struct ipa_rule_attrib attrib; - struct ipa_ipfltri_rule_eq eq_attrib; -}; - -/** - * struct ipa_ioc_write_qmapid - to write mux id to endpoint meta register - * @mux_id: mux id of wan - */ -struct ipa_ioc_write_qmapid { - enum ipa_client_type client; - uint8_t qmap_id; -}; - -enum ipacm_client_enum { - IPACM_CLIENT_USB = 1, - IPACM_CLIENT_WLAN, - IPACM_CLIENT_MAX -}; - -enum ipacm_per_client_device_type { - IPACM_CLIENT_DEVICE_TYPE_USB = 0, - IPACM_CLIENT_DEVICE_TYPE_WLAN = 1, - IPACM_CLIENT_DEVICE_TYPE_ETH = 2 -}; - -/** - * max number of device types supported. - */ -#define IPACM_MAX_CLIENT_DEVICE_TYPES 3 - -/** - * @lanIface - Name of the lan interface - * @mac: Mac address of the client. - */ -struct ipa_lan_client_msg { - char lanIface[IPA_RESOURCE_NAME_MAX]; - uint8_t mac[IPA_MAC_ADDR_SIZE]; -}; - -/** - * struct ipa_lan_client - lan client data - * @mac: MAC Address of the client. - * @client_idx: Client Index. - * @inited: Bool to indicate whether client info is set. - */ -struct ipa_lan_client { - uint8_t mac[IPA_MAC_ADDR_SIZE]; - int8_t client_idx; - uint8_t inited; -}; - -/** - * struct ipa_tether_device_info - tether device info indicated from IPACM - * @ul_src_pipe: Source pipe of the lan client. - * @hdr_len: Header length of the client. - * @num_clients: Number of clients connected. - */ -struct ipa_tether_device_info { - int32_t ul_src_pipe; - uint8_t hdr_len; - uint32_t num_clients; - struct ipa_lan_client lan_client[IPA_MAX_NUM_HW_PATH_CLIENTS]; -}; - -/** - * enum ipa_vlan_ifaces - vlan interfaces types - */ -enum ipa_vlan_ifaces { - IPA_VLAN_IF_ETH, - IPA_VLAN_IF_RNDIS, - IPA_VLAN_IF_ECM -}; - -#define IPA_VLAN_IF_EMAC IPA_VLAN_IF_ETH -#define IPA_VLAN_IF_MAX (IPA_VLAN_IF_ECM + 1) - -/** - * struct ipa_get_vlan_mode - get vlan mode of a Lan interface - * @iface: Lan interface type to be queried. - * @is_vlan_mode: output parameter, is interface in vlan mode, valid only when - * ioctl return val is non-negative - */ -struct ipa_ioc_get_vlan_mode { - enum ipa_vlan_ifaces iface; - uint32_t is_vlan_mode; -}; - -/** - * actual IOCTLs supported by IPA driver - */ -#define IPA_IOC_ADD_HDR _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ADD_HDR, \ - struct ipa_ioc_add_hdr *) -#define IPA_IOC_DEL_HDR _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_DEL_HDR, \ - struct ipa_ioc_del_hdr *) -#define IPA_IOC_ADD_RT_RULE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ADD_RT_RULE, \ - struct ipa_ioc_add_rt_rule *) -#define IPA_IOC_ADD_RT_RULE_EXT _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ADD_RT_RULE_EXT, \ - struct ipa_ioc_add_rt_rule_ext *) -#define IPA_IOC_ADD_RT_RULE_AFTER _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ADD_RT_RULE_AFTER, \ - struct ipa_ioc_add_rt_rule_after *) -#define IPA_IOC_DEL_RT_RULE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_DEL_RT_RULE, \ - struct ipa_ioc_del_rt_rule *) -#define IPA_IOC_ADD_FLT_RULE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ADD_FLT_RULE, \ - struct ipa_ioc_add_flt_rule *) -#define IPA_IOC_ADD_FLT_RULE_AFTER _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ADD_FLT_RULE_AFTER, \ - struct ipa_ioc_add_flt_rule_after *) -#define IPA_IOC_DEL_FLT_RULE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_DEL_FLT_RULE, \ - struct ipa_ioc_del_flt_rule *) -#define IPA_IOC_COMMIT_HDR _IO(IPA_IOC_MAGIC,\ - IPA_IOCTL_COMMIT_HDR) -#define IPA_IOC_RESET_HDR _IO(IPA_IOC_MAGIC,\ - IPA_IOCTL_RESET_HDR) -#define IPA_IOC_COMMIT_RT _IOW(IPA_IOC_MAGIC, \ - IPA_IOCTL_COMMIT_RT, \ - enum ipa_ip_type) -#define IPA_IOC_RESET_RT _IOW(IPA_IOC_MAGIC, \ - IPA_IOCTL_RESET_RT, \ - enum ipa_ip_type) -#define IPA_IOC_COMMIT_FLT _IOW(IPA_IOC_MAGIC, \ - IPA_IOCTL_COMMIT_FLT, \ - enum ipa_ip_type) -#define IPA_IOC_RESET_FLT _IOW(IPA_IOC_MAGIC, \ - IPA_IOCTL_RESET_FLT, \ - enum ipa_ip_type) -#define IPA_IOC_DUMP _IO(IPA_IOC_MAGIC, \ - IPA_IOCTL_DUMP) -#define IPA_IOC_GET_RT_TBL _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_GET_RT_TBL, \ - struct ipa_ioc_get_rt_tbl *) -#define IPA_IOC_PUT_RT_TBL _IOW(IPA_IOC_MAGIC, \ - IPA_IOCTL_PUT_RT_TBL, \ - uint32_t) -#define IPA_IOC_COPY_HDR _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_COPY_HDR, \ - struct ipa_ioc_copy_hdr *) -#define IPA_IOC_QUERY_INTF _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_QUERY_INTF, \ - struct ipa_ioc_query_intf *) -#define IPA_IOC_QUERY_INTF_TX_PROPS _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_QUERY_INTF_TX_PROPS, \ - struct ipa_ioc_query_intf_tx_props *) -#define IPA_IOC_QUERY_INTF_RX_PROPS _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_QUERY_INTF_RX_PROPS, \ - struct ipa_ioc_query_intf_rx_props *) -#define IPA_IOC_QUERY_INTF_EXT_PROPS _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_QUERY_INTF_EXT_PROPS, \ - struct ipa_ioc_query_intf_ext_props *) -#define IPA_IOC_GET_HDR _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_GET_HDR, \ - struct ipa_ioc_get_hdr *) -#define IPA_IOC_PUT_HDR _IOW(IPA_IOC_MAGIC, \ - IPA_IOCTL_PUT_HDR, \ - uint32_t) -#define IPA_IOC_ALLOC_NAT_MEM _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ALLOC_NAT_MEM, \ - struct ipa_ioc_nat_alloc_mem *) -#define IPA_IOC_ALLOC_NAT_TABLE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ALLOC_NAT_TABLE, \ - struct ipa_ioc_nat_ipv6ct_table_alloc *) -#define IPA_IOC_ALLOC_IPV6CT_TABLE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ALLOC_IPV6CT_TABLE, \ - struct ipa_ioc_nat_ipv6ct_table_alloc *) -#define IPA_IOC_V4_INIT_NAT _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_V4_INIT_NAT, \ - struct ipa_ioc_v4_nat_init *) -#define IPA_IOC_INIT_IPV6CT_TABLE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_INIT_IPV6CT_TABLE, \ - struct ipa_ioc_ipv6ct_init *) -#define IPA_IOC_NAT_DMA _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_NAT_DMA, \ - struct ipa_ioc_nat_dma_cmd *) -#define IPA_IOC_TABLE_DMA_CMD _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_TABLE_DMA_CMD, \ - struct ipa_ioc_nat_dma_cmd *) -#define IPA_IOC_V4_DEL_NAT _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_V4_DEL_NAT, \ - struct ipa_ioc_v4_nat_del *) -#define IPA_IOC_DEL_NAT_TABLE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_DEL_NAT_TABLE, \ - struct ipa_ioc_nat_ipv6ct_table_del *) -#define IPA_IOC_DEL_IPV6CT_TABLE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_DEL_IPV6CT_TABLE, \ - struct ipa_ioc_nat_ipv6ct_table_del *) -#define IPA_IOC_GET_NAT_OFFSET _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_GET_NAT_OFFSET, \ - uint32_t *) -#define IPA_IOC_NAT_MODIFY_PDN _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_NAT_MODIFY_PDN, \ - struct ipa_ioc_nat_pdn_entry *) -#define IPA_IOC_SET_FLT _IOW(IPA_IOC_MAGIC, \ - IPA_IOCTL_SET_FLT, \ - uint32_t) -#define IPA_IOC_PULL_MSG _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_PULL_MSG, \ - struct ipa_msg_meta *) -#define IPA_IOC_RM_ADD_DEPENDENCY _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_RM_ADD_DEPENDENCY, \ - struct ipa_ioc_rm_dependency *) -#define IPA_IOC_RM_DEL_DEPENDENCY _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_RM_DEL_DEPENDENCY, \ - struct ipa_ioc_rm_dependency *) -#define IPA_IOC_GENERATE_FLT_EQ _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_GENERATE_FLT_EQ, \ - struct ipa_ioc_generate_flt_eq *) -#define IPA_IOC_QUERY_EP_MAPPING _IOR(IPA_IOC_MAGIC, \ - IPA_IOCTL_QUERY_EP_MAPPING, \ - uint32_t) -#define IPA_IOC_QUERY_RT_TBL_INDEX _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_QUERY_RT_TBL_INDEX, \ - struct ipa_ioc_get_rt_tbl_indx *) -#define IPA_IOC_WRITE_QMAPID _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_WRITE_QMAPID, \ - struct ipa_ioc_write_qmapid *) -#define IPA_IOC_MDFY_FLT_RULE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_MDFY_FLT_RULE, \ - struct ipa_ioc_mdfy_flt_rule *) -#define IPA_IOC_MDFY_RT_RULE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_MDFY_RT_RULE, \ - struct ipa_ioc_mdfy_rt_rule *) - -#define IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_ADD _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_ADD, \ - struct ipa_wan_msg *) - -#define IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_DEL _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_DEL, \ - struct ipa_wan_msg *) -#define IPA_IOC_NOTIFY_WAN_EMBMS_CONNECTED _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_NOTIFY_WAN_EMBMS_CONNECTED, \ - struct ipa_wan_msg *) -#define IPA_IOC_ADD_HDR_PROC_CTX _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ADD_HDR_PROC_CTX, \ - struct ipa_ioc_add_hdr_proc_ctx *) -#define IPA_IOC_DEL_HDR_PROC_CTX _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_DEL_HDR_PROC_CTX, \ - struct ipa_ioc_del_hdr_proc_ctx *) - -#define IPA_IOC_GET_HW_VERSION _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_GET_HW_VERSION, \ - enum ipa_hw_type *) - -#define IPA_IOC_ADD_VLAN_IFACE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ADD_VLAN_IFACE, \ - struct ipa_ioc_vlan_iface_info *) - -#define IPA_IOC_DEL_VLAN_IFACE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_DEL_VLAN_IFACE, \ - struct ipa_ioc_vlan_iface_info *) - -#define IPA_IOC_ADD_L2TP_VLAN_MAPPING _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ADD_L2TP_VLAN_MAPPING, \ - struct ipa_ioc_l2tp_vlan_mapping_info *) - -#define IPA_IOC_DEL_L2TP_VLAN_MAPPING _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_DEL_L2TP_VLAN_MAPPING, \ - struct ipa_ioc_l2tp_vlan_mapping_info *) -#define IPA_IOC_CLEANUP _IO(IPA_IOC_MAGIC,\ - IPA_IOCTL_CLEANUP) -#define IPA_IOC_QUERY_WLAN_CLIENT _IO(IPA_IOC_MAGIC,\ - IPA_IOCTL_QUERY_WLAN_CLIENT) -#define IPA_IOC_GET_VLAN_MODE _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_GET_VLAN_MODE, \ - struct ipa_ioc_get_vlan_mode *) -/* - * unique magic number of the Tethering bridge ioctls - */ -#define TETH_BRIDGE_IOC_MAGIC 0xCE - -/* - * Ioctls supported by Tethering bridge driver - */ -#define TETH_BRIDGE_IOCTL_SET_BRIDGE_MODE 0 -#define TETH_BRIDGE_IOCTL_SET_AGGR_PARAMS 1 -#define TETH_BRIDGE_IOCTL_GET_AGGR_PARAMS 2 -#define TETH_BRIDGE_IOCTL_GET_AGGR_CAPABILITIES 3 -#define TETH_BRIDGE_IOCTL_MAX 4 - - -/** - * enum teth_link_protocol_type - link protocol (IP / Ethernet) - */ -enum teth_link_protocol_type { - TETH_LINK_PROTOCOL_IP, - TETH_LINK_PROTOCOL_ETHERNET, - TETH_LINK_PROTOCOL_MAX, -}; - -/** - * enum teth_aggr_protocol_type - Aggregation protocol (MBIM / TLP) - */ -enum teth_aggr_protocol_type { - TETH_AGGR_PROTOCOL_NONE, - TETH_AGGR_PROTOCOL_MBIM, - TETH_AGGR_PROTOCOL_TLP, - TETH_AGGR_PROTOCOL_MAX, -}; - -/** - * struct teth_aggr_params_link - Aggregation parameters for uplink/downlink - * @aggr_prot: Aggregation protocol (MBIM / TLP) - * @max_transfer_size_byte: Maximal size of aggregated packet in bytes. - * Default value is 16*1024. - * @max_datagrams: Maximal number of IP packets in an aggregated - * packet. Default value is 16 - */ -struct teth_aggr_params_link { - enum teth_aggr_protocol_type aggr_prot; - uint32_t max_transfer_size_byte; - uint32_t max_datagrams; -}; - - -/** - * struct teth_aggr_params - Aggregation parmeters - * @ul: Uplink parameters - * @dl: Downlink parmaeters - */ -struct teth_aggr_params { - struct teth_aggr_params_link ul; - struct teth_aggr_params_link dl; -}; - -/** - * struct teth_aggr_capabilities - Aggregation capabilities - * @num_protocols: Number of protocols described in the array - * @prot_caps[]: Array of aggregation capabilities per protocol - */ -struct teth_aggr_capabilities { - uint16_t num_protocols; - struct teth_aggr_params_link prot_caps[0]; -}; - -/** - * struct teth_ioc_set_bridge_mode - * @link_protocol: link protocol (IP / Ethernet) - * @lcid: logical channel number - */ -struct teth_ioc_set_bridge_mode { - enum teth_link_protocol_type link_protocol; - uint16_t lcid; -}; - -/** - * struct teth_ioc_set_aggr_params - * @aggr_params: Aggregation parmeters - * @lcid: logical channel number - */ -struct teth_ioc_aggr_params { - struct teth_aggr_params aggr_params; - uint16_t lcid; -}; - - -#define TETH_BRIDGE_IOC_SET_BRIDGE_MODE _IOW(TETH_BRIDGE_IOC_MAGIC, \ - TETH_BRIDGE_IOCTL_SET_BRIDGE_MODE, \ - struct teth_ioc_set_bridge_mode *) -#define TETH_BRIDGE_IOC_SET_AGGR_PARAMS _IOW(TETH_BRIDGE_IOC_MAGIC, \ - TETH_BRIDGE_IOCTL_SET_AGGR_PARAMS, \ - struct teth_ioc_aggr_params *) -#define TETH_BRIDGE_IOC_GET_AGGR_PARAMS _IOR(TETH_BRIDGE_IOC_MAGIC, \ - TETH_BRIDGE_IOCTL_GET_AGGR_PARAMS, \ - struct teth_ioc_aggr_params *) -#define TETH_BRIDGE_IOC_GET_AGGR_CAPABILITIES _IOWR(TETH_BRIDGE_IOC_MAGIC, \ - TETH_BRIDGE_IOCTL_GET_AGGR_CAPABILITIES, \ - struct teth_aggr_capabilities *) - -/* - * unique magic number of the ODU bridge ioctls - */ -#define ODU_BRIDGE_IOC_MAGIC 0xCD - -/* - * Ioctls supported by ODU bridge driver - */ -#define ODU_BRIDGE_IOCTL_SET_MODE 0 -#define ODU_BRIDGE_IOCTL_SET_LLV6_ADDR 1 -#define ODU_BRIDGE_IOCTL_MAX 2 - -/** - * enum odu_bridge_mode - bridge mode - * (ROUTER MODE / BRIDGE MODE) - */ -enum odu_bridge_mode { - ODU_BRIDGE_MODE_ROUTER, - ODU_BRIDGE_MODE_BRIDGE, - ODU_BRIDGE_MODE_MAX, -}; - -#define ODU_BRIDGE_IOC_SET_MODE _IOW(ODU_BRIDGE_IOC_MAGIC, \ - ODU_BRIDGE_IOCTL_SET_MODE, \ - enum odu_bridge_mode) - -#define ODU_BRIDGE_IOC_SET_LLV6_ADDR _IOW(ODU_BRIDGE_IOC_MAGIC, \ - ODU_BRIDGE_IOCTL_SET_LLV6_ADDR, \ - struct in6_addr *) - -#endif /* _MSM_IPA_H_ */ diff --git a/sdm710/original-kernel-headers/linux/msm_kgsl.h b/sdm710/original-kernel-headers/linux/msm_kgsl.h deleted file mode 100644 index cea619e2..00000000 --- a/sdm710/original-kernel-headers/linux/msm_kgsl.h +++ /dev/null @@ -1,1622 +0,0 @@ -#ifndef _MSM_KGSL_H -#define _MSM_KGSL_H - -#include <linux/types.h> -#include <linux/ioctl.h> - -/* - * The KGSL version has proven not to be very useful in userspace if features - * are cherry picked into other trees out of order so it is frozen as of 3.14. - * It is left here for backwards compatabilty and as a reminder that - * software releases are never linear. Also, I like pie. - */ - -#define KGSL_VERSION_MAJOR 3 -#define KGSL_VERSION_MINOR 14 - -/* - * We have traditionally mixed context and issueibcmds / command batch flags - * together into a big flag stew. This worked fine until we started adding a - * lot more command batch flags and we started running out of bits. Turns out - * we have a bit of room in the context type / priority mask that we could use - * for command batches, but that means we need to split out the flags into two - * coherent sets. - * - * If any future definitions are for both context and cmdbatch add both defines - * and link the cmdbatch to the context define as we do below. Otherwise feel - * free to add exclusive bits to either set. - */ - -/* --- context flags --- */ -#define KGSL_CONTEXT_SAVE_GMEM 0x00000001 -#define KGSL_CONTEXT_NO_GMEM_ALLOC 0x00000002 -/* This is a cmdbatch exclusive flag - use the CMDBATCH equivalent instead */ -#define KGSL_CONTEXT_SUBMIT_IB_LIST 0x00000004 -#define KGSL_CONTEXT_CTX_SWITCH 0x00000008 -#define KGSL_CONTEXT_PREAMBLE 0x00000010 -#define KGSL_CONTEXT_TRASH_STATE 0x00000020 -#define KGSL_CONTEXT_PER_CONTEXT_TS 0x00000040 -#define KGSL_CONTEXT_USER_GENERATED_TS 0x00000080 -/* This is a cmdbatch exclusive flag - use the CMDBATCH equivalent instead */ -#define KGSL_CONTEXT_END_OF_FRAME 0x00000100 -#define KGSL_CONTEXT_NO_FAULT_TOLERANCE 0x00000200 -/* This is a cmdbatch exclusive flag - use the CMDBATCH equivalent instead */ -#define KGSL_CONTEXT_SYNC 0x00000400 -#define KGSL_CONTEXT_PWR_CONSTRAINT 0x00000800 -#define KGSL_CONTEXT_PRIORITY_MASK 0x0000F000 -#define KGSL_CONTEXT_PRIORITY_SHIFT 12 -#define KGSL_CONTEXT_PRIORITY_UNDEF 0 - -#define KGSL_CONTEXT_IFH_NOP 0x00010000 -#define KGSL_CONTEXT_SECURE 0x00020000 -#define KGSL_CONTEXT_NO_SNAPSHOT 0x00040000 -#define KGSL_CONTEXT_SPARSE 0x00080000 - -#define KGSL_CONTEXT_PREEMPT_STYLE_MASK 0x0E000000 -#define KGSL_CONTEXT_PREEMPT_STYLE_SHIFT 25 -#define KGSL_CONTEXT_PREEMPT_STYLE_DEFAULT 0x0 -#define KGSL_CONTEXT_PREEMPT_STYLE_RINGBUFFER 0x1 -#define KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN 0x2 - -#define KGSL_CONTEXT_TYPE_MASK 0x01F00000 -#define KGSL_CONTEXT_TYPE_SHIFT 20 -#define KGSL_CONTEXT_TYPE_ANY 0 -#define KGSL_CONTEXT_TYPE_GL 1 -#define KGSL_CONTEXT_TYPE_CL 2 -#define KGSL_CONTEXT_TYPE_C2D 3 -#define KGSL_CONTEXT_TYPE_RS 4 -#define KGSL_CONTEXT_TYPE_UNKNOWN 0x1E - -#define KGSL_CONTEXT_INVALIDATE_ON_FAULT 0x10000000 - -#define KGSL_CONTEXT_INVALID 0xffffffff - -/* - * --- command batch flags --- - * The bits that are linked to a KGSL_CONTEXT equivalent are either legacy - * definitions or bits that are valid for both contexts and cmdbatches. To be - * safe the other 8 bits that are still available in the context field should be - * omitted here in case we need to share - the other bits are available for - * cmdbatch only flags as needed - */ -#define KGSL_CMDBATCH_MEMLIST 0x00000001 -#define KGSL_CMDBATCH_MARKER 0x00000002 -#define KGSL_CMDBATCH_SUBMIT_IB_LIST KGSL_CONTEXT_SUBMIT_IB_LIST /* 0x004 */ -#define KGSL_CMDBATCH_CTX_SWITCH KGSL_CONTEXT_CTX_SWITCH /* 0x008 */ -#define KGSL_CMDBATCH_PROFILING 0x00000010 -/* - * KGSL_CMDBATCH_PROFILING must also be set for KGSL_CMDBATCH_PROFILING_KTIME - * to take effect, as the latter only affects the time data returned. - */ -#define KGSL_CMDBATCH_PROFILING_KTIME 0x00000020 -#define KGSL_CMDBATCH_END_OF_FRAME KGSL_CONTEXT_END_OF_FRAME /* 0x100 */ -#define KGSL_CMDBATCH_SYNC KGSL_CONTEXT_SYNC /* 0x400 */ -#define KGSL_CMDBATCH_PWR_CONSTRAINT KGSL_CONTEXT_PWR_CONSTRAINT /* 0x800 */ -#define KGSL_CMDBATCH_SPARSE 0x1000 /* 0x1000 */ - -/* - * Reserve bits [16:19] and bits [28:31] for possible bits shared between - * contexts and command batches. Update this comment as new flags are added. - */ - -/* - * gpu_command_object flags - these flags communicate the type of command or - * memory object being submitted for a GPU command - */ - -/* Flags for GPU command objects */ -#define KGSL_CMDLIST_IB 0x00000001U -#define KGSL_CMDLIST_CTXTSWITCH_PREAMBLE 0x00000002U -#define KGSL_CMDLIST_IB_PREAMBLE 0x00000004U - -/* Flags for GPU command memory objects */ -#define KGSL_OBJLIST_MEMOBJ 0x00000008U -#define KGSL_OBJLIST_PROFILE 0x00000010U - -/* Flags for GPU command sync points */ -#define KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP 0 -#define KGSL_CMD_SYNCPOINT_TYPE_FENCE 1 - -/* --- Memory allocation flags --- */ - -/* General allocation hints */ -#define KGSL_MEMFLAGS_SECURE 0x00000008ULL -#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000U -#define KGSL_MEMFLAGS_GPUWRITEONLY 0x02000000U -#define KGSL_MEMFLAGS_FORCE_32BIT 0x100000000ULL - -/* Flag for binding all the virt range to single phys data */ -#define KGSL_SPARSE_BIND_MULTIPLE_TO_PHYS 0x400000000ULL -#define KGSL_SPARSE_BIND 0x1ULL -#define KGSL_SPARSE_UNBIND 0x2ULL - -/* Memory caching hints */ -#define KGSL_CACHEMODE_MASK 0x0C000000U -#define KGSL_CACHEMODE_SHIFT 26 - -#define KGSL_CACHEMODE_WRITECOMBINE 0 -#define KGSL_CACHEMODE_UNCACHED 1 -#define KGSL_CACHEMODE_WRITETHROUGH 2 -#define KGSL_CACHEMODE_WRITEBACK 3 - -#define KGSL_MEMFLAGS_USE_CPU_MAP 0x10000000ULL -#define KGSL_MEMFLAGS_SPARSE_PHYS 0x20000000ULL -#define KGSL_MEMFLAGS_SPARSE_VIRT 0x40000000ULL -#define KGSL_MEMFLAGS_IOCOHERENT 0x80000000ULL - -/* Memory types for which allocations are made */ -#define KGSL_MEMTYPE_MASK 0x0000FF00 -#define KGSL_MEMTYPE_SHIFT 8 - -#define KGSL_MEMTYPE_OBJECTANY 0 -#define KGSL_MEMTYPE_FRAMEBUFFER 1 -#define KGSL_MEMTYPE_RENDERBUFFER 2 -#define KGSL_MEMTYPE_ARRAYBUFFER 3 -#define KGSL_MEMTYPE_ELEMENTARRAYBUFFER 4 -#define KGSL_MEMTYPE_VERTEXARRAYBUFFER 5 -#define KGSL_MEMTYPE_TEXTURE 6 -#define KGSL_MEMTYPE_SURFACE 7 -#define KGSL_MEMTYPE_EGL_SURFACE 8 -#define KGSL_MEMTYPE_GL 9 -#define KGSL_MEMTYPE_CL 10 -#define KGSL_MEMTYPE_CL_BUFFER_MAP 11 -#define KGSL_MEMTYPE_CL_BUFFER_NOMAP 12 -#define KGSL_MEMTYPE_CL_IMAGE_MAP 13 -#define KGSL_MEMTYPE_CL_IMAGE_NOMAP 14 -#define KGSL_MEMTYPE_CL_KERNEL_STACK 15 -#define KGSL_MEMTYPE_COMMAND 16 -#define KGSL_MEMTYPE_2D 17 -#define KGSL_MEMTYPE_EGL_IMAGE 18 -#define KGSL_MEMTYPE_EGL_SHADOW 19 -#define KGSL_MEMTYPE_MULTISAMPLE 20 -#define KGSL_MEMTYPE_KERNEL 255 - -/* - * Alignment hint, passed as the power of 2 exponent. - * i.e 4k (2^12) would be 12, 64k (2^16)would be 16. - */ -#define KGSL_MEMALIGN_MASK 0x00FF0000 -#define KGSL_MEMALIGN_SHIFT 16 - -enum kgsl_user_mem_type { - KGSL_USER_MEM_TYPE_PMEM = 0x00000000, - KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001, - KGSL_USER_MEM_TYPE_ADDR = 0x00000002, - KGSL_USER_MEM_TYPE_ION = 0x00000003, - /* - * ION type is retained for backwards compatibility but Ion buffers are - * dma-bufs so try to use that naming if we can - */ - KGSL_USER_MEM_TYPE_DMABUF = 0x00000003, - KGSL_USER_MEM_TYPE_MAX = 0x00000007, -}; -#define KGSL_MEMFLAGS_USERMEM_MASK 0x000000e0 -#define KGSL_MEMFLAGS_USERMEM_SHIFT 5 - -/* - * Unfortunately, enum kgsl_user_mem_type starts at 0 which does not - * leave a good value for allocated memory. In the flags we use - * 0 to indicate allocated memory and thus need to add 1 to the enum - * values. - */ -#define KGSL_USERMEM_FLAG(x) (((x) + 1) << KGSL_MEMFLAGS_USERMEM_SHIFT) - -#define KGSL_MEMFLAGS_NOT_USERMEM 0 -#define KGSL_MEMFLAGS_USERMEM_PMEM KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_PMEM) -#define KGSL_MEMFLAGS_USERMEM_ASHMEM \ - KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ASHMEM) -#define KGSL_MEMFLAGS_USERMEM_ADDR KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ADDR) -#define KGSL_MEMFLAGS_USERMEM_ION KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ION) - -/* --- generic KGSL flag values --- */ - -#define KGSL_FLAGS_NORMALMODE 0x00000000 -#define KGSL_FLAGS_SAFEMODE 0x00000001 -#define KGSL_FLAGS_INITIALIZED0 0x00000002 -#define KGSL_FLAGS_INITIALIZED 0x00000004 -#define KGSL_FLAGS_STARTED 0x00000008 -#define KGSL_FLAGS_ACTIVE 0x00000010 -#define KGSL_FLAGS_RESERVED0 0x00000020 -#define KGSL_FLAGS_RESERVED1 0x00000040 -#define KGSL_FLAGS_RESERVED2 0x00000080 -#define KGSL_FLAGS_SOFT_RESET 0x00000100 -#define KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS 0x00000200 - -/* Server Side Sync Timeout in milliseconds */ -#define KGSL_SYNCOBJ_SERVER_TIMEOUT 2000 - -/* UBWC Modes */ -#define KGSL_UBWC_NONE 0 -#define KGSL_UBWC_1_0 1 -#define KGSL_UBWC_2_0 2 -#define KGSL_UBWC_3_0 3 - -/* - * Reset status values for context - */ -enum kgsl_ctx_reset_stat { - KGSL_CTX_STAT_NO_ERROR = 0x00000000, - KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 0x00000001, - KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 0x00000002, - KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 0x00000003 -}; - -#define KGSL_CONVERT_TO_MBPS(val) \ - (val*1000*1000U) - -/* device id */ -enum kgsl_deviceid { - KGSL_DEVICE_3D0 = 0x00000000, - KGSL_DEVICE_MAX -}; - -struct kgsl_devinfo { - - unsigned int device_id; - /* - * chip revision id - * coreid:8 majorrev:8 minorrev:8 patch:8 - */ - unsigned int chip_id; - unsigned int mmu_enabled; - unsigned long gmem_gpubaseaddr; - /* - * This field contains the adreno revision - * number 200, 205, 220, etc... - */ - unsigned int gpu_id; - size_t gmem_sizebytes; -}; - -/* - * struct kgsl_devmemstore - this structure defines the region of memory - * that can be mmap()ed from this driver. The timestamp fields are __volatile__ - * because they are written by the GPU - * @soptimestamp: Start of pipeline timestamp written by GPU before the - * commands in concern are processed - * @sbz: Unused, kept for 8 byte alignment - * @eoptimestamp: End of pipeline timestamp written by GPU after the - * commands in concern are processed - * @sbz2: Unused, kept for 8 byte alignment - * @preempted: Indicates if the context was preempted - * @sbz3: Unused, kept for 8 byte alignment - * @ref_wait_ts: Timestamp on which to generate interrupt, unused now. - * @sbz4: Unused, kept for 8 byte alignment - * @current_context: The current context the GPU is working on - * @sbz5: Unused, kept for 8 byte alignment - */ -struct kgsl_devmemstore { - __volatile__ unsigned int soptimestamp; - unsigned int sbz; - __volatile__ unsigned int eoptimestamp; - unsigned int sbz2; - __volatile__ unsigned int preempted; - unsigned int sbz3; - __volatile__ unsigned int ref_wait_ts; - unsigned int sbz4; - unsigned int current_context; - unsigned int sbz5; -}; - -#define KGSL_MEMSTORE_OFFSET(ctxt_id, field) \ - ((ctxt_id)*sizeof(struct kgsl_devmemstore) + \ - offsetof(struct kgsl_devmemstore, field)) - -/* timestamp id*/ -enum kgsl_timestamp_type { - KGSL_TIMESTAMP_CONSUMED = 0x00000001, /* start-of-pipeline timestamp */ - KGSL_TIMESTAMP_RETIRED = 0x00000002, /* end-of-pipeline timestamp*/ - KGSL_TIMESTAMP_QUEUED = 0x00000003, -}; - -/* property types - used with kgsl_device_getproperty */ -#define KGSL_PROP_DEVICE_INFO 0x1 -#define KGSL_PROP_DEVICE_SHADOW 0x2 -#define KGSL_PROP_DEVICE_POWER 0x3 -#define KGSL_PROP_SHMEM 0x4 -#define KGSL_PROP_SHMEM_APERTURES 0x5 -#define KGSL_PROP_MMU_ENABLE 0x6 -#define KGSL_PROP_INTERRUPT_WAITS 0x7 -#define KGSL_PROP_VERSION 0x8 -#define KGSL_PROP_GPU_RESET_STAT 0x9 -#define KGSL_PROP_PWRCTRL 0xE -#define KGSL_PROP_PWR_CONSTRAINT 0x12 -#define KGSL_PROP_UCHE_GMEM_VADDR 0x13 -#define KGSL_PROP_SP_GENERIC_MEM 0x14 -#define KGSL_PROP_UCODE_VERSION 0x15 -#define KGSL_PROP_GPMU_VERSION 0x16 -#define KGSL_PROP_HIGHEST_BANK_BIT 0x17 -#define KGSL_PROP_DEVICE_BITNESS 0x18 -#define KGSL_PROP_DEVICE_QDSS_STM 0x19 -#define KGSL_PROP_MIN_ACCESS_LENGTH 0x1A -#define KGSL_PROP_UBWC_MODE 0x1B -#define KGSL_PROP_DEVICE_QTIMER 0x20 -#define KGSL_PROP_L3_PWR_CONSTRAINT 0x22 - -struct kgsl_shadowprop { - unsigned long gpuaddr; - size_t size; - unsigned int flags; /* contains KGSL_FLAGS_ values */ -}; - -struct kgsl_qdss_stm_prop { - uint64_t gpuaddr; - uint64_t size; -}; - -struct kgsl_qtimer_prop { - uint64_t gpuaddr; - uint64_t size; -}; - -struct kgsl_version { - unsigned int drv_major; - unsigned int drv_minor; - unsigned int dev_major; - unsigned int dev_minor; -}; - -struct kgsl_sp_generic_mem { - uint64_t local; - uint64_t pvt; -}; - -struct kgsl_ucode_version { - unsigned int pfp; - unsigned int pm4; -}; - -struct kgsl_gpmu_version { - unsigned int major; - unsigned int minor; - unsigned int features; -}; - -/* Performance counter groups */ - -#define KGSL_PERFCOUNTER_GROUP_CP 0x0 -#define KGSL_PERFCOUNTER_GROUP_RBBM 0x1 -#define KGSL_PERFCOUNTER_GROUP_PC 0x2 -#define KGSL_PERFCOUNTER_GROUP_VFD 0x3 -#define KGSL_PERFCOUNTER_GROUP_HLSQ 0x4 -#define KGSL_PERFCOUNTER_GROUP_VPC 0x5 -#define KGSL_PERFCOUNTER_GROUP_TSE 0x6 -#define KGSL_PERFCOUNTER_GROUP_RAS 0x7 -#define KGSL_PERFCOUNTER_GROUP_UCHE 0x8 -#define KGSL_PERFCOUNTER_GROUP_TP 0x9 -#define KGSL_PERFCOUNTER_GROUP_SP 0xA -#define KGSL_PERFCOUNTER_GROUP_RB 0xB -#define KGSL_PERFCOUNTER_GROUP_PWR 0xC -#define KGSL_PERFCOUNTER_GROUP_VBIF 0xD -#define KGSL_PERFCOUNTER_GROUP_VBIF_PWR 0xE -#define KGSL_PERFCOUNTER_GROUP_MH 0xF -#define KGSL_PERFCOUNTER_GROUP_PA_SU 0x10 -#define KGSL_PERFCOUNTER_GROUP_SQ 0x11 -#define KGSL_PERFCOUNTER_GROUP_SX 0x12 -#define KGSL_PERFCOUNTER_GROUP_TCF 0x13 -#define KGSL_PERFCOUNTER_GROUP_TCM 0x14 -#define KGSL_PERFCOUNTER_GROUP_TCR 0x15 -#define KGSL_PERFCOUNTER_GROUP_L2 0x16 -#define KGSL_PERFCOUNTER_GROUP_VSC 0x17 -#define KGSL_PERFCOUNTER_GROUP_CCU 0x18 -#define KGSL_PERFCOUNTER_GROUP_LRZ 0x19 -#define KGSL_PERFCOUNTER_GROUP_CMP 0x1A -#define KGSL_PERFCOUNTER_GROUP_ALWAYSON 0x1B -#define KGSL_PERFCOUNTER_GROUP_SP_PWR 0x1C -#define KGSL_PERFCOUNTER_GROUP_TP_PWR 0x1D -#define KGSL_PERFCOUNTER_GROUP_RB_PWR 0x1E -#define KGSL_PERFCOUNTER_GROUP_CCU_PWR 0x1F -#define KGSL_PERFCOUNTER_GROUP_UCHE_PWR 0x20 -#define KGSL_PERFCOUNTER_GROUP_CP_PWR 0x21 -#define KGSL_PERFCOUNTER_GROUP_GPMU_PWR 0x22 -#define KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR 0x23 -#define KGSL_PERFCOUNTER_GROUP_MAX 0x24 - -#define KGSL_PERFCOUNTER_NOT_USED 0xFFFFFFFF -#define KGSL_PERFCOUNTER_BROKEN 0xFFFFFFFE - -/* structure holds list of ibs */ -struct kgsl_ibdesc { - unsigned long gpuaddr; - unsigned long __pad; - size_t sizedwords; - unsigned int ctrl; -}; - -/** - * struct kgsl_cmdbatch_profiling_buffer - * @wall_clock_s: Ringbuffer submission time (seconds). - * If KGSL_CMDBATCH_PROFILING_KTIME is set, time is provided - * in kernel clocks, otherwise wall clock time is used. - * @wall_clock_ns: Ringbuffer submission time (nanoseconds). - * If KGSL_CMDBATCH_PROFILING_KTIME is set time is provided - * in kernel clocks, otherwise wall clock time is used. - * @gpu_ticks_queued: GPU ticks at ringbuffer submission - * @gpu_ticks_submitted: GPU ticks when starting cmdbatch execution - * @gpu_ticks_retired: GPU ticks when finishing cmdbatch execution - * - * This structure defines the profiling buffer used to measure cmdbatch - * execution time - */ -struct kgsl_cmdbatch_profiling_buffer { - uint64_t wall_clock_s; - uint64_t wall_clock_ns; - uint64_t gpu_ticks_queued; - uint64_t gpu_ticks_submitted; - uint64_t gpu_ticks_retired; -}; - -/* ioctls */ -#define KGSL_IOC_TYPE 0x09 - -/* - * get misc info about the GPU - * type should be a value from enum kgsl_property_type - * value points to a structure that varies based on type - * sizebytes is sizeof() that structure - * for KGSL_PROP_DEVICE_INFO, use struct kgsl_devinfo - * this structure contaings hardware versioning info. - * for KGSL_PROP_DEVICE_SHADOW, use struct kgsl_shadowprop - * this is used to find mmap() offset and sizes for mapping - * struct kgsl_memstore into userspace. - */ -struct kgsl_device_getproperty { - unsigned int type; - void *value; - size_t sizebytes; -}; - -#define IOCTL_KGSL_DEVICE_GETPROPERTY \ - _IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty) - -/* IOCTL_KGSL_DEVICE_READ (0x3) - removed 03/2012 - */ - -/* block until the GPU has executed past a given timestamp - * timeout is in milliseconds. - */ -struct kgsl_device_waittimestamp { - unsigned int timestamp; - unsigned int timeout; -}; - -#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP \ - _IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp) - -struct kgsl_device_waittimestamp_ctxtid { - unsigned int context_id; - unsigned int timestamp; - unsigned int timeout; -}; - -#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID \ - _IOW(KGSL_IOC_TYPE, 0x7, struct kgsl_device_waittimestamp_ctxtid) - -/* DEPRECATED: issue indirect commands to the GPU. - * drawctxt_id must have been created with IOCTL_KGSL_DRAWCTXT_CREATE - * ibaddr and sizedwords must specify a subset of a buffer created - * with IOCTL_KGSL_SHAREDMEM_FROM_PMEM - * flags may be a mask of KGSL_CONTEXT_ values - * timestamp is a returned counter value which can be passed to - * other ioctls to determine when the commands have been executed by - * the GPU. - * - * This function is deprecated - consider using IOCTL_KGSL_SUBMIT_COMMANDS - * instead - */ -struct kgsl_ringbuffer_issueibcmds { - unsigned int drawctxt_id; - unsigned long ibdesc_addr; - unsigned int numibs; - unsigned int timestamp; /*output param */ - unsigned int flags; -}; - -#define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS \ - _IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds) - -/* read the most recently executed timestamp value - * type should be a value from enum kgsl_timestamp_type - */ -struct kgsl_cmdstream_readtimestamp { - unsigned int type; - unsigned int timestamp; /*output param */ -}; - -#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD \ - _IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) - -#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP \ - _IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) - -/* free memory when the GPU reaches a given timestamp. - * gpuaddr specify a memory region created by a - * IOCTL_KGSL_SHAREDMEM_FROM_PMEM call - * type should be a value from enum kgsl_timestamp_type - */ -struct kgsl_cmdstream_freememontimestamp { - unsigned long gpuaddr; - unsigned int type; - unsigned int timestamp; -}; - -#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP \ - _IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) - -/* - * Previous versions of this header had incorrectly defined - * IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP as a read-only ioctl instead - * of a write only ioctl. To ensure binary compatibility, the following - * #define will be used to intercept the incorrect ioctl - */ - -#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD \ - _IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) - -/* create a draw context, which is used to preserve GPU state. - * The flags field may contain a mask KGSL_CONTEXT_* values - */ -struct kgsl_drawctxt_create { - unsigned int flags; - unsigned int drawctxt_id; /*output param */ -}; - -#define IOCTL_KGSL_DRAWCTXT_CREATE \ - _IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create) - -/* destroy a draw context */ -struct kgsl_drawctxt_destroy { - unsigned int drawctxt_id; -}; - -#define IOCTL_KGSL_DRAWCTXT_DESTROY \ - _IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy) - -/* - * add a block of pmem, fb, ashmem or user allocated address - * into the GPU address space - */ -struct kgsl_map_user_mem { - int fd; - unsigned long gpuaddr; /*output param */ - size_t len; - size_t offset; - unsigned long hostptr; /*input param */ - enum kgsl_user_mem_type memtype; - unsigned int flags; -}; - -#define IOCTL_KGSL_MAP_USER_MEM \ - _IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem) - -struct kgsl_cmdstream_readtimestamp_ctxtid { - unsigned int context_id; - unsigned int type; - unsigned int timestamp; /*output param */ -}; - -#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID \ - _IOWR(KGSL_IOC_TYPE, 0x16, struct kgsl_cmdstream_readtimestamp_ctxtid) - -struct kgsl_cmdstream_freememontimestamp_ctxtid { - unsigned int context_id; - unsigned long gpuaddr; - unsigned int type; - unsigned int timestamp; -}; - -#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID \ - _IOW(KGSL_IOC_TYPE, 0x17, \ - struct kgsl_cmdstream_freememontimestamp_ctxtid) - -/* add a block of pmem or fb into the GPU address space */ -struct kgsl_sharedmem_from_pmem { - int pmem_fd; - unsigned long gpuaddr; /*output param */ - unsigned int len; - unsigned int offset; -}; - -#define IOCTL_KGSL_SHAREDMEM_FROM_PMEM \ - _IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem) - -/* remove memory from the GPU's address space */ -struct kgsl_sharedmem_free { - unsigned long gpuaddr; -}; - -#define IOCTL_KGSL_SHAREDMEM_FREE \ - _IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free) - -struct kgsl_cff_user_event { - unsigned char cff_opcode; - unsigned int op1; - unsigned int op2; - unsigned int op3; - unsigned int op4; - unsigned int op5; - unsigned int __pad[2]; -}; - -#define IOCTL_KGSL_CFF_USER_EVENT \ - _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event) - -struct kgsl_gmem_desc { - unsigned int x; - unsigned int y; - unsigned int width; - unsigned int height; - unsigned int pitch; -}; - -struct kgsl_buffer_desc { - void *hostptr; - unsigned long gpuaddr; - int size; - unsigned int format; - unsigned int pitch; - unsigned int enabled; -}; - -struct kgsl_bind_gmem_shadow { - unsigned int drawctxt_id; - struct kgsl_gmem_desc gmem_desc; - unsigned int shadow_x; - unsigned int shadow_y; - struct kgsl_buffer_desc shadow_buffer; - unsigned int buffer_id; -}; - -#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW \ - _IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow) - -/* add a block of memory into the GPU address space */ - -/* - * IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC deprecated 09/2012 - * use IOCTL_KGSL_GPUMEM_ALLOC instead - */ - -struct kgsl_sharedmem_from_vmalloc { - unsigned long gpuaddr; /*output param */ - unsigned int hostptr; - unsigned int flags; -}; - -#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC \ - _IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc) - -/* - * This is being deprecated in favor of IOCTL_KGSL_GPUMEM_CACHE_SYNC which - * supports both directions (flush and invalidate). This code will still - * work, but by definition it will do a flush of the cache which might not be - * what you want to have happen on a buffer following a GPU operation. It is - * safer to go with IOCTL_KGSL_GPUMEM_CACHE_SYNC - */ - -#define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE \ - _IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free) - -struct kgsl_drawctxt_set_bin_base_offset { - unsigned int drawctxt_id; - unsigned int offset; -}; - -#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET \ - _IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset) - -enum kgsl_cmdwindow_type { - KGSL_CMDWINDOW_MIN = 0x00000000, - KGSL_CMDWINDOW_2D = 0x00000000, - KGSL_CMDWINDOW_3D = 0x00000001, /* legacy */ - KGSL_CMDWINDOW_MMU = 0x00000002, - KGSL_CMDWINDOW_ARBITER = 0x000000FF, - KGSL_CMDWINDOW_MAX = 0x000000FF, -}; - -/* write to the command window */ -struct kgsl_cmdwindow_write { - enum kgsl_cmdwindow_type target; - unsigned int addr; - unsigned int data; -}; - -#define IOCTL_KGSL_CMDWINDOW_WRITE \ - _IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write) - -struct kgsl_gpumem_alloc { - unsigned long gpuaddr; /* output param */ - size_t size; - unsigned int flags; -}; - -#define IOCTL_KGSL_GPUMEM_ALLOC \ - _IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc) - -struct kgsl_cff_syncmem { - unsigned long gpuaddr; - size_t len; - unsigned int __pad[2]; /* For future binary compatibility */ -}; - -#define IOCTL_KGSL_CFF_SYNCMEM \ - _IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem) - -/* - * A timestamp event allows the user space to register an action following an - * expired timestamp. Note IOCTL_KGSL_TIMESTAMP_EVENT has been redefined to - * _IOWR to support fences which need to return a fd for the priv parameter. - */ - -struct kgsl_timestamp_event { - int type; /* Type of event (see list below) */ - unsigned int timestamp; /* Timestamp to trigger event on */ - unsigned int context_id; /* Context for the timestamp */ - void *priv; /* Pointer to the event specific blob */ - size_t len; /* Size of the event specific blob */ -}; - -#define IOCTL_KGSL_TIMESTAMP_EVENT_OLD \ - _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_timestamp_event) - -/* A genlock timestamp event releases an existing lock on timestamp expire */ - -#define KGSL_TIMESTAMP_EVENT_GENLOCK 1 - -struct kgsl_timestamp_event_genlock { - int handle; /* Handle of the genlock lock to release */ -}; - -/* A fence timestamp event releases an existing lock on timestamp expire */ - -#define KGSL_TIMESTAMP_EVENT_FENCE 2 - -struct kgsl_timestamp_event_fence { - int fence_fd; /* Fence to signal */ -}; - -/* - * Set a property within the kernel. Uses the same structure as - * IOCTL_KGSL_GETPROPERTY - */ - -#define IOCTL_KGSL_SETPROPERTY \ - _IOW(KGSL_IOC_TYPE, 0x32, struct kgsl_device_getproperty) - -#define IOCTL_KGSL_TIMESTAMP_EVENT \ - _IOWR(KGSL_IOC_TYPE, 0x33, struct kgsl_timestamp_event) - -/** - * struct kgsl_gpumem_alloc_id - argument to IOCTL_KGSL_GPUMEM_ALLOC_ID - * @id: returned id value for this allocation. - * @flags: mask of KGSL_MEM* values requested and actual flags on return. - * @size: requested size of the allocation and actual size on return. - * @mmapsize: returned size to pass to mmap() which may be larger than 'size' - * @gpuaddr: returned GPU address for the allocation - * - * Allocate memory for access by the GPU. The flags and size fields are echoed - * back by the kernel, so that the caller can know if the request was - * adjusted. - * - * Supported flags: - * KGSL_MEMFLAGS_GPUREADONLY: the GPU will be unable to write to the buffer - * KGSL_MEMTYPE*: usage hint for debugging aid - * KGSL_MEMALIGN*: alignment hint, may be ignored or adjusted by the kernel. - * KGSL_MEMFLAGS_USE_CPU_MAP: If set on call and return, the returned GPU - * address will be 0. Calling mmap() will set the GPU address. - */ -struct kgsl_gpumem_alloc_id { - unsigned int id; - unsigned int flags; - size_t size; - size_t mmapsize; - unsigned long gpuaddr; -/* private: reserved for future use*/ - unsigned long __pad[2]; -}; - -#define IOCTL_KGSL_GPUMEM_ALLOC_ID \ - _IOWR(KGSL_IOC_TYPE, 0x34, struct kgsl_gpumem_alloc_id) - -/** - * struct kgsl_gpumem_free_id - argument to IOCTL_KGSL_GPUMEM_FREE_ID - * @id: GPU allocation id to free - * - * Free an allocation by id, in case a GPU address has not been assigned or - * is unknown. Freeing an allocation by id with this ioctl or by GPU address - * with IOCTL_KGSL_SHAREDMEM_FREE are equivalent. - */ -struct kgsl_gpumem_free_id { - unsigned int id; -/* private: reserved for future use*/ - unsigned int __pad; -}; - -#define IOCTL_KGSL_GPUMEM_FREE_ID \ - _IOWR(KGSL_IOC_TYPE, 0x35, struct kgsl_gpumem_free_id) - -/** - * struct kgsl_gpumem_get_info - argument to IOCTL_KGSL_GPUMEM_GET_INFO - * @gpuaddr: GPU address to query. Also set on return. - * @id: GPU allocation id to query. Also set on return. - * @flags: returned mask of KGSL_MEM* values. - * @size: returned size of the allocation. - * @mmapsize: returned size to pass mmap(), which may be larger than 'size' - * @useraddr: returned address of the userspace mapping for this buffer - * - * This ioctl allows querying of all user visible attributes of an existing - * allocation, by either the GPU address or the id returned by a previous - * call to IOCTL_KGSL_GPUMEM_ALLOC_ID. Legacy allocation ioctls may not - * return all attributes so this ioctl can be used to look them up if needed. - * - */ -struct kgsl_gpumem_get_info { - unsigned long gpuaddr; - unsigned int id; - unsigned int flags; - size_t size; - size_t mmapsize; - unsigned long useraddr; -/* private: reserved for future use*/ - unsigned long __pad[4]; -}; - -#define IOCTL_KGSL_GPUMEM_GET_INFO\ - _IOWR(KGSL_IOC_TYPE, 0x36, struct kgsl_gpumem_get_info) - -/** - * struct kgsl_gpumem_sync_cache - argument to IOCTL_KGSL_GPUMEM_SYNC_CACHE - * @gpuaddr: GPU address of the buffer to sync. - * @id: id of the buffer to sync. Either gpuaddr or id is sufficient. - * @op: a mask of KGSL_GPUMEM_CACHE_* values - * @offset: offset into the buffer - * @length: number of bytes starting from offset to perform - * the cache operation on - * - * Sync the L2 cache for memory headed to and from the GPU - this replaces - * KGSL_SHAREDMEM_FLUSH_CACHE since it can handle cache management for both - * directions - * - */ -struct kgsl_gpumem_sync_cache { - unsigned long gpuaddr; - unsigned int id; - unsigned int op; - size_t offset; - size_t length; -}; - -#define KGSL_GPUMEM_CACHE_CLEAN (1 << 0) -#define KGSL_GPUMEM_CACHE_TO_GPU KGSL_GPUMEM_CACHE_CLEAN - -#define KGSL_GPUMEM_CACHE_INV (1 << 1) -#define KGSL_GPUMEM_CACHE_FROM_GPU KGSL_GPUMEM_CACHE_INV - -#define KGSL_GPUMEM_CACHE_FLUSH \ - (KGSL_GPUMEM_CACHE_CLEAN | KGSL_GPUMEM_CACHE_INV) - -/* Flag to ensure backwards compatibility of kgsl_gpumem_sync_cache struct */ -#define KGSL_GPUMEM_CACHE_RANGE (1 << 31U) - -#define IOCTL_KGSL_GPUMEM_SYNC_CACHE \ - _IOW(KGSL_IOC_TYPE, 0x37, struct kgsl_gpumem_sync_cache) - -/** - * struct kgsl_perfcounter_get - argument to IOCTL_KGSL_PERFCOUNTER_GET - * @groupid: Performance counter group ID - * @countable: Countable to select within the group - * @offset: Return offset of the reserved LO counter - * @offset_hi: Return offset of the reserved HI counter - * - * Get an available performance counter from a specified groupid. The offset - * of the performance counter will be returned after successfully assigning - * the countable to the counter for the specified group. An error will be - * returned and an offset of 0 if the groupid is invalid or there are no - * more counters left. After successfully getting a perfcounter, the user - * must call kgsl_perfcounter_put(groupid, contable) when finished with - * the perfcounter to clear up perfcounter resources. - * - */ -struct kgsl_perfcounter_get { - unsigned int groupid; - unsigned int countable; - unsigned int offset; - unsigned int offset_hi; -/* private: reserved for future use */ - unsigned int __pad; /* For future binary compatibility */ -}; - -#define IOCTL_KGSL_PERFCOUNTER_GET \ - _IOWR(KGSL_IOC_TYPE, 0x38, struct kgsl_perfcounter_get) - -/** - * struct kgsl_perfcounter_put - argument to IOCTL_KGSL_PERFCOUNTER_PUT - * @groupid: Performance counter group ID - * @countable: Countable to release within the group - * - * Put an allocated performance counter to allow others to have access to the - * resource that was previously taken. This is only to be called after - * successfully getting a performance counter from kgsl_perfcounter_get(). - * - */ -struct kgsl_perfcounter_put { - unsigned int groupid; - unsigned int countable; -/* private: reserved for future use */ - unsigned int __pad[2]; /* For future binary compatibility */ -}; - -#define IOCTL_KGSL_PERFCOUNTER_PUT \ - _IOW(KGSL_IOC_TYPE, 0x39, struct kgsl_perfcounter_put) - -/** - * struct kgsl_perfcounter_query - argument to IOCTL_KGSL_PERFCOUNTER_QUERY - * @groupid: Performance counter group ID - * @countable: Return active countables array - * @size: Size of active countables array - * @max_counters: Return total number counters for the group ID - * - * Query the available performance counters given a groupid. The array - * *countables is used to return the current active countables in counters. - * The size of the array is passed in so the kernel will only write at most - * size or counter->size for the group id. The total number of available - * counters for the group ID is returned in max_counters. - * If the array or size passed in are invalid, then only the maximum number - * of counters will be returned, no data will be written to *countables. - * If the groupid is invalid an error code will be returned. - * - */ -struct kgsl_perfcounter_query { - unsigned int groupid; - /* Array to return the current countable for up to size counters */ - unsigned int *countables; - unsigned int count; - unsigned int max_counters; -/* private: reserved for future use */ - unsigned int __pad[2]; /* For future binary compatibility */ -}; - -#define IOCTL_KGSL_PERFCOUNTER_QUERY \ - _IOWR(KGSL_IOC_TYPE, 0x3A, struct kgsl_perfcounter_query) - -/** - * struct kgsl_perfcounter_query - argument to IOCTL_KGSL_PERFCOUNTER_QUERY - * @groupid: Performance counter group IDs - * @countable: Performance counter countable IDs - * @value: Return performance counter reads - * @size: Size of all arrays (groupid/countable pair and return value) - * - * Read in the current value of a performance counter given by the groupid - * and countable. - * - */ - -struct kgsl_perfcounter_read_group { - unsigned int groupid; - unsigned int countable; - unsigned long long value; -}; - -struct kgsl_perfcounter_read { - struct kgsl_perfcounter_read_group *reads; - unsigned int count; -/* private: reserved for future use */ - unsigned int __pad[2]; /* For future binary compatibility */ -}; - -#define IOCTL_KGSL_PERFCOUNTER_READ \ - _IOWR(KGSL_IOC_TYPE, 0x3B, struct kgsl_perfcounter_read) -/* - * struct kgsl_gpumem_sync_cache_bulk - argument to - * IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK - * @id_list: list of GPU buffer ids of the buffers to sync - * @count: number of GPU buffer ids in id_list - * @op: a mask of KGSL_GPUMEM_CACHE_* values - * - * Sync the cache for memory headed to and from the GPU. Certain - * optimizations can be made on the cache operation based on the total - * size of the working set of memory to be managed. - */ -struct kgsl_gpumem_sync_cache_bulk { - unsigned int *id_list; - unsigned int count; - unsigned int op; -/* private: reserved for future use */ - unsigned int __pad[2]; /* For future binary compatibility */ -}; - -#define IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK \ - _IOWR(KGSL_IOC_TYPE, 0x3C, struct kgsl_gpumem_sync_cache_bulk) - -/* - * struct kgsl_cmd_syncpoint_timestamp - * @context_id: ID of a KGSL context - * @timestamp: GPU timestamp - * - * This structure defines a syncpoint comprising a context/timestamp pair. A - * list of these may be passed by IOCTL_KGSL_SUBMIT_COMMANDS to define - * dependencies that must be met before the command can be submitted to the - * hardware - */ -struct kgsl_cmd_syncpoint_timestamp { - unsigned int context_id; - unsigned int timestamp; -}; - -struct kgsl_cmd_syncpoint_fence { - int fd; -}; - -/** - * struct kgsl_cmd_syncpoint - Define a sync point for a command batch - * @type: type of sync point defined here - * @priv: Pointer to the type specific buffer - * @size: Size of the type specific buffer - * - * This structure contains pointers defining a specific command sync point. - * The pointer and size should point to a type appropriate structure. - */ -struct kgsl_cmd_syncpoint { - int type; - void *priv; - size_t size; -}; - -/* Flag to indicate that the cmdlist may contain memlists */ -#define KGSL_IBDESC_MEMLIST 0x1 - -/* Flag to point out the cmdbatch profiling buffer in the memlist */ -#define KGSL_IBDESC_PROFILING_BUFFER 0x2 - -/** - * struct kgsl_submit_commands - Argument to IOCTL_KGSL_SUBMIT_COMMANDS - * @context_id: KGSL context ID that owns the commands - * @flags: - * @cmdlist: User pointer to a list of kgsl_ibdesc structures - * @numcmds: Number of commands listed in cmdlist - * @synclist: User pointer to a list of kgsl_cmd_syncpoint structures - * @numsyncs: Number of sync points listed in synclist - * @timestamp: On entry the a user defined timestamp, on exist the timestamp - * assigned to the command batch - * - * This structure specifies a command to send to the GPU hardware. This is - * similar to kgsl_issueibcmds expect that it doesn't support the legacy way to - * submit IB lists and it adds sync points to block the IB until the - * dependencies are satisified. This entry point is the new and preferred way - * to submit commands to the GPU. The memory list can be used to specify all - * memory that is referrenced in the current set of commands. - */ - -struct kgsl_submit_commands { - unsigned int context_id; - unsigned int flags; - struct kgsl_ibdesc *cmdlist; - unsigned int numcmds; - struct kgsl_cmd_syncpoint *synclist; - unsigned int numsyncs; - unsigned int timestamp; -/* private: reserved for future use */ - unsigned int __pad[4]; -}; - -#define IOCTL_KGSL_SUBMIT_COMMANDS \ - _IOWR(KGSL_IOC_TYPE, 0x3D, struct kgsl_submit_commands) - -/** - * struct kgsl_device_constraint - device constraint argument - * @context_id: KGSL context ID - * @type: type of constraint i.e pwrlevel/none - * @data: constraint data - * @size: size of the constraint data - */ -struct kgsl_device_constraint { - unsigned int type; - unsigned int context_id; - void *data; - size_t size; -}; - -/* Constraint Type*/ -#define KGSL_CONSTRAINT_NONE 0 -#define KGSL_CONSTRAINT_PWRLEVEL 1 - -/* L3 constraint Type */ -#define KGSL_CONSTRAINT_L3_NONE 2 -#define KGSL_CONSTRAINT_L3_PWRLEVEL 3 - -/* PWRLEVEL constraint level*/ -/* set to min frequency */ -#define KGSL_CONSTRAINT_PWR_MIN 0 -/* set to max frequency */ -#define KGSL_CONSTRAINT_PWR_MAX 1 - -/* L3 PWRLEVEL constraint level */ -#define KGSL_CONSTRAINT_L3_PWR_MED 0 -#define KGSL_CONSTRAINT_L3_PWR_MAX 1 - -struct kgsl_device_constraint_pwrlevel { - unsigned int level; -}; - -/** - * struct kgsl_syncsource_create - Argument to IOCTL_KGSL_SYNCSOURCE_CREATE - * @id: returned id for the syncsource that was created. - * - * This ioctl creates a userspace sync timeline. - */ - -struct kgsl_syncsource_create { - unsigned int id; -/* private: reserved for future use */ - unsigned int __pad[3]; -}; - -#define IOCTL_KGSL_SYNCSOURCE_CREATE \ - _IOWR(KGSL_IOC_TYPE, 0x40, struct kgsl_syncsource_create) - -/** - * struct kgsl_syncsource_destroy - Argument to IOCTL_KGSL_SYNCSOURCE_DESTROY - * @id: syncsource id to destroy - * - * This ioctl creates a userspace sync timeline. - */ - -struct kgsl_syncsource_destroy { - unsigned int id; -/* private: reserved for future use */ - unsigned int __pad[3]; -}; - -#define IOCTL_KGSL_SYNCSOURCE_DESTROY \ - _IOWR(KGSL_IOC_TYPE, 0x41, struct kgsl_syncsource_destroy) - -/** - * struct kgsl_syncsource_create_fence - Argument to - * IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE - * @id: syncsource id - * @fence_fd: returned sync_fence fd - * - * Create a fence that may be signaled by userspace by calling - * IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE. There are no order dependencies between - * these fences. - */ -struct kgsl_syncsource_create_fence { - unsigned int id; - int fence_fd; -/* private: reserved for future use */ - unsigned int __pad[4]; -}; - -/** - * struct kgsl_syncsource_signal_fence - Argument to - * IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE - * @id: syncsource id - * @fence_fd: sync_fence fd to signal - * - * Signal a fence that was created by a IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE - * call using the same syncsource id. This allows a fence to be shared - * to other processes but only signaled by the process owning the fd - * used to create the fence. - */ -#define IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE \ - _IOWR(KGSL_IOC_TYPE, 0x42, struct kgsl_syncsource_create_fence) - -struct kgsl_syncsource_signal_fence { - unsigned int id; - int fence_fd; -/* private: reserved for future use */ - unsigned int __pad[4]; -}; - -#define IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE \ - _IOWR(KGSL_IOC_TYPE, 0x43, struct kgsl_syncsource_signal_fence) - -/** - * struct kgsl_cff_sync_gpuobj - Argument to IOCTL_KGSL_CFF_SYNC_GPUOBJ - * @offset: Offset into the GPU object to sync - * @length: Number of bytes to sync - * @id: ID of the GPU object to sync - */ -struct kgsl_cff_sync_gpuobj { - uint64_t offset; - uint64_t length; - unsigned int id; -}; - -#define IOCTL_KGSL_CFF_SYNC_GPUOBJ \ - _IOW(KGSL_IOC_TYPE, 0x44, struct kgsl_cff_sync_gpuobj) - -/** - * struct kgsl_gpuobj_alloc - Argument to IOCTL_KGSL_GPUOBJ_ALLOC - * @size: Size in bytes of the object to allocate - * @flags: mask of KGSL_MEMFLAG_* bits - * @va_len: Size in bytes of the virtual region to allocate - * @mmapsize: Returns the mmap() size of the object - * @id: Returns the GPU object ID of the new object - * @metadata_len: Length of the metdata to copy from the user - * @metadata: Pointer to the user specified metadata to store for the object - */ -struct kgsl_gpuobj_alloc { - uint64_t size; - uint64_t flags; - uint64_t va_len; - uint64_t mmapsize; - unsigned int id; - unsigned int metadata_len; - uint64_t metadata; -}; - -/* Let the user know that this header supports the gpuobj metadata */ -#define KGSL_GPUOBJ_ALLOC_METADATA_MAX 64 - -#define IOCTL_KGSL_GPUOBJ_ALLOC \ - _IOWR(KGSL_IOC_TYPE, 0x45, struct kgsl_gpuobj_alloc) - -/** - * struct kgsl_gpuobj_free - Argument to IOCTL_KGLS_GPUOBJ_FREE - * @flags: Mask of: KGSL_GUPOBJ_FREE_ON_EVENT - * @priv: Pointer to the private object if KGSL_GPUOBJ_FREE_ON_EVENT is - * specified - * @id: ID of the GPU object to free - * @type: If KGSL_GPUOBJ_FREE_ON_EVENT is specified, the type of asynchronous - * event to free on - * @len: Length of the data passed in priv - */ -struct kgsl_gpuobj_free { - uint64_t flags; - uint64_t priv; - unsigned int id; - unsigned int type; - unsigned int len; -}; - -#define KGSL_GPUOBJ_FREE_ON_EVENT 1 - -#define KGSL_GPU_EVENT_TIMESTAMP 1 -#define KGSL_GPU_EVENT_FENCE 2 - -/** - * struct kgsl_gpu_event_timestamp - Specifies a timestamp event to free a GPU - * object on - * @context_id: ID of the timestamp event to wait for - * @timestamp: Timestamp of the timestamp event to wait for - */ -struct kgsl_gpu_event_timestamp { - unsigned int context_id; - unsigned int timestamp; -}; - -/** - * struct kgsl_gpu_event_fence - Specifies a fence ID to to free a GPU object on - * @fd: File descriptor for the fence - */ -struct kgsl_gpu_event_fence { - int fd; -}; - -#define IOCTL_KGSL_GPUOBJ_FREE \ - _IOW(KGSL_IOC_TYPE, 0x46, struct kgsl_gpuobj_free) - -/** - * struct kgsl_gpuobj_info - argument to IOCTL_KGSL_GPUOBJ_INFO - * @gpuaddr: GPU address of the object - * @flags: Current flags for the object - * @size: Size of the object - * @va_len: VA size of the object - * @va_addr: Virtual address of the object (if it is mapped) - * id - GPU object ID of the object to query - */ -struct kgsl_gpuobj_info { - uint64_t gpuaddr; - uint64_t flags; - uint64_t size; - uint64_t va_len; - uint64_t va_addr; - unsigned int id; -}; - -#define IOCTL_KGSL_GPUOBJ_INFO \ - _IOWR(KGSL_IOC_TYPE, 0x47, struct kgsl_gpuobj_info) - -/** - * struct kgsl_gpuobj_import - argument to IOCTL_KGSL_GPUOBJ_IMPORT - * @priv: Pointer to the private data for the import type - * @priv_len: Length of the private data - * @flags: Mask of KGSL_MEMFLAG_ flags - * @type: Type of the import (KGSL_USER_MEM_TYPE_*) - * @id: Returns the ID of the new GPU object - */ -struct kgsl_gpuobj_import { - uint64_t priv; - uint64_t priv_len; - uint64_t flags; - unsigned int type; - unsigned int id; -}; - -/** - * struct kgsl_gpuobj_import_dma_buf - import a dmabuf object - * @fd: File descriptor for the dma-buf object - */ -struct kgsl_gpuobj_import_dma_buf { - int fd; -}; - -/** - * struct kgsl_gpuobj_import_useraddr - import an object based on a useraddr - * @virtaddr: Virtual address of the object to import - */ -struct kgsl_gpuobj_import_useraddr { - uint64_t virtaddr; -}; - -#define IOCTL_KGSL_GPUOBJ_IMPORT \ - _IOWR(KGSL_IOC_TYPE, 0x48, struct kgsl_gpuobj_import) - -/** - * struct kgsl_gpuobj_sync_obj - Individual GPU object to sync - * @offset: Offset within the GPU object to sync - * @length: Number of bytes to sync - * @id: ID of the GPU object to sync - * @op: Cache operation to execute - */ - -struct kgsl_gpuobj_sync_obj { - uint64_t offset; - uint64_t length; - unsigned int id; - unsigned int op; -}; - -/** - * struct kgsl_gpuobj_sync - Argument for IOCTL_KGSL_GPUOBJ_SYNC - * @objs: Pointer to an array of kgsl_gpuobj_sync_obj structs - * @obj_len: Size of each item in the array - * @count: Number of items in the array - */ - -struct kgsl_gpuobj_sync { - uint64_t objs; - unsigned int obj_len; - unsigned int count; -}; - -#define IOCTL_KGSL_GPUOBJ_SYNC \ - _IOW(KGSL_IOC_TYPE, 0x49, struct kgsl_gpuobj_sync) - -/** - * struct kgsl_command_object - GPU command object - * @offset: GPU address offset of the object - * @gpuaddr: GPU address of the object - * @size: Size of the object - * @flags: Current flags for the object - * @id - GPU command object ID - */ -struct kgsl_command_object { - uint64_t offset; - uint64_t gpuaddr; - uint64_t size; - unsigned int flags; - unsigned int id; -}; - -/** - * struct kgsl_command_syncpoint - GPU syncpoint object - * @priv: Pointer to the type specific buffer - * @size: Size of the type specific buffer - * @type: type of sync point defined here - */ -struct kgsl_command_syncpoint { - uint64_t priv; - uint64_t size; - unsigned int type; -}; - -/** - * struct kgsl_command_object - Argument for IOCTL_KGSL_GPU_COMMAND - * @flags: Current flags for the object - * @cmdlist: List of kgsl_command_objects for submission - * @cmd_size: Size of kgsl_command_objects structure - * @numcmds: Number of kgsl_command_objects in command list - * @objlist: List of kgsl_command_objects for tracking - * @obj_size: Size of kgsl_command_objects structure - * @numobjs: Number of kgsl_command_objects in object list - * @synclist: List of kgsl_command_syncpoints - * @sync_size: Size of kgsl_command_syncpoint structure - * @numsyncs: Number of kgsl_command_syncpoints in syncpoint list - * @context_id: Context ID submittin ghte kgsl_gpu_command - * @timestamp: Timestamp for the submitted commands - */ -struct kgsl_gpu_command { - uint64_t flags; - uint64_t cmdlist; - unsigned int cmdsize; - unsigned int numcmds; - uint64_t objlist; - unsigned int objsize; - unsigned int numobjs; - uint64_t synclist; - unsigned int syncsize; - unsigned int numsyncs; - unsigned int context_id; - unsigned int timestamp; -}; - -#define IOCTL_KGSL_GPU_COMMAND \ - _IOWR(KGSL_IOC_TYPE, 0x4A, struct kgsl_gpu_command) - -/** - * struct kgsl_preemption_counters_query - argument to - * IOCTL_KGSL_PREEMPTIONCOUNTER_QUERY - * @counters: Return preemption counters array - * @size_user: Size allocated by userspace - * @size_priority_level: Size of preemption counters for each - * priority level - * @max_priority_level: Return max number of priority levels - * - * Query the available preemption counters. The array counters - * is used to return preemption counters. The size of the array - * is passed in so the kernel will only write at most size_user - * or max available preemption counters. The total number of - * preemption counters is returned in max_priority_level. If the - * array or size passed in are invalid, then an error is - * returned back. - */ -struct kgsl_preemption_counters_query { - uint64_t counters; - unsigned int size_user; - unsigned int size_priority_level; - unsigned int max_priority_level; -}; - -#define IOCTL_KGSL_PREEMPTIONCOUNTER_QUERY \ - _IOWR(KGSL_IOC_TYPE, 0x4B, struct kgsl_preemption_counters_query) - -/** - * struct kgsl_gpuobj_set_info - argument for IOCTL_KGSL_GPUOBJ_SET_INFO - * @flags: Flags to indicate which paramaters to change - * @metadata: If KGSL_GPUOBJ_SET_INFO_METADATA is set, a pointer to the new - * metadata - * @id: GPU memory object ID to change - * @metadata_len: If KGSL_GPUOBJ_SET_INFO_METADATA is set, the length of the - * new metadata string - * @type: If KGSL_GPUOBJ_SET_INFO_TYPE is set, the new type of the memory object - */ - -#define KGSL_GPUOBJ_SET_INFO_METADATA (1 << 0) -#define KGSL_GPUOBJ_SET_INFO_TYPE (1 << 1) - -struct kgsl_gpuobj_set_info { - uint64_t flags; - uint64_t metadata; - unsigned int id; - unsigned int metadata_len; - unsigned int type; -}; - -#define IOCTL_KGSL_GPUOBJ_SET_INFO \ - _IOW(KGSL_IOC_TYPE, 0x4C, struct kgsl_gpuobj_set_info) - -/** - * struct kgsl_sparse_phys_alloc - Argument for IOCTL_KGSL_SPARSE_PHYS_ALLOC - * @size: Size in bytes to back - * @pagesize: Pagesize alignment required - * @flags: Flags for this allocation - * @id: Returned ID for this allocation - */ -struct kgsl_sparse_phys_alloc { - uint64_t size; - uint64_t pagesize; - uint64_t flags; - unsigned int id; -}; - -#define IOCTL_KGSL_SPARSE_PHYS_ALLOC \ - _IOWR(KGSL_IOC_TYPE, 0x50, struct kgsl_sparse_phys_alloc) - -/** - * struct kgsl_sparse_phys_free - Argument for IOCTL_KGSL_SPARSE_PHYS_FREE - * @id: ID to free - */ -struct kgsl_sparse_phys_free { - unsigned int id; -}; - -#define IOCTL_KGSL_SPARSE_PHYS_FREE \ - _IOW(KGSL_IOC_TYPE, 0x51, struct kgsl_sparse_phys_free) - -/** - * struct kgsl_sparse_virt_alloc - Argument for IOCTL_KGSL_SPARSE_VIRT_ALLOC - * @size: Size in bytes to reserve - * @pagesize: Pagesize alignment required - * @flags: Flags for this allocation - * @id: Returned ID for this allocation - * @gpuaddr: Returned GPU address for this allocation - */ -struct kgsl_sparse_virt_alloc { - uint64_t size; - uint64_t pagesize; - uint64_t flags; - uint64_t gpuaddr; - unsigned int id; -}; - -#define IOCTL_KGSL_SPARSE_VIRT_ALLOC \ - _IOWR(KGSL_IOC_TYPE, 0x52, struct kgsl_sparse_virt_alloc) - -/** - * struct kgsl_sparse_virt_free - Argument for IOCTL_KGSL_SPARSE_VIRT_FREE - * @id: ID to free - */ -struct kgsl_sparse_virt_free { - unsigned int id; -}; - -#define IOCTL_KGSL_SPARSE_VIRT_FREE \ - _IOW(KGSL_IOC_TYPE, 0x53, struct kgsl_sparse_virt_free) - -/** - * struct kgsl_sparse_binding_object - Argument for kgsl_sparse_bind - * @virtoffset: Offset into the virtual ID - * @physoffset: Offset into the physical ID (bind only) - * @size: Size in bytes to reserve - * @flags: Flags for this kgsl_sparse_binding_object - * @id: Physical ID to bind (bind only) - */ -struct kgsl_sparse_binding_object { - uint64_t virtoffset; - uint64_t physoffset; - uint64_t size; - uint64_t flags; - unsigned int id; -}; - -/** - * struct kgsl_sparse_bind - Argument for IOCTL_KGSL_SPARSE_BIND - * @list: List of kgsl_sparse_bind_objects to bind/unbind - * @id: Virtual ID to bind/unbind - * @size: Size of kgsl_sparse_bind_object - * @count: Number of elements in list - * - */ -struct kgsl_sparse_bind { - uint64_t list; - unsigned int id; - unsigned int size; - unsigned int count; -}; - -#define IOCTL_KGSL_SPARSE_BIND \ - _IOW(KGSL_IOC_TYPE, 0x54, struct kgsl_sparse_bind) - -/** - * struct kgsl_gpu_sparse_command - Argument for - * IOCTL_KGSL_GPU_SPARSE_COMMAND - * @flags: Current flags for the object - * @sparselist: List of kgsl_sparse_binding_object to bind/unbind - * @synclist: List of kgsl_command_syncpoints - * @sparsesize: Size of kgsl_sparse_binding_object - * @numsparse: Number of elements in list - * @sync_size: Size of kgsl_command_syncpoint structure - * @numsyncs: Number of kgsl_command_syncpoints in syncpoint list - * @context_id: Context ID submitting the kgsl_gpu_command - * @timestamp: Timestamp for the submitted commands - * @id: Virtual ID to bind/unbind - */ -struct kgsl_gpu_sparse_command { - uint64_t flags; - uint64_t sparselist; - uint64_t synclist; - unsigned int sparsesize; - unsigned int numsparse; - unsigned int syncsize; - unsigned int numsyncs; - unsigned int context_id; - unsigned int timestamp; - unsigned int id; -}; - -#define IOCTL_KGSL_GPU_SPARSE_COMMAND \ - _IOWR(KGSL_IOC_TYPE, 0x55, struct kgsl_gpu_sparse_command) - -#endif /* _MSM_KGSL_H */ diff --git a/sdm710/original-kernel-headers/linux/msm_mdp.h b/sdm710/original-kernel-headers/linux/msm_mdp.h deleted file mode 100644 index 487cb169..00000000 --- a/sdm710/original-kernel-headers/linux/msm_mdp.h +++ /dev/null @@ -1,1462 +0,0 @@ -#ifndef _MSM_MDP_H_ -#define _MSM_MDP_H_ - -#include <stdint.h> -#include <linux/fb.h> - -#define MSMFB_IOCTL_MAGIC 'm' -#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) -#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) -#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) -#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) -#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) -#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) -#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) -/* new ioctls's for set/get ccs matrix */ -#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) -#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) -#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ - struct mdp_overlay) -#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) - -#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ - struct msmfb_overlay_data) -#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY - -#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ - struct mdp_page_protection) -#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ - struct mdp_page_protection) -#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ - struct mdp_overlay) -#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) -#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ - struct msmfb_overlay_blt) -#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) -#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ - struct mdp_histogram_start_req) -#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) -#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) - -#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ - struct msmfb_overlay_3d) - -#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ - struct msmfb_mixer_info_req) -#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ - struct msmfb_overlay_data) -#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) -#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) -#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) -#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ - struct msmfb_data) -#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ - struct msmfb_data) -#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) -#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) -#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) -#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) -#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) -#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) -#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ - struct mdp_display_commit) -#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) -#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) -#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ - unsigned int) -#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) -#define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ - struct mdp_overlay_list) -#define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) -#define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, \ - struct mdp_pp_feature_version) - -#define FB_TYPE_3D_PANEL 0x10101010 -#define MDP_IMGTYPE2_START 0x10000 -#define MSMFB_DRIVER_VERSION 0xF9E8D701 -/* Maximum number of formats supported by MDP*/ -#define MDP_IMGTYPE_END 0x100 - -/* HW Revisions for different MDSS targets */ -#define MDSS_GET_MAJOR(rev) ((rev) >> 28) -#define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) -#define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) -#define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) - -#define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ - (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) - -#define MDSS_MDP_REV(major, minor, step) \ - ((((major) & 0x000F) << 28) | \ - (((minor) & 0x0FFF) << 16) | \ - ((step) & 0xFFFF)) - -#define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ -#define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ -#define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ -#define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ -#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ -#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ -#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ -#define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ -#define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */ -#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */ -#define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) /* 8996 v1 */ -#define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) /* 8996 v2 */ -#define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) /* 8996 v3 */ -#define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */ -#define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */ -#define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */ -#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ -#define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) /* 8952 v1.0 */ -#define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) /* 8937 v1.0 */ -#define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) /* msmgold */ -#define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) /* msmtitanium */ -#define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) /* msmcobalt */ -#define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) /* msmcobalt v1.0 */ - -enum { - NOTIFY_UPDATE_INIT, - NOTIFY_UPDATE_DEINIT, - NOTIFY_UPDATE_START, - NOTIFY_UPDATE_STOP, - NOTIFY_UPDATE_POWER_OFF, -}; - -enum { - NOTIFY_TYPE_NO_UPDATE, - NOTIFY_TYPE_SUSPEND, - NOTIFY_TYPE_UPDATE, - NOTIFY_TYPE_BL_UPDATE, - NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, -}; - -enum { - MDP_RGB_565, /* RGB 565 planer */ - MDP_XRGB_8888, /* RGB 888 padded */ - MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ - MDP_Y_CBCR_H2V2_ADRENO, - MDP_ARGB_8888, /* ARGB 888 */ - MDP_RGB_888, /* RGB 888 planer */ - MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ - MDP_YCRYCB_H2V1, /* YCrYCb interleave */ - MDP_CBYCRY_H2V1, /* CbYCrY interleave */ - MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ - MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ - MDP_Y_CRCB_H1V2, - MDP_Y_CBCR_H1V2, - MDP_RGBA_8888, /* ARGB 888 */ - MDP_BGRA_8888, /* ABGR 888 */ - MDP_RGBX_8888, /* RGBX 888 */ - MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ - MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ - MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ - MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ - MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ - MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ - MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ - MDP_YCRCB_H1V1, /* YCrCb interleave */ - MDP_YCBCR_H1V1, /* YCbCr interleave */ - MDP_BGR_565, /* BGR 565 planer */ - MDP_BGR_888, /* BGR 888 */ - MDP_Y_CBCR_H2V2_VENUS, - MDP_BGRX_8888, /* BGRX 8888 */ - MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ - MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ - MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ - MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ - MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ - MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ - MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ - MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ - MDP_YCBYCR_H2V1, /* YCbYCr interleave */ - MDP_RGB_565_TILE, /* RGB 565 in tile format */ - MDP_BGR_565_TILE, /* BGR 565 in tile format */ - MDP_ARGB_1555, /*ARGB 1555*/ - MDP_RGBA_5551, /*RGBA 5551*/ - MDP_ARGB_4444, /*ARGB 4444*/ - MDP_RGBA_4444, /*RGBA 4444*/ - MDP_RGB_565_UBWC, - MDP_RGBA_8888_UBWC, - MDP_Y_CBCR_H2V2_UBWC, - MDP_RGBX_8888_UBWC, - MDP_Y_CRCB_H2V2_VENUS, - MDP_IMGTYPE_LIMIT, - MDP_RGB_BORDERFILL, /* border fill pipe */ - MDP_XRGB_1555, - MDP_RGBX_5551, - MDP_XRGB_4444, - MDP_RGBX_4444, - MDP_ABGR_1555, - MDP_BGRA_5551, - MDP_XBGR_1555, - MDP_BGRX_5551, - MDP_ABGR_4444, - MDP_BGRA_4444, - MDP_XBGR_4444, - MDP_BGRX_4444, - MDP_ABGR_8888, - MDP_XBGR_8888, - MDP_RGBA_1010102, - MDP_ARGB_2101010, - MDP_RGBX_1010102, - MDP_XRGB_2101010, - MDP_BGRA_1010102, - MDP_ABGR_2101010, - MDP_BGRX_1010102, - MDP_XBGR_2101010, - MDP_RGBA_1010102_UBWC, - MDP_RGBX_1010102_UBWC, - MDP_Y_CBCR_H2V2_P010, - MDP_Y_CBCR_H2V2_TP10_UBWC, - MDP_CRYCBY_H2V1, /* CrYCbY interleave */ - MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, - MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ - MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ -}; - -#define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 - -enum { - PMEM_IMG, - FB_IMG, -}; - -enum { - HSIC_HUE = 0, - HSIC_SAT, - HSIC_INT, - HSIC_CON, - NUM_HSIC_PARAM, -}; - -enum mdss_mdp_max_bw_mode { - MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, - MDSS_MAX_BW_LIMIT_CAMERA = 0x2, - MDSS_MAX_BW_LIMIT_HFLIP = 0x4, - MDSS_MAX_BW_LIMIT_VFLIP = 0x8, -}; - -#define MDSS_MDP_ROT_ONLY 0x80 -#define MDSS_MDP_RIGHT_MIXER 0x100 -#define MDSS_MDP_DUAL_PIPE 0x200 - -/* mdp_blit_req flag values */ -#define MDP_ROT_NOP 0 -#define MDP_FLIP_LR 0x1 -#define MDP_FLIP_UD 0x2 -#define MDP_ROT_90 0x4 -#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) -#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) -#define MDP_DITHER 0x8 -#define MDP_BLUR 0x10 -#define MDP_BLEND_FG_PREMULT 0x20000 -#define MDP_IS_FG 0x40000 -#define MDP_SOLID_FILL 0x00000020 -#define MDP_VPU_PIPE 0x00000040 -#define MDP_DEINTERLACE 0x80000000 -#define MDP_SHARPENING 0x40000000 -#define MDP_NO_DMA_BARRIER_START 0x20000000 -#define MDP_NO_DMA_BARRIER_END 0x10000000 -#define MDP_NO_BLIT 0x08000000 -#define MDP_BLIT_WITH_DMA_BARRIERS 0x000 -#define MDP_BLIT_WITH_NO_DMA_BARRIERS \ - (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) -#define MDP_BLIT_SRC_GEM 0x04000000 -#define MDP_BLIT_DST_GEM 0x02000000 -#define MDP_BLIT_NON_CACHED 0x01000000 -#define MDP_OV_PIPE_SHARE 0x00800000 -#define MDP_DEINTERLACE_ODD 0x00400000 -#define MDP_OV_PLAY_NOWAIT 0x00200000 -#define MDP_SOURCE_ROTATED_90 0x00100000 -#define MDP_OVERLAY_PP_CFG_EN 0x00080000 -#define MDP_BACKEND_COMPOSITION 0x00040000 -#define MDP_BORDERFILL_SUPPORTED 0x00010000 -#define MDP_SECURE_OVERLAY_SESSION 0x00008000 -#define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 -#define MDP_OV_PIPE_FORCE_DMA 0x00004000 -#define MDP_MEMORY_ID_TYPE_FB 0x00001000 -#define MDP_BWC_EN 0x00000400 -#define MDP_DECIMATION_EN 0x00000800 -#define MDP_SMP_FORCE_ALLOC 0x00200000 -#define MDP_TRANSP_NOP 0xffffffff -#define MDP_ALPHA_NOP 0xff - -#define MDP_FB_PAGE_PROTECTION_NONCACHED (0) -#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) -#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) -#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) -#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) -/* Sentinel: Don't use! */ -#define MDP_FB_PAGE_PROTECTION_INVALID (5) -/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ -#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) - -#define MDP_DEEP_COLOR_YUV444 0x1 -#define MDP_DEEP_COLOR_RGB30B 0x2 -#define MDP_DEEP_COLOR_RGB36B 0x4 -#define MDP_DEEP_COLOR_RGB48B 0x8 - -struct mdp_rect { - uint32_t x; - uint32_t y; - uint32_t w; - uint32_t h; -}; - -struct mdp_img { - uint32_t width; - uint32_t height; - uint32_t format; - uint32_t offset; - int memory_id; /* the file descriptor */ - uint32_t priv; -}; - -struct mult_factor { - uint32_t numer; - uint32_t denom; -}; - -/* - * {3x3} + {3} ccs matrix - */ - -#define MDP_CCS_RGB2YUV 0 -#define MDP_CCS_YUV2RGB 1 - -#define MDP_CCS_SIZE 9 -#define MDP_BV_SIZE 3 - -struct mdp_ccs { - int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ - uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ - uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ -}; - -struct mdp_csc { - int id; - uint32_t csc_mv[9]; - uint32_t csc_pre_bv[3]; - uint32_t csc_post_bv[3]; - uint32_t csc_pre_lv[6]; - uint32_t csc_post_lv[6]; -}; - -/* The version of the mdp_blit_req structure so that - * user applications can selectively decide which functionality - * to include - */ - -#define MDP_BLIT_REQ_VERSION 3 - -struct color { - uint32_t r; - uint32_t g; - uint32_t b; - uint32_t alpha; -}; - -struct mdp_blit_req { - struct mdp_img src; - struct mdp_img dst; - struct mdp_rect src_rect; - struct mdp_rect dst_rect; - struct color const_color; - uint32_t alpha; - uint32_t transp_mask; - uint32_t flags; - int sharpening_strength; /* -127 <--> 127, default 64 */ - uint8_t color_space; - uint32_t fps; -}; - -struct mdp_blit_req_list { - uint32_t count; - struct mdp_blit_req req[]; -}; - -#define MSMFB_DATA_VERSION 2 - -struct msmfb_data { - uint32_t offset; - int memory_id; - int id; - uint32_t flags; - uint32_t priv; - uint32_t iova; -}; - -#define MSMFB_NEW_REQUEST -1 - -struct msmfb_overlay_data { - uint32_t id; - struct msmfb_data data; - uint32_t version_key; - struct msmfb_data plane1_data; - struct msmfb_data plane2_data; - struct msmfb_data dst_data; -}; - -struct msmfb_img { - uint32_t width; - uint32_t height; - uint32_t format; -}; - -#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 -struct msmfb_writeback_data { - struct msmfb_data buf_info; - struct msmfb_img img; -}; - -#define MDP_PP_OPS_ENABLE 0x1 -#define MDP_PP_OPS_READ 0x2 -#define MDP_PP_OPS_WRITE 0x4 -#define MDP_PP_OPS_DISABLE 0x8 -#define MDP_PP_IGC_FLAG_ROM0 0x10 -#define MDP_PP_IGC_FLAG_ROM1 0x20 - - -#define MDSS_PP_DSPP_CFG 0x000 -#define MDSS_PP_SSPP_CFG 0x100 -#define MDSS_PP_LM_CFG 0x200 -#define MDSS_PP_WB_CFG 0x300 - -#define MDSS_PP_ARG_MASK 0x3C00 -#define MDSS_PP_ARG_NUM 4 -#define MDSS_PP_ARG_SHIFT 10 -#define MDSS_PP_LOCATION_MASK 0x0300 -#define MDSS_PP_LOGICAL_MASK 0x00FF - -#define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) -#define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) -#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) -#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) - - -struct mdp_qseed_cfg { - uint32_t table_num; - uint32_t ops; - uint32_t len; - uint32_t *data; -}; - -struct mdp_sharp_cfg { - uint32_t flags; - uint32_t strength; - uint32_t edge_thr; - uint32_t smooth_thr; - uint32_t noise_thr; -}; - -struct mdp_qseed_cfg_data { - uint32_t block; - struct mdp_qseed_cfg qseed_data; -}; - -#define MDP_OVERLAY_PP_CSC_CFG 0x1 -#define MDP_OVERLAY_PP_QSEED_CFG 0x2 -#define MDP_OVERLAY_PP_PA_CFG 0x4 -#define MDP_OVERLAY_PP_IGC_CFG 0x8 -#define MDP_OVERLAY_PP_SHARP_CFG 0x10 -#define MDP_OVERLAY_PP_HIST_CFG 0x20 -#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 -#define MDP_OVERLAY_PP_PA_V2_CFG 0x80 -#define MDP_OVERLAY_PP_PCC_CFG 0x100 - -#define MDP_CSC_FLAG_ENABLE 0x1 -#define MDP_CSC_FLAG_YUV_IN 0x2 -#define MDP_CSC_FLAG_YUV_OUT 0x4 - -#define MDP_CSC_MATRIX_COEFF_SIZE 9 -#define MDP_CSC_CLAMP_SIZE 6 -#define MDP_CSC_BIAS_SIZE 3 - -struct mdp_csc_cfg { - /* flags for enable CSC, toggling RGB,YUV input/output */ - uint32_t flags; - uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; - uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; - uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; - uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; - uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; -}; - -struct mdp_csc_cfg_data { - uint32_t block; - struct mdp_csc_cfg csc_data; -}; - -struct mdp_pa_cfg { - uint32_t flags; - uint32_t hue_adj; - uint32_t sat_adj; - uint32_t val_adj; - uint32_t cont_adj; -}; - -struct mdp_pa_mem_col_cfg { - uint32_t color_adjust_p0; - uint32_t color_adjust_p1; - uint32_t hue_region; - uint32_t sat_region; - uint32_t val_region; -}; - -#define MDP_SIX_ZONE_LUT_SIZE 384 - -/* PA Write/Read extension flags */ -#define MDP_PP_PA_HUE_ENABLE 0x10 -#define MDP_PP_PA_SAT_ENABLE 0x20 -#define MDP_PP_PA_VAL_ENABLE 0x40 -#define MDP_PP_PA_CONT_ENABLE 0x80 -#define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 -#define MDP_PP_PA_SKIN_ENABLE 0x200 -#define MDP_PP_PA_SKY_ENABLE 0x400 -#define MDP_PP_PA_FOL_ENABLE 0x800 - -/* PA masks */ -/* Masks used in PA v1_7 only */ -#define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 -#define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 -#define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 -#define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 -#define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 -#define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 -/* Masks used in all PAv2 versions */ -#define MDP_PP_PA_HUE_MASK 0x1000 -#define MDP_PP_PA_SAT_MASK 0x2000 -#define MDP_PP_PA_VAL_MASK 0x4000 -#define MDP_PP_PA_CONT_MASK 0x8000 -#define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 -#define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 -#define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 -#define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 -#define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 -#define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 -#define MDP_PP_PA_MEM_PROTECT_EN 0x400000 -#define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 - -/* Flags for setting PA saturation and value hold */ -#define MDP_PP_PA_LEFT_HOLD 0x1 -#define MDP_PP_PA_RIGHT_HOLD 0x2 - -struct mdp_pa_v2_data { - /* Mask bits for PA features */ - uint32_t flags; - uint32_t global_hue_adj; - uint32_t global_sat_adj; - uint32_t global_val_adj; - uint32_t global_cont_adj; - struct mdp_pa_mem_col_cfg skin_cfg; - struct mdp_pa_mem_col_cfg sky_cfg; - struct mdp_pa_mem_col_cfg fol_cfg; - uint32_t six_zone_len; - uint32_t six_zone_thresh; - uint32_t *six_zone_curve_p0; - uint32_t *six_zone_curve_p1; -}; - -struct mdp_pa_mem_col_data_v1_7 { - uint32_t color_adjust_p0; - uint32_t color_adjust_p1; - uint32_t color_adjust_p2; - uint32_t blend_gain; - uint8_t sat_hold; - uint8_t val_hold; - uint32_t hue_region; - uint32_t sat_region; - uint32_t val_region; -}; - -struct mdp_pa_data_v1_7 { - uint32_t mode; - uint32_t global_hue_adj; - uint32_t global_sat_adj; - uint32_t global_val_adj; - uint32_t global_cont_adj; - struct mdp_pa_mem_col_data_v1_7 skin_cfg; - struct mdp_pa_mem_col_data_v1_7 sky_cfg; - struct mdp_pa_mem_col_data_v1_7 fol_cfg; - uint32_t six_zone_thresh; - uint32_t six_zone_adj_p0; - uint32_t six_zone_adj_p1; - uint8_t six_zone_sat_hold; - uint8_t six_zone_val_hold; - uint32_t six_zone_len; - uint32_t *six_zone_curve_p0; - uint32_t *six_zone_curve_p1; -}; - - -struct mdp_pa_v2_cfg_data { - uint32_t version; - uint32_t block; - uint32_t flags; - struct mdp_pa_v2_data pa_v2_data; - void *cfg_payload; -}; - - -enum { - mdp_igc_rec601 = 1, - mdp_igc_rec709, - mdp_igc_srgb, - mdp_igc_custom, - mdp_igc_rec_max, -}; - -struct mdp_igc_lut_data { - uint32_t block; - uint32_t version; - uint32_t len, ops; - uint32_t *c0_c1_data; - uint32_t *c2_data; - void *cfg_payload; -}; - -struct mdp_igc_lut_data_v1_7 { - uint32_t table_fmt; - uint32_t len; - uint32_t *c0_c1_data; - uint32_t *c2_data; -}; - -struct mdp_igc_lut_data_payload { - uint32_t table_fmt; - uint32_t len; - uint64_t c0_c1_data; - uint64_t c2_data; - uint32_t strength; -}; - -struct mdp_histogram_cfg { - uint32_t ops; - uint32_t block; - uint8_t frame_cnt; - uint8_t bit_mask; - uint16_t num_bins; -}; - -struct mdp_hist_lut_data_v1_7 { - uint32_t len; - uint32_t *data; -}; - -struct mdp_hist_lut_data { - uint32_t block; - uint32_t version; - uint32_t hist_lut_first; - uint32_t ops; - uint32_t len; - uint32_t *data; - void *cfg_payload; -}; - -struct mdp_pcc_coeff { - uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; -}; - -struct mdp_pcc_coeff_v1_7 { - uint32_t c, r, g, b, rg, gb, rb, rgb; -}; - -struct mdp_pcc_data_v1_7 { - struct mdp_pcc_coeff_v1_7 r, g, b; -}; - -struct mdp_pcc_cfg_data { - uint32_t version; - uint32_t block; - uint32_t ops; - struct mdp_pcc_coeff r, g, b; - void *cfg_payload; -}; - -enum { - mdp_lut_igc, - mdp_lut_pgc, - mdp_lut_hist, - mdp_lut_rgb, - mdp_lut_max, -}; -struct mdp_overlay_pp_params { - uint32_t config_ops; - struct mdp_csc_cfg csc_cfg; - struct mdp_qseed_cfg qseed_cfg[2]; - struct mdp_pa_cfg pa_cfg; - struct mdp_pa_v2_data pa_v2_cfg; - struct mdp_igc_lut_data igc_cfg; - struct mdp_sharp_cfg sharp_cfg; - struct mdp_histogram_cfg hist_cfg; - struct mdp_hist_lut_data hist_lut_cfg; - /* PAv2 cfg data for PA 2.x versions */ - struct mdp_pa_v2_cfg_data pa_v2_cfg_data; - struct mdp_pcc_cfg_data pcc_cfg_data; -}; - -/** - * enum mdss_mdp_blend_op - Different blend operations set by userspace - * - * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. - * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer - * would appear opaque in case fg plane alpha is - * 0xff. - * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has - * alpha pre-multiplication done. If fg plane alpha - * is less than 0xff, apply modulation as well. This - * operation is intended on layers having alpha - * channel. - * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha - * pre-multiplied. Apply pre-multiplication. If fg - * plane alpha is less than 0xff, apply modulation as - * well. - * @BLEND_OP_MAX: Used to track maximum blend operation possible by - * mdp. - */ -enum mdss_mdp_blend_op { - BLEND_OP_NOT_DEFINED = 0, - BLEND_OP_OPAQUE, - BLEND_OP_PREMULTIPLIED, - BLEND_OP_COVERAGE, - BLEND_OP_MAX, -}; - -#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) -#define MAX_PLANES 4 -struct mdp_scale_data { - uint8_t enable_pxl_ext; - - int init_phase_x[MAX_PLANES]; - int phase_step_x[MAX_PLANES]; - int init_phase_y[MAX_PLANES]; - int phase_step_y[MAX_PLANES]; - - int num_ext_pxls_left[MAX_PLANES]; - int num_ext_pxls_right[MAX_PLANES]; - int num_ext_pxls_top[MAX_PLANES]; - int num_ext_pxls_btm[MAX_PLANES]; - - int left_ftch[MAX_PLANES]; - int left_rpt[MAX_PLANES]; - int right_ftch[MAX_PLANES]; - int right_rpt[MAX_PLANES]; - - int top_rpt[MAX_PLANES]; - int btm_rpt[MAX_PLANES]; - int top_ftch[MAX_PLANES]; - int btm_ftch[MAX_PLANES]; - - uint32_t roi_w[MAX_PLANES]; -}; - -/** - * enum mdp_overlay_pipe_type - Different pipe type set by userspace - * - * @PIPE_TYPE_AUTO: Not specified, pipe will be selected according to flags. - * @PIPE_TYPE_VIG: VIG pipe. - * @PIPE_TYPE_RGB: RGB pipe. - * @PIPE_TYPE_DMA: DMA pipe. - * @PIPE_TYPE_CURSOR: CURSOR pipe. - * @PIPE_TYPE_MAX: Used to track maximum number of pipe type. - */ -enum mdp_overlay_pipe_type { - PIPE_TYPE_AUTO = 0, - PIPE_TYPE_VIG, - PIPE_TYPE_RGB, - PIPE_TYPE_DMA, - PIPE_TYPE_CURSOR, - PIPE_TYPE_MAX, -}; - -/** - * struct mdp_overlay - overlay surface structure - * @src: Source image information (width, height, format). - * @src_rect: Source crop rectangle, portion of image that will be fetched. - * This should always be within boundaries of source image. - * @dst_rect: Destination rectangle, the position and size of image on screen. - * This should always be within panel boundaries. - * @z_order: Blending stage to occupy in display, if multiple layers are - * present, highest z_order usually means the top most visible - * layer. The range acceptable is from 0-3 to support blending - * up to 4 layers. - * @is_fg: This flag is used to disable blending of any layers with z_order - * less than this overlay. It means that any layers with z_order - * less than this layer will not be blended and will be replaced - * by the background border color. - * @alpha: Used to set plane opacity. The range can be from 0-255, where - * 0 means completely transparent and 255 means fully opaque. - * @transp_mask: Color used as color key for transparency. Any pixel in fetched - * image matching this color will be transparent when blending. - * The color should be in same format as the source image format. - * @flags: This is used to customize operation of overlay. See MDP flags - * for more information. - * @pipe_type: Used to specify the type of overlay pipe. - * @user_data: DEPRECATED* Used to store user application specific information. - * @bg_color: Solid color used to fill the overlay surface when no source - * buffer is provided. - * @horz_deci: Horizontal decimation value, this indicates the amount of pixels - * dropped for each pixel that is fetched from a line. The value - * given should be power of two of decimation amount. - * 0: no decimation - * 1: decimate by 2 (drop 1 pixel for each pixel fetched) - * 2: decimate by 4 (drop 3 pixels for each pixel fetched) - * 3: decimate by 8 (drop 7 pixels for each pixel fetched) - * 4: decimate by 16 (drop 15 pixels for each pixel fetched) - * @vert_deci: Vertical decimation value, this indicates the amount of lines - * dropped for each line that is fetched from overlay. The value - * given should be power of two of decimation amount. - * 0: no decimation - * 1: decimation by 2 (drop 1 line for each line fetched) - * 2: decimation by 4 (drop 3 lines for each line fetched) - * 3: decimation by 8 (drop 7 lines for each line fetched) - * 4: decimation by 16 (drop 15 lines for each line fetched) - * @overlay_pp_cfg: Overlay post processing configuration, for more information - * see struct mdp_overlay_pp_params. - * @priority: Priority is returned by the driver when overlay is set for the - * first time. It indicates the priority of the underlying pipe - * serving the overlay. This priority can be used by user-space - * in source split when pipes are re-used and shuffled around to - * reduce fallbacks. - */ -struct mdp_overlay { - struct msmfb_img src; - struct mdp_rect src_rect; - struct mdp_rect dst_rect; - uint32_t z_order; /* stage number */ - uint32_t is_fg; /* control alpha & transp */ - uint32_t alpha; - uint32_t blend_op; - uint32_t transp_mask; - uint32_t flags; - uint32_t pipe_type; - uint32_t id; - uint8_t priority; - uint32_t user_data[6]; - uint32_t bg_color; - uint8_t horz_deci; - uint8_t vert_deci; - struct mdp_overlay_pp_params overlay_pp_cfg; - struct mdp_scale_data scale; - uint8_t color_space; - uint32_t frame_rate; -}; - -struct msmfb_overlay_3d { - uint32_t is_3d; - uint32_t width; - uint32_t height; -}; - - -struct msmfb_overlay_blt { - uint32_t enable; - uint32_t offset; - uint32_t width; - uint32_t height; - uint32_t bpp; -}; - -struct mdp_histogram { - uint32_t frame_cnt; - uint32_t bin_cnt; - uint32_t *r; - uint32_t *g; - uint32_t *b; -}; - -#define MISR_CRC_BATCH_SIZE 32 -enum { - DISPLAY_MISR_EDP, - DISPLAY_MISR_DSI0, - DISPLAY_MISR_DSI1, - DISPLAY_MISR_HDMI, - DISPLAY_MISR_LCDC, - DISPLAY_MISR_MDP, - DISPLAY_MISR_ATV, - DISPLAY_MISR_DSI_CMD, - DISPLAY_MISR_MAX -}; - -enum { - MISR_OP_NONE, - MISR_OP_SFM, - MISR_OP_MFM, - MISR_OP_BM, - MISR_OP_MAX -}; - -struct mdp_misr { - uint32_t block_id; - uint32_t frame_count; - uint32_t crc_op_mode; - uint32_t crc_value[MISR_CRC_BATCH_SIZE]; -}; - -/* - * mdp_block_type defines the identifiers for pipes in MDP 4.3 and up - * - * MDP_BLOCK_RESERVED is provided for backward compatibility and is - * deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used - * instead. - * - * MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, - * same for others. - */ - -enum { - MDP_BLOCK_RESERVED = 0, - MDP_BLOCK_OVERLAY_0, - MDP_BLOCK_OVERLAY_1, - MDP_BLOCK_VG_1, - MDP_BLOCK_VG_2, - MDP_BLOCK_RGB_1, - MDP_BLOCK_RGB_2, - MDP_BLOCK_DMA_P, - MDP_BLOCK_DMA_S, - MDP_BLOCK_DMA_E, - MDP_BLOCK_OVERLAY_2, - MDP_LOGICAL_BLOCK_DISP_0 = 0x10, - MDP_LOGICAL_BLOCK_DISP_1, - MDP_LOGICAL_BLOCK_DISP_2, - MDP_BLOCK_MAX, -}; - -/* - * mdp_histogram_start_req is used to provide the parameters for - * histogram start request - */ - -struct mdp_histogram_start_req { - uint32_t block; - uint8_t frame_cnt; - uint8_t bit_mask; - uint16_t num_bins; -}; - -/* - * mdp_histogram_data is used to return the histogram data, once - * the histogram is done/stopped/cance - */ - -struct mdp_histogram_data { - uint32_t block; - uint32_t bin_cnt; - uint32_t *c0; - uint32_t *c1; - uint32_t *c2; - uint32_t *extra_info; -}; - - -#define GC_LUT_ENTRIES_V1_7 512 - -struct mdp_ar_gc_lut_data { - uint32_t x_start; - uint32_t slope; - uint32_t offset; -}; - -#define MDP_PP_PGC_ROUNDING_ENABLE 0x10 -struct mdp_pgc_lut_data { - uint32_t version; - uint32_t block; - uint32_t flags; - uint8_t num_r_stages; - uint8_t num_g_stages; - uint8_t num_b_stages; - struct mdp_ar_gc_lut_data *r_data; - struct mdp_ar_gc_lut_data *g_data; - struct mdp_ar_gc_lut_data *b_data; - void *cfg_payload; -}; - -#define PGC_LUT_ENTRIES 1024 -struct mdp_pgc_lut_data_v1_7 { - uint32_t len; - uint32_t *c0_data; - uint32_t *c1_data; - uint32_t *c2_data; -}; - -/* - * mdp_rgb_lut_data is used to provide parameters for configuring the - * generic RGB lut in case of gamma correction or other LUT updation usecases - */ -struct mdp_rgb_lut_data { - uint32_t flags; - uint32_t lut_type; - struct fb_cmap cmap; -}; - -enum { - mdp_rgb_lut_gc, - mdp_rgb_lut_hist, -}; - -struct mdp_lut_cfg_data { - uint32_t lut_type; - union { - struct mdp_igc_lut_data igc_lut_data; - struct mdp_pgc_lut_data pgc_lut_data; - struct mdp_hist_lut_data hist_lut_data; - struct mdp_rgb_lut_data rgb_lut_data; - } data; -}; - -struct mdp_bl_scale_data { - uint32_t min_lvl; - uint32_t scale; -}; - -struct mdp_pa_cfg_data { - uint32_t block; - struct mdp_pa_cfg pa_data; -}; - -#define MDP_DITHER_DATA_V1_7_SZ 16 - -struct mdp_dither_data_v1_7 { - uint32_t g_y_depth; - uint32_t r_cr_depth; - uint32_t b_cb_depth; - uint32_t len; - uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; - uint32_t temporal_en; -}; - -struct mdp_pa_dither_data { - uint64_t data_flags; - uint32_t matrix_sz; - uint64_t matrix_data; - uint32_t strength; - uint32_t offset_en; -}; - -struct mdp_dither_cfg_data { - uint32_t version; - uint32_t block; - uint32_t flags; - uint32_t mode; - uint32_t g_y_depth; - uint32_t r_cr_depth; - uint32_t b_cb_depth; - void *cfg_payload; -}; - -#define MDP_GAMUT_TABLE_NUM 8 -#define MDP_GAMUT_TABLE_NUM_V1_7 4 -#define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 -#define MDP_GAMUT_TABLE_V1_7_SZ 1229 -#define MDP_GAMUT_SCALE_OFF_SZ 16 -#define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 - -struct mdp_gamut_cfg_data { - uint32_t block; - uint32_t flags; - uint32_t version; - /* v1 version specific params */ - uint32_t gamut_first; - uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; - uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; - uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; - uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; - /* params for newer versions of gamut */ - void *cfg_payload; -}; - -enum { - mdp_gamut_fine_mode = 0x1, - mdp_gamut_coarse_mode, -}; - -struct mdp_gamut_data_v1_7 { - uint32_t mode; - uint32_t map_en; - uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; - uint32_t *c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; - uint32_t *c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; - uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; - uint32_t *scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; -}; - -struct mdp_calib_config_data { - uint32_t ops; - uint32_t addr; - uint32_t data; -}; - -struct mdp_calib_config_buffer { - uint32_t ops; - uint32_t size; - uint32_t *buffer; -}; - -struct mdp_calib_dcm_state { - uint32_t ops; - uint32_t dcm_state; -}; - -enum { - DCM_UNINIT, - DCM_UNBLANK, - DCM_ENTER, - DCM_EXIT, - DCM_BLANK, - DTM_ENTER, - DTM_EXIT, -}; - -#define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 -#define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 -#define MDSS_PP_SPLIT_MASK 0x30000000 - -#define MDSS_MAX_BL_BRIGHTNESS 255 -#define AD_BL_LIN_LEN 256 -#define AD_BL_ATT_LUT_LEN 33 - -#define MDSS_AD_MODE_AUTO_BL 0x0 -#define MDSS_AD_MODE_AUTO_STR 0x1 -#define MDSS_AD_MODE_TARG_STR 0x3 -#define MDSS_AD_MODE_MAN_STR 0x7 -#define MDSS_AD_MODE_CALIB 0xF - -#define MDP_PP_AD_INIT 0x10 -#define MDP_PP_AD_CFG 0x20 - -struct mdss_ad_init { - uint32_t asym_lut[33]; - uint32_t color_corr_lut[33]; - uint8_t i_control[2]; - uint16_t black_lvl; - uint16_t white_lvl; - uint8_t var; - uint8_t limit_ampl; - uint8_t i_dither; - uint8_t slope_max; - uint8_t slope_min; - uint8_t dither_ctl; - uint8_t format; - uint8_t auto_size; - uint16_t frame_w; - uint16_t frame_h; - uint8_t logo_v; - uint8_t logo_h; - uint32_t alpha; - uint32_t alpha_base; - uint32_t al_thresh; - uint32_t bl_lin_len; - uint32_t bl_att_len; - uint32_t *bl_lin; - uint32_t *bl_lin_inv; - uint32_t *bl_att_lut; -}; - -#define MDSS_AD_BL_CTRL_MODE_EN 1 -#define MDSS_AD_BL_CTRL_MODE_DIS 0 -struct mdss_ad_cfg { - uint32_t mode; - uint32_t al_calib_lut[33]; - uint16_t backlight_min; - uint16_t backlight_max; - uint16_t backlight_scale; - uint16_t amb_light_min; - uint16_t filter[2]; - uint16_t calib[4]; - uint8_t strength_limit; - uint8_t t_filter_recursion; - uint16_t stab_itr; - uint32_t bl_ctrl_mode; -}; - -struct mdss_ad_bl_cfg { - uint32_t bl_min_delta; - uint32_t bl_low_limit; -}; - -/* ops uses standard MDP_PP_* flags */ -struct mdss_ad_init_cfg { - uint32_t ops; - union { - struct mdss_ad_init init; - struct mdss_ad_cfg cfg; - } params; -}; - -/* mode uses MDSS_AD_MODE_* flags */ -struct mdss_ad_input { - uint32_t mode; - union { - uint32_t amb_light; - uint32_t strength; - uint32_t calib_bl; - } in; - uint32_t output; -}; - -#define MDSS_CALIB_MODE_BL 0x1 -struct mdss_calib_cfg { - uint32_t ops; - uint32_t calib_mask; -}; - -enum { - mdp_op_pcc_cfg, - mdp_op_csc_cfg, - mdp_op_lut_cfg, - mdp_op_qseed_cfg, - mdp_bl_scale_cfg, - mdp_op_pa_cfg, - mdp_op_pa_v2_cfg, - mdp_op_dither_cfg, - mdp_op_gamut_cfg, - mdp_op_calib_cfg, - mdp_op_ad_cfg, - mdp_op_ad_input, - mdp_op_calib_mode, - mdp_op_calib_buffer, - mdp_op_calib_dcm_state, - mdp_op_max, - mdp_op_pa_dither_cfg, - mdp_op_ad_bl_cfg, - mdp_op_pp_max = 255, -}; -#define mdp_op_pa_dither_cfg mdp_op_pa_dither_cfg -#define mdp_op_pp_max mdp_op_pp_max - -#define mdp_op_ad_bl_cfg mdp_op_ad_bl_cfg - -enum { - WB_FORMAT_NV12, - WB_FORMAT_RGB_565, - WB_FORMAT_RGB_888, - WB_FORMAT_xRGB_8888, - WB_FORMAT_ARGB_8888, - WB_FORMAT_BGRA_8888, - WB_FORMAT_BGRX_8888, - WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ -}; - -struct msmfb_mdp_pp { - uint32_t op; - union { - struct mdp_pcc_cfg_data pcc_cfg_data; - struct mdp_csc_cfg_data csc_cfg_data; - struct mdp_lut_cfg_data lut_cfg_data; - struct mdp_qseed_cfg_data qseed_cfg_data; - struct mdp_bl_scale_data bl_scale_data; - struct mdp_pa_cfg_data pa_cfg_data; - struct mdp_pa_v2_cfg_data pa_v2_cfg_data; - struct mdp_dither_cfg_data dither_cfg_data; - struct mdp_gamut_cfg_data gamut_cfg_data; - struct mdp_calib_config_data calib_cfg; - struct mdss_ad_init_cfg ad_init_cfg; - struct mdss_calib_cfg mdss_calib_cfg; - struct mdss_ad_input ad_input; - struct mdp_calib_config_buffer calib_buffer; - struct mdp_calib_dcm_state calib_dcm; - struct mdss_ad_bl_cfg ad_bl_cfg; - } data; -}; - -#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 -enum { - metadata_op_none, - metadata_op_base_blend, - metadata_op_frame_rate, - metadata_op_vic, - metadata_op_wb_format, - metadata_op_wb_secure, - metadata_op_get_caps, - metadata_op_crc, - metadata_op_get_ion_fd, - metadata_op_max -}; - -struct mdp_blend_cfg { - uint32_t is_premultiplied; -}; - -struct mdp_mixer_cfg { - uint32_t writeback_format; - uint32_t alpha; -}; - -struct mdss_hw_caps { - uint32_t mdp_rev; - uint8_t rgb_pipes; - uint8_t vig_pipes; - uint8_t dma_pipes; - uint8_t max_smp_cnt; - uint8_t smp_per_pipe; - uint32_t features; -}; - -struct msmfb_metadata { - uint32_t op; - uint32_t flags; - union { - struct mdp_misr misr_request; - struct mdp_blend_cfg blend_cfg; - struct mdp_mixer_cfg mixer_cfg; - uint32_t panel_frame_rate; - uint32_t video_info_code; - struct mdss_hw_caps caps; - uint8_t secure_en; - int fbmem_ionfd; - } data; -}; - -#define MDP_MAX_FENCE_FD 32 -#define MDP_BUF_SYNC_FLAG_WAIT 1 -#define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 - -struct mdp_buf_sync { - uint32_t flags; - uint32_t acq_fen_fd_cnt; - uint32_t session_id; - int *acq_fen_fd; - int *rel_fen_fd; - int *retire_fen_fd; -}; - -struct mdp_async_blit_req_list { - struct mdp_buf_sync sync; - uint32_t count; - struct mdp_blit_req req[]; -}; - -#define MDP_DISPLAY_COMMIT_OVERLAY 1 - -struct mdp_display_commit { - uint32_t flags; - uint32_t wait_for_finish; - struct fb_var_screeninfo var; - /* - * user needs to follow guidelines as per below rules - * 1. source split is enabled: l_roi = roi and r_roi = 0 - * 2. source split is disabled: - * 2.1 split display: l_roi = l_roi and r_roi = r_roi - * 2.2 non split display: l_roi = roi and r_roi = 0 - */ - struct mdp_rect l_roi; - struct mdp_rect r_roi; -}; - -/** - * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE - * @num_overlays: Number of overlay layers as part of the frame. - * @overlay_list: Pointer to a list of overlay structures identifying - * the layers as part of the frame - * @flags: Flags can be used to extend behavior. - * @processed_overlays: Output parameter indicating how many pipes were - * successful. If there are no errors this number should - * match num_overlays. Otherwise it will indicate the last - * successful index for overlay that couldn't be set. - */ -struct mdp_overlay_list { - uint32_t num_overlays; - struct mdp_overlay **overlay_list; - uint32_t flags; - uint32_t processed_overlays; -}; - -struct mdp_page_protection { - uint32_t page_protection; -}; - - -struct mdp_mixer_info { - int pndx; - int pnum; - int ptype; - int mixer_num; - int z_order; -}; - -#define MAX_PIPE_PER_MIXER 7 - -struct msmfb_mixer_info_req { - int mixer_num; - int cnt; - struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; -}; - -enum { - DISPLAY_SUBSYSTEM_ID, - ROTATOR_SUBSYSTEM_ID, -}; - -enum { - MDP_IOMMU_DOMAIN_CP, - MDP_IOMMU_DOMAIN_NS, -}; - -enum { - MDP_WRITEBACK_MIRROR_OFF, - MDP_WRITEBACK_MIRROR_ON, - MDP_WRITEBACK_MIRROR_PAUSE, - MDP_WRITEBACK_MIRROR_RESUME, -}; - -enum mdp_color_space { - MDP_CSC_ITU_R_601, - MDP_CSC_ITU_R_601_FR, - MDP_CSC_ITU_R_709, -}; - -/* - * These definitions are a continuation of the mdp_color_space enum above - */ -#define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) -#define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) -enum { - mdp_igc_v1_7 = 1, - mdp_igc_vmax, - mdp_hist_lut_v1_7, - mdp_hist_lut_vmax, - mdp_pgc_v1_7, - mdp_pgc_vmax, - mdp_dither_v1_7, - mdp_dither_vmax, - mdp_gamut_v1_7, - mdp_gamut_vmax, - mdp_pa_v1_7, - mdp_pa_vmax, - mdp_pcc_v1_7, - mdp_pcc_vmax, - mdp_pp_legacy, - mdp_dither_pa_v1_7, - mdp_igc_v3, - mdp_pp_unknown = 255 -}; - -#define mdp_dither_pa_v1_7 mdp_dither_pa_v1_7 -#define mdp_pp_unknown mdp_pp_unknown -#define mdp_igc_v3 mdp_igc_v3 - -/* PP Features */ -enum { - IGC = 1, - PCC, - GC, - PA, - GAMUT, - DITHER, - QSEED, - HIST_LUT, - HIST, - PP_FEATURE_MAX, - PA_DITHER, - PP_MAX_FEATURES = 25, -}; - -#define PA_DITHER PA_DITHER -#define PP_MAX_FEATURES PP_MAX_FEATURES - -struct mdp_pp_feature_version { - uint32_t pp_feature; - uint32_t version_info; -}; -#endif /* _MSM_MDP_H_*/ diff --git a/sdm710/original-kernel-headers/linux/msm_mdp_ext.h b/sdm710/original-kernel-headers/linux/msm_mdp_ext.h deleted file mode 100644 index 571d5944..00000000 --- a/sdm710/original-kernel-headers/linux/msm_mdp_ext.h +++ /dev/null @@ -1,706 +0,0 @@ -#ifndef _MSM_MDP_EXT_H_ -#define _MSM_MDP_EXT_H_ - -#include <linux/msm_mdp.h> - -#define MDP_IOCTL_MAGIC 'S' -/* atomic commit ioctl used for validate and commit request */ -#define MSMFB_ATOMIC_COMMIT _IOWR(MDP_IOCTL_MAGIC, 128, void *) - -/* - * Ioctl for updating the layer position asynchronously. Initially, pipes - * should be configured with MDP_LAYER_ASYNC flag set during the atomic commit, - * after which any number of position update calls can be made. This would - * enable multiple position updates within a single vsync. However, the screen - * update would happen only after vsync, which would pick the latest update. - * - * Limitations: - * - Currently supported only for video mode panels with single LM or dual LM - * with source_split enabled. - * - Only position update is supported with no scaling/cropping. - * - Async layers should have unique z_order. - */ -#define MSMFB_ASYNC_POSITION_UPDATE _IOWR(MDP_IOCTL_MAGIC, 129, \ - struct mdp_position_update) - -/* - * Ioctl for sending the config information. - * QSEED3 coefficeint LUT tables is passed by the user space using this IOCTL. - */ -#define MSMFB_MDP_SET_CFG _IOW(MDP_IOCTL_MAGIC, 130, \ - struct mdp_set_cfg) - -/* - * To allow proper structure padding for 64bit/32bit target - */ -#ifdef __LP64 -#define MDP_LAYER_COMMIT_V1_PAD 2 -#else -#define MDP_LAYER_COMMIT_V1_PAD 3 -#endif - -/* - * LAYER FLAG CONFIGURATION - */ -/* left-right layer flip flag */ -#define MDP_LAYER_FLIP_LR 0x1 - -/* up-down layer flip flag */ -#define MDP_LAYER_FLIP_UD 0x2 - -/* - * This flag enables pixel extension for the current layer. Validate/commit - * call uses scale parameters when this flag is enabled. - */ -#define MDP_LAYER_ENABLE_PIXEL_EXT 0x4 - -/* Flag indicates that layer is foreground layer */ -#define MDP_LAYER_FORGROUND 0x8 - -/* Flag indicates that layer is associated with secure session */ -#define MDP_LAYER_SECURE_SESSION 0x10 - -/* - * Flag indicates that layer is drawing solid fill. Validate/commit call - * does not expect buffer when this flag is enabled. - */ -#define MDP_LAYER_SOLID_FILL 0x20 - -/* Layer format is deinterlace */ -#define MDP_LAYER_DEINTERLACE 0x40 - -/* layer contains bandwidth compressed format data */ -#define MDP_LAYER_BWC 0x80 - -/* layer is async position updatable */ -#define MDP_LAYER_ASYNC 0x100 - -/* layer contains postprocessing configuration data */ -#define MDP_LAYER_PP 0x200 - -/* Flag indicates that layer is associated with secure display session */ -#define MDP_LAYER_SECURE_DISPLAY_SESSION 0x400 - -/* Flag enabled qseed3 scaling for the current layer */ -#define MDP_LAYER_ENABLE_QSEED3_SCALE 0x800 - -/* - * layer will work in multirect mode, where single hardware should - * fetch multiple rectangles with a single hardware - */ -#define MDP_LAYER_MULTIRECT_ENABLE 0x1000 - -/* - * if flag present and multirect is enabled, multirect will work in parallel - * fetch mode, otherwise it will default to serial fetch mode. - */ -#define MDP_LAYER_MULTIRECT_PARALLEL_MODE 0x2000 - -/* - * DESTINATION SCALER FLAG CONFIGURATION - */ - -/* Enable/disable Destination scaler */ -#define MDP_DESTSCALER_ENABLE 0x1 - -/* - * Indicating mdp_destination_scaler_data contains - * Scaling parameter update. Can be set anytime. - */ -#define MDP_DESTSCALER_SCALE_UPDATE 0x2 - -/* - * Indicating mdp_destination_scaler_data contains - * Detail enhancement setting update. Can be set anytime. - */ -#define MDP_DESTSCALER_ENHANCER_UPDATE 0x4 - -/* - * VALIDATE/COMMIT FLAG CONFIGURATION - */ - -/* - * Client enables it to inform that call is to validate layers before commit. - * If this flag is not set then driver will use MSMFB_ATOMIC_COMMIT for commit. - */ -#define MDP_VALIDATE_LAYER 0x01 - -/* - * This flag is only valid for commit call. Commit behavior is synchronous - * when this flag is defined. It blocks current call till processing is - * complete. Behavior is asynchronous otherwise. - */ -#define MDP_COMMIT_WAIT_FOR_FINISH 0x02 - -/* - * This flag is only valid for commit call and used for debugging purpose. It - * forces the to wait for sync fences. - */ -#define MDP_COMMIT_SYNC_FENCE_WAIT 0x04 - -/* Flag to enable AVR(Adaptive variable refresh) feature. */ -#define MDP_COMMIT_AVR_EN 0x08 - -/* - * Flag to select one shot mode when AVR feature is enabled. - * Default mode is continuous mode. - */ -#define MDP_COMMIT_AVR_ONE_SHOT_MODE 0x10 - -/* Flag to enable concurrent writeback for the frame */ -#define MDP_COMMIT_CWB_EN 0x800 - -/* - * Flag to select DSPP as the data point for CWB. If CWB - * is enabled without this flag, LM will be selected as data point. - */ -#define MDP_COMMIT_CWB_DSPP 0x1000 - -#define MDP_COMMIT_VERSION_1_0 0x00010000 - -/* - * Configuration structures - * All parameters are input to driver unless mentioned output parameter - * explicitly. - */ -struct mdp_layer_plane { - /* DMA buffer file descriptor information. */ - int fd; - - /* Pixel offset in the dma buffer. */ - uint32_t offset; - - /* Number of bytes in one scan line including padding bytes. */ - uint32_t stride; -}; - -struct mdp_layer_buffer { - /* layer width in pixels. */ - uint32_t width; - - /* layer height in pixels. */ - uint32_t height; - - /* - * layer format in DRM-style fourcc, refer drm_fourcc.h for - * standard formats - */ - uint32_t format; - - /* plane to hold the fd, offset, etc for all color components */ - struct mdp_layer_plane planes[MAX_PLANES]; - - /* valid planes count in layer planes list */ - uint32_t plane_count; - - /* compression ratio factor, value depends on the pixel format */ - struct mult_factor comp_ratio; - - /* - * SyncFence associated with this buffer. It is used in two ways. - * - * 1. Driver waits to consume the buffer till producer signals in case - * of primary and external display. - * - * 2. Writeback device uses buffer structure for output buffer where - * driver is producer. However, client sends the fence with buffer to - * indicate that consumer is still using the buffer and it is not ready - * for new content. - */ - int fence; - - /* 32bits reserved value for future usage. */ - uint32_t reserved; -}; - -/* - * One layer holds configuration for one pipe. If client wants to stage single - * layer on two pipes then it should send two different layers with relative - * (x,y) information. Client must send same information during validate and - * commit call. Commit call may fail if client sends different layer information - * attached to same pipe during validate and commit. Device invalidate the pipe - * once it receives the vsync for that commit. - */ -struct mdp_input_layer { - /* - * Flag to enable/disable properties for layer configuration. Refer - * layer flag configuration section for all possible flags. - */ - uint32_t flags; - - /* - * Pipe selection for this layer by client. Client provides the index - * in validate and commit call. Device reserves the pipe once validate - * is successful. Device only uses validated pipe during commit call. - * If client sends different layer/pipe configuration in validate & - * commit then commit may fail. - */ - uint32_t pipe_ndx; - - /* - * Horizontal decimation value, this indicates the amount of pixels - * dropped for each pixel that is fetched from a line. It does not - * result in bandwidth reduction because pixels are still fetched from - * memory but dropped internally by hardware. - * The decimation value given should be power of two of decimation - * amount. - * 0: no decimation - * 1: decimate by 2 (drop 1 pixel for each pixel fetched) - * 2: decimate by 4 (drop 3 pixels for each pixel fetched) - * 3: decimate by 8 (drop 7 pixels for each pixel fetched) - * 4: decimate by 16 (drop 15 pixels for each pixel fetched) - */ - uint8_t horz_deci; - - /* - * Vertical decimation value, this indicates the amount of lines - * dropped for each line that is fetched from overlay. It saves - * bandwidth because decimated pixels are not fetched. - * The decimation value given should be power of two of decimation - * amount. - * 0: no decimation - * 1: decimation by 2 (drop 1 line for each line fetched) - * 2: decimation by 4 (drop 3 lines for each line fetched) - * 3: decimation by 8 (drop 7 lines for each line fetched) - * 4: decimation by 16 (drop 15 lines for each line fetched) - */ - uint8_t vert_deci; - - /* - * Used to set plane opacity. The range can be from 0-255, where - * 0 means completely transparent and 255 means fully opaque. - */ - uint8_t alpha; - - /* - * Blending stage to occupy in display, if multiple layers are present, - * highest z_order usually means the top most visible layer. The range - * acceptable is from 0-7 to support blending up to 8 layers. - */ - uint16_t z_order; - - /* - * Color used as color key for transparency. Any pixel in fetched - * image matching this color will be transparent when blending. - * The color should be in same format as the source image format. - */ - uint32_t transp_mask; - - /* - * Solid color used to fill the overlay surface when no source - * buffer is provided. - */ - uint32_t bg_color; - - /* blend operation defined in "mdss_mdp_blend_op" enum. */ - enum mdss_mdp_blend_op blend_op; - - /* color space of the source */ - enum mdp_color_space color_space; - - /* - * Source crop rectangle, portion of image that will be fetched. This - * should always be within boundaries of source image. - */ - struct mdp_rect src_rect; - - /* - * Destination rectangle, the position and size of image on screen. - * This should always be within panel boundaries. - */ - struct mdp_rect dst_rect; - - /* Scaling parameters. */ - void *scale; - - /* Buffer attached with each layer. Device uses it for commit call. */ - struct mdp_layer_buffer buffer; - - /* - * Source side post processing configuration information for each - * layer. - */ - void *pp_info; - - /* - * This is an output parameter. - * - * Only for validate call. Frame buffer device sets error code - * based on validate call failure scenario. - */ - int error_code; - - /* 32bits reserved value for future usage. */ - uint32_t reserved[6]; -}; - -struct mdp_output_layer { - /* - * Flag to enable/disable properties for layer configuration. Refer - * layer flag config section for all possible flags. - */ - uint32_t flags; - - /* - * Writeback destination selection for output. Client provides the index - * in validate and commit call. - */ - uint32_t writeback_ndx; - - /* Buffer attached with output layer. Device uses it for commit call */ - struct mdp_layer_buffer buffer; - - /* color space of the destination */ - enum mdp_color_space color_space; - - /* 32bits reserved value for future usage. */ - uint32_t reserved[5]; -}; - -/* - * Destination scaling info structure holds setup paramaters for upscaling - * setting in the destination scaling block. - */ -struct mdp_destination_scaler_data { - /* - * Flag to switch between mode for destination scaler. Please Refer to - * destination scaler flag config for all possible setting. - */ - uint32_t flags; - - /* - * Destination scaler selection index. Client provides the index in - * validate and commit call. - */ - uint32_t dest_scaler_ndx; - - /* - * LM width configuration per Destination scaling updates - */ - uint32_t lm_width; - - /* - * LM height configuration per Destination scaling updates - */ - uint32_t lm_height; - - /* - * The scaling parameters for all the mode except disable. For - * disabling the scaler, there is no need to provide the scale. - * A userspace pointer points to struct mdp_scale_data_v2. - */ - uint64_t scale; -}; - -/* Enable Deterministic Frame Rate Control (FRC) */ -#define MDP_VIDEO_FRC_ENABLE (1 << 0) - -struct mdp_frc_info { - /* flags to control FRC feature */ - uint32_t flags; - /* video frame count per frame */ - uint32_t frame_cnt; - /* video timestamp per frame in millisecond unit */ - int64_t timestamp; -}; - -/* - * Commit structure holds layer stack send by client for validate and commit - * call. If layers are different between validate and commit call then commit - * call will also do validation. In such case, commit may fail. - */ -struct mdp_layer_commit_v1 { - /* - * Flag to enable/disable properties for commit/validate call. Refer - * validate/commit flag config section for all possible flags. - */ - uint32_t flags; - - /* - * This is an output parameter. - * - * Frame buffer device provides release fence handle to client. It - * triggers release fence when display hardware has consumed all the - * buffers attached to this commit call and buffer is ready for reuse - * for primary and external. For writeback case, it triggers it when - * output buffer is ready for consumer. - */ - int release_fence; - - /* - * Left_roi is optional configuration. Client configures it only when - * partial update is enabled. It defines the "region of interest" on - * left part of panel when it is split display. For non-split display, - * it defines the "region of interest" on the panel. - */ - struct mdp_rect left_roi; - - /* - * Right_roi is optional configuration. Client configures it only when - * partial update is enabled. It defines the "region of interest" on - * right part of panel for split display configuration. It is not - * required for non-split display. - */ - struct mdp_rect right_roi; - - /* Pointer to a list of input layers for composition. */ - struct mdp_input_layer *input_layers; - - /* Input layer count present in input list */ - uint32_t input_layer_cnt; - - /* - * Output layer for writeback display. It supports only one - * layer as output layer. This is not required for primary - * and external displays - */ - struct mdp_output_layer *output_layer; - - /* - * This is an output parameter. - * - * Frame buffer device provides retire fence handle if - * COMMIT_RETIRE_FENCE flag is set in commit call. It triggers - * retire fence when current layers are swapped with new layers - * on display hardware. For video mode panel and writeback, - * retire fence and release fences are triggered at the same - * time while command mode panel triggers release fence first - * (on pingpong done) and retire fence (on rdptr done) - * after that. - */ - int retire_fence; - - /* - * Scaler data and control for setting up destination scaler. - * A userspace pointer that points to a list of - * struct mdp_destination_scaler_data. - */ - void *dest_scaler; - - /* - * Represents number of Destination scaler data provied by userspace. - */ - uint32_t dest_scaler_cnt; - - /* FRC info per device which contains frame count and timestamp */ - struct mdp_frc_info *frc_info; - - /* 32-bits reserved value for future usage. */ - uint32_t reserved[MDP_LAYER_COMMIT_V1_PAD]; -}; - -/* - * mdp_overlay_list - argument for ioctl MSMFB_ATOMIC_COMMIT - */ -struct mdp_layer_commit { - /* - * 32bit version indicates the commit structure selection - * from union. Lower 16bits indicates the minor version while - * higher 16bits indicates the major version. It selects the - * commit structure based on major version selection. Minor version - * indicates that reserved fields are in use. - * - * Current supported version is 1.0 (Major:1 Minor:0) - */ - uint32_t version; - union { - /* Layer commit/validate definition for V1 */ - struct mdp_layer_commit_v1 commit_v1; - }; -}; - -struct mdp_point { - uint32_t x; - uint32_t y; -}; - -/* - * Async updatable layers. One layer holds configuration for one pipe. - */ -struct mdp_async_layer { - /* - * Flag to enable/disable properties for layer configuration. Refer - * layer flag config section for all possible flags. - */ - uint32_t flags; - - /* - * Pipe selection for this layer by client. Client provides the - * pipe index that the device reserved during ATOMIC_COMMIT. - */ - uint32_t pipe_ndx; - - /* Source start x,y. */ - struct mdp_point src; - - /* Destination start x,y. */ - struct mdp_point dst; - - /* - * This is an output parameter. - * - * Frame buffer device sets error code based on the failure. - */ - int error_code; - - uint32_t reserved[3]; -}; - -/* - * mdp_position_update - argument for ioctl MSMFB_ASYNC_POSITION_UPDATE - */ -struct mdp_position_update { - /* Pointer to a list of async updatable input layers */ - struct mdp_async_layer *input_layers; - - /* Input layer count present in input list */ - uint32_t input_layer_cnt; -}; - -#define MAX_DET_CURVES 3 -struct mdp_det_enhance_data { - uint32_t enable; - int16_t sharpen_level1; - int16_t sharpen_level2; - uint16_t clip; - uint16_t limit; - uint16_t thr_quiet; - uint16_t thr_dieout; - uint16_t thr_low; - uint16_t thr_high; - uint16_t prec_shift; - int16_t adjust_a[MAX_DET_CURVES]; - int16_t adjust_b[MAX_DET_CURVES]; - int16_t adjust_c[MAX_DET_CURVES]; -}; - -/* Flags to enable Scaler and its sub components */ -#define ENABLE_SCALE 0x1 -#define ENABLE_DETAIL_ENHANCE 0x2 -#define ENABLE_DIRECTION_DETECTION 0x4 - -/* LUT configuration flags */ -#define SCALER_LUT_SWAP 0x1 -#define SCALER_LUT_DIR_WR 0x2 -#define SCALER_LUT_Y_CIR_WR 0x4 -#define SCALER_LUT_UV_CIR_WR 0x8 -#define SCALER_LUT_Y_SEP_WR 0x10 -#define SCALER_LUT_UV_SEP_WR 0x20 - -/* Y/RGB and UV filter configuration */ -#define FILTER_EDGE_DIRECTED_2D 0x0 -#define FILTER_CIRCULAR_2D 0x1 -#define FILTER_SEPARABLE_1D 0x2 -#define FILTER_BILINEAR 0x3 - -/* Alpha filters */ -#define FILTER_ALPHA_DROP_REPEAT 0x0 -#define FILTER_ALPHA_BILINEAR 0x1 - -/** - * struct mdp_scale_data_v2 - * Driver uses this new Data structure for storing all scaling params - * This structure contains all pixel extension data and QSEED3 filter - * configuration and coefficient table indices - */ -struct mdp_scale_data_v2 { - uint32_t enable; - - /* Init phase values */ - int32_t init_phase_x[MAX_PLANES]; - int32_t phase_step_x[MAX_PLANES]; - int32_t init_phase_y[MAX_PLANES]; - int32_t phase_step_y[MAX_PLANES]; - - /* - * This should be set to toal horizontal pixels - * left + right + width - */ - uint32_t num_ext_pxls_left[MAX_PLANES]; - - /* Unused param for backward compatibility */ - uint32_t num_ext_pxls_right[MAX_PLANES]; - - /* - * This should be set to vertical pixels - * top + bottom + height - */ - uint32_t num_ext_pxls_top[MAX_PLANES]; - - /* Unused param for backward compatibility */ - uint32_t num_ext_pxls_btm[MAX_PLANES]; - - /* over fetch pixels */ - int32_t left_ftch[MAX_PLANES]; - int32_t left_rpt[MAX_PLANES]; - int32_t right_ftch[MAX_PLANES]; - int32_t right_rpt[MAX_PLANES]; - - /* Repeat pixels */ - uint32_t top_rpt[MAX_PLANES]; - uint32_t btm_rpt[MAX_PLANES]; - uint32_t top_ftch[MAX_PLANES]; - uint32_t btm_ftch[MAX_PLANES]; - - uint32_t roi_w[MAX_PLANES]; - - /* - * alpha plane can only be scaled using bilinear or pixel - * repeat/drop, specify these for Y and UV planes only - */ - uint32_t preload_x[MAX_PLANES]; - uint32_t preload_y[MAX_PLANES]; - uint32_t src_width[MAX_PLANES]; - uint32_t src_height[MAX_PLANES]; - - uint32_t dst_width; - uint32_t dst_height; - - uint32_t y_rgb_filter_cfg; - uint32_t uv_filter_cfg; - uint32_t alpha_filter_cfg; - uint32_t blend_cfg; - - uint32_t lut_flag; - uint32_t dir_lut_idx; - - /* for Y(RGB) and UV planes*/ - uint32_t y_rgb_cir_lut_idx; - uint32_t uv_cir_lut_idx; - uint32_t y_rgb_sep_lut_idx; - uint32_t uv_sep_lut_idx; - - struct mdp_det_enhance_data detail_enhance; - - /* reserved value for future usage. */ - uint64_t reserved[8]; -}; - -/** - * struct mdp_scale_luts_info - * This struct pointer is received as payload in SET_CFG_IOCTL when the flags - * is set to MDP_QSEED3_LUT_CFG - * @dir_lut: Direction detection coefficients table - * @cir_lut: Circular coefficeints table - * @sep_lut: Separable coefficeints table - * @dir_lut_size: Size of direction coefficients table - * @cir_lut_size: Size of circular coefficients table - * @sep_lut_size: Size of separable coefficients table - */ -struct mdp_scale_luts_info { - uint64_t dir_lut; - uint64_t cir_lut; - uint64_t sep_lut; - uint32_t dir_lut_size; - uint32_t cir_lut_size; - uint32_t sep_lut_size; -}; - -#define MDP_QSEED3_LUT_CFG 0x1 - -struct mdp_set_cfg { - uint64_t flags; - uint32_t len; - uint64_t payload; -}; -#endif diff --git a/sdm710/original-kernel-headers/linux/msm_pft.h b/sdm710/original-kernel-headers/linux/msm_pft.h deleted file mode 100644 index 1127337e..00000000 --- a/sdm710/original-kernel-headers/linux/msm_pft.h +++ /dev/null @@ -1,134 +0,0 @@ -/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MSM_PFT_H_ -#define MSM_PFT_H_ - -#include <linux/types.h> - -/** - * enum pft_command_opcode - PFT driver command ID - * - * @PFT_CMD_OPCODE_SET_STATE - - * command ID to set PFT driver state - * @PFT_CMD_OPCODE_UPDATE_REG_APP_UID - - * command ID to update the list of registered application - * UID - * @PFT_CMD_OPCODE_PERFORM_IN_PLACE_FILE_ENC - - * command ID to perfrom in-place file encryption - */ -enum pft_command_opcode { - PFT_CMD_OPCODE_SET_STATE, - PFT_CMD_OPCODE_UPDATE_REG_APP_UID, - PFT_CMD_OPCODE_PERFORM_IN_PLACE_FILE_ENC, - /* */ - PFT_CMD_OPCODE_MAX_COMMAND_INDEX -}; - -/** - * enum pft_state - PFT driver operational states - * - * @PFT_STATE_DEACTIVATED - driver is deativated. - * @PFT_STATE_DEACTIVATING - driver is in the process of being deativated. - * @PFT_STATE_KEY_REMOVED - driver is active but no encryption key is loaded. - * @PFT_STATE_REMOVING_KEY - driver is active, but the encryption key is being - * removed. - * @PFT_STATE_KEY_LOADED - driver is active, and the encryption key is loaded - * to encryption block, hence registered apps can perform file operations - * on encrypted files. - */ -enum pft_state { - PFT_STATE_DEACTIVATED, - PFT_STATE_DEACTIVATING, - PFT_STATE_KEY_REMOVED, - PFT_STATE_REMOVING_KEY, - PFT_STATE_KEY_LOADED, - /* Internal */ - PFT_STATE_MAX_INDEX -}; - -/** - * enum pft_command_response_code - PFT response on the previous - * command - * - * @PFT_CMD_RESP_SUCCESS - The command was properly processed - * without an error. - * @PFT_CMD_RESP_GENERAL_ERROR - - * Indicates an error that cannot be better described by a - * more specific errors below. - * @PFT_CMD_RESP_INVALID_COMMAND - Invalid or unsupported - * command id. - * @PFT_CMD_RESP_INVALID_CMD_PARAMS - Invalid command - * parameters. - * @PFT_CMD_RESP_INVALID_STATE - Invalid state - * @PFT_CMD_RESP_ALREADY_IN_STATE - Used to indicates that - * the new state is equal to the existing one. - * @PFT_CMD_RESP_INPLACE_FILE_IS_OPEN - Used to indicates - * that the file that should be encrypted is already open - * and can be encrypted. - * @PFT_CMD_RESP_ENT_FILES_CLOSING_FAILURE - * Indicates about failure of the PFT to close Enterprise files - * @PFT_CMD_RESP_MAX_INDEX - */ -enum pft_command_response_code { - PFT_CMD_RESP_SUCCESS, - PFT_CMD_RESP_GENERAL_ERROR, - PFT_CMD_RESP_INVALID_COMMAND, - PFT_CMD_RESP_INVALID_CMD_PARAMS, - PFT_CMD_RESP_INVALID_STATE, - PFT_CMD_RESP_ALREADY_IN_STATE, - PFT_CMD_RESP_INPLACE_FILE_IS_OPEN, - PFT_CMD_RESP_ENT_FILES_CLOSING_FAILURE, - /* Internal */ - PFT_CMD_RESP_MAX_INDEX -}; - -/** - * struct pft_command_response - response structure - * - * @command_id - see enum pft_command_response_code - * @error_codee - see enum pft_command_response_code - */ -struct pft_command_response { - __u32 command_id; - __u32 error_code; -}; - -/** - * struct pft_command - pft command - * - * @opcode - see enum pft_command_opcode. - * @set_state.state - see enum pft_state. - * @update_app_list.count - number of items in the - * registered applications list. - * @update_app_list.table - registered applications array - * @preform_in_place_file_enc.file_descriptor - file descriptor - * of the opened file to be in-placed encrypted. - */ -struct pft_command { - __u32 opcode; - union { - struct { - /* @see pft_state */ - __u32 state; - } set_state; - struct { - __u32 items_count; /* number of items */ - uid_t table[0]; /* array of UIDs */ - } update_app_list; - struct { - __u32 file_descriptor; - } preform_in_place_file_enc; - }; -}; - -#endif /* MSM_PFT_H_ */ diff --git a/sdm710/original-kernel-headers/linux/msm_rmnet.h b/sdm710/original-kernel-headers/linux/msm_rmnet.h deleted file mode 100644 index 5b933286..00000000 --- a/sdm710/original-kernel-headers/linux/msm_rmnet.h +++ /dev/null @@ -1,152 +0,0 @@ -#ifndef _MSM_RMNET_H_ -#define _MSM_RMNET_H_ - -/* Bitmap macros for RmNET driver operation mode. */ -#define RMNET_MODE_NONE (0x00) -#define RMNET_MODE_LLP_ETH (0x01) -#define RMNET_MODE_LLP_IP (0x02) -#define RMNET_MODE_QOS (0x04) -#define RMNET_MODE_MASK (RMNET_MODE_LLP_ETH | \ - RMNET_MODE_LLP_IP | \ - RMNET_MODE_QOS) - -#define RMNET_IS_MODE_QOS(mode) \ - ((mode & RMNET_MODE_QOS) == RMNET_MODE_QOS) -#define RMNET_IS_MODE_IP(mode) \ - ((mode & RMNET_MODE_LLP_IP) == RMNET_MODE_LLP_IP) - -/* IOCTL commands - * Values chosen to not conflict with other drivers in the ecosystem - */ - -#define RMNET_IOCTL_SET_LLP_ETHERNET 0x000089F1 /* Set Ethernet protocol */ -#define RMNET_IOCTL_SET_LLP_IP 0x000089F2 /* Set RAWIP protocol */ -#define RMNET_IOCTL_GET_LLP 0x000089F3 /* Get link protocol */ -#define RMNET_IOCTL_SET_QOS_ENABLE 0x000089F4 /* Set QoS header enabled */ -#define RMNET_IOCTL_SET_QOS_DISABLE 0x000089F5 /* Set QoS header disabled*/ -#define RMNET_IOCTL_GET_QOS 0x000089F6 /* Get QoS header state */ -#define RMNET_IOCTL_GET_OPMODE 0x000089F7 /* Get operation mode */ -#define RMNET_IOCTL_OPEN 0x000089F8 /* Open transport port */ -#define RMNET_IOCTL_CLOSE 0x000089F9 /* Close transport port */ -#define RMNET_IOCTL_FLOW_ENABLE 0x000089FA /* Flow enable */ -#define RMNET_IOCTL_FLOW_DISABLE 0x000089FB /* Flow disable */ -#define RMNET_IOCTL_FLOW_SET_HNDL 0x000089FC /* Set flow handle */ -#define RMNET_IOCTL_EXTENDED 0x000089FD /* Extended IOCTLs */ - -/* RmNet Data Required IOCTLs */ -#define RMNET_IOCTL_GET_SUPPORTED_FEATURES 0x0000 /* Get features */ -#define RMNET_IOCTL_SET_MRU 0x0001 /* Set MRU */ -#define RMNET_IOCTL_GET_MRU 0x0002 /* Get MRU */ -#define RMNET_IOCTL_GET_EPID 0x0003 /* Get endpoint ID */ -#define RMNET_IOCTL_GET_DRIVER_NAME 0x0004 /* Get driver name */ -#define RMNET_IOCTL_ADD_MUX_CHANNEL 0x0005 /* Add MUX ID */ -#define RMNET_IOCTL_SET_EGRESS_DATA_FORMAT 0x0006 /* Set EDF */ -#define RMNET_IOCTL_SET_INGRESS_DATA_FORMAT 0x0007 /* Set IDF */ -#define RMNET_IOCTL_SET_AGGREGATION_COUNT 0x0008 /* Set agg count */ -#define RMNET_IOCTL_GET_AGGREGATION_COUNT 0x0009 /* Get agg count */ -#define RMNET_IOCTL_SET_AGGREGATION_SIZE 0x000A /* Set agg size */ -#define RMNET_IOCTL_GET_AGGREGATION_SIZE 0x000B /* Get agg size */ -#define RMNET_IOCTL_FLOW_CONTROL 0x000C /* Do flow control */ -#define RMNET_IOCTL_GET_DFLT_CONTROL_CHANNEL 0x000D /* For legacy use */ -#define RMNET_IOCTL_GET_HWSW_MAP 0x000E /* Get HW/SW map */ -#define RMNET_IOCTL_SET_RX_HEADROOM 0x000F /* RX Headroom */ -#define RMNET_IOCTL_GET_EP_PAIR 0x0010 /* Endpoint pair */ -#define RMNET_IOCTL_SET_QOS_VERSION 0x0011 /* 8/6 byte QoS hdr*/ -#define RMNET_IOCTL_GET_QOS_VERSION 0x0012 /* 8/6 byte QoS hdr*/ -#define RMNET_IOCTL_GET_SUPPORTED_QOS_MODES 0x0013 /* Get QoS modes */ -#define RMNET_IOCTL_SET_SLEEP_STATE 0x0014 /* Set sleep state */ -#define RMNET_IOCTL_SET_XLAT_DEV_INFO 0x0015 /* xlat dev name */ -#define RMNET_IOCTL_DEREGISTER_DEV 0x0016 /* Dereg a net dev */ -#define RMNET_IOCTL_GET_SG_SUPPORT 0x0017 /* Query sg support*/ - -/* Return values for the RMNET_IOCTL_GET_SUPPORTED_FEATURES IOCTL */ -#define RMNET_IOCTL_FEAT_NOTIFY_MUX_CHANNEL (1<<0) -#define RMNET_IOCTL_FEAT_SET_EGRESS_DATA_FORMAT (1<<1) -#define RMNET_IOCTL_FEAT_SET_INGRESS_DATA_FORMAT (1<<2) -#define RMNET_IOCTL_FEAT_SET_AGGREGATION_COUNT (1<<3) -#define RMNET_IOCTL_FEAT_GET_AGGREGATION_COUNT (1<<4) -#define RMNET_IOCTL_FEAT_SET_AGGREGATION_SIZE (1<<5) -#define RMNET_IOCTL_FEAT_GET_AGGREGATION_SIZE (1<<6) -#define RMNET_IOCTL_FEAT_FLOW_CONTROL (1<<7) -#define RMNET_IOCTL_FEAT_GET_DFLT_CONTROL_CHANNEL (1<<8) -#define RMNET_IOCTL_FEAT_GET_HWSW_MAP (1<<9) - -/* Input values for the RMNET_IOCTL_SET_EGRESS_DATA_FORMAT IOCTL */ -#define RMNET_IOCTL_EGRESS_FORMAT_MAP (1<<1) -#define RMNET_IOCTL_EGRESS_FORMAT_AGGREGATION (1<<2) -#define RMNET_IOCTL_EGRESS_FORMAT_MUXING (1<<3) -#define RMNET_IOCTL_EGRESS_FORMAT_CHECKSUM (1<<4) - -/* Input values for the RMNET_IOCTL_SET_INGRESS_DATA_FORMAT IOCTL */ -#define RMNET_IOCTL_INGRESS_FORMAT_MAP (1<<1) -#define RMNET_IOCTL_INGRESS_FORMAT_DEAGGREGATION (1<<2) -#define RMNET_IOCTL_INGRESS_FORMAT_DEMUXING (1<<3) -#define RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM (1<<4) -#define RMNET_IOCTL_INGRESS_FORMAT_AGG_DATA (1<<5) - -/* User space may not have this defined. */ -#ifndef IFNAMSIZ -#define IFNAMSIZ 16 -#endif - -struct rmnet_ioctl_extended_s { - uint32_t extended_ioctl; - union { - uint32_t data; /* Generic data field for most extended IOCTLs */ - - /* Return values for - * RMNET_IOCTL_GET_DRIVER_NAME - * RMNET_IOCTL_GET_DFLT_CONTROL_CHANNEL - */ - int8_t if_name[IFNAMSIZ]; - - /* Input values for the RMNET_IOCTL_ADD_MUX_CHANNEL IOCTL */ - struct { - uint32_t mux_id; - int8_t vchannel_name[IFNAMSIZ]; - } rmnet_mux_val; - - /* Input values for the RMNET_IOCTL_FLOW_CONTROL IOCTL */ - struct { - uint8_t flow_mode; - uint8_t mux_id; - } flow_control_prop; - - /* Return values for RMNET_IOCTL_GET_EP_PAIR */ - struct { - uint32_t consumer_pipe_num; - uint32_t producer_pipe_num; - } ipa_ep_pair; - - struct { - uint32_t __data; /* Placeholder for legacy data*/ - uint32_t agg_size; - uint32_t agg_count; - } ingress_format; - } u; -}; - -struct rmnet_ioctl_data_s { - union { - uint32_t operation_mode; - uint32_t tcm_handle; - } u; -}; - -#define RMNET_IOCTL_QOS_MODE_6 (1<<0) -#define RMNET_IOCTL_QOS_MODE_8 (1<<1) - -/* QMI QoS header definition */ -struct QMI_QOS_HDR_S { - unsigned char version; - unsigned char flags; - uint32_t flow_id; -} __attribute((__packed__)); - -/* QMI QoS 8-byte header. */ -struct qmi_qos_hdr8_s { - struct QMI_QOS_HDR_S hdr; - uint8_t reserved[2]; -} __attribute((__packed__)); - -#endif /* _MSM_RMNET_H_ */ diff --git a/sdm710/original-kernel-headers/linux/msm_rotator.h b/sdm710/original-kernel-headers/linux/msm_rotator.h deleted file mode 100644 index 6beb6293..00000000 --- a/sdm710/original-kernel-headers/linux/msm_rotator.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef __MSM_ROTATOR_H__ -#define __MSM_ROTATOR_H__ - -#include <linux/types.h> -#include <linux/msm_mdp.h> - -#define MSM_ROTATOR_IOCTL_MAGIC 'R' - -#define MSM_ROTATOR_IOCTL_START \ - _IOWR(MSM_ROTATOR_IOCTL_MAGIC, 1, struct msm_rotator_img_info) -#define MSM_ROTATOR_IOCTL_ROTATE \ - _IOW(MSM_ROTATOR_IOCTL_MAGIC, 2, struct msm_rotator_data_info) -#define MSM_ROTATOR_IOCTL_FINISH \ - _IOW(MSM_ROTATOR_IOCTL_MAGIC, 3, int) - -#define ROTATOR_VERSION_01 0xA5B4C301 - -enum rotator_clk_type { - ROTATOR_CORE_CLK, - ROTATOR_PCLK, - ROTATOR_IMEM_CLK -}; - -struct msm_rotator_img_info { - unsigned int session_id; - struct msmfb_img src; - struct msmfb_img dst; - struct mdp_rect src_rect; - unsigned int dst_x; - unsigned int dst_y; - unsigned char rotations; - int enable; - unsigned int downscale_ratio; - unsigned int secure; -}; - -struct msm_rotator_data_info { - int session_id; - struct msmfb_data src; - struct msmfb_data dst; - unsigned int version_key; - struct msmfb_data src_chroma; - struct msmfb_data dst_chroma; -}; - -struct msm_rot_clocks { - const char *clk_name; - enum rotator_clk_type clk_type; - unsigned int clk_rate; -}; - -struct msm_rotator_platform_data { - unsigned int number_of_clocks; - unsigned int hardware_version_number; - struct msm_rot_clocks *rotator_clks; - struct msm_bus_scale_pdata *bus_scale_table; - char rot_iommu_split_domain; -}; -#endif - diff --git a/sdm710/original-kernel-headers/linux/msm_thermal_ioctl.h b/sdm710/original-kernel-headers/linux/msm_thermal_ioctl.h deleted file mode 100644 index 18caab69..00000000 --- a/sdm710/original-kernel-headers/linux/msm_thermal_ioctl.h +++ /dev/null @@ -1,92 +0,0 @@ -#ifndef _MSM_THERMAL_IOCTL_H -#define _MSM_THERMAL_IOCTL_H - -#include <linux/ioctl.h> - -#define MSM_THERMAL_IOCTL_NAME "msm_thermal_query" -#define MSM_IOCTL_FREQ_SIZE 16 - -struct __attribute__((__packed__)) cpu_freq_arg { - uint32_t cpu_num; - uint32_t freq_req; -}; - -struct __attribute__((__packed__)) clock_plan_arg { - uint32_t cluster_num; - /* - ** A value of zero for freq_table_len, will fetch the length of the - ** cluster frequency table. A non-zero value will fetch the frequency - ** table contents. - */ - uint32_t freq_table_len; - /* - ** For clusters with frequency table length greater than - ** MSM_IOCTL_FREQ_SIZE, the frequency table is fetched from kernel - ** in multiple sets or iterations. The set_idx variable, - ** indicates, which set/part of frequency table the user is requesting. - ** The set index value starts from zero. A set index value of 'Z', - ** will fetch MSM_IOCTL_FREQ_SIZE or maximum available number of - ** frequency values (if it is less than MSM_IOCTL_FREQ_SIZE) - ** from the frequency table, starting from the index - ** (Z * MSM_IOCTL_FREQ_SIZE). - ** For example, in a device supporting 19 different frequencies, a set - ** index value of 0 will fetch the first 16 (MSM_IOCTL_FREQ_SIZE) - ** frequencies starting from the index 0 and a set value of 1 will fetch - ** the remaining 3 frequencies starting from the index 16. - ** A successful get, will populate the freq_table_len with the - ** number of frequency table entries fetched. - */ - uint32_t set_idx; - unsigned int freq_table[MSM_IOCTL_FREQ_SIZE]; -}; - -struct __attribute__((__packed__)) voltage_plan_arg { - uint32_t cluster_num; - uint32_t voltage_table_len; - uint32_t set_idx; - uint32_t voltage_table[MSM_IOCTL_FREQ_SIZE]; -}; - -struct __attribute__((__packed__)) msm_thermal_ioctl { - uint32_t size; - union { - struct cpu_freq_arg cpu_freq; - struct clock_plan_arg clock_freq; - struct voltage_plan_arg voltage; - }; -}; - -enum { - /*Set CPU Frequency*/ - MSM_SET_CPU_MAX_FREQ = 0x00, - MSM_SET_CPU_MIN_FREQ = 0x01, - /*Set cluster frequency*/ - MSM_SET_CLUSTER_MAX_FREQ = 0x02, - MSM_SET_CLUSTER_MIN_FREQ = 0x03, - /*Get cluster frequency plan*/ - MSM_GET_CLUSTER_FREQ_PLAN = 0x04, - /*Get cluster voltage plan */ - MSM_GET_CLUSTER_VOLTAGE_PLAN = 0x05, - MSM_CMD_MAX_NR, -}; - -#define MSM_THERMAL_MAGIC_NUM 0xCA /*Unique magic number*/ - -#define MSM_THERMAL_SET_CPU_MAX_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM,\ - MSM_SET_CPU_MAX_FREQ, struct msm_thermal_ioctl) - -#define MSM_THERMAL_SET_CPU_MIN_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM,\ - MSM_SET_CPU_MIN_FREQ, struct msm_thermal_ioctl) - -#define MSM_THERMAL_SET_CLUSTER_MAX_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM,\ - MSM_SET_CLUSTER_MAX_FREQ, struct msm_thermal_ioctl) - -#define MSM_THERMAL_SET_CLUSTER_MIN_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM,\ - MSM_SET_CLUSTER_MIN_FREQ, struct msm_thermal_ioctl) - -#define MSM_THERMAL_GET_CLUSTER_FREQUENCY_PLAN _IOR(MSM_THERMAL_MAGIC_NUM,\ - MSM_GET_CLUSTER_FREQ_PLAN, struct msm_thermal_ioctl) - -#define MSM_THERMAL_GET_CLUSTER_VOLTAGE_PLAN _IOR(MSM_THERMAL_MAGIC_NUM,\ - MSM_GET_CLUSTER_VOLTAGE_PLAN, struct msm_thermal_ioctl) -#endif diff --git a/sdm710/original-kernel-headers/linux/msm_vidc_dec.h b/sdm710/original-kernel-headers/linux/msm_vidc_dec.h deleted file mode 100644 index 2b772131..00000000 --- a/sdm710/original-kernel-headers/linux/msm_vidc_dec.h +++ /dev/null @@ -1,629 +0,0 @@ -#ifndef _MSM_VIDC_DEC_H_ -#define _MSM_VIDC_DEC_H_ - -#include <linux/types.h> -#include <linux/ioctl.h> - -/* STATUS CODES */ -/* Base value for status codes */ -#define VDEC_S_BASE 0x40000000 -/* Success */ -#define VDEC_S_SUCCESS (VDEC_S_BASE) -/* General failure */ -#define VDEC_S_EFAIL (VDEC_S_BASE + 1) -/* Fatal irrecoverable failure. Need to tear down session. */ -#define VDEC_S_EFATAL (VDEC_S_BASE + 2) -/* Error detected in the passed parameters */ -#define VDEC_S_EBADPARAM (VDEC_S_BASE + 3) -/* Command called in invalid state. */ -#define VDEC_S_EINVALSTATE (VDEC_S_BASE + 4) - /* Insufficient OS resources - thread, memory etc. */ -#define VDEC_S_ENOSWRES (VDEC_S_BASE + 5) - /* Insufficient HW resources - core capacity maxed out. */ -#define VDEC_S_ENOHWRES (VDEC_S_BASE + 6) -/* Invalid command called */ -#define VDEC_S_EINVALCMD (VDEC_S_BASE + 7) -/* Command timeout. */ -#define VDEC_S_ETIMEOUT (VDEC_S_BASE + 8) -/* Pre-requirement is not met for API. */ -#define VDEC_S_ENOPREREQ (VDEC_S_BASE + 9) -/* Command queue is full. */ -#define VDEC_S_ECMDQFULL (VDEC_S_BASE + 10) -/* Command is not supported by this driver */ -#define VDEC_S_ENOTSUPP (VDEC_S_BASE + 11) -/* Command is not implemented by thedriver. */ -#define VDEC_S_ENOTIMPL (VDEC_S_BASE + 12) -/* Command is not implemented by the driver. */ -#define VDEC_S_BUSY (VDEC_S_BASE + 13) -#define VDEC_S_INPUT_BITSTREAM_ERR (VDEC_S_BASE + 14) - -#define VDEC_INTF_VER 1 -#define VDEC_MSG_BASE 0x0000000 -/* - *Codes to identify asynchronous message responses and events that driver - *wants to communicate to the app. - */ -#define VDEC_MSG_INVALID (VDEC_MSG_BASE + 0) -#define VDEC_MSG_RESP_INPUT_BUFFER_DONE (VDEC_MSG_BASE + 1) -#define VDEC_MSG_RESP_OUTPUT_BUFFER_DONE (VDEC_MSG_BASE + 2) -#define VDEC_MSG_RESP_INPUT_FLUSHED (VDEC_MSG_BASE + 3) -#define VDEC_MSG_RESP_OUTPUT_FLUSHED (VDEC_MSG_BASE + 4) -#define VDEC_MSG_RESP_FLUSH_INPUT_DONE (VDEC_MSG_BASE + 5) -#define VDEC_MSG_RESP_FLUSH_OUTPUT_DONE (VDEC_MSG_BASE + 6) -#define VDEC_MSG_RESP_START_DONE (VDEC_MSG_BASE + 7) -#define VDEC_MSG_RESP_STOP_DONE (VDEC_MSG_BASE + 8) -#define VDEC_MSG_RESP_PAUSE_DONE (VDEC_MSG_BASE + 9) -#define VDEC_MSG_RESP_RESUME_DONE (VDEC_MSG_BASE + 10) -#define VDEC_MSG_RESP_RESOURCE_LOADED (VDEC_MSG_BASE + 11) -#define VDEC_EVT_RESOURCES_LOST (VDEC_MSG_BASE + 12) -#define VDEC_MSG_EVT_CONFIG_CHANGED (VDEC_MSG_BASE + 13) -#define VDEC_MSG_EVT_HW_ERROR (VDEC_MSG_BASE + 14) -#define VDEC_MSG_EVT_INFO_CONFIG_CHANGED (VDEC_MSG_BASE + 15) -#define VDEC_MSG_EVT_INFO_FIELD_DROPPED (VDEC_MSG_BASE + 16) -#define VDEC_MSG_EVT_HW_OVERLOAD (VDEC_MSG_BASE + 17) -#define VDEC_MSG_EVT_MAX_CLIENTS (VDEC_MSG_BASE + 18) -#define VDEC_MSG_EVT_HW_UNSUPPORTED (VDEC_MSG_BASE + 19) - -/*Buffer flags bits masks.*/ -#define VDEC_BUFFERFLAG_EOS 0x00000001 -#define VDEC_BUFFERFLAG_DECODEONLY 0x00000004 -#define VDEC_BUFFERFLAG_DATACORRUPT 0x00000008 -#define VDEC_BUFFERFLAG_ENDOFFRAME 0x00000010 -#define VDEC_BUFFERFLAG_SYNCFRAME 0x00000020 -#define VDEC_BUFFERFLAG_EXTRADATA 0x00000040 -#define VDEC_BUFFERFLAG_CODECCONFIG 0x00000080 - -/*Post processing flags bit masks*/ -#define VDEC_EXTRADATA_NONE 0x001 -#define VDEC_EXTRADATA_QP 0x004 -#define VDEC_EXTRADATA_MB_ERROR_MAP 0x008 -#define VDEC_EXTRADATA_SEI 0x010 -#define VDEC_EXTRADATA_VUI 0x020 -#define VDEC_EXTRADATA_VC1 0x040 - -#define VDEC_EXTRADATA_EXT_DATA 0x0800 -#define VDEC_EXTRADATA_USER_DATA 0x1000 -#define VDEC_EXTRADATA_EXT_BUFFER 0x2000 - -#define VDEC_CMDBASE 0x800 -#define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE) - -#define VDEC_IOCTL_MAGIC 'v' - -struct vdec_ioctl_msg { - void *in; - void *out; -}; - -/* - * CMD params: InputParam:enum vdec_codec - * OutputParam: struct vdec_profile_level - */ -#define VDEC_IOCTL_GET_PROFILE_LEVEL_SUPPORTED \ - _IOWR(VDEC_IOCTL_MAGIC, 0, struct vdec_ioctl_msg) - -/* - * CMD params:InputParam: NULL - * OutputParam: uint32_t(bitmask) - */ -#define VDEC_IOCTL_GET_INTERLACE_FORMAT \ - _IOR(VDEC_IOCTL_MAGIC, 1, struct vdec_ioctl_msg) - -/* - * CMD params: InputParam: enum vdec_codec - * OutputParam: struct vdec_profile_level - */ -#define VDEC_IOCTL_GET_CURRENT_PROFILE_LEVEL \ - _IOWR(VDEC_IOCTL_MAGIC, 2, struct vdec_ioctl_msg) - -/* - * CMD params: SET: InputParam: enum vdec_output_fromat OutputParam: NULL - * GET: InputParam: NULL OutputParam: enum vdec_output_fromat - */ -#define VDEC_IOCTL_SET_OUTPUT_FORMAT \ - _IOWR(VDEC_IOCTL_MAGIC, 3, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_OUTPUT_FORMAT \ - _IOWR(VDEC_IOCTL_MAGIC, 4, struct vdec_ioctl_msg) - -/* - * CMD params: SET: InputParam: enum vdec_codec OutputParam: NULL - * GET: InputParam: NULL OutputParam: enum vdec_codec - */ -#define VDEC_IOCTL_SET_CODEC \ - _IOW(VDEC_IOCTL_MAGIC, 5, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_CODEC \ - _IOR(VDEC_IOCTL_MAGIC, 6, struct vdec_ioctl_msg) - -/* - * CMD params: SET: InputParam: struct vdec_picsize outputparam: NULL - * GET: InputParam: NULL outputparam: struct vdec_picsize - */ -#define VDEC_IOCTL_SET_PICRES \ - _IOW(VDEC_IOCTL_MAGIC, 7, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_PICRES \ - _IOR(VDEC_IOCTL_MAGIC, 8, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_SET_EXTRADATA \ - _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_EXTRADATA \ - _IOR(VDEC_IOCTL_MAGIC, 10, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_SET_SEQUENCE_HEADER \ - _IOW(VDEC_IOCTL_MAGIC, 11, struct vdec_ioctl_msg) - -/* - * CMD params: SET: InputParam - vdec_allocatorproperty, OutputParam - NULL - * GET: InputParam - NULL, OutputParam - vdec_allocatorproperty - */ -#define VDEC_IOCTL_SET_BUFFER_REQ \ - _IOW(VDEC_IOCTL_MAGIC, 12, struct vdec_ioctl_msg) -#define VDEC_IOCTL_GET_BUFFER_REQ \ - _IOR(VDEC_IOCTL_MAGIC, 13, struct vdec_ioctl_msg) -/* CMD params: InputParam - vdec_buffer, OutputParam - uint8_t** */ -#define VDEC_IOCTL_ALLOCATE_BUFFER \ - _IOWR(VDEC_IOCTL_MAGIC, 14, struct vdec_ioctl_msg) -/* CMD params: InputParam - uint8_t *, OutputParam - NULL.*/ -#define VDEC_IOCTL_FREE_BUFFER \ - _IOW(VDEC_IOCTL_MAGIC, 15, struct vdec_ioctl_msg) - -/*CMD params: CMD: InputParam - struct vdec_setbuffer_cmd, OutputParam - NULL*/ -#define VDEC_IOCTL_SET_BUFFER \ - _IOW(VDEC_IOCTL_MAGIC, 16, struct vdec_ioctl_msg) - -/* CMD params: InputParam - struct vdec_fillbuffer_cmd, OutputParam - NULL*/ -#define VDEC_IOCTL_FILL_OUTPUT_BUFFER \ - _IOW(VDEC_IOCTL_MAGIC, 17, struct vdec_ioctl_msg) - -/*CMD params: InputParam - struct vdec_frameinfo , OutputParam - NULL*/ -#define VDEC_IOCTL_DECODE_FRAME \ - _IOW(VDEC_IOCTL_MAGIC, 18, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_LOAD_RESOURCES _IO(VDEC_IOCTL_MAGIC, 19) -#define VDEC_IOCTL_CMD_START _IO(VDEC_IOCTL_MAGIC, 20) -#define VDEC_IOCTL_CMD_STOP _IO(VDEC_IOCTL_MAGIC, 21) -#define VDEC_IOCTL_CMD_PAUSE _IO(VDEC_IOCTL_MAGIC, 22) -#define VDEC_IOCTL_CMD_RESUME _IO(VDEC_IOCTL_MAGIC, 23) - -/*CMD params: InputParam - enum vdec_bufferflush , OutputParam - NULL */ -#define VDEC_IOCTL_CMD_FLUSH _IOW(VDEC_IOCTL_MAGIC, 24, struct vdec_ioctl_msg) - -/* ======================================================== - * IOCTL for getting asynchronous notification from driver - * ======================================================== - */ - -/*IOCTL params: InputParam - NULL, OutputParam - struct vdec_msginfo*/ -#define VDEC_IOCTL_GET_NEXT_MSG \ - _IOR(VDEC_IOCTL_MAGIC, 25, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_STOP_NEXT_MSG _IO(VDEC_IOCTL_MAGIC, 26) - -#define VDEC_IOCTL_GET_NUMBER_INSTANCES \ - _IOR(VDEC_IOCTL_MAGIC, 27, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_SET_PICTURE_ORDER \ - _IOW(VDEC_IOCTL_MAGIC, 28, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_SET_FRAME_RATE \ - _IOW(VDEC_IOCTL_MAGIC, 29, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_SET_H264_MV_BUFFER \ - _IOW(VDEC_IOCTL_MAGIC, 30, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_FREE_H264_MV_BUFFER \ - _IOW(VDEC_IOCTL_MAGIC, 31, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_GET_MV_BUFFER_SIZE \ - _IOR(VDEC_IOCTL_MAGIC, 32, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_SET_IDR_ONLY_DECODING \ - _IO(VDEC_IOCTL_MAGIC, 33) - -#define VDEC_IOCTL_SET_CONT_ON_RECONFIG \ - _IO(VDEC_IOCTL_MAGIC, 34) - -#define VDEC_IOCTL_SET_DISABLE_DMX \ - _IOW(VDEC_IOCTL_MAGIC, 35, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_GET_DISABLE_DMX \ - _IOR(VDEC_IOCTL_MAGIC, 36, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_GET_DISABLE_DMX_SUPPORT \ - _IOR(VDEC_IOCTL_MAGIC, 37, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_SET_PERF_CLK \ - _IOR(VDEC_IOCTL_MAGIC, 38, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_SET_META_BUFFERS \ - _IOW(VDEC_IOCTL_MAGIC, 39, struct vdec_ioctl_msg) - -#define VDEC_IOCTL_FREE_META_BUFFERS \ - _IO(VDEC_IOCTL_MAGIC, 40) - -enum vdec_picture { - PICTURE_TYPE_I, - PICTURE_TYPE_P, - PICTURE_TYPE_B, - PICTURE_TYPE_BI, - PICTURE_TYPE_SKIP, - PICTURE_TYPE_IDR, - PICTURE_TYPE_UNKNOWN -}; - -enum vdec_buffer { - VDEC_BUFFER_TYPE_INPUT, - VDEC_BUFFER_TYPE_OUTPUT -}; - -struct vdec_allocatorproperty { - enum vdec_buffer buffer_type; - uint32_t mincount; - uint32_t maxcount; - uint32_t actualcount; - size_t buffer_size; - uint32_t alignment; - uint32_t buf_poolid; - size_t meta_buffer_size; -}; - -struct vdec_bufferpayload { - void *bufferaddr; - size_t buffer_len; - int pmem_fd; - size_t offset; - size_t mmaped_size; -}; - -struct vdec_setbuffer_cmd { - enum vdec_buffer buffer_type; - struct vdec_bufferpayload buffer; -}; - -struct vdec_fillbuffer_cmd { - struct vdec_bufferpayload buffer; - void *client_data; -}; - -enum vdec_bufferflush { - VDEC_FLUSH_TYPE_INPUT, - VDEC_FLUSH_TYPE_OUTPUT, - VDEC_FLUSH_TYPE_ALL -}; - -enum vdec_codec { - VDEC_CODECTYPE_H264 = 0x1, - VDEC_CODECTYPE_H263 = 0x2, - VDEC_CODECTYPE_MPEG4 = 0x3, - VDEC_CODECTYPE_DIVX_3 = 0x4, - VDEC_CODECTYPE_DIVX_4 = 0x5, - VDEC_CODECTYPE_DIVX_5 = 0x6, - VDEC_CODECTYPE_DIVX_6 = 0x7, - VDEC_CODECTYPE_XVID = 0x8, - VDEC_CODECTYPE_MPEG1 = 0x9, - VDEC_CODECTYPE_MPEG2 = 0xa, - VDEC_CODECTYPE_VC1 = 0xb, - VDEC_CODECTYPE_VC1_RCV = 0xc, - VDEC_CODECTYPE_HEVC = 0xd, - VDEC_CODECTYPE_MVC = 0xe, - VDEC_CODECTYPE_VP8 = 0xf, - VDEC_CODECTYPE_VP9 = 0x10, -}; - -enum vdec_mpeg2_profile { - VDEC_MPEG2ProfileSimple = 0x1, - VDEC_MPEG2ProfileMain = 0x2, - VDEC_MPEG2Profile422 = 0x4, - VDEC_MPEG2ProfileSNR = 0x8, - VDEC_MPEG2ProfileSpatial = 0x10, - VDEC_MPEG2ProfileHigh = 0x20, - VDEC_MPEG2ProfileKhronosExtensions = 0x6F000000, - VDEC_MPEG2ProfileVendorStartUnused = 0x7F000000, - VDEC_MPEG2ProfileMax = 0x7FFFFFFF -}; - -enum vdec_mpeg2_level { - - VDEC_MPEG2LevelLL = 0x1, - VDEC_MPEG2LevelML = 0x2, - VDEC_MPEG2LevelH14 = 0x4, - VDEC_MPEG2LevelHL = 0x8, - VDEC_MPEG2LevelKhronosExtensions = 0x6F000000, - VDEC_MPEG2LevelVendorStartUnused = 0x7F000000, - VDEC_MPEG2LevelMax = 0x7FFFFFFF -}; - -enum vdec_mpeg4_profile { - VDEC_MPEG4ProfileSimple = 0x01, - VDEC_MPEG4ProfileSimpleScalable = 0x02, - VDEC_MPEG4ProfileCore = 0x04, - VDEC_MPEG4ProfileMain = 0x08, - VDEC_MPEG4ProfileNbit = 0x10, - VDEC_MPEG4ProfileScalableTexture = 0x20, - VDEC_MPEG4ProfileSimpleFace = 0x40, - VDEC_MPEG4ProfileSimpleFBA = 0x80, - VDEC_MPEG4ProfileBasicAnimated = 0x100, - VDEC_MPEG4ProfileHybrid = 0x200, - VDEC_MPEG4ProfileAdvancedRealTime = 0x400, - VDEC_MPEG4ProfileCoreScalable = 0x800, - VDEC_MPEG4ProfileAdvancedCoding = 0x1000, - VDEC_MPEG4ProfileAdvancedCore = 0x2000, - VDEC_MPEG4ProfileAdvancedScalable = 0x4000, - VDEC_MPEG4ProfileAdvancedSimple = 0x8000, - VDEC_MPEG4ProfileKhronosExtensions = 0x6F000000, - VDEC_MPEG4ProfileVendorStartUnused = 0x7F000000, - VDEC_MPEG4ProfileMax = 0x7FFFFFFF -}; - -enum vdec_mpeg4_level { - VDEC_MPEG4Level0 = 0x01, - VDEC_MPEG4Level0b = 0x02, - VDEC_MPEG4Level1 = 0x04, - VDEC_MPEG4Level2 = 0x08, - VDEC_MPEG4Level3 = 0x10, - VDEC_MPEG4Level4 = 0x20, - VDEC_MPEG4Level4a = 0x40, - VDEC_MPEG4Level5 = 0x80, - VDEC_MPEG4LevelKhronosExtensions = 0x6F000000, - VDEC_MPEG4LevelVendorStartUnused = 0x7F000000, - VDEC_MPEG4LevelMax = 0x7FFFFFFF -}; - -enum vdec_avc_profile { - VDEC_AVCProfileBaseline = 0x01, - VDEC_AVCProfileMain = 0x02, - VDEC_AVCProfileExtended = 0x04, - VDEC_AVCProfileHigh = 0x08, - VDEC_AVCProfileHigh10 = 0x10, - VDEC_AVCProfileHigh422 = 0x20, - VDEC_AVCProfileHigh444 = 0x40, - VDEC_AVCProfileKhronosExtensions = 0x6F000000, - VDEC_AVCProfileVendorStartUnused = 0x7F000000, - VDEC_AVCProfileMax = 0x7FFFFFFF -}; - -enum vdec_avc_level { - VDEC_AVCLevel1 = 0x01, - VDEC_AVCLevel1b = 0x02, - VDEC_AVCLevel11 = 0x04, - VDEC_AVCLevel12 = 0x08, - VDEC_AVCLevel13 = 0x10, - VDEC_AVCLevel2 = 0x20, - VDEC_AVCLevel21 = 0x40, - VDEC_AVCLevel22 = 0x80, - VDEC_AVCLevel3 = 0x100, - VDEC_AVCLevel31 = 0x200, - VDEC_AVCLevel32 = 0x400, - VDEC_AVCLevel4 = 0x800, - VDEC_AVCLevel41 = 0x1000, - VDEC_AVCLevel42 = 0x2000, - VDEC_AVCLevel5 = 0x4000, - VDEC_AVCLevel51 = 0x8000, - VDEC_AVCLevelKhronosExtensions = 0x6F000000, - VDEC_AVCLevelVendorStartUnused = 0x7F000000, - VDEC_AVCLevelMax = 0x7FFFFFFF -}; - -enum vdec_divx_profile { - VDEC_DIVXProfile_qMobile = 0x01, - VDEC_DIVXProfile_Mobile = 0x02, - VDEC_DIVXProfile_HD = 0x04, - VDEC_DIVXProfile_Handheld = 0x08, - VDEC_DIVXProfile_Portable = 0x10, - VDEC_DIVXProfile_HomeTheater = 0x20 -}; - -enum vdec_xvid_profile { - VDEC_XVIDProfile_Simple = 0x1, - VDEC_XVIDProfile_Advanced_Realtime_Simple = 0x2, - VDEC_XVIDProfile_Advanced_Simple = 0x4 -}; - -enum vdec_xvid_level { - VDEC_XVID_LEVEL_S_L0 = 0x1, - VDEC_XVID_LEVEL_S_L1 = 0x2, - VDEC_XVID_LEVEL_S_L2 = 0x4, - VDEC_XVID_LEVEL_S_L3 = 0x8, - VDEC_XVID_LEVEL_ARTS_L1 = 0x10, - VDEC_XVID_LEVEL_ARTS_L2 = 0x20, - VDEC_XVID_LEVEL_ARTS_L3 = 0x40, - VDEC_XVID_LEVEL_ARTS_L4 = 0x80, - VDEC_XVID_LEVEL_AS_L0 = 0x100, - VDEC_XVID_LEVEL_AS_L1 = 0x200, - VDEC_XVID_LEVEL_AS_L2 = 0x400, - VDEC_XVID_LEVEL_AS_L3 = 0x800, - VDEC_XVID_LEVEL_AS_L4 = 0x1000 -}; - -enum vdec_h263profile { - VDEC_H263ProfileBaseline = 0x01, - VDEC_H263ProfileH320Coding = 0x02, - VDEC_H263ProfileBackwardCompatible = 0x04, - VDEC_H263ProfileISWV2 = 0x08, - VDEC_H263ProfileISWV3 = 0x10, - VDEC_H263ProfileHighCompression = 0x20, - VDEC_H263ProfileInternet = 0x40, - VDEC_H263ProfileInterlace = 0x80, - VDEC_H263ProfileHighLatency = 0x100, - VDEC_H263ProfileKhronosExtensions = 0x6F000000, - VDEC_H263ProfileVendorStartUnused = 0x7F000000, - VDEC_H263ProfileMax = 0x7FFFFFFF -}; - -enum vdec_h263level { - VDEC_H263Level10 = 0x01, - VDEC_H263Level20 = 0x02, - VDEC_H263Level30 = 0x04, - VDEC_H263Level40 = 0x08, - VDEC_H263Level45 = 0x10, - VDEC_H263Level50 = 0x20, - VDEC_H263Level60 = 0x40, - VDEC_H263Level70 = 0x80, - VDEC_H263LevelKhronosExtensions = 0x6F000000, - VDEC_H263LevelVendorStartUnused = 0x7F000000, - VDEC_H263LevelMax = 0x7FFFFFFF -}; - -enum vdec_wmv_format { - VDEC_WMVFormatUnused = 0x01, - VDEC_WMVFormat7 = 0x02, - VDEC_WMVFormat8 = 0x04, - VDEC_WMVFormat9 = 0x08, - VDEC_WMFFormatKhronosExtensions = 0x6F000000, - VDEC_WMFFormatVendorStartUnused = 0x7F000000, - VDEC_WMVFormatMax = 0x7FFFFFFF -}; - -enum vdec_vc1_profile { - VDEC_VC1ProfileSimple = 0x1, - VDEC_VC1ProfileMain = 0x2, - VDEC_VC1ProfileAdvanced = 0x4 -}; - -enum vdec_vc1_level { - VDEC_VC1_LEVEL_S_Low = 0x1, - VDEC_VC1_LEVEL_S_Medium = 0x2, - VDEC_VC1_LEVEL_M_Low = 0x4, - VDEC_VC1_LEVEL_M_Medium = 0x8, - VDEC_VC1_LEVEL_M_High = 0x10, - VDEC_VC1_LEVEL_A_L0 = 0x20, - VDEC_VC1_LEVEL_A_L1 = 0x40, - VDEC_VC1_LEVEL_A_L2 = 0x80, - VDEC_VC1_LEVEL_A_L3 = 0x100, - VDEC_VC1_LEVEL_A_L4 = 0x200 -}; - -struct vdec_profile_level { - uint32_t profiles; - uint32_t levels; -}; - -enum vdec_interlaced_format { - VDEC_InterlaceFrameProgressive = 0x1, - VDEC_InterlaceInterleaveFrameTopFieldFirst = 0x2, - VDEC_InterlaceInterleaveFrameBottomFieldFirst = 0x4 -}; - -#define VDEC_YUV_FORMAT_NV12_TP10_UBWC \ - VDEC_YUV_FORMAT_NV12_TP10_UBWC - -enum vdec_output_fromat { - VDEC_YUV_FORMAT_NV12 = 0x1, - VDEC_YUV_FORMAT_TILE_4x2 = 0x2, - VDEC_YUV_FORMAT_NV12_UBWC = 0x3, - VDEC_YUV_FORMAT_NV12_TP10_UBWC = 0x4 -}; - -enum vdec_output_order { - VDEC_ORDER_DISPLAY = 0x1, - VDEC_ORDER_DECODE = 0x2 -}; - -struct vdec_picsize { - uint32_t frame_width; - uint32_t frame_height; - uint32_t stride; - uint32_t scan_lines; -}; - -struct vdec_seqheader { - void *ptr_seqheader; - size_t seq_header_len; - int pmem_fd; - size_t pmem_offset; -}; - -struct vdec_mberror { - void *ptr_errormap; - size_t err_mapsize; -}; - -struct vdec_input_frameinfo { - void *bufferaddr; - size_t offset; - size_t datalen; - uint32_t flags; - int64_t timestamp; - void *client_data; - int pmem_fd; - size_t pmem_offset; - void *desc_addr; - uint32_t desc_size; -}; - -struct vdec_framesize { - uint32_t left; - uint32_t top; - uint32_t right; - uint32_t bottom; -}; - -struct vdec_aspectratioinfo { - uint32_t aspect_ratio; - uint32_t par_width; - uint32_t par_height; -}; - -struct vdec_sep_metadatainfo { - void *metabufaddr; - uint32_t size; - int fd; - int offset; - uint32_t buffer_size; -}; - -struct vdec_output_frameinfo { - void *bufferaddr; - size_t offset; - size_t len; - uint32_t flags; - int64_t time_stamp; - enum vdec_picture pic_type; - void *client_data; - void *input_frame_clientdata; - struct vdec_picsize picsize; - struct vdec_framesize framesize; - enum vdec_interlaced_format interlaced_format; - struct vdec_aspectratioinfo aspect_ratio_info; - struct vdec_sep_metadatainfo metadata_info; -}; - -union vdec_msgdata { - struct vdec_output_frameinfo output_frame; - void *input_frame_clientdata; -}; - -struct vdec_msginfo { - uint32_t status_code; - uint32_t msgcode; - union vdec_msgdata msgdata; - size_t msgdatasize; -}; - -struct vdec_framerate { - unsigned long fps_denominator; - unsigned long fps_numerator; -}; - -struct vdec_h264_mv { - size_t size; - int count; - int pmem_fd; - int offset; -}; - -struct vdec_mv_buff_size { - int width; - int height; - int size; - int alignment; -}; - -struct vdec_meta_buffers { - size_t size; - int count; - int pmem_fd; - int pmem_fd_iommu; - int offset; -}; - -#endif /* end of macro _VDECDECODER_H_ */ diff --git a/sdm710/original-kernel-headers/linux/msm_vidc_enc.h b/sdm710/original-kernel-headers/linux/msm_vidc_enc.h deleted file mode 100644 index 86d7fab4..00000000 --- a/sdm710/original-kernel-headers/linux/msm_vidc_enc.h +++ /dev/null @@ -1,752 +0,0 @@ -#ifndef _MSM_VIDC_ENC_H_ -#define _MSM_VIDC_ENC_H_ - -#include <linux/types.h> -#include <linux/ioctl.h> - -/** STATUS CODES*/ -/* Base value for status codes */ -#define VEN_S_BASE 0x00000000 -#define VEN_S_SUCCESS (VEN_S_BASE)/* Success */ -#define VEN_S_EFAIL (VEN_S_BASE+1)/* General failure */ -#define VEN_S_EFATAL (VEN_S_BASE+2)/* Fatal irrecoverable failure*/ -#define VEN_S_EBADPARAM (VEN_S_BASE+3)/* Error passed parameters*/ -/*Command called in invalid state*/ -#define VEN_S_EINVALSTATE (VEN_S_BASE+4) -#define VEN_S_ENOSWRES (VEN_S_BASE+5)/* Insufficient OS resources*/ -#define VEN_S_ENOHWRES (VEN_S_BASE+6)/*Insufficient HW resources */ -#define VEN_S_EBUFFREQ (VEN_S_BASE+7)/* Buffer requirements were not met*/ -#define VEN_S_EINVALCMD (VEN_S_BASE+8)/* Invalid command called */ -#define VEN_S_ETIMEOUT (VEN_S_BASE+9)/* Command timeout. */ -/*Re-attempt was made when multiple invocation not supported for API.*/ -#define VEN_S_ENOREATMPT (VEN_S_BASE+10) -#define VEN_S_ENOPREREQ (VEN_S_BASE+11)/*Pre-requirement is not met for API*/ -#define VEN_S_ECMDQFULL (VEN_S_BASE+12)/*Command queue is full*/ -#define VEN_S_ENOTSUPP (VEN_S_BASE+13)/*Command not supported*/ -#define VEN_S_ENOTIMPL (VEN_S_BASE+14)/*Command not implemented.*/ -#define VEN_S_ENOTPMEM (VEN_S_BASE+15)/*Buffer is not from PMEM*/ -#define VEN_S_EFLUSHED (VEN_S_BASE+16)/*returned buffer was flushed*/ -#define VEN_S_EINSUFBUF (VEN_S_BASE+17)/*provided buffer size insufficient*/ -#define VEN_S_ESAMESTATE (VEN_S_BASE+18) -#define VEN_S_EINVALTRANS (VEN_S_BASE+19) - -#define VEN_INTF_VER 1 - -/*Asynchronous messages from driver*/ -#define VEN_MSG_INDICATION 0 -#define VEN_MSG_INPUT_BUFFER_DONE 1 -#define VEN_MSG_OUTPUT_BUFFER_DONE 2 -#define VEN_MSG_NEED_OUTPUT_BUFFER 3 -#define VEN_MSG_FLUSH_INPUT_DONE 4 -#define VEN_MSG_FLUSH_OUTPUT_DONE 5 -#define VEN_MSG_START 6 -#define VEN_MSG_STOP 7 -#define VEN_MSG_PAUSE 8 -#define VEN_MSG_RESUME 9 -#define VEN_MSG_STOP_READING_MSG 10 -#define VEN_MSG_LTRUSE_FAILED 11 -#define VEN_MSG_HW_OVERLOAD 12 -#define VEN_MSG_MAX_CLIENTS 13 - - -/*Buffer flags bits masks*/ -#define VEN_BUFFLAG_EOS 0x00000001 -#define VEN_BUFFLAG_ENDOFFRAME 0x00000010 -#define VEN_BUFFLAG_SYNCFRAME 0x00000020 -#define VEN_BUFFLAG_EXTRADATA 0x00000040 -#define VEN_BUFFLAG_CODECCONFIG 0x00000080 - -/*Post processing flags bit masks*/ -#define VEN_EXTRADATA_NONE 0x001 -#define VEN_EXTRADATA_QCOMFILLER 0x002 -#define VEN_EXTRADATA_SLICEINFO 0x100 -#define VEN_EXTRADATA_LTRINFO 0x200 -#define VEN_EXTRADATA_MBINFO 0x400 - -/*ENCODER CONFIGURATION CONSTANTS*/ - -/*Encoded video frame types*/ -#define VEN_FRAME_TYPE_I 1/* I frame type */ -#define VEN_FRAME_TYPE_P 2/* P frame type */ -#define VEN_FRAME_TYPE_B 3/* B frame type */ - -/*Video codec types*/ -#define VEN_CODEC_MPEG4 1/* MPEG4 Codec */ -#define VEN_CODEC_H264 2/* H.264 Codec */ -#define VEN_CODEC_H263 3/* H.263 Codec */ - -/*Video codec profile types.*/ -#define VEN_PROFILE_MPEG4_SP 1/* 1 - MPEG4 SP profile */ -#define VEN_PROFILE_MPEG4_ASP 2/* 2 - MPEG4 ASP profile */ -#define VEN_PROFILE_H264_BASELINE 3/* 3 - H264 Baseline profile */ -#define VEN_PROFILE_H264_MAIN 4/* 4 - H264 Main profile */ -#define VEN_PROFILE_H264_HIGH 5/* 5 - H264 High profile */ -#define VEN_PROFILE_H263_BASELINE 6/* 6 - H263 Baseline profile */ - -/*Video codec profile level types.*/ -#define VEN_LEVEL_MPEG4_0 0x1/* MPEG4 Level 0 */ -#define VEN_LEVEL_MPEG4_1 0x2/* MPEG4 Level 1 */ -#define VEN_LEVEL_MPEG4_2 0x3/* MPEG4 Level 2 */ -#define VEN_LEVEL_MPEG4_3 0x4/* MPEG4 Level 3 */ -#define VEN_LEVEL_MPEG4_4 0x5/* MPEG4 Level 4 */ -#define VEN_LEVEL_MPEG4_5 0x6/* MPEG4 Level 5 */ -#define VEN_LEVEL_MPEG4_3b 0x7/* MPEG4 Level 3b */ -#define VEN_LEVEL_MPEG4_6 0x8/* MPEG4 Level 6 */ - -#define VEN_LEVEL_H264_1 0x9/* H.264 Level 1 */ -#define VEN_LEVEL_H264_1b 0xA/* H.264 Level 1b */ -#define VEN_LEVEL_H264_1p1 0xB/* H.264 Level 1.1 */ -#define VEN_LEVEL_H264_1p2 0xC/* H.264 Level 1.2 */ -#define VEN_LEVEL_H264_1p3 0xD/* H.264 Level 1.3 */ -#define VEN_LEVEL_H264_2 0xE/* H.264 Level 2 */ -#define VEN_LEVEL_H264_2p1 0xF/* H.264 Level 2.1 */ -#define VEN_LEVEL_H264_2p2 0x10/* H.264 Level 2.2 */ -#define VEN_LEVEL_H264_3 0x11/* H.264 Level 3 */ -#define VEN_LEVEL_H264_3p1 0x12/* H.264 Level 3.1 */ -#define VEN_LEVEL_H264_3p2 0x13/* H.264 Level 3.2 */ -#define VEN_LEVEL_H264_4 0x14/* H.264 Level 4 */ - -#define VEN_LEVEL_H263_10 0x15/* H.263 Level 10 */ -#define VEN_LEVEL_H263_20 0x16/* H.263 Level 20 */ -#define VEN_LEVEL_H263_30 0x17/* H.263 Level 30 */ -#define VEN_LEVEL_H263_40 0x18/* H.263 Level 40 */ -#define VEN_LEVEL_H263_45 0x19/* H.263 Level 45 */ -#define VEN_LEVEL_H263_50 0x1A/* H.263 Level 50 */ -#define VEN_LEVEL_H263_60 0x1B/* H.263 Level 60 */ -#define VEN_LEVEL_H263_70 0x1C/* H.263 Level 70 */ - -/*Entropy coding model selection for H.264 encoder.*/ -#define VEN_ENTROPY_MODEL_CAVLC 1 -#define VEN_ENTROPY_MODEL_CABAC 2 -/*Cabac model number (0,1,2) for encoder.*/ -#define VEN_CABAC_MODEL_0 1/* CABAC Model 0. */ -#define VEN_CABAC_MODEL_1 2/* CABAC Model 1. */ -#define VEN_CABAC_MODEL_2 3/* CABAC Model 2. */ - -/*Deblocking filter control type for encoder.*/ -#define VEN_DB_DISABLE 1/* 1 - Disable deblocking filter*/ -#define VEN_DB_ALL_BLKG_BNDRY 2/* 2 - All blocking boundary filtering*/ -#define VEN_DB_SKIP_SLICE_BNDRY 3/* 3 - Filtering except sliceboundary*/ - -/*Different methods of Multi slice selection.*/ -#define VEN_MSLICE_OFF 1 -#define VEN_MSLICE_CNT_MB 2 /*number of MBscount per slice*/ -#define VEN_MSLICE_CNT_BYTE 3 /*number of bytes count per slice.*/ -#define VEN_MSLICE_GOB 4 /*Multi slice by GOB for H.263 only.*/ - -/*Different modes for Rate Control.*/ -#define VEN_RC_OFF 1 -#define VEN_RC_VBR_VFR 2 -#define VEN_RC_VBR_CFR 3 -#define VEN_RC_CBR_VFR 4 -#define VEN_RC_CBR_CFR 5 - -/*Different modes for flushing buffers*/ -#define VEN_FLUSH_INPUT 1 -#define VEN_FLUSH_OUTPUT 2 -#define VEN_FLUSH_ALL 3 - -/*Different input formats for YUV data.*/ -#define VEN_INPUTFMT_NV12 1/* NV12 Linear */ -#define VEN_INPUTFMT_NV21 2/* NV21 Linear */ -#define VEN_INPUTFMT_NV12_16M2KA 3/* NV12 Linear */ - -/*Different allowed rotation modes.*/ -#define VEN_ROTATION_0 1/* 0 degrees */ -#define VEN_ROTATION_90 2/* 90 degrees */ -#define VEN_ROTATION_180 3/* 180 degrees */ -#define VEN_ROTATION_270 4/* 270 degrees */ - -/*IOCTL timeout values*/ -#define VEN_TIMEOUT_INFINITE 0xffffffff - -/*Different allowed intra refresh modes.*/ -#define VEN_IR_OFF 1 -#define VEN_IR_CYCLIC 2 -#define VEN_IR_RANDOM 3 - -/*IOCTL BASE CODES Not to be used directly by the client.*/ -/* Base value for ioctls that are not related to encoder configuration.*/ -#define VEN_IOCTLBASE_NENC 0x800 -/* Base value for encoder configuration ioctls*/ -#define VEN_IOCTLBASE_ENC 0x850 - -struct venc_ioctl_msg { - void *in; - void *out; -}; - -/*NON ENCODER CONFIGURATION IOCTLs*/ - -/*IOCTL params:SET: InputData - unsigned long, OutputData - NULL*/ -#define VEN_IOCTL_SET_INTF_VERSION \ - _IOW(VEN_IOCTLBASE_NENC, 0, struct venc_ioctl_msg) - -/*IOCTL params:CMD: InputData - venc_timeout, OutputData - venc_msg*/ -#define VEN_IOCTL_CMD_READ_NEXT_MSG \ - _IOWR(VEN_IOCTLBASE_NENC, 1, struct venc_ioctl_msg) - -/*IOCTL params:CMD: InputData - NULL, OutputData - NULL*/ -#define VEN_IOCTL_CMD_STOP_READ_MSG _IO(VEN_IOCTLBASE_NENC, 2) - -/* - * IOCTL params:SET: InputData - venc_allocatorproperty, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_allocatorproperty - */ -#define VEN_IOCTL_SET_INPUT_BUFFER_REQ \ - _IOW(VEN_IOCTLBASE_NENC, 3, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_INPUT_BUFFER_REQ \ - _IOR(VEN_IOCTLBASE_NENC, 4, struct venc_ioctl_msg) - -/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL*/ -#define VEN_IOCTL_CMD_ALLOC_INPUT_BUFFER \ - _IOW(VEN_IOCTLBASE_NENC, 5, struct venc_ioctl_msg) - -/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL*/ -#define VEN_IOCTL_SET_INPUT_BUFFER \ - _IOW(VEN_IOCTLBASE_NENC, 6, struct venc_ioctl_msg) - -/*IOCTL params: CMD: InputData - venc_bufferpayload, OutputData - NULL*/ -#define VEN_IOCTL_CMD_FREE_INPUT_BUFFER \ - _IOW(VEN_IOCTLBASE_NENC, 7, struct venc_ioctl_msg) - -/* - * IOCTL params:SET: InputData - venc_allocatorproperty, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_allocatorproperty - */ -#define VEN_IOCTL_SET_OUTPUT_BUFFER_REQ \ - _IOW(VEN_IOCTLBASE_NENC, 8, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_OUTPUT_BUFFER_REQ \ - _IOR(VEN_IOCTLBASE_NENC, 9, struct venc_ioctl_msg) - -/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL*/ -#define VEN_IOCTL_CMD_ALLOC_OUTPUT_BUFFER \ - _IOW(VEN_IOCTLBASE_NENC, 10, struct venc_ioctl_msg) - - -/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL*/ -#define VEN_IOCTL_SET_OUTPUT_BUFFER \ - _IOW(VEN_IOCTLBASE_NENC, 11, struct venc_ioctl_msg) - -/*IOCTL params:CMD: InputData - venc_bufferpayload, OutputData - NULL.*/ -#define VEN_IOCTL_CMD_FREE_OUTPUT_BUFFER \ - _IOW(VEN_IOCTLBASE_NENC, 12, struct venc_ioctl_msg) - - -/* Asynchronous respone message code:* VEN_MSG_START*/ -#define VEN_IOCTL_CMD_START _IO(VEN_IOCTLBASE_NENC, 13) - - -/* - * IOCTL params:CMD: InputData - venc_buffer, OutputData - NULL - * Asynchronous respone message code:VEN_MSG_INPUT_BUFFER_DONE - */ -#define VEN_IOCTL_CMD_ENCODE_FRAME \ - _IOW(VEN_IOCTLBASE_NENC, 14, struct venc_ioctl_msg) - - -/* - *IOCTL params:CMD: InputData - venc_buffer, OutputData - NULL - *Asynchronous response message code:VEN_MSG_OUTPUT_BUFFER_DONE - */ -#define VEN_IOCTL_CMD_FILL_OUTPUT_BUFFER \ - _IOW(VEN_IOCTLBASE_NENC, 15, struct venc_ioctl_msg) - -/* - * IOCTL params:CMD: InputData - venc_bufferflush, OutputData - NULL - * Asynchronous response message code:VEN_MSG_INPUT_BUFFER_DONE - */ -#define VEN_IOCTL_CMD_FLUSH \ - _IOW(VEN_IOCTLBASE_NENC, 16, struct venc_ioctl_msg) - - -/*Asynchronous respone message code:VEN_MSG_PAUSE*/ -#define VEN_IOCTL_CMD_PAUSE _IO(VEN_IOCTLBASE_NENC, 17) - -/*Asynchronous respone message code:VEN_MSG_RESUME*/ -#define VEN_IOCTL_CMD_RESUME _IO(VEN_IOCTLBASE_NENC, 18) - -/* Asynchronous respone message code:VEN_MSG_STOP*/ -#define VEN_IOCTL_CMD_STOP _IO(VEN_IOCTLBASE_NENC, 19) - -#define VEN_IOCTL_SET_RECON_BUFFER \ - _IOW(VEN_IOCTLBASE_NENC, 20, struct venc_ioctl_msg) - -#define VEN_IOCTL_FREE_RECON_BUFFER \ - _IOW(VEN_IOCTLBASE_NENC, 21, struct venc_ioctl_msg) - -#define VEN_IOCTL_GET_RECON_BUFFER_SIZE \ - _IOW(VEN_IOCTLBASE_NENC, 22, struct venc_ioctl_msg) - - - -/*ENCODER PROPERTY CONFIGURATION & CAPABILITY IOCTLs*/ - -/* - * IOCTL params:SET: InputData - venc_basecfg, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_basecfg - */ -#define VEN_IOCTL_SET_BASE_CFG \ - _IOW(VEN_IOCTLBASE_ENC, 1, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_BASE_CFG \ - _IOR(VEN_IOCTLBASE_ENC, 2, struct venc_ioctl_msg) - -/* - * IOCTL params:SET: InputData - venc_switch, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_switch - */ -#define VEN_IOCTL_SET_LIVE_MODE \ - _IOW(VEN_IOCTLBASE_ENC, 3, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_LIVE_MODE \ - _IOR(VEN_IOCTLBASE_ENC, 4, struct venc_ioctl_msg) - - -/* - * IOCTL params:SET: InputData - venc_profile, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_profile - */ -#define VEN_IOCTL_SET_CODEC_PROFILE \ - _IOW(VEN_IOCTLBASE_ENC, 5, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_CODEC_PROFILE \ - _IOR(VEN_IOCTLBASE_ENC, 6, struct venc_ioctl_msg) - - -/* - * IOCTL params:SET: InputData - ven_profilelevel, OutputData - NULL - * GET: InputData - NULL, OutputData - ven_profilelevel - */ -#define VEN_IOCTL_SET_PROFILE_LEVEL \ - _IOW(VEN_IOCTLBASE_ENC, 7, struct venc_ioctl_msg) - -#define VEN_IOCTL_GET_PROFILE_LEVEL \ - _IOR(VEN_IOCTLBASE_ENC, 8, struct venc_ioctl_msg) - -/* - * IOCTL params:SET: InputData - venc_switch, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_switch - */ -#define VEN_IOCTL_SET_SHORT_HDR \ - _IOW(VEN_IOCTLBASE_ENC, 9, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_SHORT_HDR \ - _IOR(VEN_IOCTLBASE_ENC, 10, struct venc_ioctl_msg) - - -/* - * IOCTL params: SET: InputData - venc_sessionqp, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_sessionqp - */ -#define VEN_IOCTL_SET_SESSION_QP \ - _IOW(VEN_IOCTLBASE_ENC, 11, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_SESSION_QP \ - _IOR(VEN_IOCTLBASE_ENC, 12, struct venc_ioctl_msg) - - -/* - * IOCTL params:SET: InputData - venc_intraperiod, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_intraperiod - */ -#define VEN_IOCTL_SET_INTRA_PERIOD \ - _IOW(VEN_IOCTLBASE_ENC, 13, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_INTRA_PERIOD \ - _IOR(VEN_IOCTLBASE_ENC, 14, struct venc_ioctl_msg) - - -/* Request an Iframe*/ -#define VEN_IOCTL_CMD_REQUEST_IFRAME _IO(VEN_IOCTLBASE_ENC, 15) - -/*IOCTL params:GET: InputData - NULL, OutputData - venc_capability*/ -#define VEN_IOCTL_GET_CAPABILITY \ - _IOR(VEN_IOCTLBASE_ENC, 16, struct venc_ioctl_msg) - - -/*IOCTL params:GET: InputData - NULL, OutputData - venc_seqheader*/ -#define VEN_IOCTL_GET_SEQUENCE_HDR \ - _IOR(VEN_IOCTLBASE_ENC, 17, struct venc_ioctl_msg) - -/* - * IOCTL params:SET: InputData - venc_entropycfg, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_entropycfg - */ -#define VEN_IOCTL_SET_ENTROPY_CFG \ - _IOW(VEN_IOCTLBASE_ENC, 18, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_ENTROPY_CFG \ - _IOR(VEN_IOCTLBASE_ENC, 19, struct venc_ioctl_msg) - -/* - * IOCTL params:SET: InputData - venc_dbcfg, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_dbcfg - */ -#define VEN_IOCTL_SET_DEBLOCKING_CFG \ - _IOW(VEN_IOCTLBASE_ENC, 20, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_DEBLOCKING_CFG \ - _IOR(VEN_IOCTLBASE_ENC, 21, struct venc_ioctl_msg) - - -/* - * IOCTL params:SET: InputData - venc_intrarefresh, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_intrarefresh - */ -#define VEN_IOCTL_SET_INTRA_REFRESH \ - _IOW(VEN_IOCTLBASE_ENC, 22, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_INTRA_REFRESH \ - _IOR(VEN_IOCTLBASE_ENC, 23, struct venc_ioctl_msg) - - -/* - * IOCTL params:SET: InputData - venc_multiclicecfg, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_multiclicecfg - */ -#define VEN_IOCTL_SET_MULTI_SLICE_CFG \ - _IOW(VEN_IOCTLBASE_ENC, 24, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_MULTI_SLICE_CFG \ - _IOR(VEN_IOCTLBASE_ENC, 25, struct venc_ioctl_msg) - -/* - * IOCTL params:SET: InputData - venc_ratectrlcfg, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_ratectrlcfg - */ -#define VEN_IOCTL_SET_RATE_CTRL_CFG \ - _IOW(VEN_IOCTLBASE_ENC, 26, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_RATE_CTRL_CFG \ - _IOR(VEN_IOCTLBASE_ENC, 27, struct venc_ioctl_msg) - - -/* - * IOCTL params:SET: InputData - venc_voptimingcfg, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_voptimingcfg - */ -#define VEN_IOCTL_SET_VOP_TIMING_CFG \ - _IOW(VEN_IOCTLBASE_ENC, 28, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_VOP_TIMING_CFG \ - _IOR(VEN_IOCTLBASE_ENC, 29, struct venc_ioctl_msg) - - -/* - * IOCTL params:SET: InputData - venc_framerate, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_framerate - */ -#define VEN_IOCTL_SET_FRAME_RATE \ - _IOW(VEN_IOCTLBASE_ENC, 30, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_FRAME_RATE \ - _IOR(VEN_IOCTLBASE_ENC, 31, struct venc_ioctl_msg) - - -/* - * IOCTL params:SET: InputData - venc_targetbitrate, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_targetbitrate - */ -#define VEN_IOCTL_SET_TARGET_BITRATE \ - _IOW(VEN_IOCTLBASE_ENC, 32, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_TARGET_BITRATE \ - _IOR(VEN_IOCTLBASE_ENC, 33, struct venc_ioctl_msg) - - -/* - * IOCTL params:SET: InputData - venc_rotation, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_rotation - */ -#define VEN_IOCTL_SET_ROTATION \ - _IOW(VEN_IOCTLBASE_ENC, 34, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_ROTATION \ - _IOR(VEN_IOCTLBASE_ENC, 35, struct venc_ioctl_msg) - - -/* - * IOCTL params:SET: InputData - venc_headerextension, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_headerextension - */ -#define VEN_IOCTL_SET_HEC \ - _IOW(VEN_IOCTLBASE_ENC, 36, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_HEC \ - _IOR(VEN_IOCTLBASE_ENC, 37, struct venc_ioctl_msg) - -/* - * IOCTL params:SET: InputData - venc_switch, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_switch - */ -#define VEN_IOCTL_SET_DATA_PARTITION \ - _IOW(VEN_IOCTLBASE_ENC, 38, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_DATA_PARTITION \ - _IOR(VEN_IOCTLBASE_ENC, 39, struct venc_ioctl_msg) - -/* - * IOCTL params:SET: InputData - venc_switch, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_switch - */ -#define VEN_IOCTL_SET_RVLC \ - _IOW(VEN_IOCTLBASE_ENC, 40, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_RVLC \ - _IOR(VEN_IOCTLBASE_ENC, 41, struct venc_ioctl_msg) - - -/* - * IOCTL params:SET: InputData - venc_switch, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_switch - */ -#define VEN_IOCTL_SET_AC_PREDICTION \ - _IOW(VEN_IOCTLBASE_ENC, 42, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_AC_PREDICTION \ - _IOR(VEN_IOCTLBASE_ENC, 43, struct venc_ioctl_msg) - - -/* - * IOCTL params:SET: InputData - venc_qprange, OutputData - NULL - * GET: InputData - NULL, OutputData - venc_qprange - */ -#define VEN_IOCTL_SET_QP_RANGE \ - _IOW(VEN_IOCTLBASE_ENC, 44, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_QP_RANGE \ - _IOR(VEN_IOCTLBASE_ENC, 45, struct venc_ioctl_msg) - -#define VEN_IOCTL_GET_NUMBER_INSTANCES \ - _IOR(VEN_IOCTLBASE_ENC, 46, struct venc_ioctl_msg) - -#define VEN_IOCTL_SET_METABUFFER_MODE \ - _IOW(VEN_IOCTLBASE_ENC, 47, struct venc_ioctl_msg) - - -/*IOCTL params:SET: InputData - unsigned int, OutputData - NULL.*/ -#define VEN_IOCTL_SET_EXTRADATA \ - _IOW(VEN_IOCTLBASE_ENC, 48, struct venc_ioctl_msg) -/*IOCTL params:GET: InputData - NULL, OutputData - unsigned int.*/ -#define VEN_IOCTL_GET_EXTRADATA \ - _IOR(VEN_IOCTLBASE_ENC, 49, struct venc_ioctl_msg) - -/*IOCTL params:SET: InputData - NULL, OutputData - NULL.*/ -#define VEN_IOCTL_SET_SLICE_DELIVERY_MODE \ - _IO(VEN_IOCTLBASE_ENC, 50) - -#define VEN_IOCTL_SET_H263_PLUSPTYPE \ - _IOW(VEN_IOCTLBASE_ENC, 51, struct venc_ioctl_msg) - -/*IOCTL params:SET: InputData - venc_range, OutputData - NULL.*/ -#define VEN_IOCTL_SET_CAPABILITY_LTRCOUNT \ - _IOW(VEN_IOCTLBASE_ENC, 52, struct venc_ioctl_msg) -/*IOCTL params:GET: InputData - NULL, OutputData - venc_range.*/ -#define VEN_IOCTL_GET_CAPABILITY_LTRCOUNT \ - _IOR(VEN_IOCTLBASE_ENC, 53, struct venc_ioctl_msg) - -/*IOCTL params:SET: InputData - venc_ltrmode, OutputData - NULL.*/ -#define VEN_IOCTL_SET_LTRMODE \ - _IOW(VEN_IOCTLBASE_ENC, 54, struct venc_ioctl_msg) -/*IOCTL params:GET: InputData - NULL, OutputData - venc_ltrmode.*/ -#define VEN_IOCTL_GET_LTRMODE \ - _IOR(VEN_IOCTLBASE_ENC, 55, struct venc_ioctl_msg) - -/*IOCTL params:SET: InputData - venc_ltrcount, OutputData - NULL.*/ -#define VEN_IOCTL_SET_LTRCOUNT \ - _IOW(VEN_IOCTLBASE_ENC, 56, struct venc_ioctl_msg) -/*IOCTL params:GET: InputData - NULL, OutputData - venc_ltrcount.*/ -#define VEN_IOCTL_GET_LTRCOUNT \ - _IOR(VEN_IOCTLBASE_ENC, 57, struct venc_ioctl_msg) - -/*IOCTL params:SET: InputData - venc_ltrperiod, OutputData - NULL.*/ -#define VEN_IOCTL_SET_LTRPERIOD \ - _IOW(VEN_IOCTLBASE_ENC, 58, struct venc_ioctl_msg) -/*IOCTL params:GET: InputData - NULL, OutputData - venc_ltrperiod.*/ -#define VEN_IOCTL_GET_LTRPERIOD \ - _IOR(VEN_IOCTLBASE_ENC, 59, struct venc_ioctl_msg) - -/*IOCTL params:SET: InputData - venc_ltruse, OutputData - NULL.*/ -#define VEN_IOCTL_SET_LTRUSE \ - _IOW(VEN_IOCTLBASE_ENC, 60, struct venc_ioctl_msg) -/*IOCTL params:GET: InputData - NULL, OutputData - venc_ltruse.*/ -#define VEN_IOCTL_GET_LTRUSE \ - _IOR(VEN_IOCTLBASE_ENC, 61, struct venc_ioctl_msg) - -/*IOCTL params:SET: InputData - venc_ltrmark, OutputData - NULL.*/ -#define VEN_IOCTL_SET_LTRMARK \ - _IOW(VEN_IOCTLBASE_ENC, 62, struct venc_ioctl_msg) -/*IOCTL params:GET: InputData - NULL, OutputData - venc_ltrmark.*/ -#define VEN_IOCTL_GET_LTRMARK \ - _IOR(VEN_IOCTLBASE_ENC, 63, struct venc_ioctl_msg) - -/*IOCTL params:SET: InputData - unsigned int, OutputData - NULL*/ -#define VEN_IOCTL_SET_SPS_PPS_FOR_IDR \ - _IOW(VEN_IOCTLBASE_ENC, 64, struct venc_ioctl_msg) - -struct venc_range { - unsigned long max; - unsigned long min; - unsigned long step_size; -}; - -struct venc_switch { - unsigned char status; -}; - -struct venc_allocatorproperty { - unsigned long mincount; - unsigned long maxcount; - unsigned long actualcount; - unsigned long datasize; - unsigned long suffixsize; - unsigned long alignment; - unsigned long bufpoolid; -}; - -struct venc_bufferpayload { - unsigned char *pbuffer; - size_t sz; - int fd; - unsigned int offset; - unsigned int maped_size; - unsigned long filled_len; -}; - -struct venc_buffer { - unsigned char *ptrbuffer; - unsigned long sz; - unsigned long len; - unsigned long offset; - long long timestamp; - unsigned long flags; - void *clientdata; -}; - -struct venc_basecfg { - unsigned long input_width; - unsigned long input_height; - unsigned long dvs_width; - unsigned long dvs_height; - unsigned long codectype; - unsigned long fps_num; - unsigned long fps_den; - unsigned long targetbitrate; - unsigned long inputformat; -}; - -struct venc_profile { - unsigned long profile; -}; -struct ven_profilelevel { - unsigned long level; -}; - -struct venc_sessionqp { - unsigned long iframeqp; - unsigned long pframqp; -}; - -struct venc_qprange { - unsigned long maxqp; - unsigned long minqp; -}; - -struct venc_plusptype { - unsigned long plusptype_enable; -}; - -struct venc_intraperiod { - unsigned long num_pframes; - unsigned long num_bframes; -}; -struct venc_seqheader { - unsigned char *hdrbufptr; - unsigned long bufsize; - unsigned long hdrlen; -}; - -struct venc_capability { - unsigned long codec_types; - unsigned long maxframe_width; - unsigned long maxframe_height; - unsigned long maxtarget_bitrate; - unsigned long maxframe_rate; - unsigned long input_formats; - unsigned char dvs; -}; - -struct venc_entropycfg { - unsigned int longentropysel; - unsigned long cabacmodel; -}; - -struct venc_dbcfg { - unsigned long db_mode; - unsigned long slicealpha_offset; - unsigned long slicebeta_offset; -}; - -struct venc_intrarefresh { - unsigned long irmode; - unsigned long mbcount; -}; - -struct venc_multiclicecfg { - unsigned long mslice_mode; - unsigned long mslice_size; -}; - -struct venc_bufferflush { - unsigned long flush_mode; -}; - -struct venc_ratectrlcfg { - unsigned long rcmode; -}; - -struct venc_voptimingcfg { - unsigned long voptime_resolution; -}; -struct venc_framerate { - unsigned long fps_denominator; - unsigned long fps_numerator; -}; - -struct venc_targetbitrate { - unsigned long target_bitrate; -}; - - -struct venc_rotation { - unsigned long rotation; -}; - -struct venc_timeout { - unsigned long millisec; -}; - -struct venc_headerextension { - unsigned long header_extension; -}; - -struct venc_msg { - unsigned long statuscode; - unsigned long msgcode; - struct venc_buffer buf; - unsigned long msgdata_size; -}; - -struct venc_recon_addr { - unsigned char *pbuffer; - unsigned long buffer_size; - unsigned long pmem_fd; - unsigned long offset; -}; - -struct venc_recon_buff_size { - int width; - int height; - int size; - int alignment; -}; - -struct venc_ltrmode { - unsigned long ltr_mode; -}; - -struct venc_ltrcount { - unsigned long ltr_count; -}; - -struct venc_ltrperiod { - unsigned long ltr_period; -}; - -struct venc_ltruse { - unsigned long ltr_id; - unsigned long ltr_frames; -}; - -#endif /* _MSM_VIDC_ENC_H_ */ diff --git a/sdm710/original-kernel-headers/linux/qseecom.h b/sdm710/original-kernel-headers/linux/qseecom.h deleted file mode 100644 index afaf0c47..00000000 --- a/sdm710/original-kernel-headers/linux/qseecom.h +++ /dev/null @@ -1,389 +0,0 @@ -#ifndef _QSEECOM_H_ -#define _QSEECOM_H_ - -#include <linux/types.h> -#include <linux/ioctl.h> - -#define MAX_ION_FD 4 -#define MAX_APP_NAME_SIZE 64 -#define QSEECOM_HASH_SIZE 32 - -/* qseecom_ta_heap allocation retry delay (ms) and max attemp count */ -#define QSEECOM_TA_ION_ALLOCATE_DELAY 50 -#define QSEECOM_TA_ION_ALLOCATE_MAX_ATTEMP 20 - -/* - * struct qseecom_register_listener_req - - * for register listener ioctl request - * @listener_id - service id (shared between userspace and QSE) - * @ifd_data_fd - ion handle - * @virt_sb_base - shared buffer base in user space - * @sb_size - shared buffer size - */ -struct qseecom_register_listener_req { - uint32_t listener_id; /* in */ - int32_t ifd_data_fd; /* in */ - void *virt_sb_base; /* in */ - uint32_t sb_size; /* in */ -}; - -/* - * struct qseecom_send_cmd_req - for send command ioctl request - * @cmd_req_len - command buffer length - * @cmd_req_buf - command buffer - * @resp_len - response buffer length - * @resp_buf - response buffer - */ -struct qseecom_send_cmd_req { - void *cmd_req_buf; /* in */ - unsigned int cmd_req_len; /* in */ - void *resp_buf; /* in/out */ - unsigned int resp_len; /* in/out */ -}; - -/* - * struct qseecom_ion_fd_info - ion fd handle data information - * @fd - ion handle to some memory allocated in user space - * @cmd_buf_offset - command buffer offset - */ -struct qseecom_ion_fd_info { - int32_t fd; - uint32_t cmd_buf_offset; -}; -/* - * struct qseecom_send_modfd_cmd_req - for send command ioctl request - * @cmd_req_len - command buffer length - * @cmd_req_buf - command buffer - * @resp_len - response buffer length - * @resp_buf - response buffer - * @ifd_data_fd - ion handle to memory allocated in user space - * @cmd_buf_offset - command buffer offset - */ -struct qseecom_send_modfd_cmd_req { - void *cmd_req_buf; /* in */ - unsigned int cmd_req_len; /* in */ - void *resp_buf; /* in/out */ - unsigned int resp_len; /* in/out */ - struct qseecom_ion_fd_info ifd_data[MAX_ION_FD]; -}; - -/* - * struct qseecom_listener_send_resp_req - signal to continue the send_cmd req. - * Used as a trigger from HLOS service to notify QSEECOM that it's done with its - * operation and provide the response for QSEECOM can continue the incomplete - * command execution - * @resp_len - Length of the response - * @resp_buf - Response buffer where the response of the cmd should go. - */ -struct qseecom_send_resp_req { - void *resp_buf; /* in */ - unsigned int resp_len; /* in */ -}; - -/* - * struct qseecom_load_img_data - for sending image length information and - * ion file descriptor to the qseecom driver. ion file descriptor is used - * for retrieving the ion file handle and in turn the physical address of - * the image location. - * @mdt_len - Length of the .mdt file in bytes. - * @img_len - Length of the .mdt + .b00 +..+.bxx images files in bytes - * @ion_fd - Ion file descriptor used when allocating memory. - * @img_name - Name of the image. - * @app_arch - Architecture of the image, i.e. 32bit or 64bit app - */ -struct qseecom_load_img_req { - uint32_t mdt_len; /* in */ - uint32_t img_len; /* in */ - int32_t ifd_data_fd; /* in */ - char img_name[MAX_APP_NAME_SIZE]; /* in */ - uint32_t app_arch; /* in */ - uint32_t app_id; /* out*/ -}; - -struct qseecom_set_sb_mem_param_req { - int32_t ifd_data_fd; /* in */ - void *virt_sb_base; /* in */ - uint32_t sb_len; /* in */ -}; - -/* - * struct qseecom_qseos_version_req - get qseos version - * @qseos_version - version number - */ -struct qseecom_qseos_version_req { - unsigned int qseos_version; /* in */ -}; - -/* - * struct qseecom_qseos_app_load_query - verify if app is loaded in qsee - * @app_name[MAX_APP_NAME_SIZE]- name of the app. - * @app_id - app id. - */ -struct qseecom_qseos_app_load_query { - char app_name[MAX_APP_NAME_SIZE]; /* in */ - uint32_t app_id; /* out */ - uint32_t app_arch; -}; - -struct qseecom_send_svc_cmd_req { - uint32_t cmd_id; - void *cmd_req_buf; /* in */ - unsigned int cmd_req_len; /* in */ - void *resp_buf; /* in/out */ - unsigned int resp_len; /* in/out */ -}; - -enum qseecom_key_management_usage_type { - QSEOS_KM_USAGE_DISK_ENCRYPTION = 0x01, - QSEOS_KM_USAGE_FILE_ENCRYPTION = 0x02, - QSEOS_KM_USAGE_UFS_ICE_DISK_ENCRYPTION = 0x03, - QSEOS_KM_USAGE_SDCC_ICE_DISK_ENCRYPTION = 0x04, - QSEOS_KM_USAGE_MAX -}; - -struct qseecom_create_key_req { - unsigned char hash32[QSEECOM_HASH_SIZE]; - enum qseecom_key_management_usage_type usage; -}; - -struct qseecom_wipe_key_req { - enum qseecom_key_management_usage_type usage; - int wipe_key_flag;/* 1->remove key from storage(alone with clear key) */ - /* 0->do not remove from storage (clear key) */ -}; - -struct qseecom_update_key_userinfo_req { - unsigned char current_hash32[QSEECOM_HASH_SIZE]; - unsigned char new_hash32[QSEECOM_HASH_SIZE]; - enum qseecom_key_management_usage_type usage; -}; - -#define SHA256_DIGEST_LENGTH (256/8) -/* - * struct qseecom_save_partition_hash_req - * @partition_id - partition id. - * @hash[SHA256_DIGEST_LENGTH] - sha256 digest. - */ -struct qseecom_save_partition_hash_req { - int partition_id; /* in */ - char digest[SHA256_DIGEST_LENGTH]; /* in */ -}; - -/* - * struct qseecom_is_es_activated_req - * @is_activated - 1=true , 0=false - */ -struct qseecom_is_es_activated_req { - int is_activated; /* out */ -}; - -/* - * struct qseecom_mdtp_cipher_dip_req - * @in_buf - input buffer - * @in_buf_size - input buffer size - * @out_buf - output buffer - * @out_buf_size - output buffer size - * @direction - 0=encrypt, 1=decrypt - */ -struct qseecom_mdtp_cipher_dip_req { - uint8_t *in_buf; - uint32_t in_buf_size; - uint8_t *out_buf; - uint32_t out_buf_size; - uint32_t direction; -}; - -enum qseecom_bandwidth_request_mode { - INACTIVE = 0, - LOW, - MEDIUM, - HIGH, -}; - -/* - * struct qseecom_send_modfd_resp - for send command ioctl request - * @req_len - command buffer length - * @req_buf - command buffer - * @ifd_data_fd - ion handle to memory allocated in user space - * @cmd_buf_offset - command buffer offset - */ -struct qseecom_send_modfd_listener_resp { - void *resp_buf_ptr; /* in */ - unsigned int resp_len; /* in */ - struct qseecom_ion_fd_info ifd_data[MAX_ION_FD]; /* in */ -}; - -struct qseecom_qteec_req { - void *req_ptr; - uint32_t req_len; - void *resp_ptr; - uint32_t resp_len; -}; - -struct qseecom_qteec_modfd_req { - void *req_ptr; - uint32_t req_len; - void *resp_ptr; - uint32_t resp_len; - struct qseecom_ion_fd_info ifd_data[MAX_ION_FD]; -}; - -struct qseecom_sg_entry { - uint32_t phys_addr; - uint32_t len; -}; - -struct qseecom_sg_entry_64bit { - uint64_t phys_addr; - uint32_t len; -} __attribute__ ((packed)); - -/* - * sg list buf format version - * 1: Legacy format to support only 512 SG list entries - * 2: new format to support > 512 entries - */ -#define QSEECOM_SG_LIST_BUF_FORMAT_VERSION_1 1 -#define QSEECOM_SG_LIST_BUF_FORMAT_VERSION_2 2 - -struct qseecom_sg_list_buf_hdr_64bit { - struct qseecom_sg_entry_64bit blank_entry; /* must be all 0 */ - uint32_t version; /* sg list buf format version */ - uint64_t new_buf_phys_addr; /* PA of new buffer */ - uint32_t nents_total; /* Total number of SG entries */ -} __attribute__ ((packed)); - -#define QSEECOM_SG_LIST_BUF_HDR_SZ_64BIT \ - sizeof(struct qseecom_sg_list_buf_hdr_64bit) - -#define MAX_CE_PIPE_PAIR_PER_UNIT 3 -#define INVALID_CE_INFO_UNIT_NUM 0xffffffff - -#define CE_PIPE_PAIR_USE_TYPE_FDE 0 -#define CE_PIPE_PAIR_USE_TYPE_PFE 1 - -struct qseecom_ce_pipe_entry { - int valid; - unsigned int ce_num; - unsigned int ce_pipe_pair; -}; - -#define MAX_CE_INFO_HANDLE_SIZE 32 -struct qseecom_ce_info_req { - unsigned char handle[MAX_CE_INFO_HANDLE_SIZE]; - unsigned int usage; - unsigned int unit_num; - unsigned int num_ce_pipe_entries; - struct qseecom_ce_pipe_entry ce_pipe_entry[MAX_CE_PIPE_PAIR_PER_UNIT]; -}; - -#define SG_ENTRY_SZ sizeof(struct qseecom_sg_entry) -#define SG_ENTRY_SZ_64BIT sizeof(struct qseecom_sg_entry_64bit) - -struct file; - - -#define QSEECOM_IOC_MAGIC 0x97 - - -#define QSEECOM_IOCTL_REGISTER_LISTENER_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 1, struct qseecom_register_listener_req) - -#define QSEECOM_IOCTL_UNREGISTER_LISTENER_REQ \ - _IO(QSEECOM_IOC_MAGIC, 2) - -#define QSEECOM_IOCTL_SEND_CMD_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 3, struct qseecom_send_cmd_req) - -#define QSEECOM_IOCTL_SEND_MODFD_CMD_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 4, struct qseecom_send_modfd_cmd_req) - -#define QSEECOM_IOCTL_RECEIVE_REQ \ - _IO(QSEECOM_IOC_MAGIC, 5) - -#define QSEECOM_IOCTL_SEND_RESP_REQ \ - _IO(QSEECOM_IOC_MAGIC, 6) - -#define QSEECOM_IOCTL_LOAD_APP_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 7, struct qseecom_load_img_req) - -#define QSEECOM_IOCTL_SET_MEM_PARAM_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 8, struct qseecom_set_sb_mem_param_req) - -#define QSEECOM_IOCTL_UNLOAD_APP_REQ \ - _IO(QSEECOM_IOC_MAGIC, 9) - -#define QSEECOM_IOCTL_GET_QSEOS_VERSION_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 10, struct qseecom_qseos_version_req) - -#define QSEECOM_IOCTL_PERF_ENABLE_REQ \ - _IO(QSEECOM_IOC_MAGIC, 11) - -#define QSEECOM_IOCTL_PERF_DISABLE_REQ \ - _IO(QSEECOM_IOC_MAGIC, 12) - -#define QSEECOM_IOCTL_LOAD_EXTERNAL_ELF_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 13, struct qseecom_load_img_req) - -#define QSEECOM_IOCTL_UNLOAD_EXTERNAL_ELF_REQ \ - _IO(QSEECOM_IOC_MAGIC, 14) - -#define QSEECOM_IOCTL_APP_LOADED_QUERY_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 15, struct qseecom_qseos_app_load_query) - -#define QSEECOM_IOCTL_SEND_CMD_SERVICE_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 16, struct qseecom_send_svc_cmd_req) - -#define QSEECOM_IOCTL_CREATE_KEY_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 17, struct qseecom_create_key_req) - -#define QSEECOM_IOCTL_WIPE_KEY_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 18, struct qseecom_wipe_key_req) - -#define QSEECOM_IOCTL_SAVE_PARTITION_HASH_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 19, struct qseecom_save_partition_hash_req) - -#define QSEECOM_IOCTL_IS_ES_ACTIVATED_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 20, struct qseecom_is_es_activated_req) - -#define QSEECOM_IOCTL_SEND_MODFD_RESP \ - _IOWR(QSEECOM_IOC_MAGIC, 21, struct qseecom_send_modfd_listener_resp) - -#define QSEECOM_IOCTL_SET_BUS_SCALING_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 23, int) - -#define QSEECOM_IOCTL_UPDATE_KEY_USER_INFO_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 24, struct qseecom_update_key_userinfo_req) - -#define QSEECOM_QTEEC_IOCTL_OPEN_SESSION_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 30, struct qseecom_qteec_modfd_req) - -#define QSEECOM_QTEEC_IOCTL_CLOSE_SESSION_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 31, struct qseecom_qteec_req) - -#define QSEECOM_QTEEC_IOCTL_INVOKE_MODFD_CMD_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 32, struct qseecom_qteec_modfd_req) - -#define QSEECOM_QTEEC_IOCTL_REQUEST_CANCELLATION_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 33, struct qseecom_qteec_modfd_req) - -#define QSEECOM_IOCTL_MDTP_CIPHER_DIP_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 34, struct qseecom_mdtp_cipher_dip_req) - -#define QSEECOM_IOCTL_SEND_MODFD_CMD_64_REQ \ - _IOWR(QSEECOM_IOC_MAGIC, 35, struct qseecom_send_modfd_cmd_req) - -#define QSEECOM_IOCTL_SEND_MODFD_RESP_64 \ - _IOWR(QSEECOM_IOC_MAGIC, 36, struct qseecom_send_modfd_listener_resp) - -#define QSEECOM_IOCTL_GET_CE_PIPE_INFO \ - _IOWR(QSEECOM_IOC_MAGIC, 40, struct qseecom_ce_info_req) - -#define QSEECOM_IOCTL_FREE_CE_PIPE_INFO \ - _IOWR(QSEECOM_IOC_MAGIC, 41, struct qseecom_ce_info_req) - -#define QSEECOM_IOCTL_QUERY_CE_PIPE_INFO \ - _IOWR(QSEECOM_IOC_MAGIC, 42, struct qseecom_ce_info_req) - - -#endif /* _QSEECOM_H_ */ diff --git a/sdm710/original-kernel-headers/linux/rmnet_data.h b/sdm710/original-kernel-headers/linux/rmnet_data.h deleted file mode 100644 index 48c173e4..00000000 --- a/sdm710/original-kernel-headers/linux/rmnet_data.h +++ /dev/null @@ -1,247 +0,0 @@ -/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * RMNET Data configuration specification - */ - -#ifndef _RMNET_DATA_H_ -#define _RMNET_DATA_H_ - -/* Constants */ -#define RMNET_LOCAL_LOGICAL_ENDPOINT -1 - -#define RMNET_EGRESS_FORMAT__RESERVED__ (1<<0) -#define RMNET_EGRESS_FORMAT_MAP (1<<1) -#define RMNET_EGRESS_FORMAT_AGGREGATION (1<<2) -#define RMNET_EGRESS_FORMAT_MUXING (1<<3) -#define RMNET_EGRESS_FORMAT_MAP_CKSUMV3 (1<<4) -#define RMNET_EGRESS_FORMAT_MAP_CKSUMV4 (1<<5) - -#define RMNET_INGRESS_FIX_ETHERNET (1<<0) -#define RMNET_INGRESS_FORMAT_MAP (1<<1) -#define RMNET_INGRESS_FORMAT_DEAGGREGATION (1<<2) -#define RMNET_INGRESS_FORMAT_DEMUXING (1<<3) -#define RMNET_INGRESS_FORMAT_MAP_COMMANDS (1<<4) -#define RMNET_INGRESS_FORMAT_MAP_CKSUMV3 (1<<5) -#define RMNET_INGRESS_FORMAT_MAP_CKSUMV4 (1<<6) - -/* Netlink API */ -#define RMNET_NETLINK_PROTO 31 -#define RMNET_MAX_STR_LEN 16 -#define RMNET_NL_DATA_MAX_LEN 64 - -#define RMNET_NETLINK_MSG_COMMAND 0 -#define RMNET_NETLINK_MSG_RETURNCODE 1 -#define RMNET_NETLINK_MSG_RETURNDATA 2 - -struct rmnet_nl_msg_s { - uint16_t reserved; - uint16_t message_type; - uint16_t reserved2:14; - uint16_t crd:2; - union { - uint16_t arg_length; - uint16_t return_code; - }; - union { - uint8_t data[RMNET_NL_DATA_MAX_LEN]; - struct { - uint8_t dev[RMNET_MAX_STR_LEN]; - uint32_t flags; - uint16_t agg_size; - uint16_t agg_count; - uint8_t tail_spacing; - } data_format; - struct { - uint8_t dev[RMNET_MAX_STR_LEN]; - int32_t ep_id; - uint8_t operating_mode; - uint8_t next_dev[RMNET_MAX_STR_LEN]; - } local_ep_config; - struct { - uint32_t id; - uint8_t vnd_name[RMNET_MAX_STR_LEN]; - } vnd; - struct { - uint32_t id; - uint32_t map_flow_id; - uint32_t tc_flow_id; - } flow_control; - }; -}; - -enum rmnet_netlink_message_types_e { - /* RMNET_NETLINK_ASSOCIATE_NETWORK_DEVICE - Register RMNET data driver - * on a particular device. - * Args: char[] dev_name: Null terminated ASCII string, max length: 15 - * Returns: status code - */ - RMNET_NETLINK_ASSOCIATE_NETWORK_DEVICE, - - /* RMNET_NETLINK_UNASSOCIATE_NETWORK_DEVICE - Unregister RMNET data - * driver on a particular - * device. - * Args: char[] dev_name: Null terminated ASCII string, max length: 15 - * Returns: status code - */ - RMNET_NETLINK_UNASSOCIATE_NETWORK_DEVICE, - - /* RMNET_NETLINK_GET_NETWORK_DEVICE_ASSOCIATED - Get if RMNET data - * driver is registered on a - * particular device. - * Args: char[] dev_name: Null terminated ASCII string, max length: 15 - * Returns: 1 if registered, 0 if not - */ - RMNET_NETLINK_GET_NETWORK_DEVICE_ASSOCIATED, - - /* RMNET_NETLINK_SET_LINK_EGRESS_DATA_FORMAT - Sets the egress data - * format for a particular - * link. - * Args: uint32_t egress_flags - * char[] dev_name: Null terminated ASCII string, max length: 15 - * Returns: status code - */ - RMNET_NETLINK_SET_LINK_EGRESS_DATA_FORMAT, - - /* RMNET_NETLINK_GET_LINK_EGRESS_DATA_FORMAT - Gets the egress data - * format for a particular - * link. - * Args: char[] dev_name: Null terminated ASCII string, max length: 15 - * Returns: 4-bytes data: uint32_t egress_flags - */ - RMNET_NETLINK_GET_LINK_EGRESS_DATA_FORMAT, - - /* RMNET_NETLINK_SET_LINK_INGRESS_DATA_FORMAT - Sets the ingress data - * format for a particular - * link. - * Args: uint32_t ingress_flags - * char[] dev_name: Null terminated ASCII string, max length: 15 - * Returns: status code - */ - RMNET_NETLINK_SET_LINK_INGRESS_DATA_FORMAT, - - /* RMNET_NETLINK_GET_LINK_INGRESS_DATA_FORMAT - Gets the ingress data - * format for a particular - * link. - * Args: char[] dev_name: Null terminated ASCII string, max length: 15 - * Returns: 4-bytes data: uint32_t ingress_flags - */ - RMNET_NETLINK_GET_LINK_INGRESS_DATA_FORMAT, - - /* RMNET_NETLINK_SET_LOGICAL_EP_CONFIG - Sets the logical endpoint - * configuration for a particular - * link. - * Args: char[] dev_name: Null terminated ASCII string, max length: 15 - * int32_t logical_ep_id, valid values are -1 through 31 - * uint8_t rmnet_mode: one of none, vnd, bridged - * char[] egress_dev_name: Egress device if operating in bridge mode - * Returns: status code - */ - RMNET_NETLINK_SET_LOGICAL_EP_CONFIG, - - /* RMNET_NETLINK_UNSET_LOGICAL_EP_CONFIG - Un-sets the logical endpoint - * configuration for a particular - * link. - * Args: char[] dev_name: Null terminated ASCII string, max length: 15 - * int32_t logical_ep_id, valid values are -1 through 31 - * Returns: status code - */ - RMNET_NETLINK_UNSET_LOGICAL_EP_CONFIG, - - /* RMNET_NETLINK_GET_LOGICAL_EP_CONFIG - Gets the logical endpoint - * configuration for a particular - * link. - * Args: char[] dev_name: Null terminated ASCII string, max length: 15 - * int32_t logical_ep_id, valid values are -1 through 31 - * Returns: uint8_t rmnet_mode: one of none, vnd, bridged - * char[] egress_dev_name: Egress device - */ - RMNET_NETLINK_GET_LOGICAL_EP_CONFIG, - - /* RMNET_NETLINK_NEW_VND - Creates a new virtual network device node - * Args: int32_t node number - * Returns: status code - */ - RMNET_NETLINK_NEW_VND, - - /* RMNET_NETLINK_NEW_VND_WITH_PREFIX - Creates a new virtual network - * device node with the specified - * prefix for the device name - * Args: int32_t node number - * char[] vnd_name - Use as prefix - * Returns: status code - */ - RMNET_NETLINK_NEW_VND_WITH_PREFIX, - - /* RMNET_NETLINK_GET_VND_NAME - Gets the string name of a VND from ID - * Args: int32_t node number - * Returns: char[] vnd_name - */ - RMNET_NETLINK_GET_VND_NAME, - - /* RMNET_NETLINK_FREE_VND - Removes virtual network device node - * Args: int32_t node number - * Returns: status code - */ - RMNET_NETLINK_FREE_VND, - - /* RMNET_NETLINK_ADD_VND_TC_FLOW - Add flow control handle on VND - * Args: int32_t node number - * uint32_t MAP Flow Handle - * uint32_t TC Flow Handle - * Returns: status code - */ - RMNET_NETLINK_ADD_VND_TC_FLOW, - - /* RMNET_NETLINK_DEL_VND_TC_FLOW - Removes flow control handle on VND - * Args: int32_t node number - * uint32_t MAP Flow Handle - * Returns: status code - */ - RMNET_NETLINK_DEL_VND_TC_FLOW, - - /* - * RMNET_NETLINK_NEW_VND_WITH_NAME - Creates a new virtual network - * device node with the specified - * device name - * Args: int32_t node number - * char[] vnd_name - Use as name - * Returns: status code - */ - RMNET_NETLINK_NEW_VND_WITH_NAME -}; -#define RMNET_NETLINK_NEW_VND_WITH_NAME RMNET_NETLINK_NEW_VND_WITH_NAME - -enum rmnet_config_endpoint_modes_e { - /* Pass the frame up the stack with no modifications to skb->dev */ - RMNET_EPMODE_NONE, - /* Replace skb->dev to a virtual rmnet device and pass up the stack */ - RMNET_EPMODE_VND, - /* Pass the frame directly to another device with dev_queue_xmit(). */ - RMNET_EPMODE_BRIDGE, - /* Must be the last item in the list */ - RMNET_EPMODE_LENGTH -}; - -enum rmnet_config_return_codes_e { - RMNET_CONFIG_OK, - RMNET_CONFIG_UNKNOWN_MESSAGE, - RMNET_CONFIG_UNKNOWN_ERROR, - RMNET_CONFIG_NOMEM, - RMNET_CONFIG_DEVICE_IN_USE, - RMNET_CONFIG_INVALID_REQUEST, - RMNET_CONFIG_NO_SUCH_DEVICE, - RMNET_CONFIG_BAD_ARGUMENTS, - RMNET_CONFIG_BAD_EGRESS_DEVICE, - RMNET_CONFIG_TC_HANDLE_FULL -}; - -#endif /* _RMNET_DATA_H_ */ diff --git a/sdm710/original-kernel-headers/linux/rmnet_ipa_fd_ioctl.h b/sdm710/original-kernel-headers/linux/rmnet_ipa_fd_ioctl.h deleted file mode 100644 index 2992e2c7..00000000 --- a/sdm710/original-kernel-headers/linux/rmnet_ipa_fd_ioctl.h +++ /dev/null @@ -1,261 +0,0 @@ -/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _RMNET_IPA_FD_IOCTL_H -#define _RMNET_IPA_FD_IOCTL_H - -#include <linux/ioctl.h> -#include <linux/ipa_qmi_service_v01.h> -#include <linux/msm_ipa.h> - -/** - * unique magic number of the IPA_WAN device - */ -#define WAN_IOC_MAGIC 0x69 - -#define WAN_IOCTL_ADD_FLT_RULE 0 -#define WAN_IOCTL_ADD_FLT_INDEX 1 -#define WAN_IOCTL_VOTE_FOR_BW_MBPS 2 -#define WAN_IOCTL_POLL_TETHERING_STATS 3 -#define WAN_IOCTL_SET_DATA_QUOTA 4 -#define WAN_IOCTL_SET_TETHER_CLIENT_PIPE 5 -#define WAN_IOCTL_QUERY_TETHER_STATS 6 -#define WAN_IOCTL_RESET_TETHER_STATS 7 -#define WAN_IOCTL_QUERY_DL_FILTER_STATS 8 -#define WAN_IOCTL_ADD_FLT_RULE_EX 9 -#define WAN_IOCTL_QUERY_TETHER_STATS_ALL 10 -#define WAN_IOCTL_NOTIFY_WAN_STATE 11 -#define WAN_IOCTL_ADD_UL_FLT_RULE 12 -#define WAN_IOCTL_ENABLE_PER_CLIENT_STATS 13 -#define WAN_IOCTL_QUERY_PER_CLIENT_STATS 14 -#define WAN_IOCTL_SET_LAN_CLIENT_INFO 15 -#define WAN_IOCTL_CLEAR_LAN_CLIENT_INFO 16 -#define WAN_IOCTL_SEND_LAN_CLIENT_MSG 17 - -/* User space may not have this defined. */ -#ifndef IFNAMSIZ -#define IFNAMSIZ 16 -#endif - -/** - * struct wan_ioctl_poll_tethering_stats - structure used for - * WAN_IOCTL_POLL_TETHERING_STATS IOCTL. - * - * @polling_interval_secs: Polling interval in seconds. - * @reset_stats: Indicate whether to reset the stats (use 1) or not. - * - * The structure to be used by the user space in order to request for the - * tethering stats to be polled. Setting the interval to 0 indicates to stop - * the polling process. - */ -struct wan_ioctl_poll_tethering_stats { - uint64_t polling_interval_secs; - uint8_t reset_stats; -}; - -/** - * struct wan_ioctl_set_data_quota - structure used for - * WAN_IOCTL_SET_DATA_QUOTA IOCTL. - * - * @interface_name: Name of the interface on which to set the quota. - * @quota_mbytes: Quota (in Mbytes) for the above interface. - * @set_quota: Indicate whether to set the quota (use 1) or - * unset the quota. - * - * The structure to be used by the user space in order to request - * a quota to be set on a specific interface (by specifying its name). - */ -struct wan_ioctl_set_data_quota { - char interface_name[IFNAMSIZ]; - uint64_t quota_mbytes; - uint8_t set_quota; -}; - -struct wan_ioctl_set_tether_client_pipe { - /* enum of tether interface */ - enum ipacm_client_enum ipa_client; - uint8_t reset_client; - uint32_t ul_src_pipe_len; - uint32_t ul_src_pipe_list[QMI_IPA_MAX_PIPES_V01]; - uint32_t dl_dst_pipe_len; - uint32_t dl_dst_pipe_list[QMI_IPA_MAX_PIPES_V01]; -}; - -struct wan_ioctl_query_tether_stats { - /* Name of the upstream interface */ - char upstreamIface[IFNAMSIZ]; - /* Name of the tethered interface */ - char tetherIface[IFNAMSIZ]; - /* enum of tether interface */ - enum ipacm_client_enum ipa_client; - uint64_t ipv4_tx_packets; - uint64_t ipv4_tx_bytes; - uint64_t ipv4_rx_packets; - uint64_t ipv4_rx_bytes; - uint64_t ipv6_tx_packets; - uint64_t ipv6_tx_bytes; - uint64_t ipv6_rx_packets; - uint64_t ipv6_rx_bytes; -}; - -struct wan_ioctl_query_tether_stats_all { - /* Name of the upstream interface */ - char upstreamIface[IFNAMSIZ]; - /* enum of tether interface */ - enum ipacm_client_enum ipa_client; - uint8_t reset_stats; - uint64_t tx_bytes; - uint64_t rx_bytes; -}; - -struct wan_ioctl_reset_tether_stats { - /* Name of the upstream interface, not support now */ - char upstreamIface[IFNAMSIZ]; - /* Indicate whether to reset the stats (use 1) or not */ - uint8_t reset_stats; -}; - -struct wan_ioctl_query_dl_filter_stats { - /* Indicate whether to reset the filter stats (use 1) or not*/ - uint8_t reset_stats; - /* Modem response QMI */ - struct ipa_get_data_stats_resp_msg_v01 stats_resp; - /* provide right index to 1st firewall rule */ - uint32_t index; -}; - -struct wan_ioctl_notify_wan_state { - uint8_t up; -}; -struct wan_ioctl_send_lan_client_msg { - /* Lan client info. */ - struct ipa_lan_client_msg lan_client; - /* Event to indicate whether client is - * connected or disconnected. - */ - enum ipa_per_client_stats_event client_event; -}; - -struct wan_ioctl_lan_client_info { - /* Device type of the client. */ - enum ipacm_per_client_device_type device_type; - /* MAC Address of the client. */ - uint8_t mac[IPA_MAC_ADDR_SIZE]; - /* Init client. */ - uint8_t client_init; - /* Client Index */ - int8_t client_idx; - /* Header length of the client. */ - uint8_t hdr_len; - /* Source pipe of the lan client. */ - enum ipa_client_type ul_src_pipe; -}; - -struct wan_ioctl_per_client_info { - /* MAC Address of the client. */ - uint8_t mac[IPA_MAC_ADDR_SIZE]; - /* Ipv4 UL traffic bytes. */ - uint64_t ipv4_tx_bytes; - /* Ipv4 DL traffic bytes. */ - uint64_t ipv4_rx_bytes; - /* Ipv6 UL traffic bytes. */ - uint64_t ipv6_tx_bytes; - /* Ipv6 DL traffic bytes. */ - uint64_t ipv6_rx_bytes; -}; - -struct wan_ioctl_query_per_client_stats { - /* Device type of the client. */ - enum ipacm_per_client_device_type device_type; - /* Indicate whether to reset the stats (use 1) or not */ - uint8_t reset_stats; - /* Indicates whether client is disconnected. */ - uint8_t disconnect_clnt; - /* Number of clients. */ - uint8_t num_clients; - /* Client information. */ - struct wan_ioctl_per_client_info - client_info[IPA_MAX_NUM_HW_PATH_CLIENTS]; -}; - -#define WAN_IOC_ADD_FLT_RULE _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_ADD_FLT_RULE, \ - struct ipa_install_fltr_rule_req_msg_v01 *) - -#define WAN_IOC_ADD_FLT_RULE_INDEX _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_ADD_FLT_INDEX, \ - struct ipa_fltr_installed_notif_req_msg_v01 *) - -#define WAN_IOC_VOTE_FOR_BW_MBPS _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_VOTE_FOR_BW_MBPS, \ - uint32_t *) - -#define WAN_IOC_POLL_TETHERING_STATS _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_POLL_TETHERING_STATS, \ - struct wan_ioctl_poll_tethering_stats *) - -#define WAN_IOC_SET_DATA_QUOTA _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_SET_DATA_QUOTA, \ - struct wan_ioctl_set_data_quota *) - -#define WAN_IOC_SET_TETHER_CLIENT_PIPE _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_SET_TETHER_CLIENT_PIPE, \ - struct wan_ioctl_set_tether_client_pipe *) - -#define WAN_IOC_QUERY_TETHER_STATS _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_QUERY_TETHER_STATS, \ - struct wan_ioctl_query_tether_stats *) - -#define WAN_IOC_RESET_TETHER_STATS _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_RESET_TETHER_STATS, \ - struct wan_ioctl_reset_tether_stats *) - -#define WAN_IOC_QUERY_DL_FILTER_STATS _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_QUERY_DL_FILTER_STATS, \ - struct wan_ioctl_query_dl_filter_stats *) - -#define WAN_IOC_ADD_FLT_RULE_EX _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_ADD_FLT_RULE_EX, \ - struct ipa_install_fltr_rule_req_ex_msg_v01 *) - -#define WAN_IOC_QUERY_TETHER_STATS_ALL _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_QUERY_TETHER_STATS_ALL, \ - struct wan_ioctl_query_tether_stats_all *) - -#define WAN_IOC_NOTIFY_WAN_STATE _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_NOTIFY_WAN_STATE, \ - struct wan_ioctl_notify_wan_state *) - -#define WAN_IOC_ADD_UL_FLT_RULE _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_ADD_UL_FLT_RULE, \ - struct ipa_configure_ul_firewall_rules_req_msg_v01 *) - -#define WAN_IOC_ENABLE_PER_CLIENT_STATS _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_ENABLE_PER_CLIENT_STATS, \ - bool *) - -#define WAN_IOC_QUERY_PER_CLIENT_STATS _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_QUERY_PER_CLIENT_STATS, \ - struct wan_ioctl_query_per_client_stats *) - -#define WAN_IOC_SET_LAN_CLIENT_INFO _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_SET_LAN_CLIENT_INFO, \ - struct wan_ioctl_lan_client_info *) - -#define WAN_IOC_SEND_LAN_CLIENT_MSG _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_SEND_LAN_CLIENT_MSG, \ - struct wan_ioctl_send_lan_client_msg *) - -#define WAN_IOC_CLEAR_LAN_CLIENT_INFO _IOWR(WAN_IOC_MAGIC, \ - WAN_IOCTL_CLEAR_LAN_CLIENT_INFO, \ - struct wan_ioctl_lan_client_info *) -#endif /* _RMNET_IPA_FD_IOCTL_H */ diff --git a/sdm710/original-kernel-headers/linux/sockios.h b/sdm710/original-kernel-headers/linux/sockios.h deleted file mode 100644 index 8e7890b2..00000000 --- a/sdm710/original-kernel-headers/linux/sockios.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * INET An implementation of the TCP/IP protocol suite for the LINUX - * operating system. INET is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * Definitions of the socket-level I/O control calls. - * - * Version: @(#)sockios.h 1.0.2 03/09/93 - * - * Authors: Ross Biro - * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef _LINUX_SOCKIOS_H -#define _LINUX_SOCKIOS_H - -#include <asm/sockios.h> - -/* Linux-specific socket ioctls */ -#define SIOCINQ FIONREAD -#define SIOCOUTQ TIOCOUTQ /* output queue size (not sent + not acked) */ - -/* Routing table calls. */ -#define SIOCADDRT 0x890B /* add routing table entry */ -#define SIOCDELRT 0x890C /* delete routing table entry */ -#define SIOCRTMSG 0x890D /* unused */ - -/* Socket configuration controls. */ -#define SIOCGIFNAME 0x8910 /* get iface name */ -#define SIOCSIFLINK 0x8911 /* set iface channel */ -#define SIOCGIFCONF 0x8912 /* get iface list */ -#define SIOCGIFFLAGS 0x8913 /* get flags */ -#define SIOCSIFFLAGS 0x8914 /* set flags */ -#define SIOCGIFADDR 0x8915 /* get PA address */ -#define SIOCSIFADDR 0x8916 /* set PA address */ -#define SIOCGIFDSTADDR 0x8917 /* get remote PA address */ -#define SIOCSIFDSTADDR 0x8918 /* set remote PA address */ -#define SIOCGIFBRDADDR 0x8919 /* get broadcast PA address */ -#define SIOCSIFBRDADDR 0x891a /* set broadcast PA address */ -#define SIOCGIFNETMASK 0x891b /* get network PA mask */ -#define SIOCSIFNETMASK 0x891c /* set network PA mask */ -#define SIOCGIFMETRIC 0x891d /* get metric */ -#define SIOCSIFMETRIC 0x891e /* set metric */ -#define SIOCGIFMEM 0x891f /* get memory address (BSD) */ -#define SIOCSIFMEM 0x8920 /* set memory address (BSD) */ -#define SIOCGIFMTU 0x8921 /* get MTU size */ -#define SIOCSIFMTU 0x8922 /* set MTU size */ -#define SIOCSIFNAME 0x8923 /* set interface name */ -#define SIOCSIFHWADDR 0x8924 /* set hardware address */ -#define SIOCGIFENCAP 0x8925 /* get/set encapsulations */ -#define SIOCSIFENCAP 0x8926 -#define SIOCGIFHWADDR 0x8927 /* Get hardware address */ -#define SIOCGIFSLAVE 0x8929 /* Driver slaving support */ -#define SIOCSIFSLAVE 0x8930 -#define SIOCADDMULTI 0x8931 /* Multicast address lists */ -#define SIOCDELMULTI 0x8932 -#define SIOCGIFINDEX 0x8933 /* name -> if_index mapping */ -#define SIOGIFINDEX SIOCGIFINDEX /* misprint compatibility :-) */ -#define SIOCSIFPFLAGS 0x8934 /* set/get extended flags set */ -#define SIOCGIFPFLAGS 0x8935 -#define SIOCDIFADDR 0x8936 /* delete PA address */ -#define SIOCSIFHWBROADCAST 0x8937 /* set hardware broadcast addr */ -#define SIOCGIFCOUNT 0x8938 /* get number of devices */ - -#define SIOCGIFBR 0x8940 /* Bridging support */ -#define SIOCSIFBR 0x8941 /* Set bridging options */ - -#define SIOCGIFTXQLEN 0x8942 /* Get the tx queue length */ -#define SIOCSIFTXQLEN 0x8943 /* Set the tx queue length */ - -/* SIOCGIFDIVERT was: 0x8944 Frame diversion support */ -/* SIOCSIFDIVERT was: 0x8945 Set frame diversion options */ - -#define SIOCETHTOOL 0x8946 /* Ethtool interface */ - -#define SIOCGMIIPHY 0x8947 /* Get address of MII PHY in use. */ -#define SIOCGMIIREG 0x8948 /* Read MII PHY register. */ -#define SIOCSMIIREG 0x8949 /* Write MII PHY register. */ - -#define SIOCWANDEV 0x894A /* get/set netdev parameters */ - -#define SIOCOUTQNSD 0x894B /* output queue size (not sent only) */ - -/* ARP cache control calls. */ - /* 0x8950 - 0x8952 * obsolete calls, don't re-use */ -#define SIOCDARP 0x8953 /* delete ARP table entry */ -#define SIOCGARP 0x8954 /* get ARP table entry */ -#define SIOCSARP 0x8955 /* set ARP table entry */ - -/* RARP cache control calls. */ -#define SIOCDRARP 0x8960 /* delete RARP table entry */ -#define SIOCGRARP 0x8961 /* get RARP table entry */ -#define SIOCSRARP 0x8962 /* set RARP table entry */ - -/* Driver configuration calls */ - -#define SIOCGIFMAP 0x8970 /* Get device parameters */ -#define SIOCSIFMAP 0x8971 /* Set device parameters */ - -/* DLCI configuration calls */ - -#define SIOCADDDLCI 0x8980 /* Create new DLCI device */ -#define SIOCDELDLCI 0x8981 /* Delete DLCI device */ - -#define SIOCGIFVLAN 0x8982 /* 802.1Q VLAN support */ -#define SIOCSIFVLAN 0x8983 /* Set 802.1Q VLAN options */ - -/* bonding calls */ - -#define SIOCBONDENSLAVE 0x8990 /* enslave a device to the bond */ -#define SIOCBONDRELEASE 0x8991 /* release a slave from the bond*/ -#define SIOCBONDSETHWADDR 0x8992 /* set the hw addr of the bond */ -#define SIOCBONDSLAVEINFOQUERY 0x8993 /* rtn info about slave state */ -#define SIOCBONDINFOQUERY 0x8994 /* rtn info about bond state */ -#define SIOCBONDCHANGEACTIVE 0x8995 /* update to a new active slave */ - -/* bridge calls */ -#define SIOCBRADDBR 0x89a0 /* create new bridge device */ -#define SIOCBRDELBR 0x89a1 /* remove bridge device */ -#define SIOCBRADDIF 0x89a2 /* add interface to bridge */ -#define SIOCBRDELIF 0x89a3 /* remove interface from bridge */ - -/* hardware time stamping: parameters in linux/net_tstamp.h */ -#define SIOCSHWTSTAMP 0x89b0 /* set and get config */ -#define SIOCGHWTSTAMP 0x89b1 /* get config */ - -/* Device private ioctl calls */ - -/* - * These 16 ioctls are available to devices via the do_ioctl() device - * vector. Each device should include this file and redefine these names - * as their own. Because these are device dependent it is a good idea - * _NOT_ to issue them to random objects and hope. - * - * THESE IOCTLS ARE _DEPRECATED_ AND WILL DISAPPEAR IN 2.5.X -DaveM - */ - -#define SIOCDEVPRIVATE 0x89F0 /* to 89FF */ - -/* - * These 16 ioctl calls are protocol private - */ - -#define SIOCPROTOPRIVATE 0x89E0 /* to 89EF */ -#endif /* _LINUX_SOCKIOS_H */ diff --git a/sdm710/original-kernel-headers/linux/spcom.h b/sdm710/original-kernel-headers/linux/spcom.h deleted file mode 100644 index 5a438db1..00000000 --- a/sdm710/original-kernel-headers/linux/spcom.h +++ /dev/null @@ -1,119 +0,0 @@ -/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SPCOM_H_ -#define _SPCOM_H_ - -#include <linux/types.h> /* uint32_t, bool */ -#ifndef BIT - #define BIT(x) (1 << x) -#endif -#ifndef PAGE_SIZE - #define PAGE_SIZE 4096 -#endif - -/** - * @brief - Secure Processor Communication interface to user space spcomlib. - * - * Sending data and control commands by write() file operation. - * Receiving data by read() file operation. - * Getting the next request size by read() file operation, - * with special size SPCOM_GET_NEXT_REQUEST_SIZE. - */ - -/* - * Maximum number of channel between Secure Processor and HLOS. - * including predefined channels, like "sp_kernel". - */ -#define SPCOM_MAX_CHANNELS 0x20 - -/* Maximum size (including null) for channel names */ -#define SPCOM_CHANNEL_NAME_SIZE 32 - -/* - * file read(fd, buf, size) with this size, - * hints the kernel that user space wants to read the next-req-size. - * This size is bigger than both SPCOM_MAX_REQUEST_SIZE and - * SPCOM_MAX_RESPONSE_SIZE , so it is not a valid data size. - */ -#define SPCOM_GET_NEXT_REQUEST_SIZE (PAGE_SIZE-1) - -/* Command Id between spcomlib and spcom driver, on write() */ -enum spcom_cmd_id { - SPCOM_CMD_LOAD_APP = 0x4C4F4144, /* "LOAD" = 0x4C4F4144 */ - SPCOM_CMD_RESET_SP = 0x52455354, /* "REST" = 0x52455354 */ - SPCOM_CMD_SEND = 0x53454E44, /* "SEND" = 0x53454E44 */ - SPCOM_CMD_SEND_MODIFIED = 0x534E444D, /* "SNDM" = 0x534E444D */ - SPCOM_CMD_LOCK_ION_BUF = 0x4C4F434B, /* "LOCK" = 0x4C4F434B */ - SPCOM_CMD_UNLOCK_ION_BUF = 0x554C434B, /* "ULCK" = 0x4C4F434B */ - SPCOM_CMD_FSSR = 0x46535352, /* "FSSR" = 0x46535352 */ - SPCOM_CMD_CREATE_CHANNEL = 0x43524554, /* "CRET" = 0x43524554 */ -}; - -/* - * @note: Event types that are always implicitly polled: - * POLLERR=0x08 | POLLHUP=0x10 | POLLNVAL=0x20 - * so bits 3,4,5 can't be used - */ -enum spcom_poll_events { - SPCOM_POLL_LINK_STATE = BIT(1), - SPCOM_POLL_CH_CONNECT = BIT(2), - SPCOM_POLL_READY_FLAG = BIT(14), /* output */ - SPCOM_POLL_WAIT_FLAG = BIT(15), /* if set , wait for the event */ -}; - -/* Common Command structure between User Space and spcom driver, on write() */ -struct spcom_user_command { - enum spcom_cmd_id cmd_id; - uint32_t arg; -} __attribute__((packed)); - -/* Command structure between User Space and spcom driver, on write() */ -struct spcom_send_command { - enum spcom_cmd_id cmd_id; - uint32_t timeout_msec; - uint32_t buf_size; - char buf[0]; /* Variable buffer size - must be last field */ -} __attribute__((packed)); - -/* Command structure between userspace spcomlib and spcom driver, on write() */ -struct spcom_user_create_channel_command { - enum spcom_cmd_id cmd_id; - char ch_name[SPCOM_CHANNEL_NAME_SIZE]; -} __attribute__((packed)); - -/* maximum ION buf for send-modfied-command */ -#define SPCOM_MAX_ION_BUF 4 - -struct spcom_ion_info { - int32_t fd; /* ION buffer File Descriptor, set -1 for invalid fd */ - uint32_t buf_offset; /* virtual address offset in request/response */ -}; - -/* Pass this FD to unlock all ION buffer for the specific channel */ -#define SPCOM_ION_FD_UNLOCK_ALL 0xFFFF - -struct spcom_ion_handle { - int32_t fd; /* File Descriptor associated with the buffer */ -}; - -/* Command structure between User Space and spcom driver, on write() */ -struct spcom_user_send_modified_command { - enum spcom_cmd_id cmd_id; - struct spcom_ion_info ion_info[SPCOM_MAX_ION_BUF]; - uint32_t timeout_msec; - uint32_t buf_size; - char buf[0]; /* Variable buffer size - must be last field */ -} __attribute__((packed)); - - -#endif /* _SPCOM_H_ */ diff --git a/sdm710/original-kernel-headers/linux/v4l2-controls.h b/sdm710/original-kernel-headers/linux/v4l2-controls.h deleted file mode 100644 index d14cd8fa..00000000 --- a/sdm710/original-kernel-headers/linux/v4l2-controls.h +++ /dev/null @@ -1,1696 +0,0 @@ -/* - * Video for Linux Two controls header file - * - * Copyright (C) 1999-2012 the contributors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Alternatively you can redistribute this file under the terms of the - * BSD license as stated below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. The names of its contributors may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * The contents of this header was split off from videodev2.h. All control - * definitions should be added to this header, which is included by - * videodev2.h. - */ - -#ifndef __LINUX_V4L2_CONTROLS_H -#define __LINUX_V4L2_CONTROLS_H - -/* Control classes */ -#define V4L2_CTRL_CLASS_USER 0x00980000 /* Old-style 'user' controls */ -#define V4L2_CTRL_CLASS_MPEG 0x00990000 /* MPEG-compression controls */ -#define V4L2_CTRL_CLASS_CAMERA 0x009a0000 /* Camera class controls */ -#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 /* FM Modulator controls */ -#define V4L2_CTRL_CLASS_FLASH 0x009c0000 /* Camera flash controls */ -#define V4L2_CTRL_CLASS_JPEG 0x009d0000 /* JPEG-compression controls */ -#define V4L2_CTRL_CLASS_IMAGE_SOURCE 0x009e0000 /* Image source controls */ -#define V4L2_CTRL_CLASS_IMAGE_PROC 0x009f0000 /* Image processing controls */ -#define V4L2_CTRL_CLASS_DV 0x00a00000 /* Digital Video controls */ -#define V4L2_CTRL_CLASS_FM_RX 0x00a10000 /* FM Receiver controls */ -#define V4L2_CTRL_CLASS_RF_TUNER 0x00a20000 /* RF tuner controls */ -#define V4L2_CTRL_CLASS_DETECT 0x00a30000 /* Detection controls */ - -/* User-class control IDs */ - -#define V4L2_CID_BASE (V4L2_CTRL_CLASS_USER | 0x900) -#define V4L2_CID_USER_BASE V4L2_CID_BASE -#define V4L2_CID_USER_CLASS (V4L2_CTRL_CLASS_USER | 1) -#define V4L2_CID_BRIGHTNESS (V4L2_CID_BASE+0) -#define V4L2_CID_CONTRAST (V4L2_CID_BASE+1) -#define V4L2_CID_SATURATION (V4L2_CID_BASE+2) -#define V4L2_CID_HUE (V4L2_CID_BASE+3) -#define V4L2_CID_AUDIO_VOLUME (V4L2_CID_BASE+5) -#define V4L2_CID_AUDIO_BALANCE (V4L2_CID_BASE+6) -#define V4L2_CID_AUDIO_BASS (V4L2_CID_BASE+7) -#define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE+8) -#define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE+9) -#define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE+10) -#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11) /* Deprecated */ -#define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE+12) -#define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE+13) -#define V4L2_CID_RED_BALANCE (V4L2_CID_BASE+14) -#define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE+15) -#define V4L2_CID_GAMMA (V4L2_CID_BASE+16) -#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) /* Deprecated */ -#define V4L2_CID_EXPOSURE (V4L2_CID_BASE+17) -#define V4L2_CID_AUTOGAIN (V4L2_CID_BASE+18) -#define V4L2_CID_GAIN (V4L2_CID_BASE+19) -#define V4L2_CID_HFLIP (V4L2_CID_BASE+20) -#define V4L2_CID_VFLIP (V4L2_CID_BASE+21) - -#define V4L2_CID_POWER_LINE_FREQUENCY (V4L2_CID_BASE+24) -enum v4l2_power_line_frequency { - V4L2_CID_POWER_LINE_FREQUENCY_DISABLED = 0, - V4L2_CID_POWER_LINE_FREQUENCY_50HZ = 1, - V4L2_CID_POWER_LINE_FREQUENCY_60HZ = 2, - V4L2_CID_POWER_LINE_FREQUENCY_AUTO = 3, -}; -#define V4L2_CID_HUE_AUTO (V4L2_CID_BASE+25) -#define V4L2_CID_WHITE_BALANCE_TEMPERATURE (V4L2_CID_BASE+26) -#define V4L2_CID_SHARPNESS (V4L2_CID_BASE+27) -#define V4L2_CID_BACKLIGHT_COMPENSATION (V4L2_CID_BASE+28) -#define V4L2_CID_CHROMA_AGC (V4L2_CID_BASE+29) -#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30) -#define V4L2_CID_COLORFX (V4L2_CID_BASE+31) -enum v4l2_colorfx { - V4L2_COLORFX_NONE = 0, - V4L2_COLORFX_BW = 1, - V4L2_COLORFX_SEPIA = 2, - V4L2_COLORFX_NEGATIVE = 3, - V4L2_COLORFX_EMBOSS = 4, - V4L2_COLORFX_SKETCH = 5, - V4L2_COLORFX_SKY_BLUE = 6, - V4L2_COLORFX_GRASS_GREEN = 7, - V4L2_COLORFX_SKIN_WHITEN = 8, - V4L2_COLORFX_VIVID = 9, - V4L2_COLORFX_AQUA = 10, - V4L2_COLORFX_ART_FREEZE = 11, - V4L2_COLORFX_SILHOUETTE = 12, - V4L2_COLORFX_SOLARIZATION = 13, - V4L2_COLORFX_ANTIQUE = 14, - V4L2_COLORFX_SET_CBCR = 15, -}; -#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32) -#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33) - -#define V4L2_CID_ROTATE (V4L2_CID_BASE+34) -#define V4L2_CID_BG_COLOR (V4L2_CID_BASE+35) - -#define V4L2_CID_CHROMA_GAIN (V4L2_CID_BASE+36) - -#define V4L2_CID_ILLUMINATORS_1 (V4L2_CID_BASE+37) -#define V4L2_CID_ILLUMINATORS_2 (V4L2_CID_BASE+38) - -#define V4L2_CID_MIN_BUFFERS_FOR_CAPTURE (V4L2_CID_BASE+39) -#define V4L2_CID_MIN_BUFFERS_FOR_OUTPUT (V4L2_CID_BASE+40) - -#define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41) -#define V4L2_CID_COLORFX_CBCR (V4L2_CID_BASE+42) - -/* last CID + 1 */ -#define V4L2_CID_LASTP1 (V4L2_CID_BASE+43) - -/* USER-class private control IDs */ - -/* The base for the meye driver controls. See linux/meye.h for the list - * of controls. We reserve 16 controls for this driver. */ -#define V4L2_CID_USER_MEYE_BASE (V4L2_CID_USER_BASE + 0x1000) - -/* The base for the bttv driver controls. - * We reserve 32 controls for this driver. */ -#define V4L2_CID_USER_BTTV_BASE (V4L2_CID_USER_BASE + 0x1010) - - -/* The base for the s2255 driver controls. - * We reserve 16 controls for this driver. */ -#define V4L2_CID_USER_S2255_BASE (V4L2_CID_USER_BASE + 0x1030) - -/* - * The base for the si476x driver controls. See include/media/drv-intf/si476x.h - * for the list of controls. Total of 16 controls is reserved for this driver - */ -#define V4L2_CID_USER_SI476X_BASE (V4L2_CID_USER_BASE + 0x1040) - -/* The base for the TI VPE driver controls. Total of 16 controls is reserved for - * this driver */ -#define V4L2_CID_USER_TI_VPE_BASE (V4L2_CID_USER_BASE + 0x1050) - -/* The base for the saa7134 driver controls. - * We reserve 16 controls for this driver. */ -#define V4L2_CID_USER_SAA7134_BASE (V4L2_CID_USER_BASE + 0x1060) - -/* The base for the adv7180 driver controls. - * We reserve 16 controls for this driver. */ -#define V4L2_CID_USER_ADV7180_BASE (V4L2_CID_USER_BASE + 0x1070) - -/* The base for the tc358743 driver controls. - * We reserve 16 controls for this driver. */ -#define V4L2_CID_USER_TC358743_BASE (V4L2_CID_USER_BASE + 0x1080) - -/* MPEG-class control IDs */ -/* The MPEG controls are applicable to all codec controls - * and the 'MPEG' part of the define is historical */ - -#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900) -#define V4L2_CID_MPEG_CLASS (V4L2_CTRL_CLASS_MPEG | 1) - -/* MPEG streams, specific to multiplexed streams */ -#define V4L2_CID_MPEG_STREAM_TYPE (V4L2_CID_MPEG_BASE+0) -enum v4l2_mpeg_stream_type { - V4L2_MPEG_STREAM_TYPE_MPEG2_PS = 0, /* MPEG-2 program stream */ - V4L2_MPEG_STREAM_TYPE_MPEG2_TS = 1, /* MPEG-2 transport stream */ - V4L2_MPEG_STREAM_TYPE_MPEG1_SS = 2, /* MPEG-1 system stream */ - V4L2_MPEG_STREAM_TYPE_MPEG2_DVD = 3, /* MPEG-2 DVD-compatible stream */ - V4L2_MPEG_STREAM_TYPE_MPEG1_VCD = 4, /* MPEG-1 VCD-compatible stream */ - V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD = 5, /* MPEG-2 SVCD-compatible stream */ -}; -#define V4L2_CID_MPEG_STREAM_PID_PMT (V4L2_CID_MPEG_BASE+1) -#define V4L2_CID_MPEG_STREAM_PID_AUDIO (V4L2_CID_MPEG_BASE+2) -#define V4L2_CID_MPEG_STREAM_PID_VIDEO (V4L2_CID_MPEG_BASE+3) -#define V4L2_CID_MPEG_STREAM_PID_PCR (V4L2_CID_MPEG_BASE+4) -#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO (V4L2_CID_MPEG_BASE+5) -#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO (V4L2_CID_MPEG_BASE+6) -#define V4L2_CID_MPEG_STREAM_VBI_FMT (V4L2_CID_MPEG_BASE+7) -enum v4l2_mpeg_stream_vbi_fmt { - V4L2_MPEG_STREAM_VBI_FMT_NONE = 0, /* No VBI in the MPEG stream */ - V4L2_MPEG_STREAM_VBI_FMT_IVTV = 1, /* VBI in private packets, IVTV format */ -}; - -/* MPEG audio controls specific to multiplexed streams */ -#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ (V4L2_CID_MPEG_BASE+100) -enum v4l2_mpeg_audio_sampling_freq { - V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100 = 0, - V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000 = 1, - V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000 = 2, -}; -#define V4L2_CID_MPEG_AUDIO_ENCODING (V4L2_CID_MPEG_BASE+101) -enum v4l2_mpeg_audio_encoding { - V4L2_MPEG_AUDIO_ENCODING_LAYER_1 = 0, - V4L2_MPEG_AUDIO_ENCODING_LAYER_2 = 1, - V4L2_MPEG_AUDIO_ENCODING_LAYER_3 = 2, - V4L2_MPEG_AUDIO_ENCODING_AAC = 3, - V4L2_MPEG_AUDIO_ENCODING_AC3 = 4, -}; -#define V4L2_CID_MPEG_AUDIO_L1_BITRATE (V4L2_CID_MPEG_BASE+102) -enum v4l2_mpeg_audio_l1_bitrate { - V4L2_MPEG_AUDIO_L1_BITRATE_32K = 0, - V4L2_MPEG_AUDIO_L1_BITRATE_64K = 1, - V4L2_MPEG_AUDIO_L1_BITRATE_96K = 2, - V4L2_MPEG_AUDIO_L1_BITRATE_128K = 3, - V4L2_MPEG_AUDIO_L1_BITRATE_160K = 4, - V4L2_MPEG_AUDIO_L1_BITRATE_192K = 5, - V4L2_MPEG_AUDIO_L1_BITRATE_224K = 6, - V4L2_MPEG_AUDIO_L1_BITRATE_256K = 7, - V4L2_MPEG_AUDIO_L1_BITRATE_288K = 8, - V4L2_MPEG_AUDIO_L1_BITRATE_320K = 9, - V4L2_MPEG_AUDIO_L1_BITRATE_352K = 10, - V4L2_MPEG_AUDIO_L1_BITRATE_384K = 11, - V4L2_MPEG_AUDIO_L1_BITRATE_416K = 12, - V4L2_MPEG_AUDIO_L1_BITRATE_448K = 13, -}; -#define V4L2_CID_MPEG_AUDIO_L2_BITRATE (V4L2_CID_MPEG_BASE+103) -enum v4l2_mpeg_audio_l2_bitrate { - V4L2_MPEG_AUDIO_L2_BITRATE_32K = 0, - V4L2_MPEG_AUDIO_L2_BITRATE_48K = 1, - V4L2_MPEG_AUDIO_L2_BITRATE_56K = 2, - V4L2_MPEG_AUDIO_L2_BITRATE_64K = 3, - V4L2_MPEG_AUDIO_L2_BITRATE_80K = 4, - V4L2_MPEG_AUDIO_L2_BITRATE_96K = 5, - V4L2_MPEG_AUDIO_L2_BITRATE_112K = 6, - V4L2_MPEG_AUDIO_L2_BITRATE_128K = 7, - V4L2_MPEG_AUDIO_L2_BITRATE_160K = 8, - V4L2_MPEG_AUDIO_L2_BITRATE_192K = 9, - V4L2_MPEG_AUDIO_L2_BITRATE_224K = 10, - V4L2_MPEG_AUDIO_L2_BITRATE_256K = 11, - V4L2_MPEG_AUDIO_L2_BITRATE_320K = 12, - V4L2_MPEG_AUDIO_L2_BITRATE_384K = 13, -}; -#define V4L2_CID_MPEG_AUDIO_L3_BITRATE (V4L2_CID_MPEG_BASE+104) -enum v4l2_mpeg_audio_l3_bitrate { - V4L2_MPEG_AUDIO_L3_BITRATE_32K = 0, - V4L2_MPEG_AUDIO_L3_BITRATE_40K = 1, - V4L2_MPEG_AUDIO_L3_BITRATE_48K = 2, - V4L2_MPEG_AUDIO_L3_BITRATE_56K = 3, - V4L2_MPEG_AUDIO_L3_BITRATE_64K = 4, - V4L2_MPEG_AUDIO_L3_BITRATE_80K = 5, - V4L2_MPEG_AUDIO_L3_BITRATE_96K = 6, - V4L2_MPEG_AUDIO_L3_BITRATE_112K = 7, - V4L2_MPEG_AUDIO_L3_BITRATE_128K = 8, - V4L2_MPEG_AUDIO_L3_BITRATE_160K = 9, - V4L2_MPEG_AUDIO_L3_BITRATE_192K = 10, - V4L2_MPEG_AUDIO_L3_BITRATE_224K = 11, - V4L2_MPEG_AUDIO_L3_BITRATE_256K = 12, - V4L2_MPEG_AUDIO_L3_BITRATE_320K = 13, -}; -#define V4L2_CID_MPEG_AUDIO_MODE (V4L2_CID_MPEG_BASE+105) -enum v4l2_mpeg_audio_mode { - V4L2_MPEG_AUDIO_MODE_STEREO = 0, - V4L2_MPEG_AUDIO_MODE_JOINT_STEREO = 1, - V4L2_MPEG_AUDIO_MODE_DUAL = 2, - V4L2_MPEG_AUDIO_MODE_MONO = 3, -}; -#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION (V4L2_CID_MPEG_BASE+106) -enum v4l2_mpeg_audio_mode_extension { - V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4 = 0, - V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8 = 1, - V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12 = 2, - V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16 = 3, -}; -#define V4L2_CID_MPEG_AUDIO_EMPHASIS (V4L2_CID_MPEG_BASE+107) -enum v4l2_mpeg_audio_emphasis { - V4L2_MPEG_AUDIO_EMPHASIS_NONE = 0, - V4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS = 1, - V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17 = 2, -}; -#define V4L2_CID_MPEG_AUDIO_CRC (V4L2_CID_MPEG_BASE+108) -enum v4l2_mpeg_audio_crc { - V4L2_MPEG_AUDIO_CRC_NONE = 0, - V4L2_MPEG_AUDIO_CRC_CRC16 = 1, -}; -#define V4L2_CID_MPEG_AUDIO_MUTE (V4L2_CID_MPEG_BASE+109) -#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE (V4L2_CID_MPEG_BASE+110) -#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE (V4L2_CID_MPEG_BASE+111) -enum v4l2_mpeg_audio_ac3_bitrate { - V4L2_MPEG_AUDIO_AC3_BITRATE_32K = 0, - V4L2_MPEG_AUDIO_AC3_BITRATE_40K = 1, - V4L2_MPEG_AUDIO_AC3_BITRATE_48K = 2, - V4L2_MPEG_AUDIO_AC3_BITRATE_56K = 3, - V4L2_MPEG_AUDIO_AC3_BITRATE_64K = 4, - V4L2_MPEG_AUDIO_AC3_BITRATE_80K = 5, - V4L2_MPEG_AUDIO_AC3_BITRATE_96K = 6, - V4L2_MPEG_AUDIO_AC3_BITRATE_112K = 7, - V4L2_MPEG_AUDIO_AC3_BITRATE_128K = 8, - V4L2_MPEG_AUDIO_AC3_BITRATE_160K = 9, - V4L2_MPEG_AUDIO_AC3_BITRATE_192K = 10, - V4L2_MPEG_AUDIO_AC3_BITRATE_224K = 11, - V4L2_MPEG_AUDIO_AC3_BITRATE_256K = 12, - V4L2_MPEG_AUDIO_AC3_BITRATE_320K = 13, - V4L2_MPEG_AUDIO_AC3_BITRATE_384K = 14, - V4L2_MPEG_AUDIO_AC3_BITRATE_448K = 15, - V4L2_MPEG_AUDIO_AC3_BITRATE_512K = 16, - V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17, - V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18, -}; -#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK (V4L2_CID_MPEG_BASE+112) -enum v4l2_mpeg_audio_dec_playback { - V4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO = 0, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO = 1, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_LEFT = 2, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_RIGHT = 3, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO = 4, - V4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO = 5, -}; -#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_MPEG_BASE+113) - -/* MPEG video controls specific to multiplexed streams */ -#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE+200) -enum v4l2_mpeg_video_encoding { - V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0, - V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1, - V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2, -}; -#define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_MPEG_BASE+201) -enum v4l2_mpeg_video_aspect { - V4L2_MPEG_VIDEO_ASPECT_1x1 = 0, - V4L2_MPEG_VIDEO_ASPECT_4x3 = 1, - V4L2_MPEG_VIDEO_ASPECT_16x9 = 2, - V4L2_MPEG_VIDEO_ASPECT_221x100 = 3, -}; -#define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_MPEG_BASE+202) -#define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_MPEG_BASE+203) -#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_MPEG_BASE+204) -#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_MPEG_BASE+205) -#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_MPEG_BASE+206) -enum v4l2_mpeg_video_bitrate_mode { - V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0, - V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1, -}; -#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_MPEG_BASE+207) -#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_MPEG_BASE+208) -#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_MPEG_BASE+209) -#define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_MPEG_BASE+210) -#define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_MPEG_BASE+211) -#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (V4L2_CID_MPEG_BASE+212) -#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER (V4L2_CID_MPEG_BASE+213) -#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (V4L2_CID_MPEG_BASE+214) -#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE (V4L2_CID_MPEG_BASE+215) -#define V4L2_CID_MPEG_VIDEO_HEADER_MODE (V4L2_CID_MPEG_BASE+216) -enum v4l2_mpeg_video_header_mode { - V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0, - V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1, - V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_I_FRAME = 2, -}; -#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_MPEG_BASE+217) -#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_MPEG_BASE+218) -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES (V4L2_CID_MPEG_BASE+219) -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB (V4L2_CID_MPEG_BASE+220) -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE (V4L2_CID_MPEG_BASE+221) -enum v4l2_mpeg_video_multi_slice_mode { - V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE = 0, - V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB = 1, - V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2, - V4L2_MPEG_VIDEO_MULTI_SLICE_GOB = 3, -}; -#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE+222) -#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_MPEG_BASE+223) -#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE+224) -#define V4L2_CID_MPEG_VIDEO_VBV_DELAY (V4L2_CID_MPEG_BASE+225) -#define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER (V4L2_CID_MPEG_BASE+226) -#define V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE (V4L2_CID_MPEG_BASE+227) -#define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE (V4L2_CID_MPEG_BASE+228) -#define V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME (V4L2_CID_MPEG_BASE+229) - -#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300) -#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301) -#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_MPEG_BASE+302) -#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP (V4L2_CID_MPEG_BASE+303) -#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP (V4L2_CID_MPEG_BASE+304) -#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_MPEG_BASE+350) -#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP (V4L2_CID_MPEG_BASE+351) -#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP (V4L2_CID_MPEG_BASE+352) -#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP (V4L2_CID_MPEG_BASE+353) -#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_MPEG_BASE+354) -#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (V4L2_CID_MPEG_BASE+355) -#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE (V4L2_CID_MPEG_BASE+356) -#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE (V4L2_CID_MPEG_BASE+357) -enum v4l2_mpeg_video_h264_entropy_mode { - V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC = 0, - V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC = 1, -}; -#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_MPEG_BASE+358) -#define V4L2_CID_MPEG_VIDEO_H264_LEVEL (V4L2_CID_MPEG_BASE+359) -enum v4l2_mpeg_video_h264_level { - V4L2_MPEG_VIDEO_H264_LEVEL_1_0 = 0, - V4L2_MPEG_VIDEO_H264_LEVEL_1B = 1, - V4L2_MPEG_VIDEO_H264_LEVEL_1_1 = 2, - V4L2_MPEG_VIDEO_H264_LEVEL_1_2 = 3, - V4L2_MPEG_VIDEO_H264_LEVEL_1_3 = 4, - V4L2_MPEG_VIDEO_H264_LEVEL_2_0 = 5, - V4L2_MPEG_VIDEO_H264_LEVEL_2_1 = 6, - V4L2_MPEG_VIDEO_H264_LEVEL_2_2 = 7, - V4L2_MPEG_VIDEO_H264_LEVEL_3_0 = 8, - V4L2_MPEG_VIDEO_H264_LEVEL_3_1 = 9, - V4L2_MPEG_VIDEO_H264_LEVEL_3_2 = 10, - V4L2_MPEG_VIDEO_H264_LEVEL_4_0 = 11, - V4L2_MPEG_VIDEO_H264_LEVEL_4_1 = 12, - V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13, - V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14, - V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15, - V4L2_MPEG_VIDEO_H264_LEVEL_5_2 = 16, -#define V4L2_MPEG_VIDEO_H264_LEVEL_UNKNOWN \ - V4L2_MPEG_VIDEO_H264_LEVEL_UNKNOWN - V4L2_MPEG_VIDEO_H264_LEVEL_UNKNOWN = 17, -}; -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE+360) -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_MPEG_BASE+361) -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE (V4L2_CID_MPEG_BASE+362) -enum v4l2_mpeg_video_h264_loop_filter_mode { - V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED = 0, - V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED = 1, - V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY = 2, -}; -#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_MPEG_BASE+363) -enum v4l2_mpeg_video_h264_profile { - V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE = 0, - V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE = 1, - V4L2_MPEG_VIDEO_H264_PROFILE_MAIN = 2, - V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED = 3, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH = 4, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10 = 5, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422 = 6, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE = 7, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10_INTRA = 8, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422_INTRA = 9, - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_INTRA = 10, - V4L2_MPEG_VIDEO_H264_PROFILE_CAVLC_444_INTRA = 11, - V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_BASELINE = 12, - V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH = 13, - V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14, - V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15, - V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16, - V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH = 17, -}; -#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+364) -#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE+365) -#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (V4L2_CID_MPEG_BASE+366) -#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC (V4L2_CID_MPEG_BASE+367) -enum v4l2_mpeg_video_h264_vui_sar_idc { - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED = 0, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 = 1, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 = 2, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 = 3, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 = 4, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 = 5, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 = 6, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 = 7, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 = 8, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 = 9, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 = 10, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 = 11, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 = 12, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 = 13, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 = 14, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 = 15, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 = 16, - V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED = 17, -}; -#define V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING (V4L2_CID_MPEG_BASE+368) -#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0 (V4L2_CID_MPEG_BASE+369) -#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE (V4L2_CID_MPEG_BASE+370) -enum v4l2_mpeg_video_h264_sei_fp_arrangement_type { - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_CHECKERBOARD = 0, - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_COLUMN = 1, - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_ROW = 2, - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE = 3, - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TOP_BOTTOM = 4, - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TEMPORAL = 5, -}; -#define V4L2_CID_MPEG_VIDEO_H264_FMO (V4L2_CID_MPEG_BASE+371) -#define V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE (V4L2_CID_MPEG_BASE+372) -enum v4l2_mpeg_video_h264_fmo_map_type { - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES = 0, - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES = 1, - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_FOREGROUND_WITH_LEFT_OVER = 2, - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_BOX_OUT = 3, - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN = 4, - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN = 5, - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_EXPLICIT = 6, -}; -#define V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP (V4L2_CID_MPEG_BASE+373) -#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION (V4L2_CID_MPEG_BASE+374) -enum v4l2_mpeg_video_h264_fmo_change_dir { - V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT = 0, - V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_LEFT = 1, -}; -#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE (V4L2_CID_MPEG_BASE+375) -#define V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH (V4L2_CID_MPEG_BASE+376) -#define V4L2_CID_MPEG_VIDEO_H264_ASO (V4L2_CID_MPEG_BASE+377) -#define V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER (V4L2_CID_MPEG_BASE+378) -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING (V4L2_CID_MPEG_BASE+379) -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE (V4L2_CID_MPEG_BASE+380) -enum v4l2_mpeg_video_h264_hierarchical_coding_type { - V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B = 0, - V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P = 1, -}; -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER (V4L2_CID_MPEG_BASE+381) -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_MPEG_BASE+382) -#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) -#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) -#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) -#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_MPEG_BASE+403) -#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_MPEG_BASE+404) -#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_MPEG_BASE+405) -enum v4l2_mpeg_video_mpeg4_level { - V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 = 0, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 = 2, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 = 3, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 = 4, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B = 5, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 = 6, - V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 = 7, -}; -#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_MPEG_BASE+406) -enum v4l2_mpeg_video_mpeg4_profile { - V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE = 0, - V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE = 1, - V4L2_MPEG_VIDEO_MPEG4_PROFILE_CORE = 2, - V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE = 3, - V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY = 4, -}; -#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_MPEG_BASE+407) - -/* Control IDs for VP8 streams - * Although VP8 is not part of MPEG we add these controls to the MPEG class - * as that class is already handling other video compression standards - */ -#define V4L2_CID_MPEG_VIDEO_VPX_NUM_PARTITIONS (V4L2_CID_MPEG_BASE+500) -enum v4l2_vp8_num_partitions { - V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION = 0, - V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS = 1, - V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS = 2, - V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS = 3, -}; -#define V4L2_CID_MPEG_VIDEO_VPX_IMD_DISABLE_4X4 (V4L2_CID_MPEG_BASE+501) -#define V4L2_CID_MPEG_VIDEO_VPX_NUM_REF_FRAMES (V4L2_CID_MPEG_BASE+502) -enum v4l2_vp8_num_ref_frames { - V4L2_CID_MPEG_VIDEO_VPX_1_REF_FRAME = 0, - V4L2_CID_MPEG_VIDEO_VPX_2_REF_FRAME = 1, - V4L2_CID_MPEG_VIDEO_VPX_3_REF_FRAME = 2, -}; -#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_LEVEL (V4L2_CID_MPEG_BASE+503) -#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_SHARPNESS (V4L2_CID_MPEG_BASE+504) -#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_REF_PERIOD (V4L2_CID_MPEG_BASE+505) -#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_SEL (V4L2_CID_MPEG_BASE+506) -enum v4l2_vp8_golden_frame_sel { - V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_PREV = 0, - V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_REF_PERIOD = 1, -}; -#define V4L2_CID_MPEG_VIDEO_VPX_MIN_QP (V4L2_CID_MPEG_BASE+507) -#define V4L2_CID_MPEG_VIDEO_VPX_MAX_QP (V4L2_CID_MPEG_BASE+508) -#define V4L2_CID_MPEG_VIDEO_VPX_I_FRAME_QP (V4L2_CID_MPEG_BASE+509) -#define V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP (V4L2_CID_MPEG_BASE+510) -#define V4L2_CID_MPEG_VIDEO_VPX_PROFILE (V4L2_CID_MPEG_BASE+511) - -/* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */ -#define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000) -#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+0) -enum v4l2_mpeg_cx2341x_video_spatial_filter_mode { - V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0, - V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO = 1, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+1) -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+2) -enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type { - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF = 0, - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT = 2, - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE = 3, - V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE = 4, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+3) -enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type { - V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF = 0, - V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR = 1, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+4) -enum v4l2_mpeg_cx2341x_video_temporal_filter_mode { - V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL = 0, - V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+5) -#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+6) -enum v4l2_mpeg_cx2341x_video_median_filter_type { - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF = 0, - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR = 1, - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_VERT = 2, - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3, - V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG = 4, -}; -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+7) -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+8) -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+9) -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+10) -#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_MPEG_CX2341X_BASE+11) - -/* MPEG-class control IDs specific to the Samsung MFC 5.1 driver as defined by V4L2 */ -#define V4L2_CID_MPEG_MFC51_BASE (V4L2_CTRL_CLASS_MPEG | 0x1100) - -#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (V4L2_CID_MPEG_MFC51_BASE+0) -#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE (V4L2_CID_MPEG_MFC51_BASE+1) -#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE (V4L2_CID_MPEG_MFC51_BASE+2) -enum v4l2_mpeg_mfc51_video_frame_skip_mode { - V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED = 0, - V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT = 1, - V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT = 2, -}; -#define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE (V4L2_CID_MPEG_MFC51_BASE+3) -enum v4l2_mpeg_mfc51_video_force_frame_type { - V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED = 0, - V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_I_FRAME = 1, - V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED = 2, -}; -#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING (V4L2_CID_MPEG_MFC51_BASE+4) -#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV (V4L2_CID_MPEG_MFC51_BASE+5) -#define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT (V4L2_CID_MPEG_MFC51_BASE+6) -#define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF (V4L2_CID_MPEG_MFC51_BASE+7) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY (V4L2_CID_MPEG_MFC51_BASE+50) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK (V4L2_CID_MPEG_MFC51_BASE+51) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH (V4L2_CID_MPEG_MFC51_BASE+52) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53) -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54) - -/* MPEG-class control IDs specific to the msm_vidc driver */ -#define V4L2_CID_MPEG_MSM_VIDC_BASE (V4L2_CTRL_CLASS_MPEG | 0x2000) - -#define V4L2_CID_MPEG_VIDC_VIDEO_PICTYPE_DEC_MODE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE+0) -enum v4l2_mpeg_vidc_video_pictype_dec_mode { - V4L2_MPEG_VIDC_VIDEO_PICTYPE_DECODE_OFF = 0, - V4L2_MPEG_VIDC_VIDEO_PICTYPE_DECODE_ON = 1, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_KEEP_ASPECT_RATIO \ - (V4L2_CID_MPEG_MSM_VIDC_BASE+1) - -#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE+2) -enum v4l2_mpeg_vidc_video_stream_format { - V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_STARTCODES = 0, - V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_NAL_PER_BUFFER = 1, - V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_BYTE_LENGTH = 2, - V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_TWO_BYTE_LENGTH = 3, - V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_FOUR_BYTE_LENGTH = 4, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_OUTPUT_ORDER (V4L2_CID_MPEG_MSM_VIDC_BASE+3) -enum v4l2_mpeg_vidc_video_output_order { - V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DISPLAY = 0, - V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DECODE = 1, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_RATE (V4L2_CID_MPEG_MSM_VIDC_BASE+4) -#define V4L2_CID_MPEG_VIDC_VIDEO_IDR_PERIOD (V4L2_CID_MPEG_MSM_VIDC_BASE+5) -#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+6) -#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+7) -#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_IFRAME (V4L2_CID_MPEG_MSM_VIDC_BASE+8) - -#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL (V4L2_CID_MPEG_MSM_VIDC_BASE+9) -enum v4l2_mpeg_vidc_video_rate_control { - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_OFF = 0, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_VFR = 1, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR = 2, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_VFR = 3, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_CFR = 4, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_CFR = 5, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_VFR = 6, - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CQ = 7, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_CFR \ - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_CFR -#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_VFR \ - V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_VFR - -#define V4L2_CID_MPEG_VIDC_VIDEO_ROTATION (V4L2_CID_MPEG_MSM_VIDC_BASE+10) -enum v4l2_mpeg_vidc_video_rotation { - V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_NONE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_90 = 1, - V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_180 = 2, - V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_270 = 3, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL \ - (V4L2_CID_MPEG_MSM_VIDC_BASE+11) -enum v4l2_mpeg_vidc_h264_cabac_model { - V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_0 = 0, - V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_1 = 1, - V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_2 = 2, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_MODE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE+12) -enum v4l2_mpeg_vidc_video_intra_refresh_mode { - V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_NONE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC = 1, - V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_RANDOM = 2, - V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_ADAPTIVE = 3, - V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC_ADAPTIVE = 4, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_IR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+13) - -#define V4L2_CID_MPEG_VIDC_VIDEO_AU_DELIMITER \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 14) -enum v4l2_mpeg_vidc_video_au_delimiter { - V4L2_MPEG_VIDC_VIDEO_AU_DELIMITER_DISABLED = 0, - V4L2_MPEG_VIDC_VIDEO_AU_DELIMITER_ENABLED = 1 -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 15) -enum v4l2_mpeg_vidc_video_sync_frame_decode { - V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_DISABLE = 0, - V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_ENABLE = 1 -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE (V4L2_CID_MPEG_MSM_VIDC_BASE+16) -#define V4L2_CID_MPEG_VIDC_VIDEO_EXTRADATA \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 17) -enum v4l2_mpeg_vidc_extradata { - V4L2_MPEG_VIDC_EXTRADATA_NONE = 0, - V4L2_MPEG_VIDC_EXTRADATA_MB_QUANTIZATION = 1, - V4L2_MPEG_VIDC_EXTRADATA_INTERLACE_VIDEO = 2, - V4L2_MPEG_VIDC_EXTRADATA_VC1_FRAMEDISP = 3, - V4L2_MPEG_VIDC_EXTRADATA_VC1_SEQDISP = 4, - V4L2_MPEG_VIDC_EXTRADATA_TIMESTAMP = 5, - V4L2_MPEG_VIDC_EXTRADATA_S3D_FRAME_PACKING = 6, - V4L2_MPEG_VIDC_EXTRADATA_FRAME_RATE = 7, - V4L2_MPEG_VIDC_EXTRADATA_PANSCAN_WINDOW = 8, - V4L2_MPEG_VIDC_EXTRADATA_RECOVERY_POINT_SEI = 9, - V4L2_MPEG_VIDC_EXTRADATA_MULTISLICE_INFO = 10, - V4L2_MPEG_VIDC_EXTRADATA_NUM_CONCEALED_MB = 11, - V4L2_MPEG_VIDC_EXTRADATA_METADATA_FILLER = 12, - V4L2_MPEG_VIDC_EXTRADATA_INPUT_CROP = 13, - V4L2_MPEG_VIDC_EXTRADATA_DIGITAL_ZOOM = 14, - V4L2_MPEG_VIDC_EXTRADATA_ASPECT_RATIO = 15, - V4L2_MPEG_VIDC_EXTRADATA_MPEG2_SEQDISP = 16, - V4L2_MPEG_VIDC_EXTRADATA_STREAM_USERDATA = 17, - V4L2_MPEG_VIDC_EXTRADATA_FRAME_QP = 18, - V4L2_MPEG_VIDC_EXTRADATA_FRAME_BITS_INFO = 19, - V4L2_MPEG_VIDC_EXTRADATA_LTR = 20, - V4L2_MPEG_VIDC_EXTRADATA_METADATA_MBI = 21, - V4L2_MPEG_VIDC_EXTRADATA_VQZIP_SEI = 22, - V4L2_MPEG_VIDC_EXTRADATA_YUV_STATS = 23, - V4L2_MPEG_VIDC_EXTRADATA_ROI_QP = 24, -#define V4L2_MPEG_VIDC_EXTRADATA_OUTPUT_CROP \ - V4L2_MPEG_VIDC_EXTRADATA_OUTPUT_CROP - V4L2_MPEG_VIDC_EXTRADATA_OUTPUT_CROP = 25, -#define V4L2_MPEG_VIDC_EXTRADATA_DISPLAY_COLOUR_SEI \ - V4L2_MPEG_VIDC_EXTRADATA_DISPLAY_COLOUR_SEI - V4L2_MPEG_VIDC_EXTRADATA_DISPLAY_COLOUR_SEI = 26, -#define V4L2_MPEG_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI \ - V4L2_MPEG_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI - V4L2_MPEG_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI = 27, -#define V4L2_MPEG_VIDC_EXTRADATA_PQ_INFO \ - V4L2_MPEG_VIDC_EXTRADATA_PQ_INFO - V4L2_MPEG_VIDC_EXTRADATA_PQ_INFO = 28, -#define V4L2_MPEG_VIDC_EXTRADATA_VUI_DISPLAY \ - V4L2_MPEG_VIDC_EXTRADATA_VUI_DISPLAY - V4L2_MPEG_VIDC_EXTRADATA_VUI_DISPLAY = 29, -#define V4L2_MPEG_VIDC_EXTRADATA_VPX_COLORSPACE \ - V4L2_MPEG_VIDC_EXTRADATA_VPX_COLORSPACE - V4L2_MPEG_VIDC_EXTRADATA_VPX_COLORSPACE = 30, -#define V4L2_MPEG_VIDC_EXTRADATA_UBWC_CR_STATS_INFO \ - V4L2_MPEG_VIDC_EXTRADATA_UBWC_CR_STATS_INFO - V4L2_MPEG_VIDC_EXTRADATA_UBWC_CR_STATS_INFO = 31, -#define V4L2_MPEG_VIDC_EXTRADATA_ENC_FRAME_QP \ - V4L2_MPEG_VIDC_EXTRADATA_ENC_FRAME_QP - V4L2_MPEG_VIDC_EXTRADATA_ENC_FRAME_QP = 32, -}; - -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_DELIVERY_MODE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 18) - -#define V4L2_CID_MPEG_VIDC_VIDEO_VUI_TIMING_INFO \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 19) -enum v4l2_mpeg_vidc_video_vui_timing_info { - V4L2_MPEG_VIDC_VIDEO_VUI_TIMING_INFO_DISABLED = 0, - V4L2_MPEG_VIDC_VIDEO_VUI_TIMING_INFO_ENABLED = 1 -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_PROFILE_LEVEL \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 20) -enum v4l2_mpeg_vidc_video_vp8_profile_level { - V4L2_MPEG_VIDC_VIDEO_VP8_UNUSED, - V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_0, - V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_1, - V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_2, - V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_3, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 21) -enum v4l2_mpeg_vidc_video_preserve_text_quality { - V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_DISABLED = 0, - V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_ENABLED = 1 -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_MODE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 22) -enum v4l2_mpeg_vidc_video_decoder_multi_stream { - V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_PRIMARY = 0, - V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_SECONDARY = 1, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE+23) -enum v4l2_mpeg_vidc_video_mpeg2_level { - V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_0 = 0, - V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_1 = 1, - V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_2 = 2, - V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_3 = 3, -}; -#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE+24) -enum v4l2_mpeg_vidc_video_mpeg2_profile { - V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SIMPLE = 0, - V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_MAIN = 1, - V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_422 = 2, - V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SNR_SCALABLE = 3, - V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SPATIAL_SCALABLE = 4, - V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_HIGH = 5, -}; - -enum v4l2_mpeg_vidc_video_mvc_layout { - V4L2_MPEG_VIDC_VIDEO_MVC_SEQUENTIAL = 0, - V4L2_MPEG_VIDC_VIDEO_MVC_TOP_BOTTOM = 1 -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_CONCEAL_COLOR \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 25) - -#define V4L2_CID_MPEG_VIDC_VIDEO_LTRMODE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 26) - -enum v4l2_mpeg_vidc_video_ltrmode { - V4L2_MPEG_VIDC_VIDEO_LTR_MODE_DISABLE = 0, - V4L2_MPEG_VIDC_VIDEO_LTR_MODE_MANUAL = 1, - V4L2_MPEG_VIDC_VIDEO_LTR_MODE_PERIODIC = 2 -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_LTRCOUNT \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 27) - -#define V4L2_CID_MPEG_VIDC_VIDEO_USELTRFRAME \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 28) - -#define V4L2_CID_MPEG_VIDC_VIDEO_MARKLTRFRAME \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 29) - -#define V4L2_CID_MPEG_VIDC_VIDEO_HIER_P_NUM_LAYERS \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 30) - -#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_OUTPUT \ - (V4L2_CID_MPEG_MSM_VIDC_BASE+31) -enum v4l2_mpeg_vidc_video_alloc_mode_type { - V4L2_MPEG_VIDC_VIDEO_STATIC = 0, - V4L2_MPEG_VIDC_VIDEO_RING = 1, - V4L2_MPEG_VIDC_VIDEO_DYNAMIC = 2, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_X_RANGE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 32) - -#define V4L2_CID_MPEG_VIDC_VIDEO_PFRAME_X_RANGE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 33) - -#define V4L2_CID_MPEG_VIDC_VIDEO_BFRAME_X_RANGE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 34) - -#define V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_Y_RANGE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 35) - -#define V4L2_CID_MPEG_VIDC_VIDEO_PFRAME_Y_RANGE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 36) - -#define V4L2_CID_MPEG_VIDC_VIDEO_BFRAME_Y_RANGE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 37) - -#define V4L2_CID_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 38) - -#define V4L2_CID_MPEG_VIDC_VIDEO_BUFFER_SIZE_LIMIT \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 39) - -enum vl42_mpeg_vidc_video_vpx_error_resilience { - V4L2_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE_DISABLED = 0, - V4L2_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE_ENABLED = 1, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_PROFILE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 40) -enum v4l2_mpeg_video_hevc_profile { - V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN = 0, - V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN10 = 1, - V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN_STILL_PIC = 2, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_TIER_LEVEL \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 41) -enum v4l2_mpeg_video_hevc_level { - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_1 = 0, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_1 = 1, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_2 = 2, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_2 = 3, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_2_1 = 4, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_2_1 = 5, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_3 = 6, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_3 = 7, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_3_1 = 8, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_3_1 = 9, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_4 = 10, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_4 = 11, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_4_1 = 12, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_4_1 = 13, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5 = 14, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5 = 15, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5_1 = 16, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5_1 = 17, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5_2 = 18, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5_2 = 19, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6 = 20, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6 = 21, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6_1 = 22, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6_1 = 23, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6_2 = 24, - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6_2 = 25, -#define V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_UNKNOWN \ - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_UNKNOWN - V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_UNKNOWN = 26, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_HIER_B_NUM_LAYERS \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 42) - -#define V4L2_CID_MPEG_VIDC_VIDEO_HYBRID_HIERP_MODE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 43) - -#define V4L2_CID_MPEG_VIDC_VIDEO_DPB_COLOR_FORMAT \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 44) - -enum v4l2_mpeg_vidc_video_dpb_color_format { - V4L2_MPEG_VIDC_VIDEO_DPB_COLOR_FMT_NONE = 0, - V4L2_MPEG_VIDC_VIDEO_DPB_COLOR_FMT_UBWC = 1, - V4L2_MPEG_VIDC_VIDEO_DPB_COLOR_FMT_TP10_UBWC = 2 -}; - -#define V4L2_CID_VIDC_QBUF_MODE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 45) -enum v4l2_vidc_qbuf_mode { - V4L2_VIDC_QBUF_STANDARD = 0, - V4L2_VIDC_QBUF_BATCHED = 1, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_MAX_HIERP_LAYERS \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 46) - -#define V4L2_CID_MPEG_VIDC_VIDEO_BASELAYER_ID \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 47) - -#define V4L2_CID_MPEG_VIDC_VENC_PARAM_SAR_WIDTH \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 48) - -#define V4L2_CID_MPEG_VIDC_VENC_PARAM_SAR_HEIGHT \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 49) - -#define V4L2_CID_MPEG_VIDC_VIDEO_VQZIP_SEI \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 50) - -enum v4l2_mpeg_vidc_video_vqzip_sei_enable { - V4L2_CID_MPEG_VIDC_VIDEO_VQZIP_SEI_DISABLE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_VQZIP_SEI_ENABLE = 1 -}; - -#define V4L2_CID_MPEG_VIDC_VENC_PARAM_LAYER_BITRATE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 51) - -#define V4L2_CID_MPEG_VIDC_VIDEO_PRIORITY \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 52) - -enum v4l2_mpeg_vidc_video_priority { - V4L2_MPEG_VIDC_VIDEO_PRIORITY_REALTIME_ENABLE = 0, - V4L2_MPEG_VIDC_VIDEO_PRIORITY_REALTIME_DISABLE = 1, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_OPERATING_RATE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 53) - -#define V4L2_CID_MPEG_VIDC_VIDEO_VENC_BITRATE_TYPE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 54) - -enum v4l2_mpeg_vidc_video_venc_bitrate_type_enable { - V4L2_CID_MPEG_VIDC_VIDEO_VENC_BITRATE_DISABLE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_VENC_BITRATE_ENABLE = 1 -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_VPE_CSC \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 55) - -enum v4l2_cid_mpeg_vidc_video_vpe_csc_type_enable { - V4L2_CID_MPEG_VIDC_VIDEO_VPE_CSC_DISABLE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_VPE_CSC_ENABLE = 1 -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_LOWLATENCY_MODE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 56) - -enum v4l2_mpeg_vidc_video_lowlatency_mode { - V4L2_CID_MPEG_VIDC_VIDEO_LOWLATENCY_DISABLE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_LOWLATENCY_ENABLE = 1, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_BLUR_WIDTH \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 57) - -#define V4L2_CID_MPEG_VIDC_VIDEO_BLUR_HEIGHT \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 58) - -#define V4L2_CID_MPEG_VIDC_VIDEO_H264_TRANSFORM_8x8 \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 59) -enum v4l2_mpeg_vidc_video_h264_transform_8x8 { - V4L2_MPEG_VIDC_VIDEO_H264_TRANSFORM_8x8_DISABLE = 0, - V4L2_MPEG_VIDC_VIDEO_H264_TRANSFORM_8x8_ENABLE = 1, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_COLOR_SPACE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 60) - -#define V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 61) - -enum v4l2_cid_mpeg_vidc_video_full_range { - V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE_DISABLE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE_ENABLE = 1, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_TRANSFER_CHARS \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 62) - -#define V4L2_CID_MPEG_VIDC_VIDEO_MATRIX_COEFFS \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 63) - -#define V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_TYPE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 64) - -#define V4L2_CID_MPEG_VIDC_VIDEO_LAYER_ID \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 65) - -#define V4L2_CID_MPEG_VIDC_VIDEO_VP9_PROFILE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 66) -enum v4l2_mpeg_vidc_video_vp9_profile { - V4L2_MPEG_VIDC_VIDEO_VP9_PROFILE_UNUSED = 0, - V4L2_MPEG_VIDC_VIDEO_VP9_PROFILE_P0 = 1, - V4L2_MPEG_VIDC_VIDEO_VP9_PROFILE_P2_10 = 2, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_VP9_LEVEL \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 67) -enum v4l2_mpeg_vidc_video_vp9_level { - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_UNUSED = 0, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_1 = 1, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_11 = 2, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_2 = 3, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_21 = 4, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_3 = 5, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_31 = 6, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_4 = 7, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_41 = 8, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_5 = 9, - V4L2_MPEG_VIDC_VIDEO_VP9_LEVEL_51 = 10, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_MB_ERROR_MAP_REPORTING \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 68) -#define V4L2_CID_MPEG_VIDC_VIDEO_CONTINUE_DATA_TRANSFER \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 69) - -#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_INPUT \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 70) - -#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_ASSEMBLY \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 71) -enum v4l2_mpeg_vidc_video_assembly { - V4L2_MPEG_VIDC_FRAME_ASSEMBLY_DISABLE = 0, - V4L2_MPEG_VIDC_FRAME_ASSEMBLY_ENABLE = 1, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_H263_PROFILE\ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 72) -enum v4l2_mpeg_vidc_video_h263_profile { - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BASELINE = 0, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_H320CODING = 1, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BACKWARDCOMPATIBLE = 2, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV2 = 3, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV3 = 4, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHCOMPRESSION = 5, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERNET = 6, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERLACE = 7, - V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHLATENCY = 8, -}; - -#define V4L2_CID_MPEG_VIDEO_MIN_QP_PACKED \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 97) -#define V4L2_CID_MPEG_VIDEO_MAX_QP_PACKED \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 98) -#define V4L2_CID_MPEG_VIDC_VIDEO_I_FRAME_QP \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 99) -#define V4L2_CID_MPEG_VIDC_VIDEO_P_FRAME_QP \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 100) -#define V4L2_CID_MPEG_VIDC_VIDEO_B_FRAME_QP \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 101) -#define V4L2_CID_MPEG_VIDC_VIDEO_I_FRAME_QP_MIN \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 102) -#define V4L2_CID_MPEG_VIDC_VIDEO_P_FRAME_QP_MIN \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 103) -#define V4L2_CID_MPEG_VIDC_VIDEO_B_FRAME_QP_MIN \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 104) -#define V4L2_CID_MPEG_VIDC_VIDEO_I_FRAME_QP_MAX \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 105) -#define V4L2_CID_MPEG_VIDC_VIDEO_P_FRAME_QP_MAX \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 106) -#define V4L2_CID_MPEG_VIDC_VIDEO_B_FRAME_QP_MAX \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 107) -#define V4L2_CID_MPEG_VIDC_VIDEO_QP_MASK \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 108) - -enum v4l2_mpeg_vidc_video_venc_iframesize_type { - V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_DEFAULT, - V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_MEDIUM, - V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_HUGE, - V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_UNLIMITED, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_CONCEAL_COLOR_8BIT \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 109) -#define V4L2_CID_MPEG_VIDC_VIDEO_CONCEAL_COLOR_10BIT \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 110) - -#define V4L2_CID_MPEG_VIDC_VIDEO_TME_PROFILE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 111) - -enum v4l2_mpeg_vidc_video_tme_profile { - V4L2_MPEG_VIDC_VIDEO_TME_PROFILE_0 = 0, - V4L2_MPEG_VIDC_VIDEO_TME_PROFILE_1 = 1, - V4L2_MPEG_VIDC_VIDEO_TME_PROFILE_2 = 2, - V4L2_MPEG_VIDC_VIDEO_TME_PROFILE_3 = 3, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_TME_LEVEL \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 112) - -enum v4l2_mpeg_vidc_video_tme_level { - V4L2_MPEG_VIDC_VIDEO_TME_LEVEL_INTEGER = 0, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_TME_PAYLOAD_VERSION \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 113) - -#define V4L2_CID_MPEG_VIDC_VIDEO_VPE_CSC_CUSTOM_MATRIX \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 114) - -#define V4L2_CID_MPEG_VIDC_VIDEO_FLIP (V4L2_CID_MPEG_MSM_VIDC_BASE + 115) -enum v4l2_mpeg_vidc_video_flip { - V4L2_CID_MPEG_VIDC_VIDEO_FLIP_NONE = 0, - V4L2_CID_MPEG_VIDC_VIDEO_FLIP_HORI = 1, - V4L2_CID_MPEG_VIDC_VIDEO_FLIP_VERT = 2, - V4L2_CID_MPEG_VIDC_VIDEO_FLIP_BOTH = 3, -}; - -/* HDR SEI INFO related control IDs and definitions*/ -#define V4L2_MPEG_VIDC_VENC_HDR_INFO_ENABLED 1 -#define V4L2_MPEG_VIDC_VENC_HDR_INFO_DISABLED 0 - -#define V4L2_CID_MPEG_VIDC_VENC_HDR_INFO \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 116) -#define V4L2_CID_MPEG_VIDC_VENC_RGB_PRIMARY_00 \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 117) -#define V4L2_CID_MPEG_VIDC_VENC_RGB_PRIMARY_01 \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 118) -#define V4L2_CID_MPEG_VIDC_VENC_RGB_PRIMARY_10 \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 119) -#define V4L2_CID_MPEG_VIDC_VENC_RGB_PRIMARY_11 \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 120) -#define V4L2_CID_MPEG_VIDC_VENC_RGB_PRIMARY_20 \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 121) -#define V4L2_CID_MPEG_VIDC_VENC_RGB_PRIMARY_21 \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 122) -#define V4L2_CID_MPEG_VIDC_VENC_WHITEPOINT_X \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 123) -#define V4L2_CID_MPEG_VIDC_VENC_WHITEPOINT_Y \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 124) -#define V4L2_CID_MPEG_VIDC_VENC_MAX_DISP_LUM \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 125) -#define V4L2_CID_MPEG_VIDC_VENC_MIN_DISP_LUM \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 126) -#define V4L2_CID_MPEG_VIDC_VENC_MAX_CLL \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 127) -#define V4L2_CID_MPEG_VIDC_VENC_MAX_FLL \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 128) - -#define V4L2_CID_MPEG_VIDC_SET_PERF_LEVEL \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 129) -enum v4l2_mpeg_vidc_perf_level { - V4L2_CID_MPEG_VIDC_PERF_LEVEL_NOMINAL = 0, - V4L2_CID_MPEG_VIDC_PERF_LEVEL_PERFORMANCE = 1, - V4L2_CID_MPEG_VIDC_PERF_LEVEL_TURBO = 2, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE + 130) -#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_REF (V4L2_CID_MPEG_MSM_VIDC_BASE + 131) -#define V4L2_CID_MPEG_VIDC_VIDEO_CIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE + 132) - -#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 135) - -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_GOB \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 136) - -#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 137) -enum v4l2_mpeg_vidc_video_h264_vui_bitstream_restrict { - V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_DISABLED = 0, - V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_ENABLED = 1 -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 138) -enum v4l2_mpeg_vidc_video_deinterlace { - V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE_DISABLED = 0, - V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE_ENABLED = 1 -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG4_TIME_RESOLUTION \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 139) - -#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_SEQ_HEADER \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 140) - -#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 141) -enum v4l2_mpeg_vidc_video_rate_control_timestamp_mode { - V4L2_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE_HONOR = 0, - V4L2_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE_IGNORE = 1, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 142) -enum vl42_mpeg_vidc_video_enable_initial_qp { - V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_IFRAME = 0x1, - V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_PFRAME = 0x2, - V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_BFRAME = 0x4, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_INITIAL_I_FRAME_QP \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 143) - -#define V4L2_CID_MPEG_VIDC_VIDEO_INITIAL_P_FRAME_QP \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 144) - -#define V4L2_CID_MPEG_VIDC_VIDEO_INITIAL_B_FRAME_QP \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 145) - -#define V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 146) - -#define V4L2_CID_MPEG_VIDC_VIDEO_PERF_MODE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 147) -enum v4l2_mpeg_vidc_video_perf_mode { - V4L2_MPEG_VIDC_VIDEO_PERF_MAX_QUALITY = 1, - V4L2_MPEG_VIDC_VIDEO_PERF_POWER_SAVE = 2 -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_MBI_STATISTICS_MODE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 148) - -#define V4L2_CID_MPEG_VIDC_VIDEO_CONFIG_QP \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 149) - -#define V4L2_CID_MPEG_VIDC_VIDEO_H264_PIC_ORDER_CNT \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 150) - -#define V4L2_CID_MPEG_VIDC_VIDEO_SCS_THRESHOLD \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 151) - -#define V4L2_CID_MPEG_VIDC_VIDEO_MVC_BUFFER_LAYOUT \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 152) - - -#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE_SCALING_THRESHOLD \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 153) - -#define V4L2_CID_MPEG_VIDC_VIDEO_NON_SECURE_OUTPUT2 \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 154) - -#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_MIN_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 155) -#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_MAX_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 156) - -#define V4L2_CID_MPEG_VIDC_VIDEO_H263_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 157) -enum v4l2_mpeg_vidc_video_h263_level { - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_1_0 = 0, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_2_0 = 1, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_3_0 = 2, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_0 = 3, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_5 = 4, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_5_0 = 5, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_6_0 = 6, - V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_7_0 = 7, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_POST_LOOP_DEBLOCKER_MODE \ - (V4L2_CID_MPEG_MSM_VIDC_BASE + 158) - - -#define V4L2_CID_MPEG_VIDC_VIDEO_DIVX_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE+159) - -enum v4l2_mpeg_vidc_video_divx_format_type { - V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_4 = 0, - V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_5 = 1, - V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_6 = 2, -}; - -#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_QUALITY \ - (V4L2_CID_MPEG_MSM_VIDC_BASE+160) - -#define V4L2_CID_MPEG_VIDC_IMG_GRID_DIMENSION \ - (V4L2_CID_MPEG_MSM_VIDC_BASE+161) - -enum v4l2_mpeg_vidc_video_mbi_statistics_mode { - V4L2_CID_MPEG_VIDC_VIDEO_MBI_MODE_DEFAULT = 0, - V4L2_CID_MPEG_VIDC_VIDEO_MBI_MODE_1 = 1, - V4L2_CID_MPEG_VIDC_VIDEO_MBI_MODE_2 = 2, - V4L2_CID_MPEG_VIDC_VIDEO_MBI_MODE_3 = 3, -}; - -enum vl42_mpeg_vidc_video_h264_svc_nal { - V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_DISABLED = 0, - V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_ENABLED = 1, -}; - -enum v4l2_mpeg_vidc_video_h264_vui_timing_info { - V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_DISABLED = 0, - V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_ENABLED = 1 -}; - -/* Camera class control IDs */ - -#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900) -#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1) - -#define V4L2_CID_EXPOSURE_AUTO (V4L2_CID_CAMERA_CLASS_BASE+1) -enum v4l2_exposure_auto_type { - V4L2_EXPOSURE_AUTO = 0, - V4L2_EXPOSURE_MANUAL = 1, - V4L2_EXPOSURE_SHUTTER_PRIORITY = 2, - V4L2_EXPOSURE_APERTURE_PRIORITY = 3 -}; -#define V4L2_CID_EXPOSURE_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+2) -#define V4L2_CID_EXPOSURE_AUTO_PRIORITY (V4L2_CID_CAMERA_CLASS_BASE+3) - -#define V4L2_CID_PAN_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+4) -#define V4L2_CID_TILT_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+5) -#define V4L2_CID_PAN_RESET (V4L2_CID_CAMERA_CLASS_BASE+6) -#define V4L2_CID_TILT_RESET (V4L2_CID_CAMERA_CLASS_BASE+7) - -#define V4L2_CID_PAN_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+8) -#define V4L2_CID_TILT_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+9) - -#define V4L2_CID_FOCUS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+10) -#define V4L2_CID_FOCUS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+11) -#define V4L2_CID_FOCUS_AUTO (V4L2_CID_CAMERA_CLASS_BASE+12) - -#define V4L2_CID_ZOOM_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+13) -#define V4L2_CID_ZOOM_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+14) -#define V4L2_CID_ZOOM_CONTINUOUS (V4L2_CID_CAMERA_CLASS_BASE+15) - -#define V4L2_CID_PRIVACY (V4L2_CID_CAMERA_CLASS_BASE+16) - -#define V4L2_CID_IRIS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+17) -#define V4L2_CID_IRIS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+18) - -#define V4L2_CID_AUTO_EXPOSURE_BIAS (V4L2_CID_CAMERA_CLASS_BASE+19) - -#define V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE (V4L2_CID_CAMERA_CLASS_BASE+20) -enum v4l2_auto_n_preset_white_balance { - V4L2_WHITE_BALANCE_MANUAL = 0, - V4L2_WHITE_BALANCE_AUTO = 1, - V4L2_WHITE_BALANCE_INCANDESCENT = 2, - V4L2_WHITE_BALANCE_FLUORESCENT = 3, - V4L2_WHITE_BALANCE_FLUORESCENT_H = 4, - V4L2_WHITE_BALANCE_HORIZON = 5, - V4L2_WHITE_BALANCE_DAYLIGHT = 6, - V4L2_WHITE_BALANCE_FLASH = 7, - V4L2_WHITE_BALANCE_CLOUDY = 8, - V4L2_WHITE_BALANCE_SHADE = 9, -}; - -#define V4L2_CID_WIDE_DYNAMIC_RANGE (V4L2_CID_CAMERA_CLASS_BASE+21) -#define V4L2_CID_IMAGE_STABILIZATION (V4L2_CID_CAMERA_CLASS_BASE+22) - -#define V4L2_CID_ISO_SENSITIVITY (V4L2_CID_CAMERA_CLASS_BASE+23) -#define V4L2_CID_ISO_SENSITIVITY_AUTO (V4L2_CID_CAMERA_CLASS_BASE+24) -enum v4l2_iso_sensitivity_auto_type { - V4L2_ISO_SENSITIVITY_MANUAL = 0, - V4L2_ISO_SENSITIVITY_AUTO = 1, -}; - -#define V4L2_CID_EXPOSURE_METERING (V4L2_CID_CAMERA_CLASS_BASE+25) -enum v4l2_exposure_metering { - V4L2_EXPOSURE_METERING_AVERAGE = 0, - V4L2_EXPOSURE_METERING_CENTER_WEIGHTED = 1, - V4L2_EXPOSURE_METERING_SPOT = 2, - V4L2_EXPOSURE_METERING_MATRIX = 3, -}; - -#define V4L2_CID_SCENE_MODE (V4L2_CID_CAMERA_CLASS_BASE+26) -enum v4l2_scene_mode { - V4L2_SCENE_MODE_NONE = 0, - V4L2_SCENE_MODE_BACKLIGHT = 1, - V4L2_SCENE_MODE_BEACH_SNOW = 2, - V4L2_SCENE_MODE_CANDLE_LIGHT = 3, - V4L2_SCENE_MODE_DAWN_DUSK = 4, - V4L2_SCENE_MODE_FALL_COLORS = 5, - V4L2_SCENE_MODE_FIREWORKS = 6, - V4L2_SCENE_MODE_LANDSCAPE = 7, - V4L2_SCENE_MODE_NIGHT = 8, - V4L2_SCENE_MODE_PARTY_INDOOR = 9, - V4L2_SCENE_MODE_PORTRAIT = 10, - V4L2_SCENE_MODE_SPORTS = 11, - V4L2_SCENE_MODE_SUNSET = 12, - V4L2_SCENE_MODE_TEXT = 13, -}; - -#define V4L2_CID_3A_LOCK (V4L2_CID_CAMERA_CLASS_BASE+27) -#define V4L2_LOCK_EXPOSURE (1 << 0) -#define V4L2_LOCK_WHITE_BALANCE (1 << 1) -#define V4L2_LOCK_FOCUS (1 << 2) - -#define V4L2_CID_AUTO_FOCUS_START (V4L2_CID_CAMERA_CLASS_BASE+28) -#define V4L2_CID_AUTO_FOCUS_STOP (V4L2_CID_CAMERA_CLASS_BASE+29) -#define V4L2_CID_AUTO_FOCUS_STATUS (V4L2_CID_CAMERA_CLASS_BASE+30) -#define V4L2_AUTO_FOCUS_STATUS_IDLE (0 << 0) -#define V4L2_AUTO_FOCUS_STATUS_BUSY (1 << 0) -#define V4L2_AUTO_FOCUS_STATUS_REACHED (1 << 1) -#define V4L2_AUTO_FOCUS_STATUS_FAILED (1 << 2) - -#define V4L2_CID_AUTO_FOCUS_RANGE (V4L2_CID_CAMERA_CLASS_BASE+31) -enum v4l2_auto_focus_range { - V4L2_AUTO_FOCUS_RANGE_AUTO = 0, - V4L2_AUTO_FOCUS_RANGE_NORMAL = 1, - V4L2_AUTO_FOCUS_RANGE_MACRO = 2, - V4L2_AUTO_FOCUS_RANGE_INFINITY = 3, -}; - -#define V4L2_CID_PAN_SPEED (V4L2_CID_CAMERA_CLASS_BASE+32) -#define V4L2_CID_TILT_SPEED (V4L2_CID_CAMERA_CLASS_BASE+33) - -/* FM Modulator class control IDs */ - -#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900) -#define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1) - -#define V4L2_CID_RDS_TX_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 1) -#define V4L2_CID_RDS_TX_PI (V4L2_CID_FM_TX_CLASS_BASE + 2) -#define V4L2_CID_RDS_TX_PTY (V4L2_CID_FM_TX_CLASS_BASE + 3) -#define V4L2_CID_RDS_TX_PS_NAME (V4L2_CID_FM_TX_CLASS_BASE + 5) -#define V4L2_CID_RDS_TX_RADIO_TEXT (V4L2_CID_FM_TX_CLASS_BASE + 6) -#define V4L2_CID_RDS_TX_MONO_STEREO (V4L2_CID_FM_TX_CLASS_BASE + 7) -#define V4L2_CID_RDS_TX_ARTIFICIAL_HEAD (V4L2_CID_FM_TX_CLASS_BASE + 8) -#define V4L2_CID_RDS_TX_COMPRESSED (V4L2_CID_FM_TX_CLASS_BASE + 9) -#define V4L2_CID_RDS_TX_DYNAMIC_PTY (V4L2_CID_FM_TX_CLASS_BASE + 10) -#define V4L2_CID_RDS_TX_TRAFFIC_ANNOUNCEMENT (V4L2_CID_FM_TX_CLASS_BASE + 11) -#define V4L2_CID_RDS_TX_TRAFFIC_PROGRAM (V4L2_CID_FM_TX_CLASS_BASE + 12) -#define V4L2_CID_RDS_TX_MUSIC_SPEECH (V4L2_CID_FM_TX_CLASS_BASE + 13) -#define V4L2_CID_RDS_TX_ALT_FREQS_ENABLE (V4L2_CID_FM_TX_CLASS_BASE + 14) -#define V4L2_CID_RDS_TX_ALT_FREQS (V4L2_CID_FM_TX_CLASS_BASE + 15) - -#define V4L2_CID_AUDIO_LIMITER_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 64) -#define V4L2_CID_AUDIO_LIMITER_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 65) -#define V4L2_CID_AUDIO_LIMITER_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 66) - -#define V4L2_CID_AUDIO_COMPRESSION_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 80) -#define V4L2_CID_AUDIO_COMPRESSION_GAIN (V4L2_CID_FM_TX_CLASS_BASE + 81) -#define V4L2_CID_AUDIO_COMPRESSION_THRESHOLD (V4L2_CID_FM_TX_CLASS_BASE + 82) -#define V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME (V4L2_CID_FM_TX_CLASS_BASE + 83) -#define V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 84) - -#define V4L2_CID_PILOT_TONE_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 96) -#define V4L2_CID_PILOT_TONE_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 97) -#define V4L2_CID_PILOT_TONE_FREQUENCY (V4L2_CID_FM_TX_CLASS_BASE + 98) - -#define V4L2_CID_TUNE_PREEMPHASIS (V4L2_CID_FM_TX_CLASS_BASE + 112) -enum v4l2_preemphasis { - V4L2_PREEMPHASIS_DISABLED = 0, - V4L2_PREEMPHASIS_50_uS = 1, - V4L2_PREEMPHASIS_75_uS = 2, -}; -#define V4L2_CID_TUNE_POWER_LEVEL (V4L2_CID_FM_TX_CLASS_BASE + 113) -#define V4L2_CID_TUNE_ANTENNA_CAPACITOR (V4L2_CID_FM_TX_CLASS_BASE + 114) - - -/* Flash and privacy (indicator) light controls */ - -#define V4L2_CID_FLASH_CLASS_BASE (V4L2_CTRL_CLASS_FLASH | 0x900) -#define V4L2_CID_FLASH_CLASS (V4L2_CTRL_CLASS_FLASH | 1) - -#define V4L2_CID_FLASH_LED_MODE (V4L2_CID_FLASH_CLASS_BASE + 1) -enum v4l2_flash_led_mode { - V4L2_FLASH_LED_MODE_NONE, - V4L2_FLASH_LED_MODE_FLASH, - V4L2_FLASH_LED_MODE_TORCH, -}; - -#define V4L2_CID_FLASH_STROBE_SOURCE (V4L2_CID_FLASH_CLASS_BASE + 2) -enum v4l2_flash_strobe_source { - V4L2_FLASH_STROBE_SOURCE_SOFTWARE, - V4L2_FLASH_STROBE_SOURCE_EXTERNAL, -}; - -#define V4L2_CID_FLASH_STROBE (V4L2_CID_FLASH_CLASS_BASE + 3) -#define V4L2_CID_FLASH_STROBE_STOP (V4L2_CID_FLASH_CLASS_BASE + 4) -#define V4L2_CID_FLASH_STROBE_STATUS (V4L2_CID_FLASH_CLASS_BASE + 5) - -#define V4L2_CID_FLASH_TIMEOUT (V4L2_CID_FLASH_CLASS_BASE + 6) -#define V4L2_CID_FLASH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 7) -#define V4L2_CID_FLASH_TORCH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 8) -#define V4L2_CID_FLASH_INDICATOR_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 9) - -#define V4L2_CID_FLASH_FAULT (V4L2_CID_FLASH_CLASS_BASE + 10) -#define V4L2_FLASH_FAULT_OVER_VOLTAGE (1 << 0) -#define V4L2_FLASH_FAULT_TIMEOUT (1 << 1) -#define V4L2_FLASH_FAULT_OVER_TEMPERATURE (1 << 2) -#define V4L2_FLASH_FAULT_SHORT_CIRCUIT (1 << 3) -#define V4L2_FLASH_FAULT_OVER_CURRENT (1 << 4) -#define V4L2_FLASH_FAULT_INDICATOR (1 << 5) -#define V4L2_FLASH_FAULT_UNDER_VOLTAGE (1 << 6) -#define V4L2_FLASH_FAULT_INPUT_VOLTAGE (1 << 7) -#define V4L2_FLASH_FAULT_LED_OVER_TEMPERATURE (1 << 8) - -#define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11) -#define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12) - - -/* JPEG-class control IDs */ - -#define V4L2_CID_JPEG_CLASS_BASE (V4L2_CTRL_CLASS_JPEG | 0x900) -#define V4L2_CID_JPEG_CLASS (V4L2_CTRL_CLASS_JPEG | 1) - -#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1) -enum v4l2_jpeg_chroma_subsampling { - V4L2_JPEG_CHROMA_SUBSAMPLING_444 = 0, - V4L2_JPEG_CHROMA_SUBSAMPLING_422 = 1, - V4L2_JPEG_CHROMA_SUBSAMPLING_420 = 2, - V4L2_JPEG_CHROMA_SUBSAMPLING_411 = 3, - V4L2_JPEG_CHROMA_SUBSAMPLING_410 = 4, - V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY = 5, -}; -#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2) -#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3) - -#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4) -#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0) -#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1) -#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16) -#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) -#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) - - -/* Image source controls */ -#define V4L2_CID_IMAGE_SOURCE_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_SOURCE | 0x900) -#define V4L2_CID_IMAGE_SOURCE_CLASS (V4L2_CTRL_CLASS_IMAGE_SOURCE | 1) - -#define V4L2_CID_VBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 1) -#define V4L2_CID_HBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 2) -#define V4L2_CID_ANALOGUE_GAIN (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 3) -#define V4L2_CID_TEST_PATTERN_RED (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 4) -#define V4L2_CID_TEST_PATTERN_GREENR (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 5) -#define V4L2_CID_TEST_PATTERN_BLUE (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 6) -#define V4L2_CID_TEST_PATTERN_GREENB (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 7) - - -/* Image processing controls */ - -#define V4L2_CID_IMAGE_PROC_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_PROC | 0x900) -#define V4L2_CID_IMAGE_PROC_CLASS (V4L2_CTRL_CLASS_IMAGE_PROC | 1) - -#define V4L2_CID_LINK_FREQ (V4L2_CID_IMAGE_PROC_CLASS_BASE + 1) -#define V4L2_CID_PIXEL_RATE (V4L2_CID_IMAGE_PROC_CLASS_BASE + 2) -#define V4L2_CID_TEST_PATTERN (V4L2_CID_IMAGE_PROC_CLASS_BASE + 3) - - -/* DV-class control IDs defined by V4L2 */ -#define V4L2_CID_DV_CLASS_BASE (V4L2_CTRL_CLASS_DV | 0x900) -#define V4L2_CID_DV_CLASS (V4L2_CTRL_CLASS_DV | 1) - -#define V4L2_CID_DV_TX_HOTPLUG (V4L2_CID_DV_CLASS_BASE + 1) -#define V4L2_CID_DV_TX_RXSENSE (V4L2_CID_DV_CLASS_BASE + 2) -#define V4L2_CID_DV_TX_EDID_PRESENT (V4L2_CID_DV_CLASS_BASE + 3) -#define V4L2_CID_DV_TX_MODE (V4L2_CID_DV_CLASS_BASE + 4) -enum v4l2_dv_tx_mode { - V4L2_DV_TX_MODE_DVI_D = 0, - V4L2_DV_TX_MODE_HDMI = 1, -}; -#define V4L2_CID_DV_TX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 5) -enum v4l2_dv_rgb_range { - V4L2_DV_RGB_RANGE_AUTO = 0, - V4L2_DV_RGB_RANGE_LIMITED = 1, - V4L2_DV_RGB_RANGE_FULL = 2, -}; - -#define V4L2_CID_DV_TX_IT_CONTENT_TYPE (V4L2_CID_DV_CLASS_BASE + 6) -enum v4l2_dv_it_content_type { - V4L2_DV_IT_CONTENT_TYPE_GRAPHICS = 0, - V4L2_DV_IT_CONTENT_TYPE_PHOTO = 1, - V4L2_DV_IT_CONTENT_TYPE_CINEMA = 2, - V4L2_DV_IT_CONTENT_TYPE_GAME = 3, - V4L2_DV_IT_CONTENT_TYPE_NO_ITC = 4, -}; - -#define V4L2_CID_DV_RX_POWER_PRESENT (V4L2_CID_DV_CLASS_BASE + 100) -#define V4L2_CID_DV_RX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 101) -#define V4L2_CID_DV_RX_IT_CONTENT_TYPE (V4L2_CID_DV_CLASS_BASE + 102) - -#define V4L2_CID_FM_RX_CLASS_BASE (V4L2_CTRL_CLASS_FM_RX | 0x900) -#define V4L2_CID_FM_RX_CLASS (V4L2_CTRL_CLASS_FM_RX | 1) - -#define V4L2_CID_TUNE_DEEMPHASIS (V4L2_CID_FM_RX_CLASS_BASE + 1) -enum v4l2_deemphasis { - V4L2_DEEMPHASIS_DISABLED = V4L2_PREEMPHASIS_DISABLED, - V4L2_DEEMPHASIS_50_uS = V4L2_PREEMPHASIS_50_uS, - V4L2_DEEMPHASIS_75_uS = V4L2_PREEMPHASIS_75_uS, -}; - -#define V4L2_CID_RDS_RECEPTION (V4L2_CID_FM_RX_CLASS_BASE + 2) -#define V4L2_CID_RDS_RX_PTY (V4L2_CID_FM_RX_CLASS_BASE + 3) -#define V4L2_CID_RDS_RX_PS_NAME (V4L2_CID_FM_RX_CLASS_BASE + 4) -#define V4L2_CID_RDS_RX_RADIO_TEXT (V4L2_CID_FM_RX_CLASS_BASE + 5) -#define V4L2_CID_RDS_RX_TRAFFIC_ANNOUNCEMENT (V4L2_CID_FM_RX_CLASS_BASE + 6) -#define V4L2_CID_RDS_RX_TRAFFIC_PROGRAM (V4L2_CID_FM_RX_CLASS_BASE + 7) -#define V4L2_CID_RDS_RX_MUSIC_SPEECH (V4L2_CID_FM_RX_CLASS_BASE + 8) - -#define V4L2_CID_RF_TUNER_CLASS_BASE (V4L2_CTRL_CLASS_RF_TUNER | 0x900) -#define V4L2_CID_RF_TUNER_CLASS (V4L2_CTRL_CLASS_RF_TUNER | 1) - -#define V4L2_CID_RF_TUNER_BANDWIDTH_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 11) -#define V4L2_CID_RF_TUNER_BANDWIDTH (V4L2_CID_RF_TUNER_CLASS_BASE + 12) -#define V4L2_CID_RF_TUNER_RF_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 32) -#define V4L2_CID_RF_TUNER_LNA_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 41) -#define V4L2_CID_RF_TUNER_LNA_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 42) -#define V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 51) -#define V4L2_CID_RF_TUNER_MIXER_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 52) -#define V4L2_CID_RF_TUNER_IF_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 61) -#define V4L2_CID_RF_TUNER_IF_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 62) -#define V4L2_CID_RF_TUNER_PLL_LOCK (V4L2_CID_RF_TUNER_CLASS_BASE + 91) - - -/* Detection-class control IDs defined by V4L2 */ -#define V4L2_CID_DETECT_CLASS_BASE (V4L2_CTRL_CLASS_DETECT | 0x900) -#define V4L2_CID_DETECT_CLASS (V4L2_CTRL_CLASS_DETECT | 1) - -#define V4L2_CID_DETECT_MD_MODE (V4L2_CID_DETECT_CLASS_BASE + 1) -enum v4l2_detect_md_mode { - V4L2_DETECT_MD_MODE_DISABLED = 0, - V4L2_DETECT_MD_MODE_GLOBAL = 1, - V4L2_DETECT_MD_MODE_THRESHOLD_GRID = 2, - V4L2_DETECT_MD_MODE_REGION_GRID = 3, -}; -#define V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD (V4L2_CID_DETECT_CLASS_BASE + 2) -#define V4L2_CID_DETECT_MD_THRESHOLD_GRID (V4L2_CID_DETECT_CLASS_BASE + 3) -#define V4L2_CID_DETECT_MD_REGION_GRID (V4L2_CID_DETECT_CLASS_BASE + 4) - -#endif diff --git a/sdm710/original-kernel-headers/linux/videodev2.h b/sdm710/original-kernel-headers/linux/videodev2.h deleted file mode 100644 index 179e78c5..00000000 --- a/sdm710/original-kernel-headers/linux/videodev2.h +++ /dev/null @@ -1,2453 +0,0 @@ -/* - * Video for Linux Two header file - * - * Copyright (C) 1999-2012 the contributors - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Alternatively you can redistribute this file under the terms of the - * BSD license as stated below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. The names of its contributors may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Header file for v4l or V4L2 drivers and applications - * with public API. - * All kernel-specific stuff were moved to media/v4l2-dev.h, so - * no #if __KERNEL tests are allowed here - * - * See https://linuxtv.org for more info - * - * Author: Bill Dirks <bill@thedirks.org> - * Justin Schoeman - * Hans Verkuil <hverkuil@xs4all.nl> - * et al. - */ -#ifndef __LINUX_VIDEODEV2_H -#define __LINUX_VIDEODEV2_H - -#include <sys/time.h> - -#include <linux/ioctl.h> -#include <linux/types.h> -#include <linux/v4l2-common.h> -#include <linux/v4l2-controls.h> - -/* - * Common stuff for both V4L1 and V4L2 - * Moved from videodev.h - */ -#define VIDEO_MAX_FRAME 64 -#define VIDEO_MAX_PLANES 8 - -/* - * M I S C E L L A N E O U S - */ - -/* Four-character-code (FOURCC) */ -#define v4l2_fourcc(a, b, c, d)\ - ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24)) -#define v4l2_fourcc_be(a, b, c, d) (v4l2_fourcc(a, b, c, d) | (1 << 31)) - -/* - * E N U M S - */ -enum v4l2_field { - V4L2_FIELD_ANY = 0, /* driver can choose from none, - top, bottom, interlaced - depending on whatever it thinks - is approximate ... */ - V4L2_FIELD_NONE = 1, /* this device has no fields ... */ - V4L2_FIELD_TOP = 2, /* top field only */ - V4L2_FIELD_BOTTOM = 3, /* bottom field only */ - V4L2_FIELD_INTERLACED = 4, /* both fields interlaced */ - V4L2_FIELD_SEQ_TB = 5, /* both fields sequential into one - buffer, top-bottom order */ - V4L2_FIELD_SEQ_BT = 6, /* same as above + bottom-top order */ - V4L2_FIELD_ALTERNATE = 7, /* both fields alternating into - separate buffers */ - V4L2_FIELD_INTERLACED_TB = 8, /* both fields interlaced, top field - first and the top field is - transmitted first */ - V4L2_FIELD_INTERLACED_BT = 9, /* both fields interlaced, top field - first and the bottom field is - transmitted first */ -}; -#define V4L2_FIELD_HAS_TOP(field) \ - ((field) == V4L2_FIELD_TOP ||\ - (field) == V4L2_FIELD_INTERLACED ||\ - (field) == V4L2_FIELD_INTERLACED_TB ||\ - (field) == V4L2_FIELD_INTERLACED_BT ||\ - (field) == V4L2_FIELD_SEQ_TB ||\ - (field) == V4L2_FIELD_SEQ_BT) -#define V4L2_FIELD_HAS_BOTTOM(field) \ - ((field) == V4L2_FIELD_BOTTOM ||\ - (field) == V4L2_FIELD_INTERLACED ||\ - (field) == V4L2_FIELD_INTERLACED_TB ||\ - (field) == V4L2_FIELD_INTERLACED_BT ||\ - (field) == V4L2_FIELD_SEQ_TB ||\ - (field) == V4L2_FIELD_SEQ_BT) -#define V4L2_FIELD_HAS_BOTH(field) \ - ((field) == V4L2_FIELD_INTERLACED ||\ - (field) == V4L2_FIELD_INTERLACED_TB ||\ - (field) == V4L2_FIELD_INTERLACED_BT ||\ - (field) == V4L2_FIELD_SEQ_TB ||\ - (field) == V4L2_FIELD_SEQ_BT) -#define V4L2_FIELD_HAS_T_OR_B(field) \ - ((field) == V4L2_FIELD_BOTTOM ||\ - (field) == V4L2_FIELD_TOP ||\ - (field) == V4L2_FIELD_ALTERNATE) - -enum v4l2_buf_type { - V4L2_BUF_TYPE_VIDEO_CAPTURE = 1, - V4L2_BUF_TYPE_VIDEO_OUTPUT = 2, - V4L2_BUF_TYPE_VIDEO_OVERLAY = 3, - V4L2_BUF_TYPE_VBI_CAPTURE = 4, - V4L2_BUF_TYPE_VBI_OUTPUT = 5, - V4L2_BUF_TYPE_SLICED_VBI_CAPTURE = 6, - V4L2_BUF_TYPE_SLICED_VBI_OUTPUT = 7, - V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY = 8, - V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE = 9, - V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE = 10, - V4L2_BUF_TYPE_SDR_CAPTURE = 11, - V4L2_BUF_TYPE_SDR_OUTPUT = 12, - /* Deprecated, do not use */ - V4L2_BUF_TYPE_PRIVATE = 0x80, -}; - -#define V4L2_TYPE_IS_MULTIPLANAR(type) \ - ((type) == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE \ - || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) - -#define V4L2_TYPE_IS_OUTPUT(type) \ - ((type) == V4L2_BUF_TYPE_VIDEO_OUTPUT \ - || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE \ - || (type) == V4L2_BUF_TYPE_VIDEO_OVERLAY \ - || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY \ - || (type) == V4L2_BUF_TYPE_VBI_OUTPUT \ - || (type) == V4L2_BUF_TYPE_SLICED_VBI_OUTPUT \ - || (type) == V4L2_BUF_TYPE_SDR_OUTPUT) - -enum v4l2_tuner_type { - V4L2_TUNER_RADIO = 1, - V4L2_TUNER_ANALOG_TV = 2, - V4L2_TUNER_DIGITAL_TV = 3, - V4L2_TUNER_SDR = 4, - V4L2_TUNER_RF = 5, -}; - -/* Deprecated, do not use */ -#define V4L2_TUNER_ADC V4L2_TUNER_SDR - -enum v4l2_memory { - V4L2_MEMORY_MMAP = 1, - V4L2_MEMORY_USERPTR = 2, - V4L2_MEMORY_OVERLAY = 3, - V4L2_MEMORY_DMABUF = 4, -}; - -/* see also http://vektor.theorem.ca/graphics/ycbcr/ */ -enum v4l2_colorspace { - /* - * Default colorspace, i.e. let the driver figure it out. - * Can only be used with video capture. - */ - V4L2_COLORSPACE_DEFAULT = 0, - - /* SMPTE 170M: used for broadcast NTSC/PAL SDTV */ - V4L2_COLORSPACE_SMPTE170M = 1, - - /* Obsolete pre-1998 SMPTE 240M HDTV standard, superseded by Rec 709 */ - V4L2_COLORSPACE_SMPTE240M = 2, - - /* Rec.709: used for HDTV */ - V4L2_COLORSPACE_REC709 = 3, - - /* - * Deprecated, do not use. No driver will ever return this. This was - * based on a misunderstanding of the bt878 datasheet. - */ - V4L2_COLORSPACE_BT878 = 4, - - /* - * NTSC 1953 colorspace. This only makes sense when dealing with - * really, really old NTSC recordings. Superseded by SMPTE 170M. - */ - V4L2_COLORSPACE_470_SYSTEM_M = 5, - - /* - * EBU Tech 3213 PAL/SECAM colorspace. This only makes sense when - * dealing with really old PAL/SECAM recordings. Superseded by - * SMPTE 170M. - */ - V4L2_COLORSPACE_470_SYSTEM_BG = 6, - - /* - * Effectively shorthand for V4L2_COLORSPACE_SRGB, V4L2_YCBCR_ENC_601 - * and V4L2_QUANTIZATION_FULL_RANGE. To be used for (Motion-)JPEG. - */ - V4L2_COLORSPACE_JPEG = 7, - - /* For RGB colorspaces such as produces by most webcams. */ - V4L2_COLORSPACE_SRGB = 8, - - /* AdobeRGB colorspace */ - V4L2_COLORSPACE_ADOBERGB = 9, - - /* BT.2020 colorspace, used for UHDTV. */ - V4L2_COLORSPACE_BT2020 = 10, - - /* Raw colorspace: for RAW unprocessed images */ - V4L2_COLORSPACE_RAW = 11, - - /* DCI-P3 colorspace, used by cinema projectors */ - V4L2_COLORSPACE_DCI_P3 = 12, -}; - -/* - * Determine how COLORSPACE_DEFAULT should map to a proper colorspace. - * This depends on whether this is a SDTV image (use SMPTE 170M), an - * HDTV image (use Rec. 709), or something else (use sRGB). - */ -#define V4L2_MAP_COLORSPACE_DEFAULT(is_sdtv, is_hdtv) \ - ((is_sdtv) ? V4L2_COLORSPACE_SMPTE170M : \ - ((is_hdtv) ? V4L2_COLORSPACE_REC709 : V4L2_COLORSPACE_SRGB)) - -enum v4l2_xfer_func { - /* - * Mapping of V4L2_XFER_FUNC_DEFAULT to actual transfer functions - * for the various colorspaces: - * - * V4L2_COLORSPACE_SMPTE170M, V4L2_COLORSPACE_470_SYSTEM_M, - * V4L2_COLORSPACE_470_SYSTEM_BG, V4L2_COLORSPACE_REC709 and - * V4L2_COLORSPACE_BT2020: V4L2_XFER_FUNC_709 - * - * V4L2_COLORSPACE_SRGB, V4L2_COLORSPACE_JPEG: V4L2_XFER_FUNC_SRGB - * - * V4L2_COLORSPACE_ADOBERGB: V4L2_XFER_FUNC_ADOBERGB - * - * V4L2_COLORSPACE_SMPTE240M: V4L2_XFER_FUNC_SMPTE240M - * - * V4L2_COLORSPACE_RAW: V4L2_XFER_FUNC_NONE - * - * V4L2_COLORSPACE_DCI_P3: V4L2_XFER_FUNC_DCI_P3 - */ - V4L2_XFER_FUNC_DEFAULT = 0, - V4L2_XFER_FUNC_709 = 1, - V4L2_XFER_FUNC_SRGB = 2, - V4L2_XFER_FUNC_ADOBERGB = 3, - V4L2_XFER_FUNC_SMPTE240M = 4, - V4L2_XFER_FUNC_NONE = 5, - V4L2_XFER_FUNC_DCI_P3 = 6, - V4L2_XFER_FUNC_SMPTE2084 = 7, -}; - -/* - * Determine how XFER_FUNC_DEFAULT should map to a proper transfer function. - * This depends on the colorspace. - */ -#define V4L2_MAP_XFER_FUNC_DEFAULT(colsp) \ - ((colsp) == V4L2_COLORSPACE_ADOBERGB ? V4L2_XFER_FUNC_ADOBERGB : \ - ((colsp) == V4L2_COLORSPACE_SMPTE240M ? V4L2_XFER_FUNC_SMPTE240M : \ - ((colsp) == V4L2_COLORSPACE_DCI_P3 ? V4L2_XFER_FUNC_DCI_P3 : \ - ((colsp) == V4L2_COLORSPACE_RAW ? V4L2_XFER_FUNC_NONE : \ - ((colsp) == V4L2_COLORSPACE_SRGB || (colsp) == V4L2_COLORSPACE_JPEG ? \ - V4L2_XFER_FUNC_SRGB : V4L2_XFER_FUNC_709))))) - -enum v4l2_ycbcr_encoding { - /* - * Mapping of V4L2_YCBCR_ENC_DEFAULT to actual encodings for the - * various colorspaces: - * - * V4L2_COLORSPACE_SMPTE170M, V4L2_COLORSPACE_470_SYSTEM_M, - * V4L2_COLORSPACE_470_SYSTEM_BG, V4L2_COLORSPACE_SRGB, - * V4L2_COLORSPACE_ADOBERGB and V4L2_COLORSPACE_JPEG: V4L2_YCBCR_ENC_601 - * - * V4L2_COLORSPACE_REC709 and V4L2_COLORSPACE_DCI_P3: V4L2_YCBCR_ENC_709 - * - * V4L2_COLORSPACE_BT2020: V4L2_YCBCR_ENC_BT2020 - * - * V4L2_COLORSPACE_SMPTE240M: V4L2_YCBCR_ENC_SMPTE240M - */ - V4L2_YCBCR_ENC_DEFAULT = 0, - - /* ITU-R 601 -- SDTV */ - V4L2_YCBCR_ENC_601 = 1, - - /* Rec. 709 -- HDTV */ - V4L2_YCBCR_ENC_709 = 2, - - /* ITU-R 601/EN 61966-2-4 Extended Gamut -- SDTV */ - V4L2_YCBCR_ENC_XV601 = 3, - - /* Rec. 709/EN 61966-2-4 Extended Gamut -- HDTV */ - V4L2_YCBCR_ENC_XV709 = 4, - - /* - * sYCC (Y'CbCr encoding of sRGB), identical to ENC_601. It was added - * originally due to a misunderstanding of the sYCC standard. It should - * not be used, instead use V4L2_YCBCR_ENC_601. - */ - V4L2_YCBCR_ENC_SYCC = 5, - - /* BT.2020 Non-constant Luminance Y'CbCr */ - V4L2_YCBCR_ENC_BT2020 = 6, - - /* BT.2020 Constant Luminance Y'CbcCrc */ - V4L2_YCBCR_ENC_BT2020_CONST_LUM = 7, - - /* SMPTE 240M -- Obsolete HDTV */ - V4L2_YCBCR_ENC_SMPTE240M = 8, -}; - -/* - * Determine how YCBCR_ENC_DEFAULT should map to a proper Y'CbCr encoding. - * This depends on the colorspace. - */ -#define V4L2_MAP_YCBCR_ENC_DEFAULT(colsp) \ - (((colsp) == V4L2_COLORSPACE_REC709 || \ - (colsp) == V4L2_COLORSPACE_DCI_P3) ? V4L2_YCBCR_ENC_709 : \ - ((colsp) == V4L2_COLORSPACE_BT2020 ? V4L2_YCBCR_ENC_BT2020 : \ - ((colsp) == V4L2_COLORSPACE_SMPTE240M ? V4L2_YCBCR_ENC_SMPTE240M : \ - V4L2_YCBCR_ENC_601))) - -enum v4l2_quantization { - /* - * The default for R'G'B' quantization is always full range, except - * for the BT2020 colorspace. For Y'CbCr the quantization is always - * limited range, except for COLORSPACE_JPEG, XV601 or XV709: those - * are full range. - */ - V4L2_QUANTIZATION_DEFAULT = 0, - V4L2_QUANTIZATION_FULL_RANGE = 1, - V4L2_QUANTIZATION_LIM_RANGE = 2, -}; - -/* - * Determine how QUANTIZATION_DEFAULT should map to a proper quantization. - * This depends on whether the image is RGB or not, the colorspace and the - * Y'CbCr encoding. - */ -#define V4L2_MAP_QUANTIZATION_DEFAULT(is_rgb, colsp, ycbcr_enc) \ - (((is_rgb) && (colsp) == V4L2_COLORSPACE_BT2020) ? V4L2_QUANTIZATION_LIM_RANGE : \ - (((is_rgb) || (ycbcr_enc) == V4L2_YCBCR_ENC_XV601 || \ - (ycbcr_enc) == V4L2_YCBCR_ENC_XV709 || (colsp) == V4L2_COLORSPACE_JPEG) ? \ - V4L2_QUANTIZATION_FULL_RANGE : V4L2_QUANTIZATION_LIM_RANGE)) - -enum v4l2_priority { - V4L2_PRIORITY_UNSET = 0, /* not initialized */ - V4L2_PRIORITY_BACKGROUND = 1, - V4L2_PRIORITY_INTERACTIVE = 2, - V4L2_PRIORITY_RECORD = 3, - V4L2_PRIORITY_DEFAULT = V4L2_PRIORITY_INTERACTIVE, -}; - -struct v4l2_rect { - __s32 left; - __s32 top; - __u32 width; - __u32 height; -}; - -struct v4l2_fract { - __u32 numerator; - __u32 denominator; -}; - -/** - * struct v4l2_capability - Describes V4L2 device caps returned by VIDIOC_QUERYCAP - * - * @driver: name of the driver module (e.g. "bttv") - * @card: name of the card (e.g. "Hauppauge WinTV") - * @bus_info: name of the bus (e.g. "PCI:" + pci_name(pci_dev) ) - * @version: KERNEL_VERSION - * @capabilities: capabilities of the physical device as a whole - * @device_caps: capabilities accessed via this particular device (node) - * @reserved: reserved fields for future extensions - */ -struct v4l2_capability { - __u8 driver[16]; - __u8 card[32]; - __u8 bus_info[32]; - __u32 version; - __u32 capabilities; - __u32 device_caps; - __u32 reserved[3]; -}; - -/* Values for 'capabilities' field */ -#define V4L2_CAP_VIDEO_CAPTURE 0x00000001 /* Is a video capture device */ -#define V4L2_CAP_VIDEO_OUTPUT 0x00000002 /* Is a video output device */ -#define V4L2_CAP_VIDEO_OVERLAY 0x00000004 /* Can do video overlay */ -#define V4L2_CAP_VBI_CAPTURE 0x00000010 /* Is a raw VBI capture device */ -#define V4L2_CAP_VBI_OUTPUT 0x00000020 /* Is a raw VBI output device */ -#define V4L2_CAP_SLICED_VBI_CAPTURE 0x00000040 /* Is a sliced VBI capture device */ -#define V4L2_CAP_SLICED_VBI_OUTPUT 0x00000080 /* Is a sliced VBI output device */ -#define V4L2_CAP_RDS_CAPTURE 0x00000100 /* RDS data capture */ -#define V4L2_CAP_VIDEO_OUTPUT_OVERLAY 0x00000200 /* Can do video output overlay */ -#define V4L2_CAP_HW_FREQ_SEEK 0x00000400 /* Can do hardware frequency seek */ -#define V4L2_CAP_RDS_OUTPUT 0x00000800 /* Is an RDS encoder */ - -/* Is a video capture device that supports multiplanar formats */ -#define V4L2_CAP_VIDEO_CAPTURE_MPLANE 0x00001000 -/* Is a video output device that supports multiplanar formats */ -#define V4L2_CAP_VIDEO_OUTPUT_MPLANE 0x00002000 -/* Is a video mem-to-mem device that supports multiplanar formats */ -#define V4L2_CAP_VIDEO_M2M_MPLANE 0x00004000 -/* Is a video mem-to-mem device */ -#define V4L2_CAP_VIDEO_M2M 0x00008000 - -#define V4L2_CAP_TUNER 0x00010000 /* has a tuner */ -#define V4L2_CAP_AUDIO 0x00020000 /* has audio support */ -#define V4L2_CAP_RADIO 0x00040000 /* is a radio device */ -#define V4L2_CAP_MODULATOR 0x00080000 /* has a modulator */ - -#define V4L2_CAP_SDR_CAPTURE 0x00100000 /* Is a SDR capture device */ -#define V4L2_CAP_EXT_PIX_FORMAT 0x00200000 /* Supports the extended pixel format */ -#define V4L2_CAP_SDR_OUTPUT 0x00400000 /* Is a SDR output device */ - -#define V4L2_CAP_READWRITE 0x01000000 /* read/write systemcalls */ -#define V4L2_CAP_ASYNCIO 0x02000000 /* async I/O */ -#define V4L2_CAP_STREAMING 0x04000000 /* streaming I/O ioctls */ - -#define V4L2_CAP_TOUCH 0x10000000 /* Is a touch device */ - -#define V4L2_CAP_DEVICE_CAPS 0x80000000 /* sets device capabilities field */ - -/* - * V I D E O I M A G E F O R M A T - */ -struct v4l2_pix_format { - __u32 width; - __u32 height; - __u32 pixelformat; - __u32 field; /* enum v4l2_field */ - __u32 bytesperline; /* for padding, zero if unused */ - __u32 sizeimage; - __u32 colorspace; /* enum v4l2_colorspace */ - __u32 priv; /* private data, depends on pixelformat */ - __u32 flags; /* format flags (V4L2_PIX_FMT_FLAG_*) */ - __u32 ycbcr_enc; /* enum v4l2_ycbcr_encoding */ - __u32 quantization; /* enum v4l2_quantization */ - __u32 xfer_func; /* enum v4l2_xfer_func */ -}; - -/* Pixel format FOURCC depth Description */ - -/* RGB formats */ -#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1') /* 8 RGB-3-3-2 */ -#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4') /* 16 xxxxrrrr ggggbbbb */ -#define V4L2_PIX_FMT_ARGB444 v4l2_fourcc('A', 'R', '1', '2') /* 16 aaaarrrr ggggbbbb */ -#define V4L2_PIX_FMT_XRGB444 v4l2_fourcc('X', 'R', '1', '2') /* 16 xxxxrrrr ggggbbbb */ -#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O') /* 16 RGB-5-5-5 */ -#define V4L2_PIX_FMT_ARGB555 v4l2_fourcc('A', 'R', '1', '5') /* 16 ARGB-1-5-5-5 */ -#define V4L2_PIX_FMT_XRGB555 v4l2_fourcc('X', 'R', '1', '5') /* 16 XRGB-1-5-5-5 */ -#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R', 'G', 'B', 'P') /* 16 RGB-5-6-5 */ -#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') /* 16 RGB-5-5-5 BE */ -#define V4L2_PIX_FMT_ARGB555X v4l2_fourcc_be('A', 'R', '1', '5') /* 16 ARGB-5-5-5 BE */ -#define V4L2_PIX_FMT_XRGB555X v4l2_fourcc_be('X', 'R', '1', '5') /* 16 XRGB-5-5-5 BE */ -#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16 RGB-5-6-5 BE */ -#define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H') /* 18 BGR-6-6-6 */ -#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') /* 24 BGR-8-8-8 */ -#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') /* 24 RGB-8-8-8 */ -#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') /* 32 BGR-8-8-8-8 */ -#define V4L2_PIX_FMT_ABGR32 v4l2_fourcc('A', 'R', '2', '4') /* 32 BGRA-8-8-8-8 */ -#define V4L2_PIX_FMT_XBGR32 v4l2_fourcc('X', 'R', '2', '4') /* 32 BGRX-8-8-8-8 */ -#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') /* 32 RGB-8-8-8-8 */ -#define V4L2_PIX_FMT_ARGB32 v4l2_fourcc('B', 'A', '2', '4') /* 32 ARGB-8-8-8-8 */ -#define V4L2_PIX_FMT_XRGB32 v4l2_fourcc('B', 'X', '2', '4') /* 32 XRGB-8-8-8-8 */ - -#define V4L2_PIX_FMT_RGBA8888_UBWC v4l2_fourcc('Q', 'R', 'G', 'B') - -/* Grey formats */ -#define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */ -#define V4L2_PIX_FMT_Y4 v4l2_fourcc('Y', '0', '4', ' ') /* 4 Greyscale */ -#define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ') /* 6 Greyscale */ -#define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ') /* 10 Greyscale */ -#define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') /* 12 Greyscale */ -#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */ -#define V4L2_PIX_FMT_Y16_BE v4l2_fourcc_be('Y', '1', '6', ' ') /* 16 Greyscale BE */ - -/* Grey bit-packed formats */ -#define V4L2_PIX_FMT_Y10BPACK v4l2_fourcc('Y', '1', '0', 'B') /* 10 Greyscale bit-packed */ - -/* Palette formats */ -#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') /* 8 8-bit palette */ - -/* Chrominance formats */ -#define V4L2_PIX_FMT_UV8 v4l2_fourcc('U', 'V', '8', ' ') /* 8 UV 4:4 */ - -/* Luminance+Chrominance formats */ -#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y', 'U', 'Y', 'V') /* 16 YUV 4:2:2 */ -#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y', 'Y', 'U', 'V') /* 16 YUV 4:2:2 */ -#define V4L2_PIX_FMT_YVYU v4l2_fourcc('Y', 'V', 'Y', 'U') /* 16 YVU 4:2:2 */ -#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U', 'Y', 'V', 'Y') /* 16 YUV 4:2:2 */ -#define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y') /* 16 YUV 4:2:2 */ -#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P') /* 12 YUV 4:1:1 */ -#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') /* 16 xxxxyyyy uuuuvvvv */ -#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') /* 16 YUV-5-5-5 */ -#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') /* 16 YUV-5-6-5 */ -#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') /* 32 YUV-8-8-8-8 */ -#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */ -#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */ -#define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') /* 12 YUV 4:2:0 2 lines y, 1 line uv interleaved */ - -/* two planes -- one Y, one Cr + Cb interleaved */ -#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ -#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */ -#define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */ -#define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */ -#define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ -#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ - -/* UBWC 8-bit Y/CbCr 4:2:0 */ -#define V4L2_PIX_FMT_NV12_UBWC v4l2_fourcc('Q', '1', '2', '8') -/* UBWC 10-bit Y/CbCr 4:2:0 */ -#define V4L2_PIX_FMT_NV12_TP10_UBWC v4l2_fourcc('Q', '1', '2', 'A') -#define V4L2_PIX_FMT_NV12_P010_UBWC v4l2_fourcc('Q', '1', '2', 'B') - -/* two non contiguous planes - one Y, one Cr + Cb interleaved */ -#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */ -#define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/CrCb 4:2:0 */ -#define V4L2_PIX_FMT_NV16M v4l2_fourcc('N', 'M', '1', '6') /* 16 Y/CbCr 4:2:2 */ -#define V4L2_PIX_FMT_NV61M v4l2_fourcc('N', 'M', '6', '1') /* 16 Y/CrCb 4:2:2 */ -#define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 64x32 macroblocks */ -#define V4L2_PIX_FMT_NV12MT_16X16 v4l2_fourcc('V', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 16x16 macroblocks */ - -/* three planes - Y Cb, Cr */ -#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y', 'U', 'V', '9') /* 9 YUV 4:1:0 */ -#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y', 'V', 'U', '9') /* 9 YVU 4:1:0 */ -#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P') /* 12 YVU411 planar */ -#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y', 'U', '1', '2') /* 12 YUV 4:2:0 */ -#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y', 'V', '1', '2') /* 12 YVU 4:2:0 */ -#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P') /* 16 YVU422 planar */ - -/* three non contiguous planes - Y, Cb, Cr */ -#define V4L2_PIX_FMT_YUV420M v4l2_fourcc('Y', 'M', '1', '2') /* 12 YUV420 planar */ -#define V4L2_PIX_FMT_YVU420M v4l2_fourcc('Y', 'M', '2', '1') /* 12 YVU420 planar */ -#define V4L2_PIX_FMT_YUV422M v4l2_fourcc('Y', 'M', '1', '6') /* 16 YUV422 planar */ -#define V4L2_PIX_FMT_YVU422M v4l2_fourcc('Y', 'M', '6', '1') /* 16 YVU422 planar */ -#define V4L2_PIX_FMT_YUV444M v4l2_fourcc('Y', 'M', '2', '4') /* 24 YUV444 planar */ -#define V4L2_PIX_FMT_YVU444M v4l2_fourcc('Y', 'M', '4', '2') /* 24 YVU444 planar */ - -/* Bayer formats - see http://www.siliconimaging.com/RGB%20Bayer.htm */ -#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') /* 8 BGBG.. GRGR.. */ -#define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G', 'B', 'R', 'G') /* 8 GBGB.. RGRG.. */ -#define V4L2_PIX_FMT_SGRBG8 v4l2_fourcc('G', 'R', 'B', 'G') /* 8 GRGR.. BGBG.. */ -#define V4L2_PIX_FMT_SRGGB8 v4l2_fourcc('R', 'G', 'G', 'B') /* 8 RGRG.. GBGB.. */ -#define V4L2_PIX_FMT_SBGGR10 v4l2_fourcc('B', 'G', '1', '0') /* 10 BGBG.. GRGR.. */ -#define V4L2_PIX_FMT_SGBRG10 v4l2_fourcc('G', 'B', '1', '0') /* 10 GBGB.. RGRG.. */ -#define V4L2_PIX_FMT_SGRBG10 v4l2_fourcc('B', 'A', '1', '0') /* 10 GRGR.. BGBG.. */ -#define V4L2_PIX_FMT_SRGGB10 v4l2_fourcc('R', 'G', '1', '0') /* 10 RGRG.. GBGB.. */ - /* 10bit raw bayer packed, 5 bytes for every 4 pixels */ -#define V4L2_PIX_FMT_SBGGR10P v4l2_fourcc('p', 'B', 'A', 'A') -#define V4L2_PIX_FMT_SGBRG10P v4l2_fourcc('p', 'G', 'A', 'A') -#define V4L2_PIX_FMT_SGRBG10P v4l2_fourcc('p', 'g', 'A', 'A') -#define V4L2_PIX_FMT_SRGGB10P v4l2_fourcc('p', 'R', 'A', 'A') - /* 10bit raw bayer a-law compressed to 8 bits */ -#define V4L2_PIX_FMT_SBGGR10ALAW8 v4l2_fourcc('a', 'B', 'A', '8') -#define V4L2_PIX_FMT_SGBRG10ALAW8 v4l2_fourcc('a', 'G', 'A', '8') -#define V4L2_PIX_FMT_SGRBG10ALAW8 v4l2_fourcc('a', 'g', 'A', '8') -#define V4L2_PIX_FMT_SRGGB10ALAW8 v4l2_fourcc('a', 'R', 'A', '8') - /* 10bit raw bayer DPCM compressed to 8 bits */ -#define V4L2_PIX_FMT_SBGGR10DPCM8 v4l2_fourcc('b', 'B', 'A', '8') -#define V4L2_PIX_FMT_SGBRG10DPCM8 v4l2_fourcc('b', 'G', 'A', '8') -#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0') -#define V4L2_PIX_FMT_SRGGB10DPCM8 v4l2_fourcc('b', 'R', 'A', '8') -#define V4L2_PIX_FMT_SBGGR12 v4l2_fourcc('B', 'G', '1', '2') /* 12 BGBG.. GRGR.. */ -#define V4L2_PIX_FMT_SGBRG12 v4l2_fourcc('G', 'B', '1', '2') /* 12 GBGB.. RGRG.. */ -#define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') /* 12 GRGR.. BGBG.. */ -#define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') /* 12 RGRG.. GBGB.. */ -#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') /* 16 BGBG.. GRGR.. */ -#define V4L2_PIX_FMT_SBGGR10DPCM6 v4l2_fourcc('b', 'B', 'A', '6') -#define V4L2_PIX_FMT_SGBRG10DPCM6 v4l2_fourcc('b', 'G', 'A', '6') -#define V4L2_PIX_FMT_SGRBG10DPCM6 v4l2_fourcc('B', 'D', '1', '6') -#define V4L2_PIX_FMT_SRGGB10DPCM6 v4l2_fourcc('b', 'R', 'A', '6') -#define V4L2_PIX_FMT_SBGGRPLAIN16 v4l2_fourcc('B', 'G', '1', '6') -#define V4L2_PIX_FMT_SGBRGPLAIN16 v4l2_fourcc('G', 'B', '1', '6') -#define V4L2_PIX_FMT_SGRBGPLAIN16 v4l2_fourcc('G', 'R', '1', '6') -#define V4L2_PIX_FMT_SRGGBPLAIN16 v4l2_fourcc('R', 'G', '1', '6') - -/* compressed formats */ -#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG */ -#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G') /* JFIF JPEG */ -#define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd') /* 1394 */ -#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G') /* MPEG-1/2/4 Multiplexed */ -#define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') /* H264 with start codes */ -#define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') /* H264 without start codes */ -#define V4L2_PIX_FMT_H264_MVC v4l2_fourcc('M', '2', '6', '4') /* H264 MVC */ -#define V4L2_PIX_FMT_H263 v4l2_fourcc('H', '2', '6', '3') /* H263 */ -#define V4L2_PIX_FMT_MPEG1 v4l2_fourcc('M', 'P', 'G', '1') /* MPEG-1 ES */ -#define V4L2_PIX_FMT_MPEG2 v4l2_fourcc('M', 'P', 'G', '2') /* MPEG-2 ES */ -#define V4L2_PIX_FMT_MPEG4 v4l2_fourcc('M', 'P', 'G', '4') /* MPEG-4 part 2 ES */ -#define V4L2_PIX_FMT_XVID v4l2_fourcc('X', 'V', 'I', 'D') /* Xvid */ -#define V4L2_PIX_FMT_VC1_ANNEX_G v4l2_fourcc('V', 'C', '1', 'G') /* SMPTE 421M Annex G compliant stream */ -#define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') /* SMPTE 421M Annex L compliant stream */ -#define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */ -#define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0') /* VP9 */ -#define V4L2_PIX_FMT_DIVX_311 v4l2_fourcc('D', 'I', 'V', '3') /* DIVX311 */ -#define V4L2_PIX_FMT_DIVX v4l2_fourcc('D', 'I', 'V', 'X') /* DIVX */ -#define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* for HEVC stream */ -#define V4L2_PIX_FMT_HEVC_HYBRID v4l2_fourcc('H', 'V', 'C', 'H') -#define V4L2_PIX_FMT_TME v4l2_fourcc('T', 'M', 'E', '0') /* for TME stream */ - -/* Vendor-specific formats */ -#define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */ -#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W', 'N', 'V', 'A') /* Winnov hw compress */ -#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S', '9', '1', '0') /* SN9C10x compression */ -#define V4L2_PIX_FMT_SN9C20X_I420 v4l2_fourcc('S', '9', '2', '0') /* SN9C20x YUV 4:2:0 */ -#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P', 'W', 'C', '1') /* pwc older webcam */ -#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P', 'W', 'C', '2') /* pwc newer webcam */ -#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E', '6', '2', '5') /* ET61X251 compression */ -#define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S', '5', '0', '1') /* YUYV per line */ -#define V4L2_PIX_FMT_SPCA505 v4l2_fourcc('S', '5', '0', '5') /* YYUV per line */ -#define V4L2_PIX_FMT_SPCA508 v4l2_fourcc('S', '5', '0', '8') /* YUVY per line */ -#define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S', '5', '6', '1') /* compressed GBRG bayer */ -#define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P', '2', '0', '7') /* compressed BGGR bayer */ -#define V4L2_PIX_FMT_MR97310A v4l2_fourcc('M', '3', '1', '0') /* compressed BGGR bayer */ -#define V4L2_PIX_FMT_JL2005BCD v4l2_fourcc('J', 'L', '2', '0') /* compressed RGGB bayer */ -#define V4L2_PIX_FMT_SN9C2028 v4l2_fourcc('S', 'O', 'N', 'X') /* compressed GBRG bayer */ -#define V4L2_PIX_FMT_SQ905C v4l2_fourcc('9', '0', '5', 'C') /* compressed RGGB bayer */ -#define V4L2_PIX_FMT_PJPG v4l2_fourcc('P', 'J', 'P', 'G') /* Pixart 73xx JPEG */ -#define V4L2_PIX_FMT_OV511 v4l2_fourcc('O', '5', '1', '1') /* ov511 JPEG */ -#define V4L2_PIX_FMT_OV518 v4l2_fourcc('O', '5', '1', '8') /* ov518 JPEG */ -#define V4L2_PIX_FMT_STV0680 v4l2_fourcc('S', '6', '8', '0') /* stv0680 bayer */ -#define V4L2_PIX_FMT_TM6000 v4l2_fourcc('T', 'M', '6', '0') /* tm5600/tm60x0 */ -#define V4L2_PIX_FMT_CIT_YYVYUY v4l2_fourcc('C', 'I', 'T', 'V') /* one line of Y then 1 line of VYUY */ -#define V4L2_PIX_FMT_KONICA420 v4l2_fourcc('K', 'O', 'N', 'I') /* YUV420 planar in blocks of 256 pixels */ -#define V4L2_PIX_FMT_JPGL v4l2_fourcc('J', 'P', 'G', 'L') /* JPEG-Lite */ -#define V4L2_PIX_FMT_SE401 v4l2_fourcc('S', '4', '0', '1') /* se401 janggu compressed rgb */ -#define V4L2_PIX_FMT_S5C_UYVY_JPG v4l2_fourcc('S', '5', 'C', 'I') /* S5C73M3 interleaved UYVY/JPEG */ -#define V4L2_PIX_FMT_Y8I v4l2_fourcc('Y', '8', 'I', ' ') /* Greyscale 8-bit L/R interleaved */ -#define V4L2_PIX_FMT_Y12I v4l2_fourcc('Y', '1', '2', 'I') /* Greyscale 12-bit L/R interleaved */ -#define V4L2_PIX_FMT_Z16 v4l2_fourcc('Z', '1', '6', ' ') /* Depth data 16-bit */ - -#define V4L2_PIX_FMT_SDE_ABGR_8888 \ - v4l2_fourcc('R', 'A', '2', '4') /* 32-bit ABGR 8:8:8:8 */ -#define V4L2_PIX_FMT_SDE_RGBA_8888 \ - v4l2_fourcc('A', 'B', '2', '4') /* 32-bit RGBA 8:8:8:8 */ -#define V4L2_PIX_FMT_SDE_RGBX_8888 \ - v4l2_fourcc('X', 'B', '2', '4') /* 32-bit RGBX 8:8:8:8 */ -#define V4L2_PIX_FMT_SDE_XBGR_8888 \ - v4l2_fourcc('R', 'X', '2', '4') /* 32-bit XBGR 8:8:8:8 */ -#define V4L2_PIX_FMT_SDE_RGBA_5551 \ - v4l2_fourcc('R', 'A', '1', '5') /* 16-bit RGBA 5:5:5:1 */ -#define V4L2_PIX_FMT_SDE_ABGR_1555 \ - v4l2_fourcc('A', 'B', '1', '5') /* 16-bit ABGR 1:5:5:5 */ -#define V4L2_PIX_FMT_SDE_BGRA_5551 \ - v4l2_fourcc('B', 'A', '1', '5') /* 16-bit BGRA 5:5:5:1 */ -#define V4L2_PIX_FMT_SDE_BGRX_5551 \ - v4l2_fourcc('B', 'X', '1', '5') /* 16-bit BGRX 5:5:5:1 */ -#define V4L2_PIX_FMT_SDE_RGBX_5551 \ - v4l2_fourcc('R', 'X', '1', '5') /* 16-bit RGBX 5:5:5:1 */ -#define V4L2_PIX_FMT_SDE_XBGR_1555 \ - v4l2_fourcc('X', 'B', '1', '5') /* 16-bit XBGR 1:5:5:5 */ -#define V4L2_PIX_FMT_SDE_RGBA_4444 \ - v4l2_fourcc('R', 'A', '1', '2') /* 16-bit RGBA 4:4:4:4 */ -#define V4L2_PIX_FMT_SDE_BGRA_4444 \ - v4l2_fourcc('b', 'A', '1', '2') /* 16-bit BGRA 4:4:4:4 */ -#define V4L2_PIX_FMT_SDE_ABGR_4444 \ - v4l2_fourcc('A', 'B', '1', '2') /* 16-bit ABGR 4:4:4:4 */ -#define V4L2_PIX_FMT_SDE_RGBX_4444 \ - v4l2_fourcc('R', 'X', '1', '2') /* 16-bit RGBX 4:4:4:4 */ -#define V4L2_PIX_FMT_SDE_BGRX_4444 \ - v4l2_fourcc('B', 'X', '1', '2') /* 16-bit BGRX 4:4:4:4 */ -#define V4L2_PIX_FMT_SDE_XBGR_4444 \ - v4l2_fourcc('X', 'B', '1', '2') /* 16-bit XBGR 4:4:4:4 */ -#define V4L2_PIX_FMT_SDE_BGR_565 \ - v4l2_fourcc('B', 'G', '1', '6') /* 16-bit BGR 5:6:5 */ -#define V4L2_PIX_FMT_SDE_Y_CR_CB_GH2V2 \ - v4l2_fourcc('Y', 'U', '4', '2') /* Planar YVU 4:2:0 A16 */ -#define V4L2_PIX_FMT_SDE_Y_CBCR_H1V2 \ - v4l2_fourcc('N', 'H', '1', '6') /* Y/CbCr 4:2:2 */ -#define V4L2_PIX_FMT_SDE_Y_CRCB_H1V2 \ - v4l2_fourcc('N', 'H', '6', '1') /* Y/CrCb 4:2:2 */ -#define V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_VENUS \ - v4l2_fourcc('Q', 'N', 'V', '2') /* Y/CbCr 4:2:0 Venus */ -#define V4L2_PIX_FMT_SDE_Y_CRCB_H2V2_VENUS \ - v4l2_fourcc('Q', 'N', 'V', '1') /* Y/CrCb 4:2:0 Venus */ -#define V4L2_PIX_FMT_SDE_RGBX_8888_UBWC \ - v4l2_fourcc('Q', 'X', 'B', '4') /* RGBX 8:8:8:8 UBWC */ -#define V4L2_PIX_FMT_SDE_RGB_565_UBWC \ - v4l2_fourcc('Q', 'R', 'G', '6') /* RGB 5:6:5 UBWC */ -#define V4L2_PIX_FMT_SDE_RGBA_1010102 \ - v4l2_fourcc('A', 'B', '3', '0') /* RGBA 10:10:10:2 */ -#define V4L2_PIX_FMT_SDE_RGBX_1010102 \ - v4l2_fourcc('X', 'B', '3', '0') /* RGBX 10:10:10:2 */ -#define V4L2_PIX_FMT_SDE_ARGB_2101010 \ - v4l2_fourcc('A', 'R', '3', '0') /* ARGB 2:10:10:10 */ -#define V4L2_PIX_FMT_SDE_XRGB_2101010 \ - v4l2_fourcc('X', 'R', '3', '0') /* XRGB 2:10:10:10 */ -#define V4L2_PIX_FMT_SDE_BGRA_1010102 \ - v4l2_fourcc('B', 'A', '3', '0') /* BGRA 10:10:10:2 */ -#define V4L2_PIX_FMT_SDE_BGRX_1010102 \ - v4l2_fourcc('B', 'X', '3', '0') /* BGRX 10:10:10:2 */ -#define V4L2_PIX_FMT_SDE_ABGR_2101010 \ - v4l2_fourcc('R', 'A', '3', '0') /* ABGR 2:10:10:10 */ -#define V4L2_PIX_FMT_SDE_XBGR_2101010 \ - v4l2_fourcc('R', 'X', '3', '0') /* XBGR 2:10:10:10 */ -#define V4L2_PIX_FMT_SDE_RGBA_1010102_UBWC \ - v4l2_fourcc('Q', 'R', 'B', 'A') /* RGBA 10:10:10:2 UBWC */ -#define V4L2_PIX_FMT_SDE_RGBX_1010102_UBWC \ - v4l2_fourcc('Q', 'X', 'B', 'A') /* RGBX 10:10:10:2 UBWC */ -#define V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_TP10 \ - v4l2_fourcc('T', 'P', '1', '0') /* Y/CbCr 4:2:0 TP10 */ -#define V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010 \ - v4l2_fourcc('P', '0', '1', '0') /* Y/CbCr 4:2:0 P10 */ -#define V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010_VENUS \ - v4l2_fourcc('Q', 'P', '1', '0') /* Y/CbCr 4:2:0 P10 Venus*/ - -/* SDR formats - used only for Software Defined Radio devices */ -#define V4L2_SDR_FMT_CU8 v4l2_fourcc('C', 'U', '0', '8') /* IQ u8 */ -#define V4L2_SDR_FMT_CU16LE v4l2_fourcc('C', 'U', '1', '6') /* IQ u16le */ -#define V4L2_SDR_FMT_CS8 v4l2_fourcc('C', 'S', '0', '8') /* complex s8 */ -#define V4L2_SDR_FMT_CS14LE v4l2_fourcc('C', 'S', '1', '4') /* complex s14le */ -#define V4L2_SDR_FMT_RU12LE v4l2_fourcc('R', 'U', '1', '2') /* real u12le */ - -/* Touch formats - used for Touch devices */ -#define V4L2_TCH_FMT_DELTA_TD16 v4l2_fourcc('T', 'D', '1', '6') /* 16-bit signed deltas */ -#define V4L2_TCH_FMT_DELTA_TD08 v4l2_fourcc('T', 'D', '0', '8') /* 8-bit signed deltas */ -#define V4L2_TCH_FMT_TU16 v4l2_fourcc('T', 'U', '1', '6') /* 16-bit unsigned touch data */ -#define V4L2_TCH_FMT_TU08 v4l2_fourcc('T', 'U', '0', '8') /* 8-bit unsigned touch data */ - -/* priv field value to indicates that subsequent fields are valid. */ -#define V4L2_PIX_FMT_PRIV_MAGIC 0xfeedcafe - -/* Flags */ -#define V4L2_PIX_FMT_FLAG_PREMUL_ALPHA 0x00000001 - -/* - * F O R M A T E N U M E R A T I O N - */ -struct v4l2_fmtdesc { - __u32 index; /* Format number */ - __u32 type; /* enum v4l2_buf_type */ - __u32 flags; - __u8 description[32]; /* Description string */ - __u32 pixelformat; /* Format fourcc */ - __u32 reserved[4]; -}; - -#define V4L2_FMT_FLAG_COMPRESSED 0x0001 -#define V4L2_FMT_FLAG_EMULATED 0x0002 - - /* Frame Size and frame rate enumeration */ -/* - * F R A M E S I Z E E N U M E R A T I O N - */ -enum v4l2_frmsizetypes { - V4L2_FRMSIZE_TYPE_DISCRETE = 1, - V4L2_FRMSIZE_TYPE_CONTINUOUS = 2, - V4L2_FRMSIZE_TYPE_STEPWISE = 3, -}; - -struct v4l2_frmsize_discrete { - __u32 width; /* Frame width [pixel] */ - __u32 height; /* Frame height [pixel] */ -}; - -struct v4l2_frmsize_stepwise { - __u32 min_width; /* Minimum frame width [pixel] */ - __u32 max_width; /* Maximum frame width [pixel] */ - __u32 step_width; /* Frame width step size [pixel] */ - __u32 min_height; /* Minimum frame height [pixel] */ - __u32 max_height; /* Maximum frame height [pixel] */ - __u32 step_height; /* Frame height step size [pixel] */ -}; - -struct v4l2_frmsizeenum { - __u32 index; /* Frame size number */ - __u32 pixel_format; /* Pixel format */ - __u32 type; /* Frame size type the device supports. */ - - union { /* Frame size */ - struct v4l2_frmsize_discrete discrete; - struct v4l2_frmsize_stepwise stepwise; - }; - - __u32 reserved[2]; /* Reserved space for future use */ -}; - -/* - * F R A M E R A T E E N U M E R A T I O N - */ -enum v4l2_frmivaltypes { - V4L2_FRMIVAL_TYPE_DISCRETE = 1, - V4L2_FRMIVAL_TYPE_CONTINUOUS = 2, - V4L2_FRMIVAL_TYPE_STEPWISE = 3, -}; - -struct v4l2_frmival_stepwise { - struct v4l2_fract min; /* Minimum frame interval [s] */ - struct v4l2_fract max; /* Maximum frame interval [s] */ - struct v4l2_fract step; /* Frame interval step size [s] */ -}; - -struct v4l2_frmivalenum { - __u32 index; /* Frame format index */ - __u32 pixel_format; /* Pixel format */ - __u32 width; /* Frame width */ - __u32 height; /* Frame height */ - __u32 type; /* Frame interval type the device supports. */ - - union { /* Frame interval */ - struct v4l2_fract discrete; - struct v4l2_frmival_stepwise stepwise; - }; - - __u32 reserved[2]; /* Reserved space for future use */ -}; - -/* - * T I M E C O D E - */ -struct v4l2_timecode { - __u32 type; - __u32 flags; - __u8 frames; - __u8 seconds; - __u8 minutes; - __u8 hours; - __u8 userbits[4]; -}; - -/* Type */ -#define V4L2_TC_TYPE_24FPS 1 -#define V4L2_TC_TYPE_25FPS 2 -#define V4L2_TC_TYPE_30FPS 3 -#define V4L2_TC_TYPE_50FPS 4 -#define V4L2_TC_TYPE_60FPS 5 - -/* Flags */ -#define V4L2_TC_FLAG_DROPFRAME 0x0001 /* "drop-frame" mode */ -#define V4L2_TC_FLAG_COLORFRAME 0x0002 -#define V4L2_TC_USERBITS_field 0x000C -#define V4L2_TC_USERBITS_USERDEFINED 0x0000 -#define V4L2_TC_USERBITS_8BITCHARS 0x0008 -/* The above is based on SMPTE timecodes */ - -struct v4l2_jpegcompression { - int quality; - - int APPn; /* Number of APP segment to be written, - * must be 0..15 */ - int APP_len; /* Length of data in JPEG APPn segment */ - char APP_data[60]; /* Data in the JPEG APPn segment. */ - - int COM_len; /* Length of data in JPEG COM segment */ - char COM_data[60]; /* Data in JPEG COM segment */ - - __u32 jpeg_markers; /* Which markers should go into the JPEG - * output. Unless you exactly know what - * you do, leave them untouched. - * Including less markers will make the - * resulting code smaller, but there will - * be fewer applications which can read it. - * The presence of the APP and COM marker - * is influenced by APP_len and COM_len - * ONLY, not by this property! */ - -#define V4L2_JPEG_MARKER_DHT (1<<3) /* Define Huffman Tables */ -#define V4L2_JPEG_MARKER_DQT (1<<4) /* Define Quantization Tables */ -#define V4L2_JPEG_MARKER_DRI (1<<5) /* Define Restart Interval */ -#define V4L2_JPEG_MARKER_COM (1<<6) /* Comment segment */ -#define V4L2_JPEG_MARKER_APP (1<<7) /* App segment, driver will - * always use APP0 */ -}; - -/* - * M E M O R Y - M A P P I N G B U F F E R S - */ -struct v4l2_requestbuffers { - __u32 count; - __u32 type; /* enum v4l2_buf_type */ - __u32 memory; /* enum v4l2_memory */ - __u32 reserved[2]; -}; - -/** - * struct v4l2_plane - plane info for multi-planar buffers - * @bytesused: number of bytes occupied by data in the plane (payload) - * @length: size of this plane (NOT the payload) in bytes - * @mem_offset: when memory in the associated struct v4l2_buffer is - * V4L2_MEMORY_MMAP, equals the offset from the start of - * the device memory for this plane (or is a "cookie" that - * should be passed to mmap() called on the video node) - * @userptr: when memory is V4L2_MEMORY_USERPTR, a userspace pointer - * pointing to this plane - * @fd: when memory is V4L2_MEMORY_DMABUF, a userspace file - * descriptor associated with this plane - * @data_offset: offset in the plane to the start of data; usually 0, - * unless there is a header in front of the data - * - * Multi-planar buffers consist of one or more planes, e.g. an YCbCr buffer - * with two planes can have one plane for Y, and another for interleaved CbCr - * components. Each plane can reside in a separate memory buffer, or even in - * a completely separate memory node (e.g. in embedded devices). - */ -struct v4l2_plane { - __u32 bytesused; - __u32 length; - union { - __u32 mem_offset; - unsigned long userptr; - __s32 fd; - } m; - __u32 data_offset; - __u32 reserved[11]; -}; - -/** - * struct v4l2_buffer - video buffer info - * @index: id number of the buffer - * @type: enum v4l2_buf_type; buffer type (type == *_MPLANE for - * multiplanar buffers); - * @bytesused: number of bytes occupied by data in the buffer (payload); - * unused (set to 0) for multiplanar buffers - * @flags: buffer informational flags - * @field: enum v4l2_field; field order of the image in the buffer - * @timestamp: frame timestamp - * @timecode: frame timecode - * @sequence: sequence count of this frame - * @memory: enum v4l2_memory; the method, in which the actual video data is - * passed - * @offset: for non-multiplanar buffers with memory == V4L2_MEMORY_MMAP; - * offset from the start of the device memory for this plane, - * (or a "cookie" that should be passed to mmap() as offset) - * @userptr: for non-multiplanar buffers with memory == V4L2_MEMORY_USERPTR; - * a userspace pointer pointing to this buffer - * @fd: for non-multiplanar buffers with memory == V4L2_MEMORY_DMABUF; - * a userspace file descriptor associated with this buffer - * @planes: for multiplanar buffers; userspace pointer to the array of plane - * info structs for this buffer - * @length: size in bytes of the buffer (NOT its payload) for single-plane - * buffers (when type != *_MPLANE); number of elements in the - * planes array for multi-plane buffers - * - * Contains data exchanged by application and driver using one of the Streaming - * I/O methods. - */ -struct v4l2_buffer { - __u32 index; - __u32 type; - __u32 bytesused; - __u32 flags; - __u32 field; - struct timeval timestamp; - struct v4l2_timecode timecode; - __u32 sequence; - - /* memory location */ - __u32 memory; - union { - __u32 offset; - unsigned long userptr; - struct v4l2_plane *planes; - __s32 fd; - } m; - __u32 length; - __u32 reserved2; - __u32 reserved; -}; - -/* Flags for 'flags' field */ -/* Buffer is mapped (flag) */ -#define V4L2_BUF_FLAG_MAPPED 0x00000001 -/* Buffer is queued for processing */ -#define V4L2_BUF_FLAG_QUEUED 0x00000002 -/* Buffer is ready */ -#define V4L2_BUF_FLAG_DONE 0x00000004 -/* Image is a keyframe (I-frame) */ -#define V4L2_BUF_FLAG_KEYFRAME 0x00000008 -/* Image is a P-frame */ -#define V4L2_BUF_FLAG_PFRAME 0x00000010 -/* Image is a B-frame */ -#define V4L2_BUF_FLAG_BFRAME 0x00000020 -/* Buffer is ready, but the data contained within is corrupted. */ -#define V4L2_BUF_FLAG_ERROR 0x00000040 -/* timecode field is valid */ -#define V4L2_BUF_FLAG_TIMECODE 0x00000100 -/* Buffer is prepared for queuing */ -#define V4L2_BUF_FLAG_PREPARED 0x00000400 -/* Cache handling flags */ -#define V4L2_BUF_FLAG_NO_CACHE_INVALIDATE 0x00000800 -#define V4L2_BUF_FLAG_NO_CACHE_CLEAN 0x00001000 -/* Timestamp type */ -#define V4L2_BUF_FLAG_TIMESTAMP_MASK 0x0000e000 -#define V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN 0x00000000 -#define V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC 0x00002000 -#define V4L2_BUF_FLAG_TIMESTAMP_COPY 0x00004000 -/* Timestamp sources. */ -#define V4L2_BUF_FLAG_TSTAMP_SRC_MASK 0x00070000 -#define V4L2_BUF_FLAG_TSTAMP_SRC_EOF 0x00000000 -#define V4L2_BUF_FLAG_TSTAMP_SRC_SOE 0x00010000 -/* mem2mem encoder/decoder */ -#define V4L2_BUF_FLAG_LAST 0x00100000 -/* Vendor extensions */ -#define V4L2_QCOM_BUF_END_OF_SUBFRAME 0x00000080 -#define V4L2_QCOM_BUF_FLAG_CODECCONFIG 0x00020000 -#define V4L2_QCOM_BUF_FLAG_EOSEQ 0x00040000 -#define V4L2_QCOM_BUF_TIMESTAMP_INVALID 0x00080000 -#define V4L2_MSM_BUF_FLAG_MBAFF 0x00000200 -#define V4L2_QCOM_BUF_FLAG_DECODEONLY 0x00200000 -#define V4L2_QCOM_BUF_DATA_CORRUPT 0x00400000 -#define V4L2_QCOM_BUF_DROP_FRAME 0x00800000 -#define V4L2_QCOM_BUF_INPUT_UNSUPPORTED 0x01000000 -#define V4L2_QCOM_BUF_FLAG_EOS 0x02000000 -#define V4L2_QCOM_BUF_FLAG_READONLY 0x04000000 -#define V4L2_MSM_VIDC_BUF_START_CODE_NOT_FOUND 0x08000000 -#define V4L2_MSM_BUF_FLAG_YUV_601_709_CLAMP 0x10000000 -#define V4L2_QCOM_BUF_FLAG_PERF_MODE 0x20000000 -#define V4L2_MSM_BUF_FLAG_DEFER 0x40000000 -#define V4L2_QCOM_BUF_FLAG_IDRFRAME 0x80000000 - -/** - * struct v4l2_exportbuffer - export of video buffer as DMABUF file descriptor - * - * @index: id number of the buffer - * @type: enum v4l2_buf_type; buffer type (type == *_MPLANE for - * multiplanar buffers); - * @plane: index of the plane to be exported, 0 for single plane queues - * @flags: flags for newly created file, currently only O_CLOEXEC is - * supported, refer to manual of open syscall for more details - * @fd: file descriptor associated with DMABUF (set by driver) - * - * Contains data used for exporting a video buffer as DMABUF file descriptor. - * The buffer is identified by a 'cookie' returned by VIDIOC_QUERYBUF - * (identical to the cookie used to mmap() the buffer to userspace). All - * reserved fields must be set to zero. The field reserved0 is expected to - * become a structure 'type' allowing an alternative layout of the structure - * content. Therefore this field should not be used for any other extensions. - */ -struct v4l2_exportbuffer { - __u32 type; /* enum v4l2_buf_type */ - __u32 index; - __u32 plane; - __u32 flags; - __s32 fd; - __u32 reserved[11]; -}; - -/* - * O V E R L A Y P R E V I E W - */ -struct v4l2_framebuffer { - __u32 capability; - __u32 flags; -/* FIXME: in theory we should pass something like PCI device + memory - * region + offset instead of some physical address */ - void *base; - struct { - __u32 width; - __u32 height; - __u32 pixelformat; - __u32 field; /* enum v4l2_field */ - __u32 bytesperline; /* for padding, zero if unused */ - __u32 sizeimage; - __u32 colorspace; /* enum v4l2_colorspace */ - __u32 priv; /* reserved field, set to 0 */ - } fmt; -}; -/* Flags for the 'capability' field. Read only */ -#define V4L2_FBUF_CAP_EXTERNOVERLAY 0x0001 -#define V4L2_FBUF_CAP_CHROMAKEY 0x0002 -#define V4L2_FBUF_CAP_LIST_CLIPPING 0x0004 -#define V4L2_FBUF_CAP_BITMAP_CLIPPING 0x0008 -#define V4L2_FBUF_CAP_LOCAL_ALPHA 0x0010 -#define V4L2_FBUF_CAP_GLOBAL_ALPHA 0x0020 -#define V4L2_FBUF_CAP_LOCAL_INV_ALPHA 0x0040 -#define V4L2_FBUF_CAP_SRC_CHROMAKEY 0x0080 -/* Flags for the 'flags' field. */ -#define V4L2_FBUF_FLAG_PRIMARY 0x0001 -#define V4L2_FBUF_FLAG_OVERLAY 0x0002 -#define V4L2_FBUF_FLAG_CHROMAKEY 0x0004 -#define V4L2_FBUF_FLAG_LOCAL_ALPHA 0x0008 -#define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010 -#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020 -#define V4L2_FBUF_FLAG_SRC_CHROMAKEY 0x0040 - -struct v4l2_clip { - struct v4l2_rect c; - struct v4l2_clip *next; -}; - -struct v4l2_window { - struct v4l2_rect w; - __u32 field; /* enum v4l2_field */ - __u32 chromakey; - struct v4l2_clip *clips; - __u32 clipcount; - void *bitmap; - __u8 global_alpha; -}; - -/* - * C A P T U R E P A R A M E T E R S - */ -struct v4l2_captureparm { - __u32 capability; /* Supported modes */ - __u32 capturemode; /* Current mode */ - struct v4l2_fract timeperframe; /* Time per frame in seconds */ - __u32 extendedmode; /* Driver-specific extensions */ - __u32 readbuffers; /* # of buffers for read */ - __u32 reserved[4]; -}; - -/* Flags for 'capability' and 'capturemode' fields */ -#define V4L2_MODE_HIGHQUALITY 0x0001 /* High quality imaging mode */ -#define V4L2_CAP_TIMEPERFRAME 0x1000 /* timeperframe field is supported */ - -struct v4l2_outputparm { - __u32 capability; /* Supported modes */ - __u32 outputmode; /* Current mode */ - struct v4l2_fract timeperframe; /* Time per frame in seconds */ - __u32 extendedmode; /* Driver-specific extensions */ - __u32 writebuffers; /* # of buffers for write */ - __u32 reserved[4]; -}; - -/* - * I N P U T I M A G E C R O P P I N G - */ -struct v4l2_cropcap { - __u32 type; /* enum v4l2_buf_type */ - struct v4l2_rect bounds; - struct v4l2_rect defrect; - struct v4l2_fract pixelaspect; -}; - -struct v4l2_crop { - __u32 type; /* enum v4l2_buf_type */ - struct v4l2_rect c; -}; - -/** - * struct v4l2_selection - selection info - * @type: buffer type (do not use *_MPLANE types) - * @target: Selection target, used to choose one of possible rectangles; - * defined in v4l2-common.h; V4L2_SEL_TGT_* . - * @flags: constraints flags, defined in v4l2-common.h; V4L2_SEL_FLAG_*. - * @r: coordinates of selection window - * @reserved: for future use, rounds structure size to 64 bytes, set to zero - * - * Hardware may use multiple helper windows to process a video stream. - * The structure is used to exchange this selection areas between - * an application and a driver. - */ -struct v4l2_selection { - __u32 type; - __u32 target; - __u32 flags; - struct v4l2_rect r; - __u32 reserved[9]; -}; - - -/* - * A N A L O G V I D E O S T A N D A R D - */ - -typedef __u64 v4l2_std_id; - -/* one bit for each */ -#define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001) -#define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002) -#define V4L2_STD_PAL_G ((v4l2_std_id)0x00000004) -#define V4L2_STD_PAL_H ((v4l2_std_id)0x00000008) -#define V4L2_STD_PAL_I ((v4l2_std_id)0x00000010) -#define V4L2_STD_PAL_D ((v4l2_std_id)0x00000020) -#define V4L2_STD_PAL_D1 ((v4l2_std_id)0x00000040) -#define V4L2_STD_PAL_K ((v4l2_std_id)0x00000080) - -#define V4L2_STD_PAL_M ((v4l2_std_id)0x00000100) -#define V4L2_STD_PAL_N ((v4l2_std_id)0x00000200) -#define V4L2_STD_PAL_Nc ((v4l2_std_id)0x00000400) -#define V4L2_STD_PAL_60 ((v4l2_std_id)0x00000800) - -#define V4L2_STD_NTSC_M ((v4l2_std_id)0x00001000) /* BTSC */ -#define V4L2_STD_NTSC_M_JP ((v4l2_std_id)0x00002000) /* EIA-J */ -#define V4L2_STD_NTSC_443 ((v4l2_std_id)0x00004000) -#define V4L2_STD_NTSC_M_KR ((v4l2_std_id)0x00008000) /* FM A2 */ - -#define V4L2_STD_SECAM_B ((v4l2_std_id)0x00010000) -#define V4L2_STD_SECAM_D ((v4l2_std_id)0x00020000) -#define V4L2_STD_SECAM_G ((v4l2_std_id)0x00040000) -#define V4L2_STD_SECAM_H ((v4l2_std_id)0x00080000) -#define V4L2_STD_SECAM_K ((v4l2_std_id)0x00100000) -#define V4L2_STD_SECAM_K1 ((v4l2_std_id)0x00200000) -#define V4L2_STD_SECAM_L ((v4l2_std_id)0x00400000) -#define V4L2_STD_SECAM_LC ((v4l2_std_id)0x00800000) - -/* ATSC/HDTV */ -#define V4L2_STD_ATSC_8_VSB ((v4l2_std_id)0x01000000) -#define V4L2_STD_ATSC_16_VSB ((v4l2_std_id)0x02000000) - -/* FIXME: - Although std_id is 64 bits, there is an issue on PPC32 architecture that - makes switch(__u64) to break. So, there's a hack on v4l2-common.c rounding - this value to 32 bits. - As, currently, the max value is for V4L2_STD_ATSC_16_VSB (30 bits wide), - it should work fine. However, if needed to add more than two standards, - v4l2-common.c should be fixed. - */ - -/* - * Some macros to merge video standards in order to make live easier for the - * drivers and V4L2 applications - */ - -/* - * "Common" NTSC/M - It should be noticed that V4L2_STD_NTSC_443 is - * Missing here. - */ -#define V4L2_STD_NTSC (V4L2_STD_NTSC_M |\ - V4L2_STD_NTSC_M_JP |\ - V4L2_STD_NTSC_M_KR) -/* Secam macros */ -#define V4L2_STD_SECAM_DK (V4L2_STD_SECAM_D |\ - V4L2_STD_SECAM_K |\ - V4L2_STD_SECAM_K1) -/* All Secam Standards */ -#define V4L2_STD_SECAM (V4L2_STD_SECAM_B |\ - V4L2_STD_SECAM_G |\ - V4L2_STD_SECAM_H |\ - V4L2_STD_SECAM_DK |\ - V4L2_STD_SECAM_L |\ - V4L2_STD_SECAM_LC) -/* PAL macros */ -#define V4L2_STD_PAL_BG (V4L2_STD_PAL_B |\ - V4L2_STD_PAL_B1 |\ - V4L2_STD_PAL_G) -#define V4L2_STD_PAL_DK (V4L2_STD_PAL_D |\ - V4L2_STD_PAL_D1 |\ - V4L2_STD_PAL_K) -/* - * "Common" PAL - This macro is there to be compatible with the old - * V4L1 concept of "PAL": /BGDKHI. - * Several PAL standards are missing here: /M, /N and /Nc - */ -#define V4L2_STD_PAL (V4L2_STD_PAL_BG |\ - V4L2_STD_PAL_DK |\ - V4L2_STD_PAL_H |\ - V4L2_STD_PAL_I) -/* Chroma "agnostic" standards */ -#define V4L2_STD_B (V4L2_STD_PAL_B |\ - V4L2_STD_PAL_B1 |\ - V4L2_STD_SECAM_B) -#define V4L2_STD_G (V4L2_STD_PAL_G |\ - V4L2_STD_SECAM_G) -#define V4L2_STD_H (V4L2_STD_PAL_H |\ - V4L2_STD_SECAM_H) -#define V4L2_STD_L (V4L2_STD_SECAM_L |\ - V4L2_STD_SECAM_LC) -#define V4L2_STD_GH (V4L2_STD_G |\ - V4L2_STD_H) -#define V4L2_STD_DK (V4L2_STD_PAL_DK |\ - V4L2_STD_SECAM_DK) -#define V4L2_STD_BG (V4L2_STD_B |\ - V4L2_STD_G) -#define V4L2_STD_MN (V4L2_STD_PAL_M |\ - V4L2_STD_PAL_N |\ - V4L2_STD_PAL_Nc |\ - V4L2_STD_NTSC) - -/* Standards where MTS/BTSC stereo could be found */ -#define V4L2_STD_MTS (V4L2_STD_NTSC_M |\ - V4L2_STD_PAL_M |\ - V4L2_STD_PAL_N |\ - V4L2_STD_PAL_Nc) - -/* Standards for Countries with 60Hz Line frequency */ -#define V4L2_STD_525_60 (V4L2_STD_PAL_M |\ - V4L2_STD_PAL_60 |\ - V4L2_STD_NTSC |\ - V4L2_STD_NTSC_443) -/* Standards for Countries with 50Hz Line frequency */ -#define V4L2_STD_625_50 (V4L2_STD_PAL |\ - V4L2_STD_PAL_N |\ - V4L2_STD_PAL_Nc |\ - V4L2_STD_SECAM) - -#define V4L2_STD_ATSC (V4L2_STD_ATSC_8_VSB |\ - V4L2_STD_ATSC_16_VSB) -/* Macros with none and all analog standards */ -#define V4L2_STD_UNKNOWN 0 -#define V4L2_STD_ALL (V4L2_STD_525_60 |\ - V4L2_STD_625_50) - -struct v4l2_standard { - __u32 index; - v4l2_std_id id; - __u8 name[24]; - struct v4l2_fract frameperiod; /* Frames, not fields */ - __u32 framelines; - __u32 reserved[4]; -}; - -/* - * D V B T T I M I N G S - */ - -/** struct v4l2_bt_timings - BT.656/BT.1120 timing data - * @width: total width of the active video in pixels - * @height: total height of the active video in lines - * @interlaced: Interlaced or progressive - * @polarities: Positive or negative polarities - * @pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000 - * @hfrontporch:Horizontal front porch in pixels - * @hsync: Horizontal Sync length in pixels - * @hbackporch: Horizontal back porch in pixels - * @vfrontporch:Vertical front porch in lines - * @vsync: Vertical Sync length in lines - * @vbackporch: Vertical back porch in lines - * @il_vfrontporch:Vertical front porch for the even field - * (aka field 2) of interlaced field formats - * @il_vsync: Vertical Sync length for the even field - * (aka field 2) of interlaced field formats - * @il_vbackporch:Vertical back porch for the even field - * (aka field 2) of interlaced field formats - * @standards: Standards the timing belongs to - * @flags: Flags - * @reserved: Reserved fields, must be zeroed. - * - * A note regarding vertical interlaced timings: height refers to the total - * height of the active video frame (= two fields). The blanking timings refer - * to the blanking of each field. So the height of the total frame is - * calculated as follows: - * - * tot_height = height + vfrontporch + vsync + vbackporch + - * il_vfrontporch + il_vsync + il_vbackporch - * - * The active height of each field is height / 2. - */ -struct v4l2_bt_timings { - __u32 width; - __u32 height; - __u32 interlaced; - __u32 polarities; - __u64 pixelclock; - __u32 hfrontporch; - __u32 hsync; - __u32 hbackporch; - __u32 vfrontporch; - __u32 vsync; - __u32 vbackporch; - __u32 il_vfrontporch; - __u32 il_vsync; - __u32 il_vbackporch; - __u32 standards; - __u32 flags; - __u32 reserved[14]; -} __attribute__ ((packed)); - -/* Interlaced or progressive format */ -#define V4L2_DV_PROGRESSIVE 0 -#define V4L2_DV_INTERLACED 1 - -/* Polarities. If bit is not set, it is assumed to be negative polarity */ -#define V4L2_DV_VSYNC_POS_POL 0x00000001 -#define V4L2_DV_HSYNC_POS_POL 0x00000002 - -/* Timings standards */ -#define V4L2_DV_BT_STD_CEA861 (1 << 0) /* CEA-861 Digital TV Profile */ -#define V4L2_DV_BT_STD_DMT (1 << 1) /* VESA Discrete Monitor Timings */ -#define V4L2_DV_BT_STD_CVT (1 << 2) /* VESA Coordinated Video Timings */ -#define V4L2_DV_BT_STD_GTF (1 << 3) /* VESA Generalized Timings Formula */ -#define V4L2_DV_BT_STD_SDI (1 << 4) /* SDI Timings */ - -/* Flags */ - -/* CVT/GTF specific: timing uses reduced blanking (CVT) or the 'Secondary - GTF' curve (GTF). In both cases the horizontal and/or vertical blanking - intervals are reduced, allowing a higher resolution over the same - bandwidth. This is a read-only flag. */ -#define V4L2_DV_FL_REDUCED_BLANKING (1 << 0) -/* CEA-861 specific: set for CEA-861 formats with a framerate of a multiple - of six. These formats can be optionally played at 1 / 1.001 speed. - This is a read-only flag. */ -#define V4L2_DV_FL_CAN_REDUCE_FPS (1 << 1) -/* CEA-861 specific: only valid for video transmitters, the flag is cleared - by receivers. - If the framerate of the format is a multiple of six, then the pixelclock - used to set up the transmitter is divided by 1.001 to make it compatible - with 60 Hz based standards such as NTSC and PAL-M that use a framerate of - 29.97 Hz. Otherwise this flag is cleared. If the transmitter can't generate - such frequencies, then the flag will also be cleared. */ -#define V4L2_DV_FL_REDUCED_FPS (1 << 2) -/* Specific to interlaced formats: if set, then field 1 is really one half-line - longer and field 2 is really one half-line shorter, so each field has - exactly the same number of half-lines. Whether half-lines can be detected - or used depends on the hardware. */ -#define V4L2_DV_FL_HALF_LINE (1 << 3) -/* If set, then this is a Consumer Electronics (CE) video format. Such formats - * differ from other formats (commonly called IT formats) in that if RGB - * encoding is used then by default the RGB values use limited range (i.e. - * use the range 16-235) as opposed to 0-255. All formats defined in CEA-861 - * except for the 640x480 format are CE formats. */ -#define V4L2_DV_FL_IS_CE_VIDEO (1 << 4) -/* Some formats like SMPTE-125M have an interlaced signal with a odd - * total height. For these formats, if this flag is set, the first - * field has the extra line. If not, it is the second field. - */ -#define V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE (1 << 5) - -/* A few useful defines to calculate the total blanking and frame sizes */ -#define V4L2_DV_BT_BLANKING_WIDTH(bt) \ - ((bt)->hfrontporch + (bt)->hsync + (bt)->hbackporch) -#define V4L2_DV_BT_FRAME_WIDTH(bt) \ - ((bt)->width + V4L2_DV_BT_BLANKING_WIDTH(bt)) -#define V4L2_DV_BT_BLANKING_HEIGHT(bt) \ - ((bt)->vfrontporch + (bt)->vsync + (bt)->vbackporch + \ - (bt)->il_vfrontporch + (bt)->il_vsync + (bt)->il_vbackporch) -#define V4L2_DV_BT_FRAME_HEIGHT(bt) \ - ((bt)->height + V4L2_DV_BT_BLANKING_HEIGHT(bt)) - -/** struct v4l2_dv_timings - DV timings - * @type: the type of the timings - * @bt: BT656/1120 timings - */ -struct v4l2_dv_timings { - __u32 type; - union { - struct v4l2_bt_timings bt; - __u32 reserved[32]; - }; -} __attribute__ ((packed)); - -/* Values for the type field */ -#define V4L2_DV_BT_656_1120 0 /* BT.656/1120 timing type */ - - -/** struct v4l2_enum_dv_timings - DV timings enumeration - * @index: enumeration index - * @pad: the pad number for which to enumerate timings (used with - * v4l-subdev nodes only) - * @reserved: must be zeroed - * @timings: the timings for the given index - */ -struct v4l2_enum_dv_timings { - __u32 index; - __u32 pad; - __u32 reserved[2]; - struct v4l2_dv_timings timings; -}; - -/** struct v4l2_bt_timings_cap - BT.656/BT.1120 timing capabilities - * @min_width: width in pixels - * @max_width: width in pixels - * @min_height: height in lines - * @max_height: height in lines - * @min_pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000 - * @max_pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000 - * @standards: Supported standards - * @capabilities: Supported capabilities - * @reserved: Must be zeroed - */ -struct v4l2_bt_timings_cap { - __u32 min_width; - __u32 max_width; - __u32 min_height; - __u32 max_height; - __u64 min_pixelclock; - __u64 max_pixelclock; - __u32 standards; - __u32 capabilities; - __u32 reserved[16]; -} __attribute__ ((packed)); - -/* Supports interlaced formats */ -#define V4L2_DV_BT_CAP_INTERLACED (1 << 0) -/* Supports progressive formats */ -#define V4L2_DV_BT_CAP_PROGRESSIVE (1 << 1) -/* Supports CVT/GTF reduced blanking */ -#define V4L2_DV_BT_CAP_REDUCED_BLANKING (1 << 2) -/* Supports custom formats */ -#define V4L2_DV_BT_CAP_CUSTOM (1 << 3) - -/** struct v4l2_dv_timings_cap - DV timings capabilities - * @type: the type of the timings (same as in struct v4l2_dv_timings) - * @pad: the pad number for which to query capabilities (used with - * v4l-subdev nodes only) - * @bt: the BT656/1120 timings capabilities - */ -struct v4l2_dv_timings_cap { - __u32 type; - __u32 pad; - __u32 reserved[2]; - union { - struct v4l2_bt_timings_cap bt; - __u32 raw_data[32]; - }; -}; - - -/* - * V I D E O I N P U T S - */ -struct v4l2_input { - __u32 index; /* Which input */ - __u8 name[32]; /* Label */ - __u32 type; /* Type of input */ - __u32 audioset; /* Associated audios (bitfield) */ - __u32 tuner; /* enum v4l2_tuner_type */ - v4l2_std_id std; - __u32 status; - __u32 capabilities; - __u32 reserved[3]; -}; - -/* Values for the 'type' field */ -#define V4L2_INPUT_TYPE_TUNER 1 -#define V4L2_INPUT_TYPE_CAMERA 2 -#define V4L2_INPUT_TYPE_TOUCH 3 - -/* field 'status' - general */ -#define V4L2_IN_ST_NO_POWER 0x00000001 /* Attached device is off */ -#define V4L2_IN_ST_NO_SIGNAL 0x00000002 -#define V4L2_IN_ST_NO_COLOR 0x00000004 - -/* field 'status' - sensor orientation */ -/* If sensor is mounted upside down set both bits */ -#define V4L2_IN_ST_HFLIP 0x00000010 /* Frames are flipped horizontally */ -#define V4L2_IN_ST_VFLIP 0x00000020 /* Frames are flipped vertically */ - -/* field 'status' - analog */ -#define V4L2_IN_ST_NO_H_LOCK 0x00000100 /* No horizontal sync lock */ -#define V4L2_IN_ST_COLOR_KILL 0x00000200 /* Color killer is active */ -#define V4L2_IN_ST_NO_V_LOCK 0x00000400 /* No vertical sync lock */ -#define V4L2_IN_ST_NO_STD_LOCK 0x00000800 /* No standard format lock */ - -/* field 'status' - digital */ -#define V4L2_IN_ST_NO_SYNC 0x00010000 /* No synchronization lock */ -#define V4L2_IN_ST_NO_EQU 0x00020000 /* No equalizer lock */ -#define V4L2_IN_ST_NO_CARRIER 0x00040000 /* Carrier recovery failed */ - -/* field 'status' - VCR and set-top box */ -#define V4L2_IN_ST_MACROVISION 0x01000000 /* Macrovision detected */ -#define V4L2_IN_ST_NO_ACCESS 0x02000000 /* Conditional access denied */ -#define V4L2_IN_ST_VTR 0x04000000 /* VTR time constant */ - -/* capabilities flags */ -#define V4L2_IN_CAP_DV_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ -#define V4L2_IN_CAP_CUSTOM_TIMINGS V4L2_IN_CAP_DV_TIMINGS /* For compatibility */ -#define V4L2_IN_CAP_STD 0x00000004 /* Supports S_STD */ -#define V4L2_IN_CAP_NATIVE_SIZE 0x00000008 /* Supports setting native size */ - -/* - * V I D E O O U T P U T S - */ -struct v4l2_output { - __u32 index; /* Which output */ - __u8 name[32]; /* Label */ - __u32 type; /* Type of output */ - __u32 audioset; /* Associated audios (bitfield) */ - __u32 modulator; /* Associated modulator */ - v4l2_std_id std; - __u32 capabilities; - __u32 reserved[3]; -}; -/* Values for the 'type' field */ -#define V4L2_OUTPUT_TYPE_MODULATOR 1 -#define V4L2_OUTPUT_TYPE_ANALOG 2 -#define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY 3 - -/* capabilities flags */ -#define V4L2_OUT_CAP_DV_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ -#define V4L2_OUT_CAP_CUSTOM_TIMINGS V4L2_OUT_CAP_DV_TIMINGS /* For compatibility */ -#define V4L2_OUT_CAP_STD 0x00000004 /* Supports S_STD */ -#define V4L2_OUT_CAP_NATIVE_SIZE 0x00000008 /* Supports setting native size */ - -/* - * C O N T R O L S - */ -struct v4l2_control { - __u32 id; - __s32 value; -}; - -struct v4l2_ext_control { - __u32 id; - __u32 size; - __u32 reserved2[1]; - union { - __s32 value; - __s64 value64; - char *string; - __u8 *p_u8; - __u16 *p_u16; - __u32 *p_u32; - void *ptr; - }; -} __attribute__ ((packed)); - -struct v4l2_ext_controls { - union { - __u32 ctrl_class; - __u32 which; - }; - __u32 count; - __u32 error_idx; - __u32 reserved[2]; - struct v4l2_ext_control *controls; -}; - -#define V4L2_CTRL_ID_MASK (0x0fffffff) -#define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL) -#define V4L2_CTRL_ID2WHICH(id) ((id) & 0x0fff0000UL) -#define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000) -#define V4L2_CTRL_MAX_DIMS (4) -#define V4L2_CTRL_WHICH_CUR_VAL 0 -#define V4L2_CTRL_WHICH_DEF_VAL 0x0f000000 - -enum v4l2_ctrl_type { - V4L2_CTRL_TYPE_INTEGER = 1, - V4L2_CTRL_TYPE_BOOLEAN = 2, - V4L2_CTRL_TYPE_MENU = 3, - V4L2_CTRL_TYPE_BUTTON = 4, - V4L2_CTRL_TYPE_INTEGER64 = 5, - V4L2_CTRL_TYPE_CTRL_CLASS = 6, - V4L2_CTRL_TYPE_STRING = 7, - V4L2_CTRL_TYPE_BITMASK = 8, - V4L2_CTRL_TYPE_INTEGER_MENU = 9, - - /* Compound types are >= 0x0100 */ - V4L2_CTRL_COMPOUND_TYPES = 0x0100, - V4L2_CTRL_TYPE_U8 = 0x0100, - V4L2_CTRL_TYPE_U16 = 0x0101, - V4L2_CTRL_TYPE_U32 = 0x0102, -}; - -/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ -struct v4l2_queryctrl { - __u32 id; - __u32 type; /* enum v4l2_ctrl_type */ - __u8 name[32]; /* Whatever */ - __s32 minimum; /* Note signedness */ - __s32 maximum; - __s32 step; - __s32 default_value; - __u32 flags; - __u32 reserved[2]; -}; - -/* Used in the VIDIOC_QUERY_EXT_CTRL ioctl for querying extended controls */ -struct v4l2_query_ext_ctrl { - __u32 id; - __u32 type; - char name[32]; - __s64 minimum; - __s64 maximum; - __u64 step; - __s64 default_value; - __u32 flags; - __u32 elem_size; - __u32 elems; - __u32 nr_of_dims; - __u32 dims[V4L2_CTRL_MAX_DIMS]; - __u32 reserved[32]; -}; - -/* Used in the VIDIOC_QUERYMENU ioctl for querying menu items */ -struct v4l2_querymenu { - __u32 id; - __u32 index; - union { - __u8 name[32]; /* Whatever */ - __s64 value; - }; - __u32 reserved; -} __attribute__ ((packed)); - -/* Control flags */ -#define V4L2_CTRL_FLAG_DISABLED 0x0001 -#define V4L2_CTRL_FLAG_GRABBED 0x0002 -#define V4L2_CTRL_FLAG_READ_ONLY 0x0004 -#define V4L2_CTRL_FLAG_UPDATE 0x0008 -#define V4L2_CTRL_FLAG_INACTIVE 0x0010 -#define V4L2_CTRL_FLAG_SLIDER 0x0020 -#define V4L2_CTRL_FLAG_WRITE_ONLY 0x0040 -#define V4L2_CTRL_FLAG_VOLATILE 0x0080 -#define V4L2_CTRL_FLAG_HAS_PAYLOAD 0x0100 -#define V4L2_CTRL_FLAG_EXECUTE_ON_WRITE 0x0200 - -/* Query flags, to be ORed with the control ID */ -#define V4L2_CTRL_FLAG_NEXT_CTRL 0x80000000 -#define V4L2_CTRL_FLAG_NEXT_COMPOUND 0x40000000 - -/* User-class control IDs defined by V4L2 */ -#define V4L2_CID_MAX_CTRLS 1024 -/* IDs reserved for driver specific controls */ -#define V4L2_CID_PRIVATE_BASE 0x08000000 - - -/* - * T U N I N G - */ -struct v4l2_tuner { - __u32 index; - __u8 name[32]; - __u32 type; /* enum v4l2_tuner_type */ - __u32 capability; - __u32 rangelow; - __u32 rangehigh; - __u32 rxsubchans; - __u32 audmode; - __s32 signal; - __s32 afc; - __u32 reserved[4]; -}; - -struct v4l2_modulator { - __u32 index; - __u8 name[32]; - __u32 capability; - __u32 rangelow; - __u32 rangehigh; - __u32 txsubchans; - __u32 type; /* enum v4l2_tuner_type */ - __u32 reserved[3]; -}; - -/* Flags for the 'capability' field */ -#define V4L2_TUNER_CAP_LOW 0x0001 -#define V4L2_TUNER_CAP_NORM 0x0002 -#define V4L2_TUNER_CAP_HWSEEK_BOUNDED 0x0004 -#define V4L2_TUNER_CAP_HWSEEK_WRAP 0x0008 -#define V4L2_TUNER_CAP_STEREO 0x0010 -#define V4L2_TUNER_CAP_LANG2 0x0020 -#define V4L2_TUNER_CAP_SAP 0x0020 -#define V4L2_TUNER_CAP_LANG1 0x0040 -#define V4L2_TUNER_CAP_RDS 0x0080 -#define V4L2_TUNER_CAP_RDS_BLOCK_IO 0x0100 -#define V4L2_TUNER_CAP_RDS_CONTROLS 0x0200 -#define V4L2_TUNER_CAP_FREQ_BANDS 0x0400 -#define V4L2_TUNER_CAP_HWSEEK_PROG_LIM 0x0800 -#define V4L2_TUNER_CAP_1HZ 0x1000 - -/* Flags for the 'rxsubchans' field */ -#define V4L2_TUNER_SUB_MONO 0x0001 -#define V4L2_TUNER_SUB_STEREO 0x0002 -#define V4L2_TUNER_SUB_LANG2 0x0004 -#define V4L2_TUNER_SUB_SAP 0x0004 -#define V4L2_TUNER_SUB_LANG1 0x0008 -#define V4L2_TUNER_SUB_RDS 0x0010 - -/* Values for the 'audmode' field */ -#define V4L2_TUNER_MODE_MONO 0x0000 -#define V4L2_TUNER_MODE_STEREO 0x0001 -#define V4L2_TUNER_MODE_LANG2 0x0002 -#define V4L2_TUNER_MODE_SAP 0x0002 -#define V4L2_TUNER_MODE_LANG1 0x0003 -#define V4L2_TUNER_MODE_LANG1_LANG2 0x0004 - -struct v4l2_frequency { - __u32 tuner; - __u32 type; /* enum v4l2_tuner_type */ - __u32 frequency; - __u32 reserved[8]; -}; - -#define V4L2_BAND_MODULATION_VSB (1 << 1) -#define V4L2_BAND_MODULATION_FM (1 << 2) -#define V4L2_BAND_MODULATION_AM (1 << 3) - -struct v4l2_frequency_band { - __u32 tuner; - __u32 type; /* enum v4l2_tuner_type */ - __u32 index; - __u32 capability; - __u32 rangelow; - __u32 rangehigh; - __u32 modulation; - __u32 reserved[9]; -}; - -struct v4l2_hw_freq_seek { - __u32 tuner; - __u32 type; /* enum v4l2_tuner_type */ - __u32 seek_upward; - __u32 wrap_around; - __u32 spacing; - __u32 rangelow; - __u32 rangehigh; - __u32 reserved[5]; -}; - -/* - * R D S - */ - -struct v4l2_rds_data { - __u8 lsb; - __u8 msb; - __u8 block; -} __attribute__ ((packed)); - -#define V4L2_RDS_BLOCK_MSK 0x7 -#define V4L2_RDS_BLOCK_A 0 -#define V4L2_RDS_BLOCK_B 1 -#define V4L2_RDS_BLOCK_C 2 -#define V4L2_RDS_BLOCK_D 3 -#define V4L2_RDS_BLOCK_C_ALT 4 -#define V4L2_RDS_BLOCK_INVALID 7 - -#define V4L2_RDS_BLOCK_CORRECTED 0x40 -#define V4L2_RDS_BLOCK_ERROR 0x80 - -/* - * A U D I O - */ -struct v4l2_audio { - __u32 index; - __u8 name[32]; - __u32 capability; - __u32 mode; - __u32 reserved[2]; -}; - -/* Flags for the 'capability' field */ -#define V4L2_AUDCAP_STEREO 0x00001 -#define V4L2_AUDCAP_AVL 0x00002 - -/* Flags for the 'mode' field */ -#define V4L2_AUDMODE_AVL 0x00001 - -struct v4l2_audioout { - __u32 index; - __u8 name[32]; - __u32 capability; - __u32 mode; - __u32 reserved[2]; -}; - -/* - * M P E G S E R V I C E S - */ -#if 1 -#define V4L2_ENC_IDX_FRAME_I (0) -#define V4L2_ENC_IDX_FRAME_P (1) -#define V4L2_ENC_IDX_FRAME_B (2) -#define V4L2_ENC_IDX_FRAME_MASK (0xf) - -struct v4l2_enc_idx_entry { - __u64 offset; - __u64 pts; - __u32 length; - __u32 flags; - __u32 reserved[2]; -}; - -#define V4L2_ENC_IDX_ENTRIES (64) -struct v4l2_enc_idx { - __u32 entries; - __u32 entries_cap; - __u32 reserved[4]; - struct v4l2_enc_idx_entry entry[V4L2_ENC_IDX_ENTRIES]; -}; - - -#define V4L2_ENC_CMD_START (0) -#define V4L2_ENC_CMD_STOP (1) -#define V4L2_ENC_CMD_PAUSE (2) -#define V4L2_ENC_CMD_RESUME (3) - -/* Flags for V4L2_ENC_CMD_STOP */ -#define V4L2_ENC_CMD_STOP_AT_GOP_END (1 << 0) - -struct v4l2_encoder_cmd { - __u32 cmd; - __u32 flags; - union { - struct { - __u32 data[8]; - } raw; - }; -}; - -/* Decoder commands */ -#define V4L2_DEC_CMD_START (0) -#define V4L2_DEC_CMD_STOP (1) -#define V4L2_DEC_CMD_PAUSE (2) -#define V4L2_DEC_CMD_RESUME (3) -#define V4L2_QCOM_CMD_FLUSH (4) -#define V4L2_DEC_QCOM_CMD_RECONFIG_HINT (5) -#define V4L2_QCOM_CMD_SESSION_CONTINUE (6) -/* Flags for V4L2_DEC_CMD_START */ -#define V4L2_DEC_CMD_START_MUTE_AUDIO (1 << 0) - -/* Flags for V4L2_DEC_CMD_PAUSE */ -#define V4L2_DEC_CMD_PAUSE_TO_BLACK (1 << 0) - -/* Flags for V4L2_DEC_CMD_STOP */ -#define V4L2_DEC_CMD_STOP_TO_BLACK (1 << 0) -#define V4L2_DEC_CMD_STOP_IMMEDIATELY (1 << 1) - -#define V4L2_QCOM_CMD_FLUSH_OUTPUT (1 << 0) -#define V4L2_QCOM_CMD_FLUSH_CAPTURE (1 << 1) - -/* Play format requirements (returned by the driver): */ - -/* The decoder has no special format requirements */ -#define V4L2_DEC_START_FMT_NONE (0) -/* The decoder requires full GOPs */ -#define V4L2_DEC_START_FMT_GOP (1) - -/* The structure must be zeroed before use by the application - This ensures it can be extended safely in the future. */ -struct v4l2_decoder_cmd { - __u32 cmd; - __u32 flags; - union { - struct { - __u64 pts; - } stop; - - struct { - /* 0 or 1000 specifies normal speed, - 1 specifies forward single stepping, - -1 specifies backward single stepping, - >1: playback at speed/1000 of the normal speed, - <-1: reverse playback at (-speed/1000) of the normal speed. */ - __s32 speed; - __u32 format; - } start; - - struct { - __u32 data[16]; - } raw; - }; -}; -#endif - - -/* - * D A T A S E R V I C E S ( V B I ) - * - * Data services API by Michael Schimek - */ - -/* Raw VBI */ -struct v4l2_vbi_format { - __u32 sampling_rate; /* in 1 Hz */ - __u32 offset; - __u32 samples_per_line; - __u32 sample_format; /* V4L2_PIX_FMT_* */ - __s32 start[2]; - __u32 count[2]; - __u32 flags; /* V4L2_VBI_* */ - __u32 reserved[2]; /* must be zero */ -}; - -/* VBI flags */ -#define V4L2_VBI_UNSYNC (1 << 0) -#define V4L2_VBI_INTERLACED (1 << 1) - -/* ITU-R start lines for each field */ -#define V4L2_VBI_ITU_525_F1_START (1) -#define V4L2_VBI_ITU_525_F2_START (264) -#define V4L2_VBI_ITU_625_F1_START (1) -#define V4L2_VBI_ITU_625_F2_START (314) - -/* Sliced VBI - * - * This implements is a proposal V4L2 API to allow SLICED VBI - * required for some hardware encoders. It should change without - * notice in the definitive implementation. - */ - -struct v4l2_sliced_vbi_format { - __u16 service_set; - /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field - service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field - (equals frame lines 313-336 for 625 line video - standards, 263-286 for 525 line standards) */ - __u16 service_lines[2][24]; - __u32 io_size; - __u32 reserved[2]; /* must be zero */ -}; - -/* Teletext World System Teletext - (WST), defined on ITU-R BT.653-2 */ -#define V4L2_SLICED_TELETEXT_B (0x0001) -/* Video Program System, defined on ETS 300 231*/ -#define V4L2_SLICED_VPS (0x0400) -/* Closed Caption, defined on EIA-608 */ -#define V4L2_SLICED_CAPTION_525 (0x1000) -/* Wide Screen System, defined on ITU-R BT1119.1 */ -#define V4L2_SLICED_WSS_625 (0x4000) - -#define V4L2_SLICED_VBI_525 (V4L2_SLICED_CAPTION_525) -#define V4L2_SLICED_VBI_625 (V4L2_SLICED_TELETEXT_B | V4L2_SLICED_VPS | V4L2_SLICED_WSS_625) - -struct v4l2_sliced_vbi_cap { - __u16 service_set; - /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field - service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field - (equals frame lines 313-336 for 625 line video - standards, 263-286 for 525 line standards) */ - __u16 service_lines[2][24]; - __u32 type; /* enum v4l2_buf_type */ - __u32 reserved[3]; /* must be 0 */ -}; - -struct v4l2_sliced_vbi_data { - __u32 id; - __u32 field; /* 0: first field, 1: second field */ - __u32 line; /* 1-23 */ - __u32 reserved; /* must be 0 */ - __u8 data[48]; -}; - -/* - * Sliced VBI data inserted into MPEG Streams - */ - -/* - * V4L2_MPEG_STREAM_VBI_FMT_IVTV: - * - * Structure of payload contained in an MPEG 2 Private Stream 1 PES Packet in an - * MPEG-2 Program Pack that contains V4L2_MPEG_STREAM_VBI_FMT_IVTV Sliced VBI - * data - * - * Note, the MPEG-2 Program Pack and Private Stream 1 PES packet header - * definitions are not included here. See the MPEG-2 specifications for details - * on these headers. - */ - -/* Line type IDs */ -#define V4L2_MPEG_VBI_IVTV_TELETEXT_B (1) -#define V4L2_MPEG_VBI_IVTV_CAPTION_525 (4) -#define V4L2_MPEG_VBI_IVTV_WSS_625 (5) -#define V4L2_MPEG_VBI_IVTV_VPS (7) - -struct v4l2_mpeg_vbi_itv0_line { - __u8 id; /* One of V4L2_MPEG_VBI_IVTV_* above */ - __u8 data[42]; /* Sliced VBI data for the line */ -} __attribute__ ((packed)); - -struct v4l2_mpeg_vbi_itv0 { - __le32 linemask[2]; /* Bitmasks of VBI service lines present */ - struct v4l2_mpeg_vbi_itv0_line line[35]; -} __attribute__ ((packed)); - -struct v4l2_mpeg_vbi_ITV0 { - struct v4l2_mpeg_vbi_itv0_line line[36]; -} __attribute__ ((packed)); - -#define V4L2_MPEG_VBI_IVTV_MAGIC0 "itv0" -#define V4L2_MPEG_VBI_IVTV_MAGIC1 "ITV0" - -struct v4l2_mpeg_vbi_fmt_ivtv { - __u8 magic[4]; - union { - struct v4l2_mpeg_vbi_itv0 itv0; - struct v4l2_mpeg_vbi_ITV0 ITV0; - }; -} __attribute__ ((packed)); - -/* - * A G G R E G A T E S T R U C T U R E S - */ - -/** - * struct v4l2_plane_pix_format - additional, per-plane format definition - * @sizeimage: maximum size in bytes required for data, for which - * this plane will be used - * @bytesperline: distance in bytes between the leftmost pixels in two - * adjacent lines - */ -struct v4l2_plane_pix_format { - __u32 sizeimage; - __u32 bytesperline; - __u16 reserved[6]; -} __attribute__ ((packed)); - -/** - * struct v4l2_pix_format_mplane - multiplanar format definition - * @width: image width in pixels - * @height: image height in pixels - * @pixelformat: little endian four character code (fourcc) - * @field: enum v4l2_field; field order (for interlaced video) - * @colorspace: enum v4l2_colorspace; supplemental to pixelformat - * @plane_fmt: per-plane information - * @num_planes: number of planes for this format - * @flags: format flags (V4L2_PIX_FMT_FLAG_*) - * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding - * @quantization: enum v4l2_quantization, colorspace quantization - * @xfer_func: enum v4l2_xfer_func, colorspace transfer function - */ -struct v4l2_pix_format_mplane { - __u32 width; - __u32 height; - __u32 pixelformat; - __u32 field; - __u32 colorspace; - - struct v4l2_plane_pix_format plane_fmt[VIDEO_MAX_PLANES]; - __u8 num_planes; - __u8 flags; - __u8 ycbcr_enc; - __u8 quantization; - __u8 xfer_func; - __u8 reserved[7]; -} __attribute__ ((packed)); - -/** - * struct v4l2_sdr_format - SDR format definition - * @pixelformat: little endian four character code (fourcc) - * @buffersize: maximum size in bytes required for data - */ -struct v4l2_sdr_format { - __u32 pixelformat; - __u32 buffersize; - __u8 reserved[24]; -} __attribute__ ((packed)); - -/** - * struct v4l2_format - stream data format - * @type: enum v4l2_buf_type; type of the data stream - * @pix: definition of an image format - * @pix_mp: definition of a multiplanar image format - * @win: definition of an overlaid image - * @vbi: raw VBI capture or output parameters - * @sliced: sliced VBI capture or output parameters - * @raw_data: placeholder for future extensions and custom formats - */ -struct v4l2_format { - __u32 type; - union { - struct v4l2_pix_format pix; /* V4L2_BUF_TYPE_VIDEO_CAPTURE */ - struct v4l2_pix_format_mplane pix_mp; /* V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE */ - struct v4l2_window win; /* V4L2_BUF_TYPE_VIDEO_OVERLAY */ - struct v4l2_vbi_format vbi; /* V4L2_BUF_TYPE_VBI_CAPTURE */ - struct v4l2_sliced_vbi_format sliced; /* V4L2_BUF_TYPE_SLICED_VBI_CAPTURE */ - struct v4l2_sdr_format sdr; /* V4L2_BUF_TYPE_SDR_CAPTURE */ - __u8 raw_data[200]; /* user-defined */ - } fmt; -}; - -/* Stream type-dependent parameters - */ -struct v4l2_streamparm { - __u32 type; /* enum v4l2_buf_type */ - union { - struct v4l2_captureparm capture; - struct v4l2_outputparm output; - __u8 raw_data[200]; /* user-defined */ - } parm; -}; - -/* - * E V E N T S - */ - -#define V4L2_EVENT_ALL 0 -#define V4L2_EVENT_VSYNC 1 -#define V4L2_EVENT_EOS 2 -#define V4L2_EVENT_CTRL 3 -#define V4L2_EVENT_FRAME_SYNC 4 -#define V4L2_EVENT_SOURCE_CHANGE 5 -#define V4L2_EVENT_MOTION_DET 6 -#define V4L2_EVENT_PRIVATE_START 0x08000000 - -#define V4L2_EVENT_BITDEPTH_FLAG 0x1 -#define V4L2_EVENT_PICSTRUCT_FLAG 0x2 -#define V4L2_EVENT_COLOUR_SPACE_FLAG 0x4 - -#define V4L2_EVENT_MSM_VIDC_START (V4L2_EVENT_PRIVATE_START + 0x00001000) -#define V4L2_EVENT_MSM_VIDC_FLUSH_DONE (V4L2_EVENT_MSM_VIDC_START + 1) -#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_SUFFICIENT \ - (V4L2_EVENT_MSM_VIDC_START + 2) -#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_INSUFFICIENT \ - (V4L2_EVENT_MSM_VIDC_START + 3) -/* - * Bitdepth changed insufficient is deprecated now, however retaining - * to prevent changing the values of the other macros after bitdepth - */ -#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_BITDEPTH_CHANGED_INSUFFICIENT \ - (V4L2_EVENT_MSM_VIDC_START + 4) -#define V4L2_EVENT_MSM_VIDC_SYS_ERROR (V4L2_EVENT_MSM_VIDC_START + 5) -#define V4L2_EVENT_MSM_VIDC_RELEASE_BUFFER_REFERENCE \ - (V4L2_EVENT_MSM_VIDC_START + 6) -#define V4L2_EVENT_MSM_VIDC_RELEASE_UNQUEUED_BUFFER \ - (V4L2_EVENT_MSM_VIDC_START + 7) -#define V4L2_EVENT_MSM_VIDC_HW_OVERLOAD (V4L2_EVENT_MSM_VIDC_START + 8) -#define V4L2_EVENT_MSM_VIDC_MAX_CLIENTS (V4L2_EVENT_MSM_VIDC_START + 9) -#define V4L2_EVENT_MSM_VIDC_HW_UNSUPPORTED (V4L2_EVENT_MSM_VIDC_START + 10) - -/* Payload for V4L2_EVENT_VSYNC */ -struct v4l2_event_vsync { - /* Can be V4L2_FIELD_ANY, _NONE, _TOP or _BOTTOM */ - __u8 field; -} __attribute__ ((packed)); - -/* Payload for V4L2_EVENT_CTRL */ -#define V4L2_EVENT_CTRL_CH_VALUE (1 << 0) -#define V4L2_EVENT_CTRL_CH_FLAGS (1 << 1) -#define V4L2_EVENT_CTRL_CH_RANGE (1 << 2) - -struct v4l2_event_ctrl { - __u32 changes; - __u32 type; - union { - __s32 value; - __s64 value64; - }; - __u32 flags; - __s32 minimum; - __s32 maximum; - __s32 step; - __s32 default_value; -}; - -struct v4l2_event_frame_sync { - __u32 frame_sequence; -}; - -#define V4L2_EVENT_SRC_CH_RESOLUTION (1 << 0) - -struct v4l2_event_src_change { - __u32 changes; -}; - -#define V4L2_EVENT_MD_FL_HAVE_FRAME_SEQ (1 << 0) - -/** - * struct v4l2_event_motion_det - motion detection event - * @flags: if V4L2_EVENT_MD_FL_HAVE_FRAME_SEQ is set, then the - * frame_sequence field is valid. - * @frame_sequence: the frame sequence number associated with this event. - * @region_mask: which regions detected motion. - */ -struct v4l2_event_motion_det { - __u32 flags; - __u32 frame_sequence; - __u32 region_mask; -}; - -struct v4l2_event { - __u32 type; - union { - struct v4l2_event_vsync vsync; - struct v4l2_event_ctrl ctrl; - struct v4l2_event_frame_sync frame_sync; - struct v4l2_event_src_change src_change; - struct v4l2_event_motion_det motion_det; - __u8 data[64]; - } u; - __u32 pending; - __u32 sequence; - struct timespec timestamp; - __u32 id; - __u32 reserved[8]; -}; - -#define V4L2_EVENT_SUB_FL_SEND_INITIAL (1 << 0) -#define V4L2_EVENT_SUB_FL_ALLOW_FEEDBACK (1 << 1) - -struct v4l2_event_subscription { - __u32 type; - __u32 id; - __u32 flags; - __u32 reserved[5]; -}; - -/* - * A D V A N C E D D E B U G G I N G - * - * NOTE: EXPERIMENTAL API, NEVER RELY ON THIS IN APPLICATIONS! - * FOR DEBUGGING, TESTING AND INTERNAL USE ONLY! - */ - -/* VIDIOC_DBG_G_REGISTER and VIDIOC_DBG_S_REGISTER */ - -#define V4L2_CHIP_MATCH_BRIDGE 0 /* Match against chip ID on the bridge (0 for the bridge) */ -#define V4L2_CHIP_MATCH_SUBDEV 4 /* Match against subdev index */ - -/* The following four defines are no longer in use */ -#define V4L2_CHIP_MATCH_HOST V4L2_CHIP_MATCH_BRIDGE -#define V4L2_CHIP_MATCH_I2C_DRIVER 1 /* Match against I2C driver name */ -#define V4L2_CHIP_MATCH_I2C_ADDR 2 /* Match against I2C 7-bit address */ -#define V4L2_CHIP_MATCH_AC97 3 /* Match against ancillary AC97 chip */ - -struct v4l2_dbg_match { - __u32 type; /* Match type */ - union { /* Match this chip, meaning determined by type */ - __u32 addr; - char name[32]; - }; -} __attribute__ ((packed)); - -struct v4l2_dbg_register { - struct v4l2_dbg_match match; - __u32 size; /* register size in bytes */ - __u64 reg; - __u64 val; -} __attribute__ ((packed)); - -#define V4L2_CHIP_FL_READABLE (1 << 0) -#define V4L2_CHIP_FL_WRITABLE (1 << 1) - -/* VIDIOC_DBG_G_CHIP_INFO */ -struct v4l2_dbg_chip_info { - struct v4l2_dbg_match match; - char name[32]; - __u32 flags; - __u32 reserved[32]; -} __attribute__ ((packed)); - -/** - * struct v4l2_create_buffers - VIDIOC_CREATE_BUFS argument - * @index: on return, index of the first created buffer - * @count: entry: number of requested buffers, - * return: number of created buffers - * @memory: enum v4l2_memory; buffer memory type - * @format: frame format, for which buffers are requested - * @reserved: future extensions - */ -struct v4l2_create_buffers { - __u32 index; - __u32 count; - __u32 memory; - struct v4l2_format format; - __u32 reserved[8]; -}; - -/* - * I O C T L C O D E S F O R V I D E O D E V I C E S - * - */ -#define VIDIOC_QUERYCAP _IOR('V', 0, struct v4l2_capability) -#define VIDIOC_RESERVED _IO('V', 1) -#define VIDIOC_ENUM_FMT _IOWR('V', 2, struct v4l2_fmtdesc) -#define VIDIOC_G_FMT _IOWR('V', 4, struct v4l2_format) -#define VIDIOC_S_FMT _IOWR('V', 5, struct v4l2_format) -#define VIDIOC_REQBUFS _IOWR('V', 8, struct v4l2_requestbuffers) -#define VIDIOC_QUERYBUF _IOWR('V', 9, struct v4l2_buffer) -#define VIDIOC_G_FBUF _IOR('V', 10, struct v4l2_framebuffer) -#define VIDIOC_S_FBUF _IOW('V', 11, struct v4l2_framebuffer) -#define VIDIOC_OVERLAY _IOW('V', 14, int) -#define VIDIOC_QBUF _IOWR('V', 15, struct v4l2_buffer) -#define VIDIOC_EXPBUF _IOWR('V', 16, struct v4l2_exportbuffer) -#define VIDIOC_DQBUF _IOWR('V', 17, struct v4l2_buffer) -#define VIDIOC_STREAMON _IOW('V', 18, int) -#define VIDIOC_STREAMOFF _IOW('V', 19, int) -#define VIDIOC_G_PARM _IOWR('V', 21, struct v4l2_streamparm) -#define VIDIOC_S_PARM _IOWR('V', 22, struct v4l2_streamparm) -#define VIDIOC_G_STD _IOR('V', 23, v4l2_std_id) -#define VIDIOC_S_STD _IOW('V', 24, v4l2_std_id) -#define VIDIOC_ENUMSTD _IOWR('V', 25, struct v4l2_standard) -#define VIDIOC_ENUMINPUT _IOWR('V', 26, struct v4l2_input) -#define VIDIOC_G_CTRL _IOWR('V', 27, struct v4l2_control) -#define VIDIOC_S_CTRL _IOWR('V', 28, struct v4l2_control) -#define VIDIOC_G_TUNER _IOWR('V', 29, struct v4l2_tuner) -#define VIDIOC_S_TUNER _IOW('V', 30, struct v4l2_tuner) -#define VIDIOC_G_AUDIO _IOR('V', 33, struct v4l2_audio) -#define VIDIOC_S_AUDIO _IOW('V', 34, struct v4l2_audio) -#define VIDIOC_QUERYCTRL _IOWR('V', 36, struct v4l2_queryctrl) -#define VIDIOC_QUERYMENU _IOWR('V', 37, struct v4l2_querymenu) -#define VIDIOC_G_INPUT _IOR('V', 38, int) -#define VIDIOC_S_INPUT _IOWR('V', 39, int) -#define VIDIOC_G_EDID _IOWR('V', 40, struct v4l2_edid) -#define VIDIOC_S_EDID _IOWR('V', 41, struct v4l2_edid) -#define VIDIOC_G_OUTPUT _IOR('V', 46, int) -#define VIDIOC_S_OUTPUT _IOWR('V', 47, int) -#define VIDIOC_ENUMOUTPUT _IOWR('V', 48, struct v4l2_output) -#define VIDIOC_G_AUDOUT _IOR('V', 49, struct v4l2_audioout) -#define VIDIOC_S_AUDOUT _IOW('V', 50, struct v4l2_audioout) -#define VIDIOC_G_MODULATOR _IOWR('V', 54, struct v4l2_modulator) -#define VIDIOC_S_MODULATOR _IOW('V', 55, struct v4l2_modulator) -#define VIDIOC_G_FREQUENCY _IOWR('V', 56, struct v4l2_frequency) -#define VIDIOC_S_FREQUENCY _IOW('V', 57, struct v4l2_frequency) -#define VIDIOC_CROPCAP _IOWR('V', 58, struct v4l2_cropcap) -#define VIDIOC_G_CROP _IOWR('V', 59, struct v4l2_crop) -#define VIDIOC_S_CROP _IOW('V', 60, struct v4l2_crop) -#define VIDIOC_G_JPEGCOMP _IOR('V', 61, struct v4l2_jpegcompression) -#define VIDIOC_S_JPEGCOMP _IOW('V', 62, struct v4l2_jpegcompression) -#define VIDIOC_QUERYSTD _IOR('V', 63, v4l2_std_id) -#define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format) -#define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio) -#define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout) -#define VIDIOC_G_PRIORITY _IOR('V', 67, __u32) /* enum v4l2_priority */ -#define VIDIOC_S_PRIORITY _IOW('V', 68, __u32) /* enum v4l2_priority */ -#define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap) -#define VIDIOC_LOG_STATUS _IO('V', 70) -#define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls) -#define VIDIOC_S_EXT_CTRLS _IOWR('V', 72, struct v4l2_ext_controls) -#define VIDIOC_TRY_EXT_CTRLS _IOWR('V', 73, struct v4l2_ext_controls) -#define VIDIOC_ENUM_FRAMESIZES _IOWR('V', 74, struct v4l2_frmsizeenum) -#define VIDIOC_ENUM_FRAMEINTERVALS _IOWR('V', 75, struct v4l2_frmivalenum) -#define VIDIOC_G_ENC_INDEX _IOR('V', 76, struct v4l2_enc_idx) -#define VIDIOC_ENCODER_CMD _IOWR('V', 77, struct v4l2_encoder_cmd) -#define VIDIOC_TRY_ENCODER_CMD _IOWR('V', 78, struct v4l2_encoder_cmd) - -/* - * Experimental, meant for debugging, testing and internal use. - * Only implemented if CONFIG_VIDEO_ADV_DEBUG is defined. - * You must be root to use these ioctls. Never use these in applications! - */ -#define VIDIOC_DBG_S_REGISTER _IOW('V', 79, struct v4l2_dbg_register) -#define VIDIOC_DBG_G_REGISTER _IOWR('V', 80, struct v4l2_dbg_register) - -#define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek) -#define VIDIOC_S_DV_TIMINGS _IOWR('V', 87, struct v4l2_dv_timings) -#define VIDIOC_G_DV_TIMINGS _IOWR('V', 88, struct v4l2_dv_timings) -#define VIDIOC_DQEVENT _IOR('V', 89, struct v4l2_event) -#define VIDIOC_SUBSCRIBE_EVENT _IOW('V', 90, struct v4l2_event_subscription) -#define VIDIOC_UNSUBSCRIBE_EVENT _IOW('V', 91, struct v4l2_event_subscription) -#define VIDIOC_CREATE_BUFS _IOWR('V', 92, struct v4l2_create_buffers) -#define VIDIOC_PREPARE_BUF _IOWR('V', 93, struct v4l2_buffer) -#define VIDIOC_G_SELECTION _IOWR('V', 94, struct v4l2_selection) -#define VIDIOC_S_SELECTION _IOWR('V', 95, struct v4l2_selection) -#define VIDIOC_DECODER_CMD _IOWR('V', 96, struct v4l2_decoder_cmd) -#define VIDIOC_TRY_DECODER_CMD _IOWR('V', 97, struct v4l2_decoder_cmd) -#define VIDIOC_ENUM_DV_TIMINGS _IOWR('V', 98, struct v4l2_enum_dv_timings) -#define VIDIOC_QUERY_DV_TIMINGS _IOR('V', 99, struct v4l2_dv_timings) -#define VIDIOC_DV_TIMINGS_CAP _IOWR('V', 100, struct v4l2_dv_timings_cap) -#define VIDIOC_ENUM_FREQ_BANDS _IOWR('V', 101, struct v4l2_frequency_band) - -/* - * Experimental, meant for debugging, testing and internal use. - * Never use this in applications! - */ -#define VIDIOC_DBG_G_CHIP_INFO _IOWR('V', 102, struct v4l2_dbg_chip_info) - -#define VIDIOC_QUERY_EXT_CTRL _IOWR('V', 103, struct v4l2_query_ext_ctrl) - -/* Reminder: when adding new ioctls please add support for them to - drivers/media/v4l2-core/v4l2-compat-ioctl32.c as well! */ - -#define BASE_VIDIOC_PRIVATE 192 /* 192-255 are private */ - -#endif /* __LINUX_VIDEODEV2_H */ diff --git a/sdm710/original-kernel-headers/linux/wcd-spi-ac-params.h b/sdm710/original-kernel-headers/linux/wcd-spi-ac-params.h deleted file mode 100644 index cdb0aecd..00000000 --- a/sdm710/original-kernel-headers/linux/wcd-spi-ac-params.h +++ /dev/null @@ -1,52 +0,0 @@ -#ifndef __UAPI_WCD_SPI_AC_PARAMS_H__ -#define __UAPI_WCD_SPI_AC_PARAMS_H__ - -#include <linux/types.h> - -#define WCD_SPI_AC_CMD_CONC_BEGIN 0x01 -#define WCD_SPI_AC_CMD_CONC_END 0x02 -#define WCD_SPI_AC_CMD_BUF_DATA 0x03 - -#define WCD_SPI_AC_MAX_BUFFERS 2 -#define WCD_SPI_AC_MAX_CH_PER_BUF 8 - -#define WCD_SPI_AC_CLIENT_CDEV_NAME "wcd-spi-ac-client" -#define WCD_SPI_AC_PROCFS_DIR_NAME "wcd-spi-ac" -#define WCD_SPI_AC_PROCFS_STATE_NAME "svc-state" - -/* - * wcd_spi_ac_buf_data: - * Buffer address for one buffer. Should have data - * for all the channels. If channels are unused, the - * value must be NULL. - * - * @addr: - * Address where each channel of the buffer starts. - */ -struct wcd_spi_ac_buf_data { - __u32 addr[WCD_SPI_AC_MAX_CH_PER_BUF]; -} __attribute__((packed)); - -/* - * wcd_spi_ac_write_cmd: - * Data sent to the driver's write interface should - * be packed in this format. - * - * @cmd_type: - * Indicates the type of command that is sent. Should - * be one of the valid commands defined with - * WCD_SPI_AC_CMD_* - * @payload: - * No payload for: - * WCD_SPI_AC_CMD_CONC_BEGIN - * WCD_SPI_AC_CMD_CONC_END - * Upto WCD_SPI_AC_MAX_BUFFERS of type - * struct wcd_spi_ac_buf_data for: - * WCD_SPI_AC_CMD_BUF_DATA - */ -struct wcd_spi_ac_write_cmd { - __u32 cmd_type; - __u8 payload[0]; -} __attribute__((packed)); - -#endif /* end of __UAPI_WCD_SPI_AC_PARAMS_H__ */ diff --git a/sdm710/original-kernel-headers/media/cam_cpas.h b/sdm710/original-kernel-headers/media/cam_cpas.h deleted file mode 100644 index c5cbac82..00000000 --- a/sdm710/original-kernel-headers/media/cam_cpas.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __UAPI_CAM_CPAS_H__ -#define __UAPI_CAM_CPAS_H__ - -#include "cam_defs.h" - -#define CAM_FAMILY_CAMERA_SS 1 -#define CAM_FAMILY_CPAS_SS 2 - -/** - * struct cam_cpas_query_cap - CPAS query device capability payload - * - * @camera_family : Camera family type - * @reserved : Reserved field for alignment - * @camera_version : Camera platform version - * @cpas_version : Camera CPAS version within camera platform - * - */ -struct cam_cpas_query_cap { - uint32_t camera_family; - uint32_t reserved; - struct cam_hw_version camera_version; - struct cam_hw_version cpas_version; -}; - -#endif /* __UAPI_CAM_CPAS_H__ */ diff --git a/sdm710/original-kernel-headers/media/cam_defs.h b/sdm710/original-kernel-headers/media/cam_defs.h deleted file mode 100644 index e006463d..00000000 --- a/sdm710/original-kernel-headers/media/cam_defs.h +++ /dev/null @@ -1,477 +0,0 @@ -#ifndef __UAPI_CAM_DEFS_H__ -#define __UAPI_CAM_DEFS_H__ - -#include <linux/videodev2.h> -#include <linux/types.h> -#include <linux/ioctl.h> - - -/* camera op codes */ -#define CAM_COMMON_OPCODE_BASE 0x100 -#define CAM_QUERY_CAP (CAM_COMMON_OPCODE_BASE + 0x1) -#define CAM_ACQUIRE_DEV (CAM_COMMON_OPCODE_BASE + 0x2) -#define CAM_START_DEV (CAM_COMMON_OPCODE_BASE + 0x3) -#define CAM_STOP_DEV (CAM_COMMON_OPCODE_BASE + 0x4) -#define CAM_CONFIG_DEV (CAM_COMMON_OPCODE_BASE + 0x5) -#define CAM_RELEASE_DEV (CAM_COMMON_OPCODE_BASE + 0x6) -#define CAM_SD_SHUTDOWN (CAM_COMMON_OPCODE_BASE + 0x7) -#define CAM_FLUSH_REQ (CAM_COMMON_OPCODE_BASE + 0x8) -#define CAM_COMMON_OPCODE_MAX (CAM_COMMON_OPCODE_BASE + 0x9) - -#define CAM_EXT_OPCODE_BASE 0x200 -#define CAM_CONFIG_DEV_EXTERNAL (CAM_EXT_OPCODE_BASE + 0x1) - -/* camera handle type */ -#define CAM_HANDLE_USER_POINTER 1 -#define CAM_HANDLE_MEM_HANDLE 2 - -/* Generic Blob CmdBuffer header properties */ -#define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_MASK 0xFFFFFF00 -#define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_SHIFT 8 -#define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_MASK 0xFF -#define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_SHIFT 0 - -/* Command Buffer Types */ -#define CAM_CMD_BUF_DMI 0x1 -#define CAM_CMD_BUF_DMI16 0x2 -#define CAM_CMD_BUF_DMI32 0x3 -#define CAM_CMD_BUF_DMI64 0x4 -#define CAM_CMD_BUF_DIRECT 0x5 -#define CAM_CMD_BUF_INDIRECT 0x6 -#define CAM_CMD_BUF_I2C 0x7 -#define CAM_CMD_BUF_FW 0x8 -#define CAM_CMD_BUF_GENERIC 0x9 -#define CAM_CMD_BUF_LEGACY 0xA - -/** - * enum flush_type_t - Identifies the various flush types - * - * @CAM_FLUSH_TYPE_REQ: Flush specific request - * @CAM_FLUSH_TYPE_ALL: Flush all requests belonging to a context - * @CAM_FLUSH_TYPE_MAX: Max enum to validate flush type - * - */ -enum flush_type_t { - CAM_FLUSH_TYPE_REQ, - CAM_FLUSH_TYPE_ALL, - CAM_FLUSH_TYPE_MAX -}; - -/** - * struct cam_control - Structure used by ioctl control for camera - * - * @op_code: This is the op code for camera control - * @size: Control command size - * @handle_type: User pointer or shared memory handle - * @reserved: Reserved field for 64 bit alignment - * @handle: Control command payload - */ -struct cam_control { - uint32_t op_code; - uint32_t size; - uint32_t handle_type; - uint32_t reserved; - uint64_t handle; -}; - -/* camera IOCTL */ -#define VIDIOC_CAM_CONTROL \ - _IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_control) - -/** - * struct cam_hw_version - Structure for HW version of camera devices - * - * @major : Hardware version major - * @minor : Hardware version minor - * @incr : Hardware version increment - * @reserved : Reserved for 64 bit aligngment - */ -struct cam_hw_version { - uint32_t major; - uint32_t minor; - uint32_t incr; - uint32_t reserved; -}; - -/** - * struct cam_iommu_handle - Structure for IOMMU handles of camera hw devices - * - * @non_secure: Device Non Secure IOMMU handle - * @secure: Device Secure IOMMU handle - * - */ -struct cam_iommu_handle { - int32_t non_secure; - int32_t secure; -}; - -/* camera secure mode */ -#define CAM_SECURE_MODE_NON_SECURE 0 -#define CAM_SECURE_MODE_SECURE 1 - -/* Camera Format Type */ -#define CAM_FORMAT_BASE 0 -#define CAM_FORMAT_MIPI_RAW_6 1 -#define CAM_FORMAT_MIPI_RAW_8 2 -#define CAM_FORMAT_MIPI_RAW_10 3 -#define CAM_FORMAT_MIPI_RAW_12 4 -#define CAM_FORMAT_MIPI_RAW_14 5 -#define CAM_FORMAT_MIPI_RAW_16 6 -#define CAM_FORMAT_MIPI_RAW_20 7 -#define CAM_FORMAT_QTI_RAW_8 8 -#define CAM_FORMAT_QTI_RAW_10 9 -#define CAM_FORMAT_QTI_RAW_12 10 -#define CAM_FORMAT_QTI_RAW_14 11 -#define CAM_FORMAT_PLAIN8 12 -#define CAM_FORMAT_PLAIN16_8 13 -#define CAM_FORMAT_PLAIN16_10 14 -#define CAM_FORMAT_PLAIN16_12 15 -#define CAM_FORMAT_PLAIN16_14 16 -#define CAM_FORMAT_PLAIN16_16 17 -#define CAM_FORMAT_PLAIN32_20 18 -#define CAM_FORMAT_PLAIN64 19 -#define CAM_FORMAT_PLAIN128 20 -#define CAM_FORMAT_ARGB 21 -#define CAM_FORMAT_ARGB_10 22 -#define CAM_FORMAT_ARGB_12 23 -#define CAM_FORMAT_ARGB_14 24 -#define CAM_FORMAT_DPCM_10_6_10 25 -#define CAM_FORMAT_DPCM_10_8_10 26 -#define CAM_FORMAT_DPCM_12_6_12 27 -#define CAM_FORMAT_DPCM_12_8_12 28 -#define CAM_FORMAT_DPCM_14_8_14 29 -#define CAM_FORMAT_DPCM_14_10_14 30 -#define CAM_FORMAT_NV21 31 -#define CAM_FORMAT_NV12 32 -#define CAM_FORMAT_TP10 33 -#define CAM_FORMAT_YUV422 34 -#define CAM_FORMAT_PD8 35 -#define CAM_FORMAT_PD10 36 -#define CAM_FORMAT_UBWC_NV12 37 -#define CAM_FORMAT_UBWC_NV12_4R 38 -#define CAM_FORMAT_UBWC_TP10 39 -#define CAM_FORMAT_UBWC_P010 40 -#define CAM_FORMAT_PLAIN8_SWAP 41 -#define CAM_FORMAT_PLAIN8_10 42 -#define CAM_FORMAT_PLAIN8_10_SWAP 43 -#define CAM_FORMAT_YV12 44 -#define CAM_FORMAT_Y_ONLY 45 -#define CAM_FORMAT_MAX 46 - -/* camera rotaion */ -#define CAM_ROTATE_CW_0_DEGREE 0 -#define CAM_ROTATE_CW_90_DEGREE 1 -#define CAM_RORATE_CW_180_DEGREE 2 -#define CAM_ROTATE_CW_270_DEGREE 3 - -/* camera Color Space */ -#define CAM_COLOR_SPACE_BASE 0 -#define CAM_COLOR_SPACE_BT601_FULL 1 -#define CAM_COLOR_SPACE_BT601625 2 -#define CAM_COLOR_SPACE_BT601525 3 -#define CAM_COLOR_SPACE_BT709 4 -#define CAM_COLOR_SPACE_DEPTH 5 -#define CAM_COLOR_SPACE_MAX 6 - -/* camera buffer direction */ -#define CAM_BUF_INPUT 1 -#define CAM_BUF_OUTPUT 2 -#define CAM_BUF_IN_OUT 3 - -/* camera packet device Type */ -#define CAM_PACKET_DEV_BASE 0 -#define CAM_PACKET_DEV_IMG_SENSOR 1 -#define CAM_PACKET_DEV_ACTUATOR 2 -#define CAM_PACKET_DEV_COMPANION 3 -#define CAM_PACKET_DEV_EEPOM 4 -#define CAM_PACKET_DEV_CSIPHY 5 -#define CAM_PACKET_DEV_OIS 6 -#define CAM_PACKET_DEV_FLASH 7 -#define CAM_PACKET_DEV_FD 8 -#define CAM_PACKET_DEV_JPEG_ENC 9 -#define CAM_PACKET_DEV_JPEG_DEC 10 -#define CAM_PACKET_DEV_VFE 11 -#define CAM_PACKET_DEV_CPP 12 -#define CAM_PACKET_DEV_CSID 13 -#define CAM_PACKET_DEV_ISPIF 14 -#define CAM_PACKET_DEV_IFE 15 -#define CAM_PACKET_DEV_ICP 16 -#define CAM_PACKET_DEV_LRME 17 -#define CAM_PACKET_DEV_MAX 18 - - -/* constants */ -#define CAM_PACKET_MAX_PLANES 3 - -/** - * struct cam_plane_cfg - Plane configuration info - * - * @width: Plane width in pixels - * @height: Plane height in lines - * @plane_stride: Plane stride in pixel - * @slice_height: Slice height in line (not used by ISP) - * @meta_stride: UBWC metadata stride - * @meta_size: UBWC metadata plane size - * @meta_offset: UBWC metadata offset - * @packer_config: UBWC packer config - * @mode_config: UBWC mode config - * @tile_config: UBWC tile config - * @h_init: UBWC horizontal initial coordinate in pixels - * @v_init: UBWC vertical initial coordinate in lines - * - */ -struct cam_plane_cfg { - uint32_t width; - uint32_t height; - uint32_t plane_stride; - uint32_t slice_height; - uint32_t meta_stride; - uint32_t meta_size; - uint32_t meta_offset; - uint32_t packer_config; - uint32_t mode_config; - uint32_t tile_config; - uint32_t h_init; - uint32_t v_init; -}; - -/** - * struct cam_cmd_buf_desc - Command buffer descriptor - * - * @mem_handle: Command buffer handle - * @offset: Command start offset - * @size: Size of the command buffer in bytes - * @length: Used memory in command buffer in bytes - * @type: Type of the command buffer - * @meta_data: Data type for private command buffer - * Between UMD and KMD - * - */ -struct cam_cmd_buf_desc { - int32_t mem_handle; - uint32_t offset; - uint32_t size; - uint32_t length; - uint32_t type; - uint32_t meta_data; -}; - -/** - * struct cam_buf_io_cfg - Buffer io configuration for buffers - * - * @mem_handle: Mem_handle array for the buffers. - * @offsets: Offsets for each planes in the buffer - * @planes: Per plane information - * @width: Main plane width in pixel - * @height: Main plane height in lines - * @format: Format of the buffer - * @color_space: Color space for the buffer - * @color_pattern: Color pattern in the buffer - * @bpp: Bit per pixel - * @rotation: Rotation information for the buffer - * @resource_type: Resource type associated with the buffer - * @fence: Fence handle - * @early_fence: Fence handle for early signal - * @aux_cmd_buf: An auxiliary command buffer that may be - * used for programming the IO - * @direction: Direction of the config - * @batch_size: Batch size in HFR mode - * @subsample_pattern: Subsample pattern. Used in HFR mode. It - * should be consistent with batchSize and - * CAMIF programming. - * @subsample_period: Subsample period. Used in HFR mode. It - * should be consistent with batchSize and - * CAMIF programming. - * @framedrop_pattern: Framedrop pattern - * @framedrop_period: Framedrop period - * @flag: Flags for extra information - * @direction: Buffer direction: input or output - * @padding: Padding for the structure - * - */ -struct cam_buf_io_cfg { - int32_t mem_handle[CAM_PACKET_MAX_PLANES]; - uint32_t offsets[CAM_PACKET_MAX_PLANES]; - struct cam_plane_cfg planes[CAM_PACKET_MAX_PLANES]; - uint32_t format; - uint32_t color_space; - uint32_t color_pattern; - uint32_t bpp; - uint32_t rotation; - uint32_t resource_type; - int32_t fence; - int32_t early_fence; - struct cam_cmd_buf_desc aux_cmd_buf; - uint32_t direction; - uint32_t batch_size; - uint32_t subsample_pattern; - uint32_t subsample_period; - uint32_t framedrop_pattern; - uint32_t framedrop_period; - uint32_t flag; - uint32_t padding; -}; - -/** - * struct cam_packet_header - Camera packet header - * - * @op_code: Camera packet opcode - * @size: Size of the camera packet in bytes - * @request_id: Request id for this camera packet - * @flags: Flags for the camera packet - * @padding: Padding - * - */ -struct cam_packet_header { - uint32_t op_code; - uint32_t size; - uint64_t request_id; - uint32_t flags; - uint32_t padding; -}; - -/** - * struct cam_patch_desc - Patch structure - * - * @dst_buf_hdl: Memory handle for the dest buffer - * @dst_offset: Offset byte in the dest buffer - * @src_buf_hdl: Memory handle for the source buffer - * @src_offset: Offset byte in the source buffer - * - */ -struct cam_patch_desc { - int32_t dst_buf_hdl; - uint32_t dst_offset; - int32_t src_buf_hdl; - uint32_t src_offset; -}; - -/** - * struct cam_packet - Camera packet structure - * - * @header: Camera packet header - * @cmd_buf_offset: Command buffer start offset - * @num_cmd_buf: Number of the command buffer in the packet - * @io_config_offset: Buffer io configuration start offset - * @num_io_configs: Number of the buffer io configurations - * @patch_offset: Patch offset for the patch structure - * @num_patches: Number of the patch structure - * @kmd_cmd_buf_index: Command buffer index which contains extra - * space for the KMD buffer - * @kmd_cmd_buf_offset: Offset from the beginning of the command - * buffer for KMD usage. - * @payload: Camera packet payload - * - */ -struct cam_packet { - struct cam_packet_header header; - uint32_t cmd_buf_offset; - uint32_t num_cmd_buf; - uint32_t io_configs_offset; - uint32_t num_io_configs; - uint32_t patch_offset; - uint32_t num_patches; - uint32_t kmd_cmd_buf_index; - uint32_t kmd_cmd_buf_offset; - uint64_t payload[1]; - -}; - -/** - * struct cam_release_dev_cmd - Control payload for release devices - * - * @session_handle: Session handle for the release - * @dev_handle: Device handle for the release - */ -struct cam_release_dev_cmd { - int32_t session_handle; - int32_t dev_handle; -}; - -/** - * struct cam_start_stop_dev_cmd - Control payload for start/stop device - * - * @session_handle: Session handle for the start/stop command - * @dev_handle: Device handle for the start/stop command - * - */ -struct cam_start_stop_dev_cmd { - int32_t session_handle; - int32_t dev_handle; -}; - -/** - * struct cam_config_dev_cmd - Command payload for configure device - * - * @session_handle: Session handle for the command - * @dev_handle: Device handle for the command - * @offset: Offset byte in the packet handle. - * @packet_handle: Packet memory handle for the actual packet: - * struct cam_packet. - * - */ -struct cam_config_dev_cmd { - int32_t session_handle; - int32_t dev_handle; - uint64_t offset; - uint64_t packet_handle; -}; - -/** - * struct cam_query_cap_cmd - Payload for query device capability - * - * @size: Handle size - * @handle_type: User pointer or shared memory handle - * @caps_handle: Device specific query command payload - * - */ -struct cam_query_cap_cmd { - uint32_t size; - uint32_t handle_type; - uint64_t caps_handle; -}; - -/** - * struct cam_acquire_dev_cmd - Control payload for acquire devices - * - * @session_handle: Session handle for the acquire command - * @dev_handle: Device handle to be returned - * @handle_type: Resource handle type: - * 1 = user pointer, 2 = mem handle - * @num_resources: Number of the resources to be acquired - * @resources_hdl: Resource handle that refers to the actual - * resource array. Each item in this - * array is device specific resource structure - * - */ -struct cam_acquire_dev_cmd { - int32_t session_handle; - int32_t dev_handle; - uint32_t handle_type; - uint32_t num_resources; - uint64_t resource_hdl; -}; - -/** - * struct cam_flush_dev_cmd - Control payload for flush devices - * - * @version: Version - * @session_handle: Session handle for the acquire command - * @dev_handle: Device handle to be returned - * @flush_type: Flush type: - * 0 = flush specific request - * 1 = flush all - * @reserved: Reserved for 64 bit aligngment - * @req_id: Request id that needs to cancel - * - */ -struct cam_flush_dev_cmd { - uint64_t version; - int32_t session_handle; - int32_t dev_handle; - uint32_t flush_type; - uint32_t reserved; - int64_t req_id; -}; - -#endif /* __UAPI_CAM_DEFS_H__ */ diff --git a/sdm710/original-kernel-headers/media/cam_fd.h b/sdm710/original-kernel-headers/media/cam_fd.h deleted file mode 100644 index 6b2247f6..00000000 --- a/sdm710/original-kernel-headers/media/cam_fd.h +++ /dev/null @@ -1,127 +0,0 @@ -#ifndef __UAPI_CAM_FD_H__ -#define __UAPI_CAM_FD_H__ - -#include "cam_defs.h" - -#define CAM_FD_MAX_FACES 35 -#define CAM_FD_RAW_RESULT_ENTRIES 512 - -/* FD Op Codes */ -#define CAM_PACKET_OPCODES_FD_FRAME_UPDATE 0x0 - -/* FD Command Buffer identifiers */ -#define CAM_FD_CMD_BUFFER_ID_GENERIC 0x0 -#define CAM_FD_CMD_BUFFER_ID_CDM 0x1 -#define CAM_FD_CMD_BUFFER_ID_MAX 0x2 - -/* FD Blob types */ -#define CAM_FD_BLOB_TYPE_SOC_CLOCK_BW_REQUEST 0x0 -#define CAM_FD_BLOB_TYPE_RAW_RESULTS_REQUIRED 0x1 - -/* FD Resource IDs */ -#define CAM_FD_INPUT_PORT_ID_IMAGE 0x0 -#define CAM_FD_INPUT_PORT_ID_MAX 0x1 - -#define CAM_FD_OUTPUT_PORT_ID_RESULTS 0x0 -#define CAM_FD_OUTPUT_PORT_ID_RAW_RESULTS 0x1 -#define CAM_FD_OUTPUT_PORT_ID_WORK_BUFFER 0x2 -#define CAM_FD_OUTPUT_PORT_ID_MAX 0x3 - -/** - * struct cam_fd_soc_clock_bw_request - SOC clock, bandwidth request info - * - * @clock_rate : Clock rate required while processing frame - * @bandwidth : Bandwidth required while processing frame - * @reserved : Reserved for future use - */ -struct cam_fd_soc_clock_bw_request { - uint64_t clock_rate; - uint64_t bandwidth; - uint64_t reserved[4]; -}; - -/** - * struct cam_fd_face - Face properties - * - * @prop1 : Property 1 of face - * @prop2 : Property 2 of face - * @prop3 : Property 3 of face - * @prop4 : Property 4 of face - * - * Do not change this layout, this is __inline__ with how HW writes - * these values directly when the buffer is programmed to HW - */ -struct cam_fd_face { - uint32_t prop1; - uint32_t prop2; - uint32_t prop3; - uint32_t prop4; -}; - -/** - * struct cam_fd_results - FD results layout - * - * @faces : Array of faces with face properties - * @face_count : Number of faces detected - * @reserved : Reserved for alignment - * - * Do not change this layout, this is __inline__ with how HW writes - * these values directly when the buffer is programmed to HW - */ -struct cam_fd_results { - struct cam_fd_face faces[CAM_FD_MAX_FACES]; - uint32_t face_count; - uint32_t reserved[3]; -}; - -/** - * struct cam_fd_hw_caps - Face properties - * - * @core_version : FD core version - * @wrapper_version : FD wrapper version - * @raw_results_available : Whether raw results are available on this HW - * @supported_modes : Modes supported by this HW. - * @reserved : Reserved for future use - */ -struct cam_fd_hw_caps { - struct cam_hw_version core_version; - struct cam_hw_version wrapper_version; - uint32_t raw_results_available; - uint32_t supported_modes; - uint64_t reserved; -}; - -/** - * struct cam_fd_query_cap_cmd - FD Query capabilities information - * - * @device_iommu : FD IOMMU handles - * @cdm_iommu : CDM iommu handles - * @hw_caps : FD HW capabilities - * @reserved : Reserved for alignment - */ -struct cam_fd_query_cap_cmd { - struct cam_iommu_handle device_iommu; - struct cam_iommu_handle cdm_iommu; - struct cam_fd_hw_caps hw_caps; - uint64_t reserved; -}; - -/** - * struct cam_fd_acquire_dev_info - FD acquire device information - * - * @clk_bw_request : SOC clock, bandwidth request - * @priority : Priority for this acquire - * @mode : Mode in which to run FD HW. - * @get_raw_results : Whether this acquire needs face raw results - * while frame processing - * @reserved : Reserved field for 64 bit alignment - */ -struct cam_fd_acquire_dev_info { - struct cam_fd_soc_clock_bw_request clk_bw_request; - uint32_t priority; - uint32_t mode; - uint32_t get_raw_results; - uint32_t reserved[13]; -}; - -#endif /* __UAPI_CAM_FD_H__ */ diff --git a/sdm710/original-kernel-headers/media/cam_icp.h b/sdm710/original-kernel-headers/media/cam_icp.h deleted file mode 100644 index cd2d2d29..00000000 --- a/sdm710/original-kernel-headers/media/cam_icp.h +++ /dev/null @@ -1,178 +0,0 @@ -#ifndef __UAPI_CAM_ICP_H__ -#define __UAPI_CAM_ICP_H__ - -#include "cam_defs.h" - -/* icp, ipe, bps, cdm(ipe/bps) are used in querycap */ -#define CAM_ICP_DEV_TYPE_A5 1 -#define CAM_ICP_DEV_TYPE_IPE 2 -#define CAM_ICP_DEV_TYPE_BPS 3 -#define CAM_ICP_DEV_TYPE_IPE_CDM 4 -#define CAM_ICP_DEV_TYPE_BPS_CDM 5 -#define CAM_ICP_DEV_TYPE_MAX 5 - -/* definitions needed for icp aquire device */ -#define CAM_ICP_RES_TYPE_BPS 1 -#define CAM_ICP_RES_TYPE_IPE_RT 2 -#define CAM_ICP_RES_TYPE_IPE 3 -#define CAM_ICP_RES_TYPE_MAX 4 - -/* packet opcode types */ -#define CAM_ICP_OPCODE_IPE_UPDATE 0 -#define CAM_ICP_OPCODE_BPS_UPDATE 1 - -/* IPE input port resource type */ -#define CAM_ICP_IPE_INPUT_IMAGE_FULL 0x0 -#define CAM_ICP_IPE_INPUT_IMAGE_DS4 0x1 -#define CAM_ICP_IPE_INPUT_IMAGE_DS16 0x2 -#define CAM_ICP_IPE_INPUT_IMAGE_DS64 0x3 -#define CAM_ICP_IPE_INPUT_IMAGE_FULL_REF 0x4 -#define CAM_ICP_IPE_INPUT_IMAGE_DS4_REF 0x5 -#define CAM_ICP_IPE_INPUT_IMAGE_DS16_REF 0x6 -#define CAM_ICP_IPE_INPUT_IMAGE_DS64_REF 0x7 - -/* IPE output port resource type */ -#define CAM_ICP_IPE_OUTPUT_IMAGE_DISPLAY 0x8 -#define CAM_ICP_IPE_OUTPUT_IMAGE_VIDEO 0x9 -#define CAM_ICP_IPE_OUTPUT_IMAGE_FULL_REF 0xA -#define CAM_ICP_IPE_OUTPUT_IMAGE_DS4_REF 0xB -#define CAM_ICP_IPE_OUTPUT_IMAGE_DS16_REF 0xC -#define CAM_ICP_IPE_OUTPUT_IMAGE_DS64_REF 0xD - -#define CAM_ICP_IPE_IMAGE_MAX 0xE - -/* BPS input port resource type */ -#define CAM_ICP_BPS_INPUT_IMAGE 0x0 - -/* BPS output port resource type */ -#define CAM_ICP_BPS_OUTPUT_IMAGE_FULL 0x1 -#define CAM_ICP_BPS_OUTPUT_IMAGE_DS4 0x2 -#define CAM_ICP_BPS_OUTPUT_IMAGE_DS16 0x3 -#define CAM_ICP_BPS_OUTPUT_IMAGE_DS64 0x4 -#define CAM_ICP_BPS_OUTPUT_IMAGE_STATS_BG 0x5 -#define CAM_ICP_BPS_OUTPUT_IMAGE_STATS_BHIST 0x6 -#define CAM_ICP_BPS_OUTPUT_IMAGE_REG1 0x7 -#define CAM_ICP_BPS_OUTPUT_IMAGE_REG2 0x8 - -#define CAM_ICP_BPS_IO_IMAGES_MAX 0x9 - -/* Command meta types */ -#define CAM_ICP_CMD_META_GENERIC_BLOB 0x1 - -/* Generic blon types */ -#define CAM_ICP_CMD_GENERIC_BLOB_CLK 0x1 - -/** - * struct cam_icp_clk_bw_request - * - * @budget_ns: Time required to process frame - * @frame_cycles: Frame cycles needed to process the frame - * @rt_flag: Flag to indicate real time stream - * @uncompressed_bw: Bandwidth required to process frame - * @compressed_bw: Compressed bandwidth to process frame - */ -struct cam_icp_clk_bw_request { - uint64_t budget_ns; - uint32_t frame_cycles; - uint32_t rt_flag; - uint64_t uncompressed_bw; - uint64_t compressed_bw; -}; - -/** - * struct cam_icp_dev_ver - Device information for particular hw type - * - * This is used to get device version info of - * ICP, IPE, BPS and CDM related IPE and BPS from firmware - * and use this info in CAM_QUERY_CAP IOCTL - * - * @dev_type: hardware type for the cap info(icp, ipe, bps, cdm(ipe/bps)) - * @reserved: reserved field - * @hw_ver: major, minor and incr values of a device version - */ -struct cam_icp_dev_ver { - uint32_t dev_type; - uint32_t reserved; - struct cam_hw_version hw_ver; -}; - -/** - * struct cam_icp_ver - ICP version info - * - * This strcuture is used for fw and api version - * this is used to get firmware version and api version from firmware - * and use this info in CAM_QUERY_CAP IOCTL - * - * @major: FW version major - * @minor: FW version minor - * @revision: FW version increment - */ -struct cam_icp_ver { - uint32_t major; - uint32_t minor; - uint32_t revision; - uint32_t reserved; -}; - -/** - * struct cam_icp_query_cap_cmd - ICP query device capability payload - * - * @dev_iommu_handle: icp iommu handles for secure/non secure modes - * @cdm_iommu_handle: iommu handles for secure/non secure modes - * @fw_version: firmware version info - * @api_version: api version info - * @num_ipe: number of ipes - * @num_bps: number of bps - * @dev_ver: returned device capability array - */ -struct cam_icp_query_cap_cmd { - struct cam_iommu_handle dev_iommu_handle; - struct cam_iommu_handle cdm_iommu_handle; - struct cam_icp_ver fw_version; - struct cam_icp_ver api_version; - uint32_t num_ipe; - uint32_t num_bps; - struct cam_icp_dev_ver dev_ver[CAM_ICP_DEV_TYPE_MAX]; -}; - -/** - * struct cam_icp_res_info - ICP output resource info - * - * @format: format of the resource - * @width: width in pixels - * @height: height in lines - * @fps: fps - */ -struct cam_icp_res_info { - uint32_t format; - uint32_t width; - uint32_t height; - uint32_t fps; -}; - -/** - * struct cam_icp_acquire_dev_info - An ICP device info - * - * @scratch_mem_size: Output param - size of scratch memory - * @dev_type: device type (IPE_RT/IPE_NON_RT/BPS) - * @io_config_cmd_size: size of IO config command - * @io_config_cmd_handle: IO config command for each acquire - * @secure_mode: camera mode (secure/non secure) - * @chain_info: chaining info of FW device handles - * @in_res: resource info used for clock and bandwidth calculation - * @num_out_res: number of output resources - * @out_res: output resource - */ -struct cam_icp_acquire_dev_info { - uint32_t scratch_mem_size; - uint32_t dev_type; - uint32_t io_config_cmd_size; - int32_t io_config_cmd_handle; - uint32_t secure_mode; - int32_t chain_info; - struct cam_icp_res_info in_res; - uint32_t num_out_res; - struct cam_icp_res_info out_res[1]; -} __attribute__((__packed__)); - -#endif /* __UAPI_CAM_ICP_H__ */ diff --git a/sdm710/original-kernel-headers/media/cam_isp.h b/sdm710/original-kernel-headers/media/cam_isp.h deleted file mode 100644 index afd109fc..00000000 --- a/sdm710/original-kernel-headers/media/cam_isp.h +++ /dev/null @@ -1,378 +0,0 @@ -#ifndef __UAPI_CAM_ISP_H__ -#define __UAPI_CAM_ISP_H__ - -#include "cam_defs.h" -#include "cam_isp_vfe.h" -#include "cam_isp_ife.h" - - -/* ISP driver name */ -#define CAM_ISP_DEV_NAME "cam-isp" - -/* HW type */ -#define CAM_ISP_HW_BASE 0 -#define CAM_ISP_HW_CSID 1 -#define CAM_ISP_HW_VFE 2 -#define CAM_ISP_HW_IFE 3 -#define CAM_ISP_HW_ISPIF 4 -#define CAM_ISP_HW_MAX 5 - -/* Color Pattern */ -#define CAM_ISP_PATTERN_BAYER_RGRGRG 0 -#define CAM_ISP_PATTERN_BAYER_GRGRGR 1 -#define CAM_ISP_PATTERN_BAYER_BGBGBG 2 -#define CAM_ISP_PATTERN_BAYER_GBGBGB 3 -#define CAM_ISP_PATTERN_YUV_YCBYCR 4 -#define CAM_ISP_PATTERN_YUV_YCRYCB 5 -#define CAM_ISP_PATTERN_YUV_CBYCRY 6 -#define CAM_ISP_PATTERN_YUV_CRYCBY 7 -#define CAM_ISP_PATTERN_MAX 8 - -/* Usage Type */ -#define CAM_ISP_RES_USAGE_SINGLE 0 -#define CAM_ISP_RES_USAGE_DUAL 1 -#define CAM_ISP_RES_USAGE_MAX 2 - -/* Resource ID */ -#define CAM_ISP_RES_ID_PORT 0 -#define CAM_ISP_RES_ID_CLK 1 -#define CAM_ISP_RES_ID_MAX 2 - -/* Resource Type - Type of resource for the resource id - * defined in cam_isp_vfe.h, cam_isp_ife.h - */ - -/* Lane Type in input resource for Port */ -#define CAM_ISP_LANE_TYPE_DPHY 0 -#define CAM_ISP_LANE_TYPE_CPHY 1 -#define CAM_ISP_LANE_TYPE_MAX 2 - -/* ISP Resurce Composite Group ID */ -#define CAM_ISP_RES_COMP_GROUP_NONE 0 -#define CAM_ISP_RES_COMP_GROUP_ID_0 1 -#define CAM_ISP_RES_COMP_GROUP_ID_1 2 -#define CAM_ISP_RES_COMP_GROUP_ID_2 3 -#define CAM_ISP_RES_COMP_GROUP_ID_3 4 -#define CAM_ISP_RES_COMP_GROUP_ID_4 5 -#define CAM_ISP_RES_COMP_GROUP_ID_5 6 -#define CAM_ISP_RES_COMP_GROUP_ID_MAX 6 - -/* ISP packet opcode for ISP */ -#define CAM_ISP_PACKET_OP_BASE 0 -#define CAM_ISP_PACKET_INIT_DEV 1 -#define CAM_ISP_PACKET_UPDATE_DEV 2 -#define CAM_ISP_PACKET_OP_MAX 3 - -/* ISP packet meta_data type for command buffer */ -#define CAM_ISP_PACKET_META_BASE 0 -#define CAM_ISP_PACKET_META_LEFT 1 -#define CAM_ISP_PACKET_META_RIGHT 2 -#define CAM_ISP_PACKET_META_COMMON 3 -#define CAM_ISP_PACKET_META_DMI_LEFT 4 -#define CAM_ISP_PACKET_META_DMI_RIGHT 5 -#define CAM_ISP_PACKET_META_DMI_COMMON 6 -#define CAM_ISP_PACKET_META_CLOCK 7 -#define CAM_ISP_PACKET_META_CSID 8 -#define CAM_ISP_PACKET_META_DUAL_CONFIG 9 -#define CAM_ISP_PACKET_META_GENERIC_BLOB_LEFT 10 -#define CAM_ISP_PACKET_META_GENERIC_BLOB_RIGHT 11 -#define CAM_ISP_PACKET_META_GENERIC_BLOB_COMMON 12 - -/* DSP mode */ -#define CAM_ISP_DSP_MODE_NONE 0 -#define CAM_ISP_DSP_MODE_ONE_WAY 1 -#define CAM_ISP_DSP_MODE_ROUND 2 - -/* ISP Generic Cmd Buffer Blob types */ -#define CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG 0 -#define CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1 -#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG 2 - -/* Query devices */ -/** - * struct cam_isp_dev_cap_info - A cap info for particular hw type - * - * @hw_type: Hardware type for the cap info - * @reserved: reserved field for alignment - * @hw_version: Hardware version - * - */ -struct cam_isp_dev_cap_info { - uint32_t hw_type; - uint32_t reserved; - struct cam_hw_version hw_version; -}; - -/** - * struct cam_isp_query_cap_cmd - ISP query device capability payload - * - * @device_iommu: returned iommu handles for device - * @cdm_iommu: returned iommu handles for cdm - * @num_dev: returned number of device capabilities - * @reserved: reserved field for alignment - * @dev_caps: returned device capability array - * - */ -struct cam_isp_query_cap_cmd { - struct cam_iommu_handle device_iommu; - struct cam_iommu_handle cdm_iommu; - int32_t num_dev; - uint32_t reserved; - struct cam_isp_dev_cap_info dev_caps[CAM_ISP_HW_MAX]; -}; - -/* Acquire Device */ -/** - * struct cam_isp_out_port_info - An output port resource info - * - * @res_type: output resource type defined in file - * cam_isp_vfe.h or cam_isp_ife.h - * @format: output format of the resource - * @wdith: output width in pixels - * @height: output height in lines - * @comp_grp_id: composite group id for the resource. - * @split_point: split point in pixels for the dual VFE. - * @secure_mode: flag to tell if output should be run in secure - * mode or not. See cam_defs.h for definition - * @reserved: reserved field for alignment - * - */ -struct cam_isp_out_port_info { - uint32_t res_type; - uint32_t format; - uint32_t width; - uint32_t height; - uint32_t comp_grp_id; - uint32_t split_point; - uint32_t secure_mode; - uint32_t reserved; -}; - -/** - * struct cam_isp_in_port_info - An input port resource info - * - * @res_type: input resource type define in file - * cam_isp_vfe.h or cam_isp_ife.h - * @lane_type: lane type: c-phy or d-phy. - * @lane_num: active lane number - * @lane_cfg: lane configurations: 4 bits per lane - * @vc: input virtual channel number - * @dt: input data type number - * @format: input format - * @test_pattern: test pattern for the testgen - * @usage_type: whether dual vfe is required - * @left_start: left input start offset in pixels - * @left_stop: left input stop offset in pixels - * @left_width: left input width in pixels - * @right_start: right input start offset in pixels. - * Only for Dual VFE - * @right_stop: right input stop offset in pixels. - * Only for Dual VFE - * @right_width: right input width in pixels. - * Only for dual VFE - * @line_start: top of the line number - * @line_stop: bottome of the line number - * @height: input height in lines - * @pixel_clk; sensor output clock - * @batch_size: batch size for HFR mode - * @dsp_mode: DSP stream mode (Defines as CAM_ISP_DSP_MODE_*) - * @hbi_cnt: HBI count for the camif input - * @reserved: Reserved field for alignment - * @num_out_res: number of the output resource associated - * @data: payload that contains the output resources - * - */ -struct cam_isp_in_port_info { - uint32_t res_type; - uint32_t lane_type; - uint32_t lane_num; - uint32_t lane_cfg; - uint32_t vc; - uint32_t dt; - uint32_t format; - uint32_t test_pattern; - uint32_t usage_type; - uint32_t left_start; - uint32_t left_stop; - uint32_t left_width; - uint32_t right_start; - uint32_t right_stop; - uint32_t right_width; - uint32_t line_start; - uint32_t line_stop; - uint32_t height; - uint32_t pixel_clk; - uint32_t batch_size; - uint32_t dsp_mode; - uint32_t hbi_cnt; - uint32_t reserved; - uint32_t num_out_res; - struct cam_isp_out_port_info data[1]; -}; - -/** - * struct cam_isp_resource - A resource bundle - * - * @resoruce_id: resource id for the resource bundle - * @length: length of the while resource blob - * @handle_type: type of the resource handle - * @reserved: reserved field for alignment - * @res_hdl: resource handle that points to the - * resource array; - * - */ -struct cam_isp_resource { - uint32_t resource_id; - uint32_t length; - uint32_t handle_type; - uint32_t reserved; - uint64_t res_hdl; -}; - -/** - * struct cam_isp_port_hfr_config - HFR configuration for this port - * - * @resource_type: Resource type - * @subsample_pattern: Subsample pattern. Used in HFR mode. It - * should be consistent with batchSize and - * CAMIF programming. - * @subsample_period: Subsample period. Used in HFR mode. It - * should be consistent with batchSize and - * CAMIF programming. - * @framedrop_pattern: Framedrop pattern - * @framedrop_period: Framedrop period - * @reserved: Reserved for alignment - */ -struct cam_isp_port_hfr_config { - uint32_t resource_type; - uint32_t subsample_pattern; - uint32_t subsample_period; - uint32_t framedrop_pattern; - uint32_t framedrop_period; - uint32_t reserved; -} __attribute__((packed)); - -/** - * struct cam_isp_resource_hfr_config - Resource HFR configuration - * - * @num_ports: Number of ports - * @reserved: Reserved for alignment - * @port_hfr_config: HFR configuration for each IO port - */ -struct cam_isp_resource_hfr_config { - uint32_t num_ports; - uint32_t reserved; - struct cam_isp_port_hfr_config port_hfr_config[1]; -} __attribute__((packed)); - -/** - * struct cam_isp_dual_split_params - dual isp spilt parameters - * - * @split_point: Split point information x, where (0 < x < width) - * left ISP's input ends at x + righ padding and - * Right ISP's input starts at x - left padding - * @right_padding: Padding added past the split point for left - * ISP's input - * @left_padding: Padding added before split point for right - * ISP's input - * @reserved: Reserved filed for alignment - * - */ -struct cam_isp_dual_split_params { - uint32_t split_point; - uint32_t right_padding; - uint32_t left_padding; - uint32_t reserved; -}; - -/** - * struct cam_isp_dual_stripe_config - stripe config per bus client - * - * @offset: Start horizontal offset relative to - * output buffer - * In UBWC mode, this value indicates the H_INIT - * value in pixel - * @width: Width of the stripe in bytes - * @tileconfig Ubwc meta tile config. Contain the partial - * tile info - * @port_id: port id of ISP output - * - */ -struct cam_isp_dual_stripe_config { - uint32_t offset; - uint32_t width; - uint32_t tileconfig; - uint32_t port_id; -}; - -/** - * struct cam_isp_dual_config - dual isp configuration - * - * @num_ports Number of isp output ports - * @reserved Reserved field for alignment - * @split_params: Inpput split parameters - * @stripes: Stripe information - * - */ -struct cam_isp_dual_config { - uint32_t num_ports; - uint32_t reserved; - struct cam_isp_dual_split_params split_params; - struct cam_isp_dual_stripe_config stripes[1]; -} __attribute__((packed)); - -/** - * struct cam_isp_clock_config - Clock configuration - * - * @usage_type: Usage type (Single/Dual) - * @num_rdi: Number of RDI votes - * @left_pix_hz: Pixel Clock for Left ISP - * @right_pix_hz: Pixel Clock for Right ISP, valid only if Dual - * @rdi_hz: RDI Clock. ISP clock will be max of RDI and - * PIX clocks. For a particular context which ISP - * HW the RDI is allocated to is not known to UMD. - * Hence pass the clock and let KMD decide. - */ -struct cam_isp_clock_config { - uint32_t usage_type; - uint32_t num_rdi; - uint64_t left_pix_hz; - uint64_t right_pix_hz; - uint64_t rdi_hz[1]; -} __attribute__((packed)); - -/** - * struct cam_isp_bw_vote - Bandwidth vote information - * - * @resource_id: Resource ID - * @reserved: Reserved field for alignment - * @cam_bw_bps: Bandwidth vote for CAMNOC - * @ext_bw_bps: Bandwidth vote for path-to-DDR after CAMNOC - */ - -struct cam_isp_bw_vote { - uint32_t resource_id; - uint32_t reserved; - uint64_t cam_bw_bps; - uint64_t ext_bw_bps; -} __attribute__((packed)); - -/** - * struct cam_isp_bw_config - Bandwidth configuration - * - * @usage_type: Usage type (Single/Dual) - * @num_rdi: Number of RDI votes - * @left_pix_vote: Bandwidth vote for left ISP - * @right_pix_vote: Bandwidth vote for right ISP - * @rdi_vote: RDI bandwidth requirements - */ - -struct cam_isp_bw_config { - uint32_t usage_type; - uint32_t num_rdi; - struct cam_isp_bw_vote left_pix_vote; - struct cam_isp_bw_vote right_pix_vote; - struct cam_isp_bw_vote rdi_vote[1]; -} __attribute__((packed)); - -#endif /* __UAPI_CAM_ISP_H__ */ diff --git a/sdm710/original-kernel-headers/media/cam_isp_ife.h b/sdm710/original-kernel-headers/media/cam_isp_ife.h deleted file mode 100644 index f5e72813..00000000 --- a/sdm710/original-kernel-headers/media/cam_isp_ife.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef __UAPI_CAM_ISP_IFE_H__ -#define __UAPI_CAM_ISP_IFE_H__ - -/* IFE output port resource type (global unique)*/ -#define CAM_ISP_IFE_OUT_RES_BASE 0x3000 - -#define CAM_ISP_IFE_OUT_RES_FULL (CAM_ISP_IFE_OUT_RES_BASE + 0) -#define CAM_ISP_IFE_OUT_RES_DS4 (CAM_ISP_IFE_OUT_RES_BASE + 1) -#define CAM_ISP_IFE_OUT_RES_DS16 (CAM_ISP_IFE_OUT_RES_BASE + 2) -#define CAM_ISP_IFE_OUT_RES_RAW_DUMP (CAM_ISP_IFE_OUT_RES_BASE + 3) -#define CAM_ISP_IFE_OUT_RES_FD (CAM_ISP_IFE_OUT_RES_BASE + 4) -#define CAM_ISP_IFE_OUT_RES_PDAF (CAM_ISP_IFE_OUT_RES_BASE + 5) -#define CAM_ISP_IFE_OUT_RES_RDI_0 (CAM_ISP_IFE_OUT_RES_BASE + 6) -#define CAM_ISP_IFE_OUT_RES_RDI_1 (CAM_ISP_IFE_OUT_RES_BASE + 7) -#define CAM_ISP_IFE_OUT_RES_RDI_2 (CAM_ISP_IFE_OUT_RES_BASE + 8) -#define CAM_ISP_IFE_OUT_RES_RDI_3 (CAM_ISP_IFE_OUT_RES_BASE + 9) -#define CAM_ISP_IFE_OUT_RES_STATS_HDR_BE (CAM_ISP_IFE_OUT_RES_BASE + 10) -#define CAM_ISP_IFE_OUT_RES_STATS_HDR_BHIST (CAM_ISP_IFE_OUT_RES_BASE + 11) -#define CAM_ISP_IFE_OUT_RES_STATS_TL_BG (CAM_ISP_IFE_OUT_RES_BASE + 12) -#define CAM_ISP_IFE_OUT_RES_STATS_BF (CAM_ISP_IFE_OUT_RES_BASE + 13) -#define CAM_ISP_IFE_OUT_RES_STATS_AWB_BG (CAM_ISP_IFE_OUT_RES_BASE + 14) -#define CAM_ISP_IFE_OUT_RES_STATS_BHIST (CAM_ISP_IFE_OUT_RES_BASE + 15) -#define CAM_ISP_IFE_OUT_RES_STATS_RS (CAM_ISP_IFE_OUT_RES_BASE + 16) -#define CAM_ISP_IFE_OUT_RES_STATS_CS (CAM_ISP_IFE_OUT_RES_BASE + 17) -#define CAM_ISP_IFE_OUT_RES_STATS_IHIST (CAM_ISP_IFE_OUT_RES_BASE + 18) -#define CAM_ISP_IFE_OUT_RES_MAX (CAM_ISP_IFE_OUT_RES_BASE + 19) - - -/* IFE input port resource type (global unique) */ -#define CAM_ISP_IFE_IN_RES_BASE 0x4000 - -#define CAM_ISP_IFE_IN_RES_TPG (CAM_ISP_IFE_IN_RES_BASE + 0) -#define CAM_ISP_IFE_IN_RES_PHY_0 (CAM_ISP_IFE_IN_RES_BASE + 1) -#define CAM_ISP_IFE_IN_RES_PHY_1 (CAM_ISP_IFE_IN_RES_BASE + 2) -#define CAM_ISP_IFE_IN_RES_PHY_2 (CAM_ISP_IFE_IN_RES_BASE + 3) -#define CAM_ISP_IFE_IN_RES_PHY_3 (CAM_ISP_IFE_IN_RES_BASE + 4) -#define CAM_ISP_IFE_IN_RES_MAX (CAM_ISP_IFE_IN_RES_BASE + 5) - -#endif /* __UAPI_CAM_ISP_IFE_H__ */ diff --git a/sdm710/original-kernel-headers/media/cam_isp_vfe.h b/sdm710/original-kernel-headers/media/cam_isp_vfe.h deleted file mode 100644 index e48db2f9..00000000 --- a/sdm710/original-kernel-headers/media/cam_isp_vfe.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef __UAPI_CAM_ISP_VFE_H__ -#define __UAPI_CAM_ISP_VFE_H__ - -/* VFE output port resource type (global unique) */ -#define CAM_ISP_VFE_OUT_RES_BASE 0x1000 - -#define CAM_ISP_VFE_OUT_RES_ENC (CAM_ISP_VFE_OUT_RES_BASE + 0) -#define CAM_ISP_VFE_OUT_RES_VIEW (CAM_ISP_VFE_OUT_RES_BASE + 1) -#define CAM_ISP_VFE_OUT_RES_VID (CAM_ISP_VFE_OUT_RES_BASE + 2) -#define CAM_ISP_VFE_OUT_RES_RDI_0 (CAM_ISP_VFE_OUT_RES_BASE + 3) -#define CAM_ISP_VFE_OUT_RES_RDI_1 (CAM_ISP_VFE_OUT_RES_BASE + 4) -#define CAM_ISP_VFE_OUT_RES_RDI_2 (CAM_ISP_VFE_OUT_RES_BASE + 5) -#define CAM_ISP_VFE_OUT_RES_RDI_3 (CAM_ISP_VFE_OUT_RES_BASE + 6) -#define CAM_ISP_VFE_OUT_RES_STATS_AEC (CAM_ISP_VFE_OUT_RES_BASE + 7) -#define CAM_ISP_VFE_OUT_RES_STATS_AF (CAM_ISP_VFE_OUT_RES_BASE + 8) -#define CAM_ISP_VFE_OUT_RES_STATS_AWB (CAM_ISP_VFE_OUT_RES_BASE + 9) -#define CAM_ISP_VFE_OUT_RES_STATS_RS (CAM_ISP_VFE_OUT_RES_BASE + 10) -#define CAM_ISP_VFE_OUT_RES_STATS_CS (CAM_ISP_VFE_OUT_RES_BASE + 11) -#define CAM_ISP_VFE_OUT_RES_STATS_IHIST (CAM_ISP_VFE_OUT_RES_BASE + 12) -#define CAM_ISP_VFE_OUT_RES_STATS_SKIN (CAM_ISP_VFE_OUT_RES_BASE + 13) -#define CAM_ISP_VFE_OUT_RES_STATS_BG (CAM_ISP_VFE_OUT_RES_BASE + 14) -#define CAM_ISP_VFE_OUT_RES_STATS_BF (CAM_ISP_VFE_OUT_RES_BASE + 15) -#define CAM_ISP_VFE_OUT_RES_STATS_BE (CAM_ISP_VFE_OUT_RES_BASE + 16) -#define CAM_ISP_VFE_OUT_RES_STATS_BHIST (CAM_ISP_VFE_OUT_RES_BASE + 17) -#define CAM_ISP_VFE_OUT_RES_STATS_BF_SCALE (CAM_ISP_VFE_OUT_RES_BASE + 18) -#define CAM_ISP_VFE_OUT_RES_STATS_HDR_BE (CAM_ISP_VFE_OUT_RES_BASE + 19) -#define CAM_ISP_VFE_OUT_RES_STATS_HDR_BHIST (CAM_ISP_VFE_OUT_RES_BASE + 20) -#define CAM_ISP_VFE_OUT_RES_STATS_AEC_BG (CAM_ISP_VFE_OUT_RES_BASE + 21) -#define CAM_ISP_VFE_OUT_RES_CAMIF_RAW (CAM_ISP_VFE_OUT_RES_BASE + 22) -#define CAM_ISP_VFE_OUT_RES_IDEAL_RAW (CAM_ISP_VFE_OUT_RES_BASE + 23) -#define CAM_ISP_VFE_OUT_RES_MAX (CAM_ISP_VFE_OUT_RES_BASE + 24) - -/* VFE input port_ resource type (global unique) */ -#define CAM_ISP_VFE_IN_RES_BASE 0x2000 - -#define CAM_ISP_VFE_IN_RES_TPG (CAM_ISP_VFE_IN_RES_BASE + 0) -#define CAM_ISP_VFE_IN_RES_PHY_0 (CAM_ISP_VFE_IN_RES_BASE + 1) -#define CAM_ISP_VFE_IN_RES_PHY_1 (CAM_ISP_VFE_IN_RES_BASE + 2) -#define CAM_ISP_VFE_IN_RES_PHY_2 (CAM_ISP_VFE_IN_RES_BASE + 3) -#define CAM_ISP_VFE_IN_RES_PHY_3 (CAM_ISP_VFE_IN_RES_BASE + 4) -#define CAM_ISP_VFE_IN_RES_FE (CAM_ISP_VFE_IN_RES_BASE + 5) -#define CAM_ISP_VFE_IN_RES_MAX (CAM_ISP_VFE_IN_RES_BASE + 6) - -#endif /* __UAPI_CAM_ISP_VFE_H__ */ diff --git a/sdm710/original-kernel-headers/media/cam_jpeg.h b/sdm710/original-kernel-headers/media/cam_jpeg.h deleted file mode 100644 index f3082f3b..00000000 --- a/sdm710/original-kernel-headers/media/cam_jpeg.h +++ /dev/null @@ -1,117 +0,0 @@ -#ifndef __UAPI_CAM_JPEG_H__ -#define __UAPI_CAM_JPEG_H__ - -#include "cam_defs.h" - -/* enc, dma, cdm(enc/dma) are used in querycap */ -#define CAM_JPEG_DEV_TYPE_ENC 0 -#define CAM_JPEG_DEV_TYPE_DMA 1 -#define CAM_JPEG_DEV_TYPE_MAX 2 - -#define CAM_JPEG_NUM_DEV_PER_RES_MAX 1 - -/* definitions needed for jpeg aquire device */ -#define CAM_JPEG_RES_TYPE_ENC 0 -#define CAM_JPEG_RES_TYPE_DMA 1 -#define CAM_JPEG_RES_TYPE_MAX 2 - -/* packet opcode types */ -#define CAM_JPEG_OPCODE_ENC_UPDATE 0 -#define CAM_JPEG_OPCODE_DMA_UPDATE 1 - -/* ENC input port resource type */ -#define CAM_JPEG_ENC_INPUT_IMAGE 0x0 - -/* ENC output port resource type */ -#define CAM_JPEG_ENC_OUTPUT_IMAGE 0x1 - -#define CAM_JPEG_ENC_IO_IMAGES_MAX 0x2 - -/* DMA input port resource type */ -#define CAM_JPEG_DMA_INPUT_IMAGE 0x0 - -/* DMA output port resource type */ -#define CAM_JPEG_DMA_OUTPUT_IMAGE 0x1 - -#define CAM_JPEG_DMA_IO_IMAGES_MAX 0x2 - -#define CAM_JPEG_IMAGE_MAX 0x2 - -/** - * struct cam_jpeg_dev_ver - Device information for particular hw type - * - * This is used to get device version info of JPEG ENC, JPEG DMA - * from hardware and use this info in CAM_QUERY_CAP IOCTL - * - * @size : Size of struct passed - * @dev_type: Hardware type for the cap info(jpeg enc, jpeg dma) - * @hw_ver: Major, minor and incr values of a device version - */ -struct cam_jpeg_dev_ver { - uint32_t size; - uint32_t dev_type; - struct cam_hw_version hw_ver; -}; - -/** - * struct cam_jpeg_query_cap_cmd - JPEG query device capability payload - * - * @dev_iommu_handle: Jpeg iommu handles for secure/non secure - * modes - * @cdm_iommu_handle: Iommu handles for secure/non secure modes - * @num_enc: Number of encoder - * @num_dma: Number of dma - * @dev_ver: Returned device capability array - */ -struct cam_jpeg_query_cap_cmd { - struct cam_iommu_handle dev_iommu_handle; - struct cam_iommu_handle cdm_iommu_handle; - uint32_t num_enc; - uint32_t num_dma; - struct cam_jpeg_dev_ver dev_ver[CAM_JPEG_DEV_TYPE_MAX]; -}; - -/** - * struct cam_jpeg_res_info - JPEG output resource info - * - * @format: Format of the resource - * @width: Width in pixels - * @height: Height in lines - * @fps: Fps - */ -struct cam_jpeg_res_info { - uint32_t format; - uint32_t width; - uint32_t height; - uint32_t fps; -}; - -/** - * struct cam_jpeg_acquire_dev_info - An JPEG device info - * - * @dev_type: Device type (ENC/DMA) - * @reserved: Reserved Bytes - * @in_res: In resource info - * @in_res: Iut resource info - */ -struct cam_jpeg_acquire_dev_info { - uint32_t dev_type; - uint32_t reserved; - struct cam_jpeg_res_info in_res; - struct cam_jpeg_res_info out_res; -}; - -/** - * struct cam_jpeg_config_inout_param_info - JPEG Config time - * input output params - * - * @clk_index: Input Param- clock selection index.(-1 default) - * @output_size: Output Param - jpeg encode/dma output size in - * bytes - */ -struct cam_jpeg_config_inout_param_info { - int32_t clk_index; - int32_t output_size; -}; - -#endif /* __UAPI_CAM_JPEG_H__ */ diff --git a/sdm710/original-kernel-headers/media/cam_lrme.h b/sdm710/original-kernel-headers/media/cam_lrme.h deleted file mode 100644 index 97d95783..00000000 --- a/sdm710/original-kernel-headers/media/cam_lrme.h +++ /dev/null @@ -1,65 +0,0 @@ -#ifndef __UAPI_CAM_LRME_H__ -#define __UAPI_CAM_LRME_H__ - -#include "cam_defs.h" - -/* LRME Resource Types */ - -enum CAM_LRME_IO_TYPE { - CAM_LRME_IO_TYPE_TAR, - CAM_LRME_IO_TYPE_REF, - CAM_LRME_IO_TYPE_RES, - CAM_LRME_IO_TYPE_DS2, -}; - -#define CAM_LRME_INPUT_PORT_TYPE_TAR (1 << 0) -#define CAM_LRME_INPUT_PORT_TYPE_REF (1 << 1) - -#define CAM_LRME_OUTPUT_PORT_TYPE_DS2 (1 << 0) -#define CAM_LRME_OUTPUT_PORT_TYPE_RES (1 << 1) - -#define CAM_LRME_DEV_MAX 1 - - -struct cam_lrme_hw_version { - uint32_t gen; - uint32_t rev; - uint32_t step; -}; - -struct cam_lrme_dev_cap { - struct cam_lrme_hw_version clc_hw_version; - struct cam_lrme_hw_version bus_rd_hw_version; - struct cam_lrme_hw_version bus_wr_hw_version; - struct cam_lrme_hw_version top_hw_version; - struct cam_lrme_hw_version top_titan_version; -}; - -/** - * struct cam_lrme_query_cap_cmd - LRME query device capability payload - * - * @dev_iommu_handle: LRME iommu handles for secure/non secure - * modes - * @cdm_iommu_handle: Iommu handles for secure/non secure modes - * @num_devices: number of hardware devices - * @dev_caps: Returned device capability array - */ -struct cam_lrme_query_cap_cmd { - struct cam_iommu_handle device_iommu; - struct cam_iommu_handle cdm_iommu; - uint32_t num_devices; - struct cam_lrme_dev_cap dev_caps[CAM_LRME_DEV_MAX]; -}; - -struct cam_lrme_soc_info { - uint64_t clock_rate; - uint64_t bandwidth; - uint64_t reserved[4]; -}; - -struct cam_lrme_acquire_args { - struct cam_lrme_soc_info lrme_soc_info; -}; - -#endif /* __UAPI_CAM_LRME_H__ */ - diff --git a/sdm710/original-kernel-headers/media/cam_req_mgr.h b/sdm710/original-kernel-headers/media/cam_req_mgr.h deleted file mode 100644 index a24f1266..00000000 --- a/sdm710/original-kernel-headers/media/cam_req_mgr.h +++ /dev/null @@ -1,434 +0,0 @@ -#ifndef __UAPI_LINUX_CAM_REQ_MGR_H -#define __UAPI_LINUX_CAM_REQ_MGR_H - -#include <linux/videodev2.h> -#include <linux/types.h> -#include <linux/ioctl.h> -#include <linux/media.h> -#include <media/cam_defs.h> - -#define CAM_REQ_MGR_VNODE_NAME "cam-req-mgr-devnode" - -#define CAM_DEVICE_TYPE_BASE (MEDIA_ENT_F_OLD_BASE) -#define CAM_VNODE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE) -#define CAM_SENSOR_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 1) -#define CAM_IFE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 2) -#define CAM_ICP_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 3) -#define CAM_LRME_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 4) -#define CAM_JPEG_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 5) -#define CAM_FD_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 6) -#define CAM_CPAS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 7) -#define CAM_CSIPHY_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 8) -#define CAM_ACTUATOR_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 9) -#define CAM_CCI_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 10) -#define CAM_FLASH_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 11) -#define CAM_EEPROM_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 12) -#define CAM_OIS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 13) - -/* cam_req_mgr hdl info */ -#define CAM_REQ_MGR_HDL_IDX_POS 8 -#define CAM_REQ_MGR_HDL_IDX_MASK ((1 << CAM_REQ_MGR_HDL_IDX_POS) - 1) -#define CAM_REQ_MGR_GET_HDL_IDX(hdl) (hdl & CAM_REQ_MGR_HDL_IDX_MASK) - -/** - * Max handles supported by cam_req_mgr - * It includes both session and device handles - */ -#define CAM_REQ_MGR_MAX_HANDLES 64 -#define MAX_LINKS_PER_SESSION 2 - -/* V4L event type which user space will subscribe to */ -#define V4L_EVENT_CAM_REQ_MGR_EVENT (V4L2_EVENT_PRIVATE_START + 0) - -/* Specific event ids to get notified in user space */ -#define V4L_EVENT_CAM_REQ_MGR_SOF 0 -#define V4L_EVENT_CAM_REQ_MGR_ERROR 1 -#define V4L_EVENT_CAM_REQ_MGR_SOF_BOOT_TS 2 -#define V4L_EVENT_CAM_REQ_MGR_MAX 3 - -/* SOF Event status */ -#define CAM_REQ_MGR_SOF_EVENT_SUCCESS 0 -#define CAM_REQ_MGR_SOF_EVENT_ERROR 1 - -/* Link control operations */ -#define CAM_REQ_MGR_LINK_ACTIVATE 0 -#define CAM_REQ_MGR_LINK_DEACTIVATE 1 - -/** - * Request Manager : flush_type - * @CAM_REQ_MGR_FLUSH_TYPE_ALL: Req mgr will remove all the pending - * requests from input/processing queue. - * @CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ: Req mgr will remove only particular - * request id from input/processing queue. - * @CAM_REQ_MGR_FLUSH_TYPE_MAX: Max number of the flush type - * @opcode: CAM_REQ_MGR_FLUSH_REQ - */ -#define CAM_REQ_MGR_FLUSH_TYPE_ALL 0 -#define CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ 1 -#define CAM_REQ_MGR_FLUSH_TYPE_MAX 2 - -/** - * Request Manager : Sync Mode type - * @CAM_REQ_MGR_SYNC_MODE_NO_SYNC: Req mgr will apply non-sync mode for this - * request. - * @CAM_REQ_MGR_SYNC_MODE_SYNC: Req mgr will apply sync mode for this request. - */ -#define CAM_REQ_MGR_SYNC_MODE_NO_SYNC 0 -#define CAM_REQ_MGR_SYNC_MODE_SYNC 1 - -/** - * struct cam_req_mgr_event_data - * @session_hdl: session handle - * @link_hdl: link handle - * @frame_id: frame id - * @reserved: reserved for 64 bit aligngment - * @req_id: request id - * @tv_sec: timestamp in seconds - * @tv_usec: timestamp in micro seconds - */ -struct cam_req_mgr_event_data { - int32_t session_hdl; - int32_t link_hdl; - int32_t frame_id; - int32_t reserved; - int64_t req_id; - uint64_t tv_sec; - uint64_t tv_usec; -}; - -/** - * struct cam_req_mgr_session_info - * @session_hdl: In/Output param - session_handle - * @opcode1: CAM_REQ_MGR_CREATE_SESSION - * @opcode2: CAM_REQ_MGR_DESTROY_SESSION - */ -struct cam_req_mgr_session_info { - int32_t session_hdl; - int32_t reserved; -}; - -/** - * struct cam_req_mgr_link_info - * @session_hdl: Input param - Identifier for CSL session - * @num_devices: Input Param - Num of devices to be linked - * @dev_hdls: Input param - List of device handles to be linked - * @link_hdl: Output Param -Identifier for link - * @opcode: CAM_REQ_MGR_LINK - */ -struct cam_req_mgr_link_info { - int32_t session_hdl; - uint32_t num_devices; - int32_t dev_hdls[CAM_REQ_MGR_MAX_HANDLES]; - int32_t link_hdl; -}; - -/** - * struct cam_req_mgr_unlink_info - * @session_hdl: input param - session handle - * @link_hdl: input param - link handle - * @opcode: CAM_REQ_MGR_UNLINK - */ -struct cam_req_mgr_unlink_info { - int32_t session_hdl; - int32_t link_hdl; -}; - -/** - * struct cam_req_mgr_flush_info - * @brief: User can tell drivers to flush a particular request id or - * flush all requests from its pending processing queue. Flush is a - * blocking call and driver shall ensure all requests are flushed - * before returning. - * @session_hdl: Input param - Identifier for CSL session - * @link_hdl: Input Param -Identifier for link - * @flush_type: User can cancel a particular req id or can flush - * all requests in queue - * @reserved: reserved for 64 bit aligngment - * @req_id: field is valid only if flush type is cancel request - * for flush all this field value is not considered. - * @opcode: CAM_REQ_MGR_FLUSH_REQ - */ -struct cam_req_mgr_flush_info { - int32_t session_hdl; - int32_t link_hdl; - uint32_t flush_type; - uint32_t reserved; - int64_t req_id; -}; - -/** struct cam_req_mgr_sched_info - * @session_hdl: Input param - Identifier for CSL session - * @link_hdl: Input Param -Identifier for link - * inluding itself. - * @bubble_enable: Input Param - Cam req mgr will do bubble recovery if this - * flag is set. - * @sync_mode: Type of Sync mode for this request - * @req_id: Input Param - Request Id from which all requests will be flushed - */ -struct cam_req_mgr_sched_request { - int32_t session_hdl; - int32_t link_hdl; - int32_t bubble_enable; - int32_t sync_mode; - int64_t req_id; -}; - -/** - * struct cam_req_mgr_sync_mode - * @session_hdl: Input param - Identifier for CSL session - * @sync_mode: Input Param - Type of sync mode - * @num_links: Input Param - Num of links in sync mode (Valid only - * when sync_mode is one of SYNC enabled modes) - * @link_hdls: Input Param - Array of link handles to be in sync mode - * (Valid only when sync_mode is one of SYNC - * enabled modes) - * @master_link_hdl: Input Param - To dictate which link's SOF drives system - * (Valid only when sync_mode is one of SYNC - * enabled modes) - * - * @opcode: CAM_REQ_MGR_SYNC_MODE - */ -struct cam_req_mgr_sync_mode { - int32_t session_hdl; - int32_t sync_mode; - int32_t num_links; - int32_t link_hdls[MAX_LINKS_PER_SESSION]; - int32_t master_link_hdl; - int32_t reserved; -}; - -/** - * struct cam_req_mgr_link_control - * @ops: Link operations: activate/deactive - * @session_hdl: Input param - Identifier for CSL session - * @num_links: Input Param - Num of links - * @reserved: reserved field - * @link_hdls: Input Param - Links to be activated/deactivated - * - * @opcode: CAM_REQ_MGR_LINK_CONTROL - */ -struct cam_req_mgr_link_control { - int32_t ops; - int32_t session_hdl; - int32_t num_links; - int32_t reserved; - int32_t link_hdls[MAX_LINKS_PER_SESSION]; -}; - -/** - * cam_req_mgr specific opcode ids - */ -#define CAM_REQ_MGR_CREATE_DEV_NODES (CAM_COMMON_OPCODE_MAX + 1) -#define CAM_REQ_MGR_CREATE_SESSION (CAM_COMMON_OPCODE_MAX + 2) -#define CAM_REQ_MGR_DESTROY_SESSION (CAM_COMMON_OPCODE_MAX + 3) -#define CAM_REQ_MGR_LINK (CAM_COMMON_OPCODE_MAX + 4) -#define CAM_REQ_MGR_UNLINK (CAM_COMMON_OPCODE_MAX + 5) -#define CAM_REQ_MGR_SCHED_REQ (CAM_COMMON_OPCODE_MAX + 6) -#define CAM_REQ_MGR_FLUSH_REQ (CAM_COMMON_OPCODE_MAX + 7) -#define CAM_REQ_MGR_SYNC_MODE (CAM_COMMON_OPCODE_MAX + 8) -#define CAM_REQ_MGR_ALLOC_BUF (CAM_COMMON_OPCODE_MAX + 9) -#define CAM_REQ_MGR_MAP_BUF (CAM_COMMON_OPCODE_MAX + 10) -#define CAM_REQ_MGR_RELEASE_BUF (CAM_COMMON_OPCODE_MAX + 11) -#define CAM_REQ_MGR_CACHE_OPS (CAM_COMMON_OPCODE_MAX + 12) -#define CAM_REQ_MGR_LINK_CONTROL (CAM_COMMON_OPCODE_MAX + 13) -/* end of cam_req_mgr opcodes */ - -#define CAM_MEM_FLAG_HW_READ_WRITE (1<<0) -#define CAM_MEM_FLAG_HW_READ_ONLY (1<<1) -#define CAM_MEM_FLAG_HW_WRITE_ONLY (1<<2) -#define CAM_MEM_FLAG_KMD_ACCESS (1<<3) -#define CAM_MEM_FLAG_UMD_ACCESS (1<<4) -#define CAM_MEM_FLAG_PROTECTED_MODE (1<<5) -#define CAM_MEM_FLAG_CMD_BUF_TYPE (1<<6) -#define CAM_MEM_FLAG_PIXEL_BUF_TYPE (1<<7) -#define CAM_MEM_FLAG_STATS_BUF_TYPE (1<<8) -#define CAM_MEM_FLAG_PACKET_BUF_TYPE (1<<9) -#define CAM_MEM_FLAG_CACHE (1<<10) -#define CAM_MEM_FLAG_HW_SHARED_ACCESS (1<<11) - -#define CAM_MEM_MMU_MAX_HANDLE 16 - -/* Maximum allowed buffers in existence */ -#define CAM_MEM_BUFQ_MAX 1024 - -#define CAM_MEM_MGR_SECURE_BIT_POS 15 -#define CAM_MEM_MGR_HDL_IDX_SIZE 15 -#define CAM_MEM_MGR_HDL_FD_SIZE 16 -#define CAM_MEM_MGR_HDL_IDX_END_POS 16 -#define CAM_MEM_MGR_HDL_FD_END_POS 32 - -#define CAM_MEM_MGR_HDL_IDX_MASK ((1 << CAM_MEM_MGR_HDL_IDX_SIZE) - 1) - -#define GET_MEM_HANDLE(idx, fd) \ - ((idx & CAM_MEM_MGR_HDL_IDX_MASK) | \ - (fd << (CAM_MEM_MGR_HDL_FD_END_POS - CAM_MEM_MGR_HDL_FD_SIZE))) \ - -#define CAM_MEM_MGR_GET_HDL_IDX(hdl) (hdl & CAM_MEM_MGR_HDL_IDX_MASK) - -#define CAM_MEM_MGR_SET_SECURE_HDL(hdl, flag) \ - ((flag) ? (hdl |= (1 << CAM_MEM_MGR_SECURE_BIT_POS)) : \ - ((hdl) &= ~(1 << CAM_MEM_MGR_SECURE_BIT_POS))) - -#define CAM_MEM_MGR_IS_SECURE_HDL(hdl) \ - (((hdl) & \ - (1<<CAM_MEM_MGR_SECURE_BIT_POS)) >> CAM_MEM_MGR_SECURE_BIT_POS) - -/** - * memory allocation type - */ -#define CAM_MEM_DMA_NONE 0 -#define CAM_MEM_DMA_BIDIRECTIONAL 1 -#define CAM_MEM_DMA_TO_DEVICE 2 -#define CAM_MEM_DMA_FROM_DEVICE 3 - - -/** - * memory cache operation - */ -#define CAM_MEM_CLEAN_CACHE 1 -#define CAM_MEM_INV_CACHE 2 -#define CAM_MEM_CLEAN_INV_CACHE 3 - - -/** - * struct cam_mem_alloc_out_params - * @buf_handle: buffer handle - * @fd: output buffer file descriptor - * @vaddr: virtual address pointer - */ -struct cam_mem_alloc_out_params { - uint32_t buf_handle; - int32_t fd; - uint64_t vaddr; -}; - -/** - * struct cam_mem_map_out_params - * @buf_handle: buffer handle - * @reserved: reserved for future - * @vaddr: virtual address pointer - */ -struct cam_mem_map_out_params { - uint32_t buf_handle; - uint32_t reserved; - uint64_t vaddr; -}; - -/** - * struct cam_mem_mgr_alloc_cmd - * @len: size of buffer to allocate - * @align: alignment of the buffer - * @mmu_hdls: array of mmu handles - * @num_hdl: number of handles - * @flags: flags of the buffer - * @out: out params - */ -/* CAM_REQ_MGR_ALLOC_BUF */ -struct cam_mem_mgr_alloc_cmd { - uint64_t len; - uint64_t align; - int32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE]; - uint32_t num_hdl; - uint32_t flags; - struct cam_mem_alloc_out_params out; -}; - -/** - * struct cam_mem_mgr_map_cmd - * @mmu_hdls: array of mmu handles - * @num_hdl: number of handles - * @flags: flags of the buffer - * @fd: output buffer file descriptor - * @reserved: reserved field - * @out: out params - */ - -/* CAM_REQ_MGR_MAP_BUF */ -struct cam_mem_mgr_map_cmd { - int32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE]; - uint32_t num_hdl; - uint32_t flags; - int32_t fd; - uint32_t reserved; - struct cam_mem_map_out_params out; -}; - -/** - * struct cam_mem_mgr_map_cmd - * @buf_handle: buffer handle - * @reserved: reserved field - */ -/* CAM_REQ_MGR_RELEASE_BUF */ -struct cam_mem_mgr_release_cmd { - int32_t buf_handle; - uint32_t reserved; -}; - -/** - * struct cam_mem_mgr_map_cmd - * @buf_handle: buffer handle - * @ops: cache operations - */ -/* CAM_REQ_MGR_CACHE_OPS */ -struct cam_mem_cache_ops_cmd { - int32_t buf_handle; - uint32_t mem_cache_ops; -}; - -/** - * Request Manager : error message type - * @CAM_REQ_MGR_ERROR_TYPE_DEVICE: Device error message, fatal to session - * @CAM_REQ_MGR_ERROR_TYPE_REQUEST: Error on a single request, not fatal - * @CAM_REQ_MGR_ERROR_TYPE_BUFFER: Buffer was not filled, not fatal - */ -#define CAM_REQ_MGR_ERROR_TYPE_DEVICE 0 -#define CAM_REQ_MGR_ERROR_TYPE_REQUEST 1 -#define CAM_REQ_MGR_ERROR_TYPE_BUFFER 2 - -/** - * struct cam_req_mgr_error_msg - * @error_type: type of error - * @request_id: request id of frame - * @device_hdl: device handle - * @linke_hdl: link_hdl - * @resource_size: size of the resource - */ -struct cam_req_mgr_error_msg { - uint32_t error_type; - uint32_t request_id; - int32_t device_hdl; - int32_t link_hdl; - uint64_t resource_size; -}; - -/** - * struct cam_req_mgr_frame_msg - * @request_id: request id of the frame - * @frame_id: frame id of the frame - * @timestamp: timestamp of the frame - * @link_hdl: link handle associated with this message - * @sof_status: sof status success or fail - */ -struct cam_req_mgr_frame_msg { - uint64_t request_id; - uint64_t frame_id; - uint64_t timestamp; - int32_t link_hdl; - uint32_t sof_status; -}; - -/** - * struct cam_req_mgr_message - * @session_hdl: session to which the frame belongs to - * @reserved: reserved field - * @u: union which can either be error or frame message - */ -struct cam_req_mgr_message { - int32_t session_hdl; - int32_t reserved; - union { - struct cam_req_mgr_error_msg err_msg; - struct cam_req_mgr_frame_msg frame_msg; - } u; -}; -#endif /* __UAPI_LINUX_CAM_REQ_MGR_H */ diff --git a/sdm710/original-kernel-headers/media/cam_sensor.h b/sdm710/original-kernel-headers/media/cam_sensor.h deleted file mode 100644 index 2fcd6f53..00000000 --- a/sdm710/original-kernel-headers/media/cam_sensor.h +++ /dev/null @@ -1,526 +0,0 @@ -#ifndef __UAPI_CAM_SENSOR_H__ -#define __UAPI_CAM_SENSOR_H__ - -#include <linux/types.h> -#include <linux/ioctl.h> -#include <media/cam_defs.h> - -#define CAM_SENSOR_PROBE_CMD (CAM_COMMON_OPCODE_MAX + 1) -#define CAM_FLASH_MAX_LED_TRIGGERS 3 -#define MAX_OIS_NAME_SIZE 32 -#define CAM_CSIPHY_SECURE_MODE_ENABLED 1 -#define MAX_RAINBOW_CONFIG_SIZE 32 - -enum rainbow_op_type { - RAINBOW_SEQ_READ, - RAINBOW_RANDOM_READ, - RAINBOW_SEQ_WRITE, - RAINBOW_RANDOM_WRITE -}; - -struct rainbow_config { - enum rainbow_op_type operation; - uint32_t size; - uint32_t reg_addr[MAX_RAINBOW_CONFIG_SIZE]; - uint32_t reg_data[MAX_RAINBOW_CONFIG_SIZE]; -} __attribute__((packed)); - -#define RAINBOW_CONFIG \ - _IOWR('R', 1, struct rainbow_config) - -/** - * struct cam_sensor_query_cap - capabilities info for sensor - * - * @slot_info : Indicates about the slotId or cell Index - * @secure_camera : Camera is in secure/Non-secure mode - * @pos_pitch : Sensor position pitch - * @pos_roll : Sensor position roll - * @pos_yaw : Sensor position yaw - * @actuator_slot_id : Actuator slot id which connected to sensor - * @eeprom_slot_id : EEPROM slot id which connected to sensor - * @ois_slot_id : OIS slot id which connected to sensor - * @flash_slot_id : Flash slot id which connected to sensor - * @csiphy_slot_id : CSIphy slot id which connected to sensor - * - */ -struct cam_sensor_query_cap { - uint32_t slot_info; - uint32_t secure_camera; - uint32_t pos_pitch; - uint32_t pos_roll; - uint32_t pos_yaw; - uint32_t actuator_slot_id; - uint32_t eeprom_slot_id; - uint32_t ois_slot_id; - uint32_t flash_slot_id; - uint32_t csiphy_slot_id; -} __attribute__((packed)); - -/** - * struct cam_csiphy_query_cap - capabilities info for csiphy - * - * @slot_info : Indicates about the slotId or cell Index - * @version : CSIphy version - * @clk lane : Of the 5 lanes, informs lane configured - * as clock lane - * @reserved - */ -struct cam_csiphy_query_cap { - uint32_t slot_info; - uint32_t version; - uint32_t clk_lane; - uint32_t reserved; -} __attribute__((packed)); - -/** - * struct cam_actuator_query_cap - capabilities info for actuator - * - * @slot_info : Indicates about the slotId or cell Index - * @reserved - */ -struct cam_actuator_query_cap { - uint32_t slot_info; - uint32_t reserved; -} __attribute__((packed)); - -/** - * struct cam_eeprom_query_cap_t - capabilities info for eeprom - * - * @slot_info : Indicates about the slotId or cell Index - * @eeprom_kernel_probe : Indicates about the kernel or userspace probe - */ -struct cam_eeprom_query_cap_t { - uint32_t slot_info; - uint16_t eeprom_kernel_probe; - uint16_t reserved; -} __attribute__((packed)); - -/** - * struct cam_ois_query_cap_t - capabilities info for ois - * - * @slot_info : Indicates about the slotId or cell Index - */ -struct cam_ois_query_cap_t { - uint32_t slot_info; - uint16_t reserved; -} __attribute__((packed)); - -/** - * struct cam_cmd_i2c_info - Contains slave I2C related info - * - * @slave_addr : Slave address - * @i2c_freq_mode : 4 bits are used for I2c freq mode - * @cmd_type : Explains type of command - */ -struct cam_cmd_i2c_info { - uint16_t slave_addr; - uint8_t i2c_freq_mode; - uint8_t cmd_type; -} __attribute__((packed)); - -/** - * struct cam_cmd_get_ois_data - Contains OIS data read cmd - * - * @reg_addr : register addr to read data from - * @reg_data : number of bytes to read - * @query_size_handle : handle to user space query_size address - * @query_data_handle : handle to user space query_data address - */ -struct cam_cmd_get_ois_data { - uint32_t reg_addr; - uint32_t reg_data; - uint64_t query_size_handle; - uint64_t query_data_handle; -} __attribute__((packed)); - -/** - * struct cam_ois_shift - Contains OIS shift data - * - * @ois_shift_x : shift in x dim - * @ois_shift_y : shift in y dim - * @time_readout : time that the shift is read out - */ -struct cam_ois_shift { - int16_t ois_shift_x; - int16_t ois_shift_y; - int64_t time_readout; -} __attribute__((packed)); - -/** - * struct cam_ois_opcode - Contains OIS opcode - * - * @prog : OIS FW prog register address - * @coeff : OIS FW coeff register address - * @pheripheral : OIS pheripheral - * @memory : OIS memory - */ -struct cam_ois_opcode { - uint32_t prog; - uint32_t coeff; - uint32_t pheripheral; - uint32_t memory; -} __attribute__((packed)); - -/** - * struct cam_cmd_ois_info - Contains OIS slave info - * - * @slave_addr : OIS i2c slave address - * @i2c_freq_mode : i2c frequency mode - * @cmd_type : Explains type of command - * @ois_fw_flag : indicates if fw is present or not - * @is_ois_calib : indicates the calibration data is available - * @ois_name : OIS name - * @opcode : opcode - */ -struct cam_cmd_ois_info { - uint16_t slave_addr; - uint8_t i2c_freq_mode; - uint8_t cmd_type; - uint8_t ois_fw_flag; - uint8_t is_ois_calib; - char ois_name[MAX_OIS_NAME_SIZE]; - struct cam_ois_opcode opcode; -} __attribute__((packed)); - -/** - * struct cam_cmd_probe - Contains sensor slave info - * - * @data_type : Slave register data type - * @addr_type : Slave register address type - * @op_code : Don't Care - * @cmd_type : Explains type of command - * @reg_addr : Slave register address - * @expected_data : Data expected at slave register address - * @data_mask : Data mask if only few bits are valid - * @camera_id : Indicates the slot to which camera - * needs to be probed - * @fw_update_flag : Update OIS firmware - * @reserved - */ -struct cam_cmd_probe { - uint8_t data_type; - uint8_t addr_type; - uint8_t op_code; - uint8_t cmd_type; - uint32_t reg_addr; - uint32_t expected_data; - uint32_t data_mask; - uint16_t camera_id; - uint8_t fw_update_flag; - uint16_t reserved; -} __attribute__((packed)); - -/** - * struct cam_power_settings - Contains sensor power setting info - * - * @power_seq_type : Type of power sequence - * @reserved - * @config_val_low : Lower 32 bit value configuration value - * @config_val_high : Higher 32 bit value configuration value - * - */ -struct cam_power_settings { - uint16_t power_seq_type; - uint16_t reserved; - uint32_t config_val_low; - uint32_t config_val_high; -} __attribute__((packed)); - -/** - * struct cam_cmd_power - Explains about the power settings - * - * @count : Number of power settings follows - * @reserved - * @cmd_type : Explains type of command - * @power_settings : Contains power setting info - */ -struct cam_cmd_power { - uint16_t count; - uint8_t reserved; - uint8_t cmd_type; - struct cam_power_settings power_settings[1]; -} __attribute__((packed)); - -/** - * struct i2c_rdwr_header - header of READ/WRITE I2C command - * - * @ count : Number of registers / data / reg-data pairs - * @ op_code : Operation code - * @ cmd_type : Command buffer type - * @ data_type : I2C data type - * @ addr_type : I2C address type - * @ slave_addr : Slave address - */ -struct i2c_rdwr_header { - uint16_t count; - uint8_t op_code; - uint8_t cmd_type; - uint8_t data_type; - uint8_t addr_type; - uint16_t slave_addr; -} __attribute__((packed)); - -/** - * struct i2c_random_wr_payload - payload for I2C random write - * - * @ reg_addr : Register address - * @ reg_data : Register data - * - */ -struct i2c_random_wr_payload { - uint32_t reg_addr; - uint32_t reg_data; -} __attribute__((packed)); - -/** - * struct cam_cmd_i2c_random_wr - I2C random write command - * @ header : header of READ/WRITE I2C command - * @ random_wr_payload : payload for I2C random write - */ -struct cam_cmd_i2c_random_wr { - struct i2c_rdwr_header header; - struct i2c_random_wr_payload random_wr_payload[1]; -} __attribute__((packed)); - -/** - * struct cam_cmd_read - I2C read command - * @ reg_data : Register data - * @ reserved - */ -struct cam_cmd_read { - uint32_t reg_data; - uint32_t reserved; -} __attribute__((packed)); - -/** - * struct cam_cmd_i2c_continuous_wr - I2C continuous write command - * @ header : header of READ/WRITE I2C command - * @ reg_addr : Register address - * @ data_read : I2C read command - */ -struct cam_cmd_i2c_continuous_wr { - struct i2c_rdwr_header header; - uint32_t reg_addr; - struct cam_cmd_read data_read[1]; -} __attribute__((packed)); - -/** - * struct cam_cmd_i2c_random_rd - I2C random read command - * @ header : header of READ/WRITE I2C command - * @ data_read : I2C read command - */ -struct cam_cmd_i2c_random_rd { - struct i2c_rdwr_header header; - struct cam_cmd_read data_read[1]; -} __attribute__((packed)); - -/** - * struct cam_cmd_i2c_continuous_rd - I2C continuous continuous read command - * @ header : header of READ/WRITE I2C command - * @ reg_addr : Register address - * - */ -struct cam_cmd_i2c_continuous_rd { - struct i2c_rdwr_header header; - uint32_t reg_addr; -} __attribute__((packed)); - -/** - * struct cam_cmd_conditional_wait - Conditional wait command - * @data_type : Data type - * @addr_type : Address type - * @op_code : Opcode - * @cmd_type : Explains type of command - * @timeout : Timeout for retries - * @reserved - * @reg_addr : Register Address - * @reg_data : Register data - * @data_mask : Data mask if only few bits are valid - * @camera_id : Indicates the slot to which camera - * needs to be probed - * - */ -struct cam_cmd_conditional_wait { - uint8_t data_type; - uint8_t addr_type; - uint8_t op_code; - uint8_t cmd_type; - uint16_t timeout; - uint16_t reserved; - uint32_t reg_addr; - uint32_t reg_data; - uint32_t data_mask; -} __attribute__((packed)); - -/** - * struct cam_cmd_unconditional_wait - Un-conditional wait command - * @delay : Delay - * @op_code : Opcode - * @cmd_type : Explains type of command - */ -struct cam_cmd_unconditional_wait { - int16_t delay; - uint8_t op_code; - uint8_t cmd_type; -} __attribute__((packed)); - -/** - * cam_csiphy_info: Provides cmdbuffer structre - * @lane_mask : Lane mask details - * @lane_assign : Lane sensor will be using - * @csiphy_3phase : Total number of lanes - * @combo_mode : Info regarding combo_mode is enable / disable - * @lane_cnt : Total number of lanes - * @secure_mode : Secure mode flag to enable / disable - * @3phase : Details whether 3Phase / 2Phase operation - * @settle_time : Settling time in ms - * @data_rate : Data rate - * - */ -struct cam_csiphy_info { - uint16_t lane_mask; - uint16_t lane_assign; - uint8_t csiphy_3phase; - uint8_t combo_mode; - uint8_t lane_cnt; - uint8_t secure_mode; - uint64_t settle_time; - uint64_t data_rate; -} __attribute__((packed)); - -/** - * cam_csiphy_acquire_dev_info : Information needed for - * csiphy at the time of acquire - * @combo_mode : Indicates the device mode of operation - * @reserved - * - */ -struct cam_csiphy_acquire_dev_info { - uint32_t combo_mode; - uint32_t reserved; -} __attribute__((packed)); - -/** - * cam_sensor_acquire_dev : Updates sensor acuire cmd - * @device_handle : Updates device handle - * @session_handle : Session handle for acquiring device - * @handle_type : Resource handle type - * @reserved - * @info_handle : Handle to additional info - * needed for sensor sub modules - * - */ -struct cam_sensor_acquire_dev { - uint32_t session_handle; - uint32_t device_handle; - uint32_t handle_type; - uint32_t reserved; - uint64_t info_handle; -} __attribute__((packed)); - -/** - * cam_sensor_streamon_dev : StreamOn command for the sensor - * @session_handle : Session handle for acquiring device - * @device_handle : Updates device handle - * @handle_type : Resource handle type - * @reserved - * @info_handle : Information Needed at the time of streamOn - * - */ -struct cam_sensor_streamon_dev { - uint32_t session_handle; - uint32_t device_handle; - uint32_t handle_type; - uint32_t reserved; - uint64_t info_handle; -} __attribute__((packed)); - -/** - * struct cam_flash_init : Init command for the flash - * @flash_type : flash hw type - * @reserved - * @cmd_type : command buffer type - */ -struct cam_flash_init { - uint8_t flash_type; - uint16_t reserved; - uint8_t cmd_type; -} __attribute__((packed)); - -/** - * struct cam_flash_set_rer : RedEyeReduction command buffer - * - * @count : Number of flash leds - * @opcode : Command buffer opcode - * CAM_FLASH_FIRE_RER - * @cmd_type : command buffer operation type - * @num_iteration : Number of led turn on/off sequence - * @reserved - * @led_on_delay_ms : flash led turn on time in ms - * @led_off_delay_ms : flash led turn off time in ms - * @led_current_ma : flash led current in ma - * - */ -struct cam_flash_set_rer { - uint16_t count; - uint8_t opcode; - uint8_t cmd_type; - uint16_t num_iteration; - uint16_t reserved; - uint32_t led_on_delay_ms; - uint32_t led_off_delay_ms; - uint32_t led_current_ma[CAM_FLASH_MAX_LED_TRIGGERS]; -} __attribute__((packed)); - -/** - * struct cam_flash_set_on_off : led turn on/off command buffer - * - * @count : Number of Flash leds - * @opcode : command buffer opcodes - * CAM_FLASH_FIRE_LOW - * CAM_FLASH_FIRE_HIGH - * CAM_FLASH_OFF - * @cmd_type : command buffer operation type - * @led_current_ma : flash led current in ma - * - */ -struct cam_flash_set_on_off { - uint16_t count; - uint8_t opcode; - uint8_t cmd_type; - uint32_t led_current_ma[CAM_FLASH_MAX_LED_TRIGGERS]; -} __attribute__((packed)); - -/** - * struct cam_flash_query_curr : query current command buffer - * - * @reserved - * @opcode : command buffer opcode - * @cmd_type : command buffer operation type - * @query_current_ma : battery current in ma - * - */ -struct cam_flash_query_curr { - uint16_t reserved; - uint8_t opcode; - uint8_t cmd_type; - uint32_t query_current_ma; -} __attribute__ ((packed)); - -/** - * struct cam_flash_query_cap : capabilities info for flash - * - * @slot_info : Indicates about the slotId or cell Index - * @max_current_flash : max supported current for flash - * @max_duration_flash : max flash turn on duration - * @max_current_torch : max supported current for torch - * - */ -struct cam_flash_query_cap_info { - uint32_t slot_info; - uint32_t max_current_flash[CAM_FLASH_MAX_LED_TRIGGERS]; - uint32_t max_duration_flash[CAM_FLASH_MAX_LED_TRIGGERS]; - uint32_t max_current_torch[CAM_FLASH_MAX_LED_TRIGGERS]; -} __attribute__ ((packed)); - -#endif diff --git a/sdm710/original-kernel-headers/media/cam_sync.h b/sdm710/original-kernel-headers/media/cam_sync.h deleted file mode 100644 index 4a8781fc..00000000 --- a/sdm710/original-kernel-headers/media/cam_sync.h +++ /dev/null @@ -1,134 +0,0 @@ -#ifndef __UAPI_CAM_SYNC_H__ -#define __UAPI_CAM_SYNC_H__ - -#include <linux/videodev2.h> -#include <linux/types.h> -#include <linux/ioctl.h> -#include <linux/media.h> - -#define CAM_SYNC_DEVICE_NAME "cam_sync_device" - -/* V4L event which user space will subscribe to */ -#define CAM_SYNC_V4L_EVENT (V4L2_EVENT_PRIVATE_START + 0) - -/* Specific event ids to get notified in user space */ -#define CAM_SYNC_V4L_EVENT_ID_CB_TRIG 0 - -/* Size of opaque payload sent to kernel for safekeeping until signal time */ -#define CAM_SYNC_USER_PAYLOAD_SIZE 2 - -/* Device type for sync device needed for device discovery */ -#define CAM_SYNC_DEVICE_TYPE (MEDIA_ENT_F_OLD_BASE) - -#define CAM_SYNC_GET_PAYLOAD_PTR(ev, type) \ - (type *)((char *)ev.u.data + sizeof(struct cam_sync_ev_header)) - -#define CAM_SYNC_GET_HEADER_PTR(ev) \ - ((struct cam_sync_ev_header *)ev.u.data) - -#define CAM_SYNC_STATE_INVALID 0 -#define CAM_SYNC_STATE_ACTIVE 1 -#define CAM_SYNC_STATE_SIGNALED_SUCCESS 2 -#define CAM_SYNC_STATE_SIGNALED_ERROR 3 - -/** - * struct cam_sync_ev_header - Event header for sync event notification - * - * @sync_obj: Sync object - * @status: Status of the object - */ -struct cam_sync_ev_header { - int32_t sync_obj; - int32_t status; -}; - -/** - * struct cam_sync_info - Sync object creation information - * - * @name: Optional string representation of the sync object - * @sync_obj: Sync object returned after creation in kernel - */ -struct cam_sync_info { - char name[64]; - int32_t sync_obj; -}; - -/** - * struct cam_sync_signal - Sync object signaling struct - * - * @sync_obj: Sync object to be signaled - * @sync_state: State of the sync object to which it should be signaled - */ -struct cam_sync_signal { - int32_t sync_obj; - uint32_t sync_state; -}; - -/** - * struct cam_sync_merge - Merge information for sync objects - * - * @sync_objs: Pointer to sync objects - * @num_objs: Number of objects in the array - * @merged: Merged sync object - */ -struct cam_sync_merge { - __u64 sync_objs; - uint32_t num_objs; - int32_t merged; -}; - -/** - * struct cam_sync_userpayload_info - Payload info from user space - * - * @sync_obj: Sync object for which payload has to be registered for - * @reserved: Reserved - * @payload: Pointer to user payload - */ -struct cam_sync_userpayload_info { - int32_t sync_obj; - uint32_t reserved; - __u64 payload[CAM_SYNC_USER_PAYLOAD_SIZE]; -}; - -/** - * struct cam_sync_wait - Sync object wait information - * - * @sync_obj: Sync object to wait on - * @reserved: Reserved - * @timeout_ms: Timeout in milliseconds - */ -struct cam_sync_wait { - int32_t sync_obj; - uint32_t reserved; - uint64_t timeout_ms; -}; - -/** - * struct cam_private_ioctl_arg - Sync driver ioctl argument - * - * @id: IOCTL command id - * @size: Size of command payload - * @result: Result of command execution - * @reserved: Reserved - * @ioctl_ptr: Pointer to user data - */ -struct cam_private_ioctl_arg { - __u32 id; - __u32 size; - __u32 result; - __u32 reserved; - __u64 ioctl_ptr; -}; - -#define CAM_PRIVATE_IOCTL_CMD \ - _IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_private_ioctl_arg) - -#define CAM_SYNC_CREATE 0 -#define CAM_SYNC_DESTROY 1 -#define CAM_SYNC_SIGNAL 2 -#define CAM_SYNC_MERGE 3 -#define CAM_SYNC_REGISTER_PAYLOAD 4 -#define CAM_SYNC_DEREGISTER_PAYLOAD 5 -#define CAM_SYNC_WAIT 6 - -#endif /* __UAPI_CAM_SYNC_H__ */ diff --git a/sdm710/original-kernel-headers/media/msm_cam_sensor.h b/sdm710/original-kernel-headers/media/msm_cam_sensor.h deleted file mode 100644 index 56685f10..00000000 --- a/sdm710/original-kernel-headers/media/msm_cam_sensor.h +++ /dev/null @@ -1,635 +0,0 @@ -#ifndef __UAPI_LINUX_MSM_CAM_SENSOR_H -#define __UAPI_LINUX_MSM_CAM_SENSOR_H - -#include <linux/v4l2-mediabus.h> -#include <media/msm_camsensor_sdk.h> - -#include <linux/types.h> -#include <linux/i2c.h> - -#define I2C_SEQ_REG_SETTING_MAX 5 - -#define MSM_SENSOR_MCLK_8HZ 8000000 -#define MSM_SENSOR_MCLK_16HZ 16000000 -#define MSM_SENSOR_MCLK_24HZ 24000000 - -#define MAX_SENSOR_NAME 32 -#define MAX_ACTUATOR_AF_TOTAL_STEPS 1024 - -#define MAX_OIS_MOD_NAME_SIZE 32 -#define MAX_OIS_NAME_SIZE 32 -#define MAX_OIS_REG_SETTINGS 800 - -#define MOVE_NEAR 0 -#define MOVE_FAR 1 - -#define MSM_ACTUATOR_MOVE_SIGNED_FAR -1 -#define MSM_ACTUATOR_MOVE_SIGNED_NEAR 1 - -#define MAX_ACTUATOR_REGION 5 - -#define MAX_EEPROM_NAME 32 - -#define MAX_AF_ITERATIONS 3 -#define MAX_NUMBER_OF_STEPS 47 -#define MAX_REGULATOR 5 - -/*msm_flash_query_data_t query types*/ -#define FLASH_QUERY_CURRENT 1 - -#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */ -#define MSM_V4L2_PIX_FMT_META10 v4l2_fourcc('M', 'E', '1', '0') /* META10 */ -#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') - /* 14 BGBG.. GRGR.. */ -#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') - /* 14 GBGB.. RGRG.. */ -#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') - /* 14 GRGR.. BGBG.. */ -#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') - /* 14 RGRG.. GBGB.. */ - -enum flash_type { - LED_FLASH = 1, - STROBE_FLASH, - GPIO_FLASH -}; - -enum msm_sensor_resolution_t { - MSM_SENSOR_RES_FULL, - MSM_SENSOR_RES_QTR, - MSM_SENSOR_RES_2, - MSM_SENSOR_RES_3, - MSM_SENSOR_RES_4, - MSM_SENSOR_RES_5, - MSM_SENSOR_RES_6, - MSM_SENSOR_RES_7, - MSM_SENSOR_INVALID_RES, -}; - -enum msm_camera_stream_type_t { - MSM_CAMERA_STREAM_PREVIEW, - MSM_CAMERA_STREAM_SNAPSHOT, - MSM_CAMERA_STREAM_VIDEO, - MSM_CAMERA_STREAM_INVALID, -}; - -enum sensor_sub_module_t { - SUB_MODULE_SENSOR, - SUB_MODULE_CHROMATIX, - SUB_MODULE_ACTUATOR, - SUB_MODULE_EEPROM, - SUB_MODULE_LED_FLASH, - SUB_MODULE_STROBE_FLASH, - SUB_MODULE_CSID, - SUB_MODULE_CSID_3D, - SUB_MODULE_CSIPHY, - SUB_MODULE_CSIPHY_3D, - SUB_MODULE_OIS, - SUB_MODULE_EXT, - SUB_MODULE_IR_LED, - SUB_MODULE_IR_CUT, - SUB_MODULE_LASER_LED, - SUB_MODULE_MAX, -}; - -enum { - MSM_CAMERA_EFFECT_MODE_OFF, - MSM_CAMERA_EFFECT_MODE_MONO, - MSM_CAMERA_EFFECT_MODE_NEGATIVE, - MSM_CAMERA_EFFECT_MODE_SOLARIZE, - MSM_CAMERA_EFFECT_MODE_SEPIA, - MSM_CAMERA_EFFECT_MODE_POSTERIZE, - MSM_CAMERA_EFFECT_MODE_WHITEBOARD, - MSM_CAMERA_EFFECT_MODE_BLACKBOARD, - MSM_CAMERA_EFFECT_MODE_AQUA, - MSM_CAMERA_EFFECT_MODE_EMBOSS, - MSM_CAMERA_EFFECT_MODE_SKETCH, - MSM_CAMERA_EFFECT_MODE_NEON, - MSM_CAMERA_EFFECT_MODE_MAX -}; - -enum { - MSM_CAMERA_WB_MODE_AUTO, - MSM_CAMERA_WB_MODE_CUSTOM, - MSM_CAMERA_WB_MODE_INCANDESCENT, - MSM_CAMERA_WB_MODE_FLUORESCENT, - MSM_CAMERA_WB_MODE_WARM_FLUORESCENT, - MSM_CAMERA_WB_MODE_DAYLIGHT, - MSM_CAMERA_WB_MODE_CLOUDY_DAYLIGHT, - MSM_CAMERA_WB_MODE_TWILIGHT, - MSM_CAMERA_WB_MODE_SHADE, - MSM_CAMERA_WB_MODE_OFF, - MSM_CAMERA_WB_MODE_MAX -}; - -enum { - MSM_CAMERA_SCENE_MODE_OFF, - MSM_CAMERA_SCENE_MODE_AUTO, - MSM_CAMERA_SCENE_MODE_LANDSCAPE, - MSM_CAMERA_SCENE_MODE_SNOW, - MSM_CAMERA_SCENE_MODE_BEACH, - MSM_CAMERA_SCENE_MODE_SUNSET, - MSM_CAMERA_SCENE_MODE_NIGHT, - MSM_CAMERA_SCENE_MODE_PORTRAIT, - MSM_CAMERA_SCENE_MODE_BACKLIGHT, - MSM_CAMERA_SCENE_MODE_SPORTS, - MSM_CAMERA_SCENE_MODE_ANTISHAKE, - MSM_CAMERA_SCENE_MODE_FLOWERS, - MSM_CAMERA_SCENE_MODE_CANDLELIGHT, - MSM_CAMERA_SCENE_MODE_FIREWORKS, - MSM_CAMERA_SCENE_MODE_PARTY, - MSM_CAMERA_SCENE_MODE_NIGHT_PORTRAIT, - MSM_CAMERA_SCENE_MODE_THEATRE, - MSM_CAMERA_SCENE_MODE_ACTION, - MSM_CAMERA_SCENE_MODE_AR, - MSM_CAMERA_SCENE_MODE_FACE_PRIORITY, - MSM_CAMERA_SCENE_MODE_BARCODE, - MSM_CAMERA_SCENE_MODE_HDR, - MSM_CAMERA_SCENE_MODE_MAX -}; - -enum csid_cfg_type_t { - CSID_INIT, - CSID_CFG, - CSID_TESTMODE_CFG, - CSID_RELEASE, -}; - -enum csiphy_cfg_type_t { - CSIPHY_INIT, - CSIPHY_CFG, - CSIPHY_RELEASE, -}; - -enum camera_vreg_type { - VREG_TYPE_DEFAULT, - VREG_TYPE_CUSTOM, -}; - -enum sensor_af_t { - SENSOR_AF_FOCUSSED, - SENSOR_AF_NOT_FOCUSSED, -}; - -enum cci_i2c_master_t { - MASTER_0, - MASTER_1, - MASTER_MAX, -}; - -struct msm_camera_i2c_array_write_config { - struct msm_camera_i2c_reg_setting conf_array; - uint16_t slave_addr; -}; - -struct msm_camera_i2c_read_config { - uint16_t slave_addr; - uint16_t reg_addr; - enum msm_camera_i2c_reg_addr_type addr_type; - enum msm_camera_i2c_data_type data_type; - uint16_t data; -}; - -struct msm_camera_csi2_params { - struct msm_camera_csid_params csid_params; - struct msm_camera_csiphy_params csiphy_params; - uint8_t csi_clk_scale_enable; -}; - -struct msm_camera_csi_lane_params { - uint16_t csi_lane_assign; - uint16_t csi_lane_mask; -}; - -struct csi_lane_params_t { - uint16_t csi_lane_assign; - uint8_t csi_lane_mask; - uint8_t csi_if; - int8_t csid_core[2]; - uint8_t csi_phy_sel; -}; - -struct msm_sensor_info_t { - char sensor_name[MAX_SENSOR_NAME]; - uint32_t session_id; - int32_t subdev_id[SUB_MODULE_MAX]; - int32_t subdev_intf[SUB_MODULE_MAX]; - uint8_t is_mount_angle_valid; - uint32_t sensor_mount_angle; - int modes_supported; - enum camb_position_t position; -}; - -struct camera_vreg_t { - const char *reg_name; - int min_voltage; - int max_voltage; - int op_mode; - uint32_t delay; - const char *custom_vreg_name; - enum camera_vreg_type type; -}; - -struct sensorb_cfg_data { - int cfgtype; - union { - struct msm_sensor_info_t sensor_info; - struct msm_sensor_init_params sensor_init_params; - void *setting; - struct msm_sensor_i2c_sync_params sensor_i2c_sync_params; - } cfg; -}; - -struct csid_cfg_data { - enum csid_cfg_type_t cfgtype; - union { - uint32_t csid_version; - struct msm_camera_csid_params *csid_params; - struct msm_camera_csid_testmode_parms *csid_testmode_params; - } cfg; -}; - -struct csiphy_cfg_data { - enum csiphy_cfg_type_t cfgtype; - union { - struct msm_camera_csiphy_params *csiphy_params; - struct msm_camera_csi_lane_params *csi_lane_params; - } cfg; -}; - -enum eeprom_cfg_type_t { - CFG_EEPROM_GET_INFO, - CFG_EEPROM_GET_CAL_DATA, - CFG_EEPROM_READ_CAL_DATA, - CFG_EEPROM_WRITE_DATA, - CFG_EEPROM_GET_MM_INFO, - CFG_EEPROM_INIT, -}; - -struct eeprom_get_t { - uint32_t num_bytes; -}; - -struct eeprom_read_t { - uint8_t *dbuffer; - uint32_t num_bytes; -}; - -struct eeprom_write_t { - uint8_t *dbuffer; - uint32_t num_bytes; -}; - -struct eeprom_get_cmm_t { - uint32_t cmm_support; - uint32_t cmm_compression; - uint32_t cmm_size; -}; - -struct msm_eeprom_info_t { - struct msm_sensor_power_setting_array *power_setting_array; - enum i2c_freq_mode_t i2c_freq_mode; - struct msm_eeprom_memory_map_array *mem_map_array; -}; - -struct msm_ir_led_cfg_data_t { - enum msm_ir_led_cfg_type_t cfg_type; - int32_t pwm_duty_on_ns; - int32_t pwm_period_ns; -}; - -struct msm_ir_cut_cfg_data_t { - enum msm_ir_cut_cfg_type_t cfg_type; -}; - -struct msm_laser_led_cfg_data_t { - enum msm_laser_led_cfg_type_t cfg_type; - void *setting; - void *debug_reg; - uint32_t debug_reg_size; - uint16_t i2c_addr; - enum i2c_freq_mode_t i2c_freq_mode; -}; - -struct msm_eeprom_cfg_data { - enum eeprom_cfg_type_t cfgtype; - uint8_t is_supported; - union { - char eeprom_name[MAX_EEPROM_NAME]; - struct eeprom_get_t get_data; - struct eeprom_read_t read_data; - struct eeprom_write_t write_data; - struct eeprom_get_cmm_t get_cmm_data; - struct msm_eeprom_info_t eeprom_info; - } cfg; -}; - -enum msm_sensor_cfg_type_t { - CFG_SET_SLAVE_INFO, - CFG_SLAVE_READ_I2C, - CFG_WRITE_I2C_ARRAY, - CFG_SLAVE_WRITE_I2C_ARRAY, - CFG_WRITE_I2C_SEQ_ARRAY, - CFG_POWER_UP, - CFG_POWER_DOWN, - CFG_SET_STOP_STREAM_SETTING, - CFG_GET_SENSOR_INFO, - CFG_GET_SENSOR_INIT_PARAMS, - CFG_SET_INIT_SETTING, - CFG_SET_RESOLUTION, - CFG_SET_STOP_STREAM, - CFG_SET_START_STREAM, - CFG_SET_SATURATION, - CFG_SET_CONTRAST, - CFG_SET_SHARPNESS, - CFG_SET_ISO, - CFG_SET_EXPOSURE_COMPENSATION, - CFG_SET_ANTIBANDING, - CFG_SET_BESTSHOT_MODE, - CFG_SET_EFFECT, - CFG_SET_WHITE_BALANCE, - CFG_SET_AUTOFOCUS, - CFG_CANCEL_AUTOFOCUS, - CFG_SET_STREAM_TYPE, - CFG_SET_I2C_SYNC_PARAM, - CFG_WRITE_I2C_ARRAY_ASYNC, - CFG_WRITE_I2C_ARRAY_SYNC, - CFG_WRITE_I2C_ARRAY_SYNC_BLOCK, -}; - -enum msm_actuator_cfg_type_t { - CFG_GET_ACTUATOR_INFO, - CFG_SET_ACTUATOR_INFO, - CFG_SET_DEFAULT_FOCUS, - CFG_MOVE_FOCUS, - CFG_SET_POSITION, - CFG_ACTUATOR_POWERDOWN, - CFG_ACTUATOR_POWERUP, - CFG_ACTUATOR_INIT, -}; - -struct msm_ois_opcode { - uint32_t prog; - uint32_t coeff; - uint32_t pheripheral; - uint32_t memory; -}; - -enum msm_ois_cfg_type_t { - CFG_OIS_INIT, - CFG_OIS_POWERDOWN, - CFG_OIS_POWERUP, - CFG_OIS_CONTROL, - CFG_OIS_I2C_WRITE_SEQ_TABLE, -}; - -enum msm_ois_cfg_download_type_t { - CFG_OIS_DOWNLOAD, - CFG_OIS_DATA_CONFIG, -}; - -enum msm_ois_i2c_operation { - MSM_OIS_WRITE = 0, - MSM_OIS_POLL, - MSM_OIS_READ, -}; -#define MSM_OIS_READ MSM_OIS_READ - -struct reg_settings_ois_t { - uint16_t reg_addr; - enum msm_camera_i2c_reg_addr_type addr_type; - uint32_t reg_data; - enum msm_camera_i2c_data_type data_type; - enum msm_ois_i2c_operation i2c_operation; - uint32_t delay; -}; - -struct msm_ois_params_t { - uint16_t data_size; - uint16_t setting_size; - uint32_t i2c_addr; - enum i2c_freq_mode_t i2c_freq_mode; - enum msm_camera_i2c_reg_addr_type i2c_addr_type; - enum msm_camera_i2c_data_type i2c_data_type; - struct reg_settings_ois_t *settings; -}; - -struct msm_ois_set_info_t { - struct msm_ois_params_t ois_params; -}; - -struct msm_actuator_move_params_t { - int8_t dir; - int8_t sign_dir; - int16_t dest_step_pos; - int32_t num_steps; - uint16_t curr_lens_pos; - struct damping_params_t *ringing_params; -}; - -struct msm_actuator_tuning_params_t { - int16_t initial_code; - uint16_t pwd_step; - uint16_t region_size; - uint32_t total_steps; - struct region_params_t *region_params; -}; - -struct park_lens_data_t { - uint32_t damping_step; - uint32_t damping_delay; - uint32_t hw_params; - uint32_t max_step; -}; - -struct msm_actuator_params_t { - enum actuator_type act_type; - uint8_t reg_tbl_size; - uint16_t data_size; - uint16_t init_setting_size; - uint32_t i2c_addr; - enum i2c_freq_mode_t i2c_freq_mode; - enum msm_camera_i2c_reg_addr_type i2c_addr_type; - enum msm_camera_i2c_data_type i2c_data_type; - struct msm_actuator_reg_params_t *reg_tbl_params; - struct reg_settings_t *init_settings; - struct park_lens_data_t park_lens; -}; - -struct msm_actuator_set_info_t { - struct msm_actuator_params_t actuator_params; - struct msm_actuator_tuning_params_t af_tuning_params; -}; - -struct msm_actuator_get_info_t { - uint32_t focal_length_num; - uint32_t focal_length_den; - uint32_t f_number_num; - uint32_t f_number_den; - uint32_t f_pix_num; - uint32_t f_pix_den; - uint32_t total_f_dist_num; - uint32_t total_f_dist_den; - uint32_t hor_view_angle_num; - uint32_t hor_view_angle_den; - uint32_t ver_view_angle_num; - uint32_t ver_view_angle_den; -}; - -enum af_camera_name { - ACTUATOR_MAIN_CAM_0, - ACTUATOR_MAIN_CAM_1, - ACTUATOR_MAIN_CAM_2, - ACTUATOR_MAIN_CAM_3, - ACTUATOR_MAIN_CAM_4, - ACTUATOR_MAIN_CAM_5, - ACTUATOR_WEB_CAM_0, - ACTUATOR_WEB_CAM_1, - ACTUATOR_WEB_CAM_2, -}; - -struct msm_ois_slave_info { - char ois_name[MAX_OIS_NAME_SIZE]; - uint32_t i2c_addr; - struct msm_ois_opcode opcode; -}; -struct msm_ois_cfg_data { - int cfgtype; - union { - struct msm_ois_set_info_t set_info; - struct msm_camera_i2c_seq_reg_setting *settings; - } cfg; -}; - -struct msm_ois_cfg_download_data { - int cfgtype; - struct msm_ois_slave_info slave_info; -}; - -struct msm_actuator_set_position_t { - uint16_t number_of_steps; - uint32_t hw_params; - uint16_t pos[MAX_NUMBER_OF_STEPS]; - uint16_t delay[MAX_NUMBER_OF_STEPS]; -}; - -struct msm_actuator_cfg_data { - int cfgtype; - uint8_t is_af_supported; - union { - struct msm_actuator_move_params_t move; - struct msm_actuator_set_info_t set_info; - struct msm_actuator_get_info_t get_info; - struct msm_actuator_set_position_t setpos; - enum af_camera_name cam_name; - } cfg; -}; - -enum msm_camera_led_config_t { - MSM_CAMERA_LED_OFF, - MSM_CAMERA_LED_LOW, - MSM_CAMERA_LED_HIGH, - MSM_CAMERA_LED_INIT, - MSM_CAMERA_LED_RELEASE, -}; - -struct msm_camera_led_cfg_t { - enum msm_camera_led_config_t cfgtype; - int32_t torch_current[MAX_LED_TRIGGERS]; - int32_t flash_current[MAX_LED_TRIGGERS]; - int32_t flash_duration[MAX_LED_TRIGGERS]; -}; - -struct msm_flash_init_info_t { - enum msm_flash_driver_type flash_driver_type; - uint32_t slave_addr; - enum i2c_freq_mode_t i2c_freq_mode; - struct msm_sensor_power_setting_array *power_setting_array; - struct msm_camera_i2c_reg_setting_array *settings; -}; - -struct msm_flash_cfg_data_t { - enum msm_flash_cfg_type_t cfg_type; - int32_t flash_current[MAX_LED_TRIGGERS]; - int32_t flash_duration[MAX_LED_TRIGGERS]; - union { - struct msm_flash_init_info_t *flash_init_info; - struct msm_camera_i2c_reg_setting_array *settings; - } cfg; -}; - -struct msm_flash_query_data_t { - int32_t flags; - int32_t query_type; - int32_t max_avail_curr; -}; - -/* sensor init structures and enums */ -enum msm_sensor_init_cfg_type_t { - CFG_SINIT_PROBE, - CFG_SINIT_PROBE_DONE, - CFG_SINIT_PROBE_WAIT_DONE, -}; - -struct sensor_init_cfg_data { - enum msm_sensor_init_cfg_type_t cfgtype; - struct msm_sensor_info_t probed_info; - char entity_name[MAX_SENSOR_NAME]; - union { - void *setting; - } cfg; -}; - -#define VIDIOC_MSM_SENSOR_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data) - -#define VIDIOC_MSM_SENSOR_RELEASE \ - _IO('V', BASE_VIDIOC_PRIVATE + 2) - -#define VIDIOC_MSM_SENSOR_GET_SUBDEV_ID \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 3, uint32_t) - -#define VIDIOC_MSM_CSIPHY_IO_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data) - -#define VIDIOC_MSM_CSID_IO_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data) - -#define VIDIOC_MSM_ACTUATOR_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data) - -#define VIDIOC_MSM_FLASH_LED_DATA_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_led_cfg_t) - -#define VIDIOC_MSM_EEPROM_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data) - -#define VIDIOC_MSM_SENSOR_GET_AF_STATUS \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 9, uint32_t) - -#define VIDIOC_MSM_SENSOR_INIT_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data) - -#define VIDIOC_MSM_OIS_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data) - -#define VIDIOC_MSM_FLASH_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t) - -#define VIDIOC_MSM_OIS_CFG_DOWNLOAD \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_ois_cfg_download_data) - -#define VIDIOC_MSM_FLASH_QUERY_DATA \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_flash_query_data_t) - -#define VIDIOC_MSM_IR_LED_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_ir_led_cfg_data_t) - -#define VIDIOC_MSM_IR_CUT_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_ir_cut_cfg_data_t) - -#define VIDIOC_MSM_LASER_LED_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_laser_led_cfg_data_t) - -#endif - diff --git a/sdm710/original-kernel-headers/media/msm_camera.h b/sdm710/original-kernel-headers/media/msm_camera.h deleted file mode 100644 index 67255403..00000000 --- a/sdm710/original-kernel-headers/media/msm_camera.h +++ /dev/null @@ -1,2232 +0,0 @@ -/* Copyright (c) 2009-2012, 2014-2016, 2018, The Linux Foundation. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef __UAPI_MSM_CAMERA_H -#define __UAPI_MSM_CAMERA_H - -#define CAM_API_V1 - -#include <linux/videodev2.h> -#include <linux/types.h> -#include <linux/ioctl.h> -#include <linux/media.h> - -#include <linux/msm_ion.h> - -#define BIT(nr) (1UL << (nr)) - -#define MSM_CAM_IOCTL_MAGIC 'm' - -#define MAX_SERVER_PAYLOAD_LENGTH 8192 - -#define MSM_CAM_IOCTL_GET_SENSOR_INFO \ - _IOR(MSM_CAM_IOCTL_MAGIC, 1, struct msm_camsensor_info *) - -#define MSM_CAM_IOCTL_REGISTER_PMEM \ - _IOW(MSM_CAM_IOCTL_MAGIC, 2, struct msm_pmem_info *) - -#define MSM_CAM_IOCTL_UNREGISTER_PMEM \ - _IOW(MSM_CAM_IOCTL_MAGIC, 3, unsigned int) - -#define MSM_CAM_IOCTL_CTRL_COMMAND \ - _IOW(MSM_CAM_IOCTL_MAGIC, 4, struct msm_ctrl_cmd *) - -#define MSM_CAM_IOCTL_CONFIG_VFE \ - _IOW(MSM_CAM_IOCTL_MAGIC, 5, struct msm_camera_vfe_cfg_cmd *) - -#define MSM_CAM_IOCTL_GET_STATS \ - _IOR(MSM_CAM_IOCTL_MAGIC, 6, struct msm_camera_stats_event_ctrl *) - -#define MSM_CAM_IOCTL_GETFRAME \ - _IOR(MSM_CAM_IOCTL_MAGIC, 7, struct msm_camera_get_frame *) - -#define MSM_CAM_IOCTL_ENABLE_VFE \ - _IOW(MSM_CAM_IOCTL_MAGIC, 8, struct camera_enable_cmd *) - -#define MSM_CAM_IOCTL_CTRL_CMD_DONE \ - _IOW(MSM_CAM_IOCTL_MAGIC, 9, struct camera_cmd *) - -#define MSM_CAM_IOCTL_CONFIG_CMD \ - _IOW(MSM_CAM_IOCTL_MAGIC, 10, struct camera_cmd *) - -#define MSM_CAM_IOCTL_DISABLE_VFE \ - _IOW(MSM_CAM_IOCTL_MAGIC, 11, struct camera_enable_cmd *) - -#define MSM_CAM_IOCTL_PAD_REG_RESET2 \ - _IOW(MSM_CAM_IOCTL_MAGIC, 12, struct camera_enable_cmd *) - -#define MSM_CAM_IOCTL_VFE_APPS_RESET \ - _IOW(MSM_CAM_IOCTL_MAGIC, 13, struct camera_enable_cmd *) - -#define MSM_CAM_IOCTL_RELEASE_FRAME_BUFFER \ - _IOW(MSM_CAM_IOCTL_MAGIC, 14, struct camera_enable_cmd *) - -#define MSM_CAM_IOCTL_RELEASE_STATS_BUFFER \ - _IOW(MSM_CAM_IOCTL_MAGIC, 15, struct msm_stats_buf *) - -#define MSM_CAM_IOCTL_AXI_CONFIG \ - _IOW(MSM_CAM_IOCTL_MAGIC, 16, struct msm_camera_vfe_cfg_cmd *) - -#define MSM_CAM_IOCTL_GET_PICTURE \ - _IOW(MSM_CAM_IOCTL_MAGIC, 17, struct msm_frame *) - -#define MSM_CAM_IOCTL_SET_CROP \ - _IOW(MSM_CAM_IOCTL_MAGIC, 18, struct crop_info *) - -#define MSM_CAM_IOCTL_PICT_PP \ - _IOW(MSM_CAM_IOCTL_MAGIC, 19, uint8_t *) - -#define MSM_CAM_IOCTL_PICT_PP_DONE \ - _IOW(MSM_CAM_IOCTL_MAGIC, 20, struct msm_snapshot_pp_status *) - -#define MSM_CAM_IOCTL_SENSOR_IO_CFG \ - _IOW(MSM_CAM_IOCTL_MAGIC, 21, struct sensor_cfg_data *) - -#define MSM_CAM_IOCTL_FLASH_LED_CFG \ - _IOW(MSM_CAM_IOCTL_MAGIC, 22, unsigned int *) - -#define MSM_CAM_IOCTL_UNBLOCK_POLL_FRAME \ - _IO(MSM_CAM_IOCTL_MAGIC, 23) - -#define MSM_CAM_IOCTL_CTRL_COMMAND_2 \ - _IOW(MSM_CAM_IOCTL_MAGIC, 24, struct msm_ctrl_cmd *) - -#define MSM_CAM_IOCTL_AF_CTRL \ - _IOR(MSM_CAM_IOCTL_MAGIC, 25, struct msm_ctrl_cmt_t *) - -#define MSM_CAM_IOCTL_AF_CTRL_DONE \ - _IOW(MSM_CAM_IOCTL_MAGIC, 26, struct msm_ctrl_cmt_t *) - -#define MSM_CAM_IOCTL_CONFIG_VPE \ - _IOW(MSM_CAM_IOCTL_MAGIC, 27, struct msm_camera_vpe_cfg_cmd *) - -#define MSM_CAM_IOCTL_AXI_VPE_CONFIG \ - _IOW(MSM_CAM_IOCTL_MAGIC, 28, struct msm_camera_vpe_cfg_cmd *) - -#define MSM_CAM_IOCTL_STROBE_FLASH_CFG \ - _IOW(MSM_CAM_IOCTL_MAGIC, 29, uint32_t *) - -#define MSM_CAM_IOCTL_STROBE_FLASH_CHARGE \ - _IOW(MSM_CAM_IOCTL_MAGIC, 30, uint32_t *) - -#define MSM_CAM_IOCTL_STROBE_FLASH_RELEASE \ - _IO(MSM_CAM_IOCTL_MAGIC, 31) - -#define MSM_CAM_IOCTL_FLASH_CTRL \ - _IOW(MSM_CAM_IOCTL_MAGIC, 32, struct flash_ctrl_data *) - -#define MSM_CAM_IOCTL_ERROR_CONFIG \ - _IOW(MSM_CAM_IOCTL_MAGIC, 33, uint32_t *) - -#define MSM_CAM_IOCTL_ABORT_CAPTURE \ - _IO(MSM_CAM_IOCTL_MAGIC, 34) - -#define MSM_CAM_IOCTL_SET_FD_ROI \ - _IOW(MSM_CAM_IOCTL_MAGIC, 35, struct fd_roi_info *) - -#define MSM_CAM_IOCTL_GET_CAMERA_INFO \ - _IOR(MSM_CAM_IOCTL_MAGIC, 36, struct msm_camera_info *) - -#define MSM_CAM_IOCTL_UNBLOCK_POLL_PIC_FRAME \ - _IO(MSM_CAM_IOCTL_MAGIC, 37) - -#define MSM_CAM_IOCTL_RELEASE_PIC_BUFFER \ - _IOW(MSM_CAM_IOCTL_MAGIC, 38, struct camera_enable_cmd *) - -#define MSM_CAM_IOCTL_PUT_ST_FRAME \ - _IOW(MSM_CAM_IOCTL_MAGIC, 39, struct msm_camera_st_frame *) - -#define MSM_CAM_IOCTL_V4L2_EVT_NOTIFY \ - _IOW(MSM_CAM_IOCTL_MAGIC, 40, struct v4l2_event_and_payload) - -#define MSM_CAM_IOCTL_SET_MEM_MAP_INFO \ - _IOR(MSM_CAM_IOCTL_MAGIC, 41, struct msm_mem_map_info *) - -#define MSM_CAM_IOCTL_ACTUATOR_IO_CFG \ - _IOW(MSM_CAM_IOCTL_MAGIC, 42, struct msm_actuator_cfg_data *) - -#define MSM_CAM_IOCTL_MCTL_POST_PROC \ - _IOW(MSM_CAM_IOCTL_MAGIC, 43, struct msm_mctl_post_proc_cmd *) - -#define MSM_CAM_IOCTL_RESERVE_FREE_FRAME \ - _IOW(MSM_CAM_IOCTL_MAGIC, 44, struct msm_cam_evt_divert_frame *) - -#define MSM_CAM_IOCTL_RELEASE_FREE_FRAME \ - _IOR(MSM_CAM_IOCTL_MAGIC, 45, struct msm_cam_evt_divert_frame *) - -#define MSM_CAM_IOCTL_PICT_PP_DIVERT_DONE \ - _IOR(MSM_CAM_IOCTL_MAGIC, 46, struct msm_pp_frame *) - -#define MSM_CAM_IOCTL_SENSOR_V4l2_S_CTRL \ - _IOR(MSM_CAM_IOCTL_MAGIC, 47, struct v4l2_control) - -#define MSM_CAM_IOCTL_SENSOR_V4l2_QUERY_CTRL \ - _IOR(MSM_CAM_IOCTL_MAGIC, 48, struct v4l2_queryctrl) - -#define MSM_CAM_IOCTL_GET_KERNEL_SYSTEM_TIME \ - _IOW(MSM_CAM_IOCTL_MAGIC, 49, struct timeval *) - -#define MSM_CAM_IOCTL_SET_VFE_OUTPUT_TYPE \ - _IOW(MSM_CAM_IOCTL_MAGIC, 50, uint32_t *) - -#define MSM_CAM_IOCTL_MCTL_DIVERT_DONE \ - _IOR(MSM_CAM_IOCTL_MAGIC, 51, struct msm_cam_evt_divert_frame *) - -#define MSM_CAM_IOCTL_GET_ACTUATOR_INFO \ - _IOW(MSM_CAM_IOCTL_MAGIC, 52, struct msm_actuator_cfg_data *) - -#define MSM_CAM_IOCTL_EEPROM_IO_CFG \ - _IOW(MSM_CAM_IOCTL_MAGIC, 53, struct msm_eeprom_cfg_data *) - -#define MSM_CAM_IOCTL_ISPIF_IO_CFG \ - _IOR(MSM_CAM_IOCTL_MAGIC, 54, struct ispif_cfg_data *) - -#define MSM_CAM_IOCTL_STATS_REQBUF \ - _IOR(MSM_CAM_IOCTL_MAGIC, 55, struct msm_stats_reqbuf *) - -#define MSM_CAM_IOCTL_STATS_ENQUEUEBUF \ - _IOR(MSM_CAM_IOCTL_MAGIC, 56, struct msm_stats_buf_info *) - -#define MSM_CAM_IOCTL_STATS_FLUSH_BUFQ \ - _IOR(MSM_CAM_IOCTL_MAGIC, 57, struct msm_stats_flush_bufq *) - -#define MSM_CAM_IOCTL_SET_MCTL_SDEV \ - _IOW(MSM_CAM_IOCTL_MAGIC, 58, struct msm_mctl_set_sdev_data *) - -#define MSM_CAM_IOCTL_UNSET_MCTL_SDEV \ - _IOW(MSM_CAM_IOCTL_MAGIC, 59, struct msm_mctl_set_sdev_data *) - -#define MSM_CAM_IOCTL_GET_INST_HANDLE \ - _IOR(MSM_CAM_IOCTL_MAGIC, 60, uint32_t *) - -#define MSM_CAM_IOCTL_STATS_UNREG_BUF \ - _IOR(MSM_CAM_IOCTL_MAGIC, 61, struct msm_stats_flush_bufq *) - -#define MSM_CAM_IOCTL_CSIC_IO_CFG \ - _IOWR(MSM_CAM_IOCTL_MAGIC, 62, struct csic_cfg_data *) - -#define MSM_CAM_IOCTL_CSID_IO_CFG \ - _IOWR(MSM_CAM_IOCTL_MAGIC, 63, struct csid_cfg_data *) - -#define MSM_CAM_IOCTL_CSIPHY_IO_CFG \ - _IOR(MSM_CAM_IOCTL_MAGIC, 64, struct csiphy_cfg_data *) - -#define MSM_CAM_IOCTL_OEM \ - _IOW(MSM_CAM_IOCTL_MAGIC, 65, struct sensor_cfg_data *) - -#define MSM_CAM_IOCTL_AXI_INIT \ - _IOWR(MSM_CAM_IOCTL_MAGIC, 66, uint8_t *) - -#define MSM_CAM_IOCTL_AXI_RELEASE \ - _IO(MSM_CAM_IOCTL_MAGIC, 67) - -struct v4l2_event_and_payload { - struct v4l2_event evt; - uint32_t payload_length; - uint32_t transaction_id; - void *payload; -}; - -struct msm_stats_reqbuf { - int num_buf; /* how many buffers requested */ - int stats_type; /* stats type */ -}; - -struct msm_stats_flush_bufq { - int stats_type; /* enum msm_stats_enum_type */ -}; - -struct msm_mctl_pp_cmd { - int32_t id; - uint16_t length; - void *value; -}; - -struct msm_mctl_post_proc_cmd { - int32_t type; - struct msm_mctl_pp_cmd cmd; -}; - -#define MSM_CAMERA_LED_OFF 0 -#define MSM_CAMERA_LED_LOW 1 -#define MSM_CAMERA_LED_HIGH 2 -#define MSM_CAMERA_LED_INIT 3 -#define MSM_CAMERA_LED_RELEASE 4 - -#define MSM_CAMERA_STROBE_FLASH_NONE 0 -#define MSM_CAMERA_STROBE_FLASH_XENON 1 - -#define MSM_MAX_CAMERA_SENSORS 5 -#define MAX_SENSOR_NAME 32 -#define MAX_CAM_NAME_SIZE 32 -#define MAX_ACT_MOD_NAME_SIZE 32 -#define MAX_ACT_NAME_SIZE 32 -#define NUM_ACTUATOR_DIR 2 -#define MAX_ACTUATOR_SCENARIO 8 -#define MAX_ACTUATOR_REGION 5 -#define MAX_ACTUATOR_INIT_SET 12 -#define MAX_ACTUATOR_TYPE_SIZE 32 -#define MAX_ACTUATOR_REG_TBL_SIZE 8 - - -#define MSM_MAX_CAMERA_CONFIGS 2 - -#define PP_SNAP 0x01 -#define PP_RAW_SNAP ((0x01)<<1) -#define PP_PREV ((0x01)<<2) -#define PP_THUMB ((0x01)<<3) -#define PP_MASK (PP_SNAP|PP_RAW_SNAP|PP_PREV|PP_THUMB) - -#define MSM_CAM_CTRL_CMD_DONE 0 -#define MSM_CAM_SENSOR_VFE_CMD 1 - -/* Should be same as VIDEO_MAX_PLANES in videodev2.h */ -#define MAX_PLANES 8 - -/***************************************************** - * structure - *****************************************************/ - -/* define five type of structures for userspace <==> kernel - * space communication: - * command 1 - 2 are from userspace ==> kernel - * command 3 - 4 are from kernel ==> userspace - * - * 1. control command: control command(from control thread), - * control status (from config thread); - */ -struct msm_ctrl_cmd { - uint16_t type; - uint16_t length; - void *value; - uint16_t status; - uint32_t timeout_ms; - int resp_fd; /* FIXME: to be used by the kernel, pass-through for now */ - int vnode_id; /* video dev id. Can we overload resp_fd? */ - int queue_idx; - uint32_t evt_id; - uint32_t stream_type; /* used to pass value to qcamera server */ - int config_ident; /*used as identifier for config node*/ -}; - -struct msm_cam_evt_msg { - unsigned short type; /* 1 == event (RPC), 0 == message (adsp) */ - unsigned short msg_id; - unsigned int len; /* size in, number of bytes out */ - uint32_t frame_id; - void *data; - struct timespec timestamp; -}; - -struct msm_pp_frame_sp { - /* phy addr of the buffer */ - unsigned long phy_addr; - uint32_t y_off; - uint32_t cbcr_off; - /* buffer length */ - uint32_t length; - int32_t fd; - uint32_t addr_offset; - /* mapped addr */ - unsigned long vaddr; -}; - -struct msm_pp_frame_mp { - /* phy addr of the plane */ - unsigned long phy_addr; - /* offset of plane data */ - uint32_t data_offset; - /* plane length */ - uint32_t length; - int32_t fd; - uint32_t addr_offset; - /* mapped addr */ - unsigned long vaddr; -}; - -struct msm_pp_frame { - uint32_t handle; /* stores vb cookie */ - uint32_t frame_id; - unsigned short buf_idx; - int path; - unsigned short image_type; - unsigned short num_planes; /* 1 for sp */ - struct timeval timestamp; - union { - struct msm_pp_frame_sp sp; - struct msm_pp_frame_mp mp[MAX_PLANES]; - }; - int node_type; - uint32_t inst_handle; -}; - -struct msm_pp_crop { - uint32_t src_x; - uint32_t src_y; - uint32_t src_w; - uint32_t src_h; - uint32_t dst_x; - uint32_t dst_y; - uint32_t dst_w; - uint32_t dst_h; - uint8_t update_flag; -}; - -struct msm_mctl_pp_frame_cmd { - uint32_t cookie; - uint8_t vpe_output_action; - struct msm_pp_frame src_frame; - struct msm_pp_frame dest_frame; - struct msm_pp_crop crop; - int path; -}; - -struct msm_cam_evt_divert_frame { - unsigned short image_mode; - unsigned short op_mode; - unsigned short inst_idx; - unsigned short node_idx; - struct msm_pp_frame frame; - int do_pp; -}; - -struct msm_mctl_pp_cmd_ack_event { - uint32_t cmd; /* VPE_CMD_ZOOM? */ - int status; /* 0 done, < 0 err */ - uint32_t cookie; /* daemon's cookie */ -}; - -struct msm_mctl_pp_event_info { - int32_t event; - union { - struct msm_mctl_pp_cmd_ack_event ack; - }; -}; - -struct msm_isp_event_ctrl { - unsigned short resptype; - union { - struct msm_cam_evt_msg isp_msg; - struct msm_ctrl_cmd ctrl; - struct msm_cam_evt_divert_frame div_frame; - struct msm_mctl_pp_event_info pp_event_info; - } isp_data; -}; - -#define MSM_CAM_RESP_CTRL 0 -#define MSM_CAM_RESP_STAT_EVT_MSG 1 -#define MSM_CAM_RESP_STEREO_OP_1 2 -#define MSM_CAM_RESP_STEREO_OP_2 3 -#define MSM_CAM_RESP_V4L2 4 -#define MSM_CAM_RESP_DIV_FRAME_EVT_MSG 5 -#define MSM_CAM_RESP_DONE_EVENT 6 -#define MSM_CAM_RESP_MCTL_PP_EVENT 7 -#define MSM_CAM_RESP_MAX 8 - -#define MSM_CAM_APP_NOTIFY_EVENT 0 -#define MSM_CAM_APP_NOTIFY_ERROR_EVENT 1 - -/* this one is used to send ctrl/status up to config thread */ - -struct msm_stats_event_ctrl { - /* 0 - ctrl_cmd from control thread, - * 1 - stats/event kernel, - * 2 - V4L control or read request - */ - int resptype; - int timeout_ms; - struct msm_ctrl_cmd ctrl_cmd; - /* struct vfe_event_t stats_event; */ - struct msm_cam_evt_msg stats_event; -}; - -/* 2. config command: config command(from config thread); */ -struct msm_camera_cfg_cmd { - /* what to config: - * 1 - sensor config, 2 - vfe config - */ - uint16_t cfg_type; - - /* sensor config type */ - uint16_t cmd_type; - uint16_t queue; - uint16_t length; - void *value; -}; - -#define CMD_GENERAL 0 -#define CMD_AXI_CFG_OUT1 1 -#define CMD_AXI_CFG_SNAP_O1_AND_O2 2 -#define CMD_AXI_CFG_OUT2 3 -#define CMD_PICT_T_AXI_CFG 4 -#define CMD_PICT_M_AXI_CFG 5 -#define CMD_RAW_PICT_AXI_CFG 6 - -#define CMD_FRAME_BUF_RELEASE 7 -#define CMD_PREV_BUF_CFG 8 -#define CMD_SNAP_BUF_RELEASE 9 -#define CMD_SNAP_BUF_CFG 10 -#define CMD_STATS_DISABLE 11 -#define CMD_STATS_AEC_AWB_ENABLE 12 -#define CMD_STATS_AF_ENABLE 13 -#define CMD_STATS_AEC_ENABLE 14 -#define CMD_STATS_AWB_ENABLE 15 -#define CMD_STATS_ENABLE 16 - -#define CMD_STATS_AXI_CFG 17 -#define CMD_STATS_AEC_AXI_CFG 18 -#define CMD_STATS_AF_AXI_CFG 19 -#define CMD_STATS_AWB_AXI_CFG 20 -#define CMD_STATS_RS_AXI_CFG 21 -#define CMD_STATS_CS_AXI_CFG 22 -#define CMD_STATS_IHIST_AXI_CFG 23 -#define CMD_STATS_SKIN_AXI_CFG 24 - -#define CMD_STATS_BUF_RELEASE 25 -#define CMD_STATS_AEC_BUF_RELEASE 26 -#define CMD_STATS_AF_BUF_RELEASE 27 -#define CMD_STATS_AWB_BUF_RELEASE 28 -#define CMD_STATS_RS_BUF_RELEASE 29 -#define CMD_STATS_CS_BUF_RELEASE 30 -#define CMD_STATS_IHIST_BUF_RELEASE 31 -#define CMD_STATS_SKIN_BUF_RELEASE 32 - -#define UPDATE_STATS_INVALID 33 -#define CMD_AXI_CFG_SNAP_GEMINI 34 -#define CMD_AXI_CFG_SNAP 35 -#define CMD_AXI_CFG_PREVIEW 36 -#define CMD_AXI_CFG_VIDEO 37 - -#define CMD_STATS_IHIST_ENABLE 38 -#define CMD_STATS_RS_ENABLE 39 -#define CMD_STATS_CS_ENABLE 40 -#define CMD_VPE 41 -#define CMD_AXI_CFG_VPE 42 -#define CMD_AXI_CFG_ZSL 43 -#define CMD_AXI_CFG_SNAP_VPE 44 -#define CMD_AXI_CFG_SNAP_THUMB_VPE 45 - -#define CMD_CONFIG_PING_ADDR 46 -#define CMD_CONFIG_PONG_ADDR 47 -#define CMD_CONFIG_FREE_BUF_ADDR 48 -#define CMD_AXI_CFG_ZSL_ALL_CHNLS 49 -#define CMD_AXI_CFG_VIDEO_ALL_CHNLS 50 -#define CMD_VFE_BUFFER_RELEASE 51 -#define CMD_VFE_PROCESS_IRQ 52 -#define CMD_STATS_BG_ENABLE 53 -#define CMD_STATS_BF_ENABLE 54 -#define CMD_STATS_BHIST_ENABLE 55 -#define CMD_STATS_BG_BUF_RELEASE 56 -#define CMD_STATS_BF_BUF_RELEASE 57 -#define CMD_STATS_BHIST_BUF_RELEASE 58 -#define CMD_VFE_PIX_SOF_COUNT_UPDATE 59 -#define CMD_VFE_COUNT_PIX_SOF_ENABLE 60 -#define CMD_STATS_BE_ENABLE 61 -#define CMD_STATS_BE_BUF_RELEASE 62 - -#define CMD_AXI_CFG_PRIM BIT(8) -#define CMD_AXI_CFG_PRIM_ALL_CHNLS BIT(9) -#define CMD_AXI_CFG_SEC BIT(10) -#define CMD_AXI_CFG_SEC_ALL_CHNLS BIT(11) -#define CMD_AXI_CFG_TERT1 BIT(12) -#define CMD_AXI_CFG_TERT2 BIT(13) - -#define CMD_AXI_START 0xE1 -#define CMD_AXI_STOP 0xE2 -#define CMD_AXI_RESET 0xE3 -#define CMD_AXI_ABORT 0xE4 - - - -#define AXI_CMD_PREVIEW BIT(0) -#define AXI_CMD_CAPTURE BIT(1) -#define AXI_CMD_RECORD BIT(2) -#define AXI_CMD_ZSL BIT(3) -#define AXI_CMD_RAW_CAPTURE BIT(4) -#define AXI_CMD_LIVESHOT BIT(5) - -/* vfe config command: config command(from config thread)*/ -struct msm_vfe_cfg_cmd { - int cmd_type; - uint16_t length; - void *value; -}; - -struct msm_vpe_cfg_cmd { - int cmd_type; - uint16_t length; - void *value; -}; - -#define MAX_CAMERA_ENABLE_NAME_LEN 32 -struct camera_enable_cmd { - char name[MAX_CAMERA_ENABLE_NAME_LEN]; -}; - -#define MSM_PMEM_OUTPUT1 0 -#define MSM_PMEM_OUTPUT2 1 -#define MSM_PMEM_OUTPUT1_OUTPUT2 2 -#define MSM_PMEM_THUMBNAIL 3 -#define MSM_PMEM_MAINIMG 4 -#define MSM_PMEM_RAW_MAINIMG 5 -#define MSM_PMEM_AEC_AWB 6 -#define MSM_PMEM_AF 7 -#define MSM_PMEM_AEC 8 -#define MSM_PMEM_AWB 9 -#define MSM_PMEM_RS 10 -#define MSM_PMEM_CS 11 -#define MSM_PMEM_IHIST 12 -#define MSM_PMEM_SKIN 13 -#define MSM_PMEM_VIDEO 14 -#define MSM_PMEM_PREVIEW 15 -#define MSM_PMEM_VIDEO_VPE 16 -#define MSM_PMEM_C2D 17 -#define MSM_PMEM_MAINIMG_VPE 18 -#define MSM_PMEM_THUMBNAIL_VPE 19 -#define MSM_PMEM_BAYER_GRID 20 -#define MSM_PMEM_BAYER_FOCUS 21 -#define MSM_PMEM_BAYER_HIST 22 -#define MSM_PMEM_BAYER_EXPOSURE 23 -#define MSM_PMEM_MAX 24 - -#define STAT_AEAW 0 -#define STAT_AEC 1 -#define STAT_AF 2 -#define STAT_AWB 3 -#define STAT_RS 4 -#define STAT_CS 5 -#define STAT_IHIST 6 -#define STAT_SKIN 7 -#define STAT_BG 8 -#define STAT_BF 9 -#define STAT_BE 10 -#define STAT_BHIST 11 -#define STAT_MAX 12 - -#define FRAME_PREVIEW_OUTPUT1 0 -#define FRAME_PREVIEW_OUTPUT2 1 -#define FRAME_SNAPSHOT 2 -#define FRAME_THUMBNAIL 3 -#define FRAME_RAW_SNAPSHOT 4 -#define FRAME_MAX 5 - -enum msm_stats_enum_type { - MSM_STATS_TYPE_AEC, /* legacy based AEC */ - MSM_STATS_TYPE_AF, /* legacy based AF */ - MSM_STATS_TYPE_AWB, /* legacy based AWB */ - MSM_STATS_TYPE_RS, /* legacy based RS */ - MSM_STATS_TYPE_CS, /* legacy based CS */ - MSM_STATS_TYPE_IHIST, /* legacy based HIST */ - MSM_STATS_TYPE_SKIN, /* legacy based SKIN */ - MSM_STATS_TYPE_BG, /* Bayer Grids */ - MSM_STATS_TYPE_BF, /* Bayer Focus */ - MSM_STATS_TYPE_BE, /* Bayer Exposure*/ - MSM_STATS_TYPE_BHIST, /* Bayer Hist */ - MSM_STATS_TYPE_AE_AW, /* legacy stats for vfe 2.x*/ - MSM_STATS_TYPE_COMP, /* Composite stats */ - MSM_STATS_TYPE_MAX /* MAX */ -}; - -struct msm_stats_buf_info { - int type; /* msm_stats_enum_type */ - int fd; - void *vaddr; - uint32_t offset; - uint32_t len; - uint32_t y_off; - uint32_t cbcr_off; - uint32_t planar0_off; - uint32_t planar1_off; - uint32_t planar2_off; - uint8_t active; - int buf_idx; -}; - -struct msm_pmem_info { - int type; - int fd; - void *vaddr; - uint32_t offset; - uint32_t len; - uint32_t y_off; - uint32_t cbcr_off; - uint32_t planar0_off; - uint32_t planar1_off; - uint32_t planar2_off; - uint8_t active; -}; - -struct outputCfg { - uint32_t height; - uint32_t width; - - uint32_t window_height_firstline; - uint32_t window_height_lastline; -}; - -#define VIDEO_NODE 0 -#define MCTL_NODE 1 - -#define OUTPUT_1 0 -#define OUTPUT_2 1 -#define OUTPUT_1_AND_2 2 /* snapshot only */ -#define OUTPUT_1_AND_3 3 /* video */ -#define CAMIF_TO_AXI_VIA_OUTPUT_2 4 -#define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 5 -#define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 6 -#define OUTPUT_1_2_AND_3 7 -#define OUTPUT_ALL_CHNLS 8 -#define OUTPUT_VIDEO_ALL_CHNLS 9 -#define OUTPUT_ZSL_ALL_CHNLS 10 -#define LAST_AXI_OUTPUT_MODE_ENUM OUTPUT_ZSL_ALL_CHNLS - -#define OUTPUT_PRIM BIT(8) -#define OUTPUT_PRIM_ALL_CHNLS BIT(9) -#define OUTPUT_SEC BIT(10) -#define OUTPUT_SEC_ALL_CHNLS BIT(11) -#define OUTPUT_TERT1 BIT(12) -#define OUTPUT_TERT2 BIT(13) - - - -#define MSM_FRAME_PREV_1 0 -#define MSM_FRAME_PREV_2 1 -#define MSM_FRAME_ENC 2 - -#define OUTPUT_TYPE_P BIT(0) -#define OUTPUT_TYPE_T BIT(1) -#define OUTPUT_TYPE_S BIT(2) -#define OUTPUT_TYPE_V BIT(3) -#define OUTPUT_TYPE_L BIT(4) -#define OUTPUT_TYPE_ST_L BIT(5) -#define OUTPUT_TYPE_ST_R BIT(6) -#define OUTPUT_TYPE_ST_D BIT(7) -#define OUTPUT_TYPE_R BIT(8) -#define OUTPUT_TYPE_R1 BIT(9) -#define OUTPUT_TYPE_SAEC BIT(10) -#define OUTPUT_TYPE_SAFC BIT(11) -#define OUTPUT_TYPE_SAWB BIT(12) -#define OUTPUT_TYPE_IHST BIT(13) -#define OUTPUT_TYPE_CSTA BIT(14) - -struct fd_roi_info { - void *info; - int info_len; -}; - -struct msm_mem_map_info { - uint32_t cookie; - uint32_t length; - uint32_t mem_type; -}; - -#define MSM_MEM_MMAP 0 -#define MSM_MEM_USERPTR 1 -#define MSM_PLANE_MAX 8 -#define MSM_PLANE_Y 0 -#define MSM_PLANE_UV 1 - -struct msm_frame { - struct timespec ts; - int path; - int type; - unsigned long buffer; - uint32_t phy_offset; - uint32_t y_off; - uint32_t cbcr_off; - uint32_t planar0_off; - uint32_t planar1_off; - uint32_t planar2_off; - int fd; - - void *cropinfo; - int croplen; - uint32_t error_code; - struct fd_roi_info roi_info; - uint32_t frame_id; - int stcam_quality_ind; - uint32_t stcam_conv_value; - - struct ion_allocation_data ion_alloc; - struct ion_fd_data fd_data; - int ion_dev_fd; -}; - -enum msm_st_frame_packing { - SIDE_BY_SIDE_HALF, - SIDE_BY_SIDE_FULL, - TOP_DOWN_HALF, - TOP_DOWN_FULL, -}; - -struct msm_st_crop { - uint32_t in_w; - uint32_t in_h; - uint32_t out_w; - uint32_t out_h; -}; - -struct msm_st_half { - uint32_t buf_p0_off; - uint32_t buf_p1_off; - uint32_t buf_p0_stride; - uint32_t buf_p1_stride; - uint32_t pix_x_off; - uint32_t pix_y_off; - struct msm_st_crop stCropInfo; -}; - -struct msm_st_frame { - struct msm_frame buf_info; - int type; - enum msm_st_frame_packing packing; - struct msm_st_half L; - struct msm_st_half R; - int frame_id; -}; - -#define MSM_CAMERA_ERR_MASK (0xFFFFFFFF & 1) - -struct stats_buff { - unsigned long buff; - int fd; -}; - -struct msm_stats_buf { - uint8_t awb_ymin; - struct stats_buff aec; - struct stats_buff awb; - struct stats_buff af; - struct stats_buff be; - struct stats_buff ihist; - struct stats_buff rs; - struct stats_buff cs; - struct stats_buff skin; - int type; - uint32_t status_bits; - unsigned long buffer; - int fd; - int length; - struct ion_handle *handle; - uint32_t frame_id; - int buf_idx; -}; -#define MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT 0 -/* video capture mode in VIDIOC_S_PARM */ -#define MSM_V4L2_EXT_CAPTURE_MODE_PREVIEW \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+1) -/* extendedmode for video recording in VIDIOC_S_PARM */ -#define MSM_V4L2_EXT_CAPTURE_MODE_VIDEO \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+2) -/* extendedmode for the full size main image in VIDIOC_S_PARM */ -#define MSM_V4L2_EXT_CAPTURE_MODE_MAIN (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+3) -/* extendedmode for the thumb nail image in VIDIOC_S_PARM */ -#define MSM_V4L2_EXT_CAPTURE_MODE_THUMBNAIL \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+4) -/* ISP_PIX_OUTPUT1: no pp, directly send output1 buf to user */ -#define MSM_V4L2_EXT_CAPTURE_MODE_ISP_PIX_OUTPUT1 \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+5) -/* ISP_PIX_OUTPUT2: no pp, directly send output2 buf to user */ -#define MSM_V4L2_EXT_CAPTURE_MODE_ISP_PIX_OUTPUT2 \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+6) -/* raw image type */ -#define MSM_V4L2_EXT_CAPTURE_MODE_RAW \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+7) -/* RDI dump */ -#define MSM_V4L2_EXT_CAPTURE_MODE_RDI \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+8) -/* RDI dump 1 */ -#define MSM_V4L2_EXT_CAPTURE_MODE_RDI1 \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+9) -/* RDI dump 2 */ -#define MSM_V4L2_EXT_CAPTURE_MODE_RDI2 \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+10) -#define MSM_V4L2_EXT_CAPTURE_MODE_AEC \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+11) -#define MSM_V4L2_EXT_CAPTURE_MODE_AWB \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+12) -#define MSM_V4L2_EXT_CAPTURE_MODE_AF \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+13) -#define MSM_V4L2_EXT_CAPTURE_MODE_IHIST \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+14) -#define MSM_V4L2_EXT_CAPTURE_MODE_CS \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+15) -#define MSM_V4L2_EXT_CAPTURE_MODE_RS \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+16) -#define MSM_V4L2_EXT_CAPTURE_MODE_CSTA \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+17) -#define MSM_V4L2_EXT_CAPTURE_MODE_V2X_LIVESHOT \ - (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+18) -#define MSM_V4L2_EXT_CAPTURE_MODE_MAX (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+19) - - -#define MSM_V4L2_PID_MOTION_ISO V4L2_CID_PRIVATE_BASE -#define MSM_V4L2_PID_EFFECT (V4L2_CID_PRIVATE_BASE+1) -#define MSM_V4L2_PID_HJR (V4L2_CID_PRIVATE_BASE+2) -#define MSM_V4L2_PID_LED_MODE (V4L2_CID_PRIVATE_BASE+3) -#define MSM_V4L2_PID_PREP_SNAPSHOT (V4L2_CID_PRIVATE_BASE+4) -#define MSM_V4L2_PID_EXP_METERING (V4L2_CID_PRIVATE_BASE+5) -#define MSM_V4L2_PID_ISO (V4L2_CID_PRIVATE_BASE+6) -#define MSM_V4L2_PID_CAM_MODE (V4L2_CID_PRIVATE_BASE+7) -#define MSM_V4L2_PID_LUMA_ADAPTATION (V4L2_CID_PRIVATE_BASE+8) -#define MSM_V4L2_PID_BEST_SHOT (V4L2_CID_PRIVATE_BASE+9) -#define MSM_V4L2_PID_FOCUS_MODE (V4L2_CID_PRIVATE_BASE+10) -#define MSM_V4L2_PID_BL_DETECTION (V4L2_CID_PRIVATE_BASE+11) -#define MSM_V4L2_PID_SNOW_DETECTION (V4L2_CID_PRIVATE_BASE+12) -#define MSM_V4L2_PID_CTRL_CMD (V4L2_CID_PRIVATE_BASE+13) -#define MSM_V4L2_PID_EVT_SUB_INFO (V4L2_CID_PRIVATE_BASE+14) -#define MSM_V4L2_PID_STROBE_FLASH (V4L2_CID_PRIVATE_BASE+15) -#define MSM_V4L2_PID_INST_HANDLE (V4L2_CID_PRIVATE_BASE+16) -#define MSM_V4L2_PID_MMAP_INST (V4L2_CID_PRIVATE_BASE+17) -#define MSM_V4L2_PID_PP_PLANE_INFO (V4L2_CID_PRIVATE_BASE+18) -#define MSM_V4L2_PID_MAX MSM_V4L2_PID_PP_PLANE_INFO - -/* camera operation mode for video recording - two frame output queues */ -#define MSM_V4L2_CAM_OP_DEFAULT 0 -/* camera operation mode for video recording - two frame output queues */ -#define MSM_V4L2_CAM_OP_PREVIEW (MSM_V4L2_CAM_OP_DEFAULT+1) -/* camera operation mode for video recording - two frame output queues */ -#define MSM_V4L2_CAM_OP_VIDEO (MSM_V4L2_CAM_OP_DEFAULT+2) -/* camera operation mode for standard shapshot - two frame output queues */ -#define MSM_V4L2_CAM_OP_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+3) -/* camera operation mode for zsl shapshot - three output queues */ -#define MSM_V4L2_CAM_OP_ZSL (MSM_V4L2_CAM_OP_DEFAULT+4) -/* camera operation mode for raw snapshot - one frame output queue */ -#define MSM_V4L2_CAM_OP_RAW (MSM_V4L2_CAM_OP_DEFAULT+5) -/* camera operation mode for jpeg snapshot - one frame output queue */ -#define MSM_V4L2_CAM_OP_JPEG_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+6) - - -#define MSM_V4L2_VID_CAP_TYPE 0 -#define MSM_V4L2_STREAM_ON 1 -#define MSM_V4L2_STREAM_OFF 2 -#define MSM_V4L2_SNAPSHOT 3 -#define MSM_V4L2_QUERY_CTRL 4 -#define MSM_V4L2_GET_CTRL 5 -#define MSM_V4L2_SET_CTRL 6 -#define MSM_V4L2_QUERY 7 -#define MSM_V4L2_GET_CROP 8 -#define MSM_V4L2_SET_CROP 9 -#define MSM_V4L2_OPEN 10 -#define MSM_V4L2_CLOSE 11 -#define MSM_V4L2_SET_CTRL_CMD 12 -#define MSM_V4L2_EVT_SUB_MASK 13 -#define MSM_V4L2_PRIVATE_CMD 14 -#define MSM_V4L2_MAX 15 -#define V4L2_CAMERA_EXIT 43 - -struct crop_info { - void *info; - int len; -}; - -struct msm_postproc { - int ftnum; - struct msm_frame fthumnail; - int fmnum; - struct msm_frame fmain; -}; - -struct msm_snapshot_pp_status { - void *status; -}; - -#define CFG_SET_MODE 0 -#define CFG_SET_EFFECT 1 -#define CFG_START 2 -#define CFG_PWR_UP 3 -#define CFG_PWR_DOWN 4 -#define CFG_WRITE_EXPOSURE_GAIN 5 -#define CFG_SET_DEFAULT_FOCUS 6 -#define CFG_MOVE_FOCUS 7 -#define CFG_REGISTER_TO_REAL_GAIN 8 -#define CFG_REAL_TO_REGISTER_GAIN 9 -#define CFG_SET_FPS 10 -#define CFG_SET_PICT_FPS 11 -#define CFG_SET_BRIGHTNESS 12 -#define CFG_SET_CONTRAST 13 -#define CFG_SET_ZOOM 14 -#define CFG_SET_EXPOSURE_MODE 15 -#define CFG_SET_WB 16 -#define CFG_SET_ANTIBANDING 17 -#define CFG_SET_EXP_GAIN 18 -#define CFG_SET_PICT_EXP_GAIN 19 -#define CFG_SET_LENS_SHADING 20 -#define CFG_GET_PICT_FPS 21 -#define CFG_GET_PREV_L_PF 22 -#define CFG_GET_PREV_P_PL 23 -#define CFG_GET_PICT_L_PF 24 -#define CFG_GET_PICT_P_PL 25 -#define CFG_GET_AF_MAX_STEPS 26 -#define CFG_GET_PICT_MAX_EXP_LC 27 -#define CFG_SEND_WB_INFO 28 -#define CFG_SENSOR_INIT 29 -#define CFG_GET_3D_CALI_DATA 30 -#define CFG_GET_CALIB_DATA 31 -#define CFG_GET_OUTPUT_INFO 32 -#define CFG_GET_EEPROM_INFO 33 -#define CFG_GET_EEPROM_DATA 34 -#define CFG_SET_ACTUATOR_INFO 35 -#define CFG_GET_ACTUATOR_INFO 36 -/* TBD: QRD */ -#define CFG_SET_SATURATION 37 -#define CFG_SET_SHARPNESS 38 -#define CFG_SET_TOUCHAEC 39 -#define CFG_SET_AUTO_FOCUS 40 -#define CFG_SET_AUTOFLASH 41 -#define CFG_SET_EXPOSURE_COMPENSATION 42 -#define CFG_SET_ISO 43 -#define CFG_START_STREAM 44 -#define CFG_STOP_STREAM 45 -#define CFG_GET_CSI_PARAMS 46 -#define CFG_POWER_UP 47 -#define CFG_POWER_DOWN 48 -#define CFG_WRITE_I2C_ARRAY 49 -#define CFG_READ_I2C_ARRAY 50 -#define CFG_PCLK_CHANGE 51 -#define CFG_CONFIG_VREG_ARRAY 52 -#define CFG_CONFIG_CLK_ARRAY 53 -#define CFG_GPIO_OP 54 -#define CFG_MAX 55 - - -#define MOVE_NEAR 0 -#define MOVE_FAR 1 - -#define SENSOR_PREVIEW_MODE 0 -#define SENSOR_SNAPSHOT_MODE 1 -#define SENSOR_RAW_SNAPSHOT_MODE 2 -#define SENSOR_HFR_60FPS_MODE 3 -#define SENSOR_HFR_90FPS_MODE 4 -#define SENSOR_HFR_120FPS_MODE 5 - -#define SENSOR_QTR_SIZE 0 -#define SENSOR_FULL_SIZE 1 -#define SENSOR_QVGA_SIZE 2 -#define SENSOR_INVALID_SIZE 3 - -#define CAMERA_EFFECT_OFF 0 -#define CAMERA_EFFECT_MONO 1 -#define CAMERA_EFFECT_NEGATIVE 2 -#define CAMERA_EFFECT_SOLARIZE 3 -#define CAMERA_EFFECT_SEPIA 4 -#define CAMERA_EFFECT_POSTERIZE 5 -#define CAMERA_EFFECT_WHITEBOARD 6 -#define CAMERA_EFFECT_BLACKBOARD 7 -#define CAMERA_EFFECT_AQUA 8 -#define CAMERA_EFFECT_EMBOSS 9 -#define CAMERA_EFFECT_SKETCH 10 -#define CAMERA_EFFECT_NEON 11 -#define CAMERA_EFFECT_FADED 12 -#define CAMERA_EFFECT_VINTAGECOOL 13 -#define CAMERA_EFFECT_VINTAGEWARM 14 -#define CAMERA_EFFECT_ACCENT_BLUE 15 -#define CAMERA_EFFECT_ACCENT_GREEN 16 -#define CAMERA_EFFECT_ACCENT_ORANGE 17 -#define CAMERA_EFFECT_MAX 18 - -/* QRD */ -#define CAMERA_EFFECT_BW 10 -#define CAMERA_EFFECT_BLUISH 12 -#define CAMERA_EFFECT_REDDISH 13 -#define CAMERA_EFFECT_GREENISH 14 - -/* QRD */ -#define CAMERA_ANTIBANDING_OFF 0 -#define CAMERA_ANTIBANDING_50HZ 2 -#define CAMERA_ANTIBANDING_60HZ 1 -#define CAMERA_ANTIBANDING_AUTO 3 - -#define CAMERA_CONTRAST_LV0 0 -#define CAMERA_CONTRAST_LV1 1 -#define CAMERA_CONTRAST_LV2 2 -#define CAMERA_CONTRAST_LV3 3 -#define CAMERA_CONTRAST_LV4 4 -#define CAMERA_CONTRAST_LV5 5 -#define CAMERA_CONTRAST_LV6 6 -#define CAMERA_CONTRAST_LV7 7 -#define CAMERA_CONTRAST_LV8 8 -#define CAMERA_CONTRAST_LV9 9 - -#define CAMERA_BRIGHTNESS_LV0 0 -#define CAMERA_BRIGHTNESS_LV1 1 -#define CAMERA_BRIGHTNESS_LV2 2 -#define CAMERA_BRIGHTNESS_LV3 3 -#define CAMERA_BRIGHTNESS_LV4 4 -#define CAMERA_BRIGHTNESS_LV5 5 -#define CAMERA_BRIGHTNESS_LV6 6 -#define CAMERA_BRIGHTNESS_LV7 7 -#define CAMERA_BRIGHTNESS_LV8 8 - - -#define CAMERA_SATURATION_LV0 0 -#define CAMERA_SATURATION_LV1 1 -#define CAMERA_SATURATION_LV2 2 -#define CAMERA_SATURATION_LV3 3 -#define CAMERA_SATURATION_LV4 4 -#define CAMERA_SATURATION_LV5 5 -#define CAMERA_SATURATION_LV6 6 -#define CAMERA_SATURATION_LV7 7 -#define CAMERA_SATURATION_LV8 8 - -#define CAMERA_SHARPNESS_LV0 0 -#define CAMERA_SHARPNESS_LV1 3 -#define CAMERA_SHARPNESS_LV2 6 -#define CAMERA_SHARPNESS_LV3 9 -#define CAMERA_SHARPNESS_LV4 12 -#define CAMERA_SHARPNESS_LV5 15 -#define CAMERA_SHARPNESS_LV6 18 -#define CAMERA_SHARPNESS_LV7 21 -#define CAMERA_SHARPNESS_LV8 24 -#define CAMERA_SHARPNESS_LV9 27 -#define CAMERA_SHARPNESS_LV10 30 - -#define CAMERA_SETAE_AVERAGE 0 -#define CAMERA_SETAE_CENWEIGHT 1 - -#define CAMERA_WB_AUTO 1 /* This list must match aeecamera.h */ -#define CAMERA_WB_CUSTOM 2 -#define CAMERA_WB_INCANDESCENT 3 -#define CAMERA_WB_FLUORESCENT 4 -#define CAMERA_WB_DAYLIGHT 5 -#define CAMERA_WB_CLOUDY_DAYLIGHT 6 -#define CAMERA_WB_TWILIGHT 7 -#define CAMERA_WB_SHADE 8 - -#define CAMERA_EXPOSURE_COMPENSATION_LV0 12 -#define CAMERA_EXPOSURE_COMPENSATION_LV1 6 -#define CAMERA_EXPOSURE_COMPENSATION_LV2 0 -#define CAMERA_EXPOSURE_COMPENSATION_LV3 -6 -#define CAMERA_EXPOSURE_COMPENSATION_LV4 -12 - -enum msm_v4l2_saturation_level { - MSM_V4L2_SATURATION_L0, - MSM_V4L2_SATURATION_L1, - MSM_V4L2_SATURATION_L2, - MSM_V4L2_SATURATION_L3, - MSM_V4L2_SATURATION_L4, - MSM_V4L2_SATURATION_L5, - MSM_V4L2_SATURATION_L6, - MSM_V4L2_SATURATION_L7, - MSM_V4L2_SATURATION_L8, - MSM_V4L2_SATURATION_L9, - MSM_V4L2_SATURATION_L10, -}; - -enum msm_v4l2_contrast_level { - MSM_V4L2_CONTRAST_L0, - MSM_V4L2_CONTRAST_L1, - MSM_V4L2_CONTRAST_L2, - MSM_V4L2_CONTRAST_L3, - MSM_V4L2_CONTRAST_L4, - MSM_V4L2_CONTRAST_L5, - MSM_V4L2_CONTRAST_L6, - MSM_V4L2_CONTRAST_L7, - MSM_V4L2_CONTRAST_L8, - MSM_V4L2_CONTRAST_L9, - MSM_V4L2_CONTRAST_L10, -}; - - -enum msm_v4l2_exposure_level { - MSM_V4L2_EXPOSURE_N2, - MSM_V4L2_EXPOSURE_N1, - MSM_V4L2_EXPOSURE_D, - MSM_V4L2_EXPOSURE_P1, - MSM_V4L2_EXPOSURE_P2, -}; - -enum msm_v4l2_sharpness_level { - MSM_V4L2_SHARPNESS_L0, - MSM_V4L2_SHARPNESS_L1, - MSM_V4L2_SHARPNESS_L2, - MSM_V4L2_SHARPNESS_L3, - MSM_V4L2_SHARPNESS_L4, - MSM_V4L2_SHARPNESS_L5, - MSM_V4L2_SHARPNESS_L6, -}; - -enum msm_v4l2_expo_metering_mode { - MSM_V4L2_EXP_FRAME_AVERAGE, - MSM_V4L2_EXP_CENTER_WEIGHTED, - MSM_V4L2_EXP_SPOT_METERING, -}; - -enum msm_v4l2_iso_mode { - MSM_V4L2_ISO_AUTO = 0, - MSM_V4L2_ISO_DEBLUR, - MSM_V4L2_ISO_100, - MSM_V4L2_ISO_200, - MSM_V4L2_ISO_400, - MSM_V4L2_ISO_800, - MSM_V4L2_ISO_1600, -}; - -enum msm_v4l2_wb_mode { - MSM_V4L2_WB_OFF, - MSM_V4L2_WB_AUTO, - MSM_V4L2_WB_CUSTOM, - MSM_V4L2_WB_INCANDESCENT, - MSM_V4L2_WB_FLUORESCENT, - MSM_V4L2_WB_DAYLIGHT, - MSM_V4L2_WB_CLOUDY_DAYLIGHT, -}; - -enum msm_v4l2_special_effect { - MSM_V4L2_EFFECT_OFF, - MSM_V4L2_EFFECT_MONO, - MSM_V4L2_EFFECT_NEGATIVE, - MSM_V4L2_EFFECT_SOLARIZE, - MSM_V4L2_EFFECT_SEPIA, - MSM_V4L2_EFFECT_POSTERAIZE, - MSM_V4L2_EFFECT_WHITEBOARD, - MSM_V4L2_EFFECT_BLACKBOARD, - MSM_V4L2_EFFECT_AQUA, - MSM_V4L2_EFFECT_EMBOSS, - MSM_V4L2_EFFECT_SKETCH, - MSM_V4L2_EFFECT_NEON, - MSM_V4L2_EFFECT_MAX, -}; - -enum msm_v4l2_power_line_frequency { - MSM_V4L2_POWER_LINE_OFF, - MSM_V4L2_POWER_LINE_60HZ, - MSM_V4L2_POWER_LINE_50HZ, - MSM_V4L2_POWER_LINE_AUTO, -}; - -#define CAMERA_ISO_TYPE_AUTO 0 -#define CAMEAR_ISO_TYPE_HJR 1 -#define CAMEAR_ISO_TYPE_100 2 -#define CAMERA_ISO_TYPE_200 3 -#define CAMERA_ISO_TYPE_400 4 -#define CAMEAR_ISO_TYPE_800 5 -#define CAMERA_ISO_TYPE_1600 6 - -struct sensor_pict_fps { - uint16_t prevfps; - uint16_t pictfps; -}; - -struct exp_gain_cfg { - uint16_t gain; - uint32_t line; -}; - -struct focus_cfg { - int32_t steps; - int dir; -}; - -struct fps_cfg { - uint16_t f_mult; - uint16_t fps_div; - uint32_t pict_fps_div; -}; -struct wb_info_cfg { - uint16_t red_gain; - uint16_t green_gain; - uint16_t blue_gain; -}; -struct sensor_3d_exp_cfg { - uint16_t gain; - uint32_t line; - uint16_t r_gain; - uint16_t b_gain; - uint16_t gr_gain; - uint16_t gb_gain; - uint16_t gain_adjust; -}; -struct sensor_3d_cali_data_t { - unsigned char left_p_matrix[3][4][8]; - unsigned char right_p_matrix[3][4][8]; - unsigned char square_len[8]; - unsigned char focal_len[8]; - unsigned char pixel_pitch[8]; - uint16_t left_r; - uint16_t left_b; - uint16_t left_gb; - uint16_t left_af_far; - uint16_t left_af_mid; - uint16_t left_af_short; - uint16_t left_af_5um; - uint16_t left_af_50up; - uint16_t left_af_50down; - uint16_t right_r; - uint16_t right_b; - uint16_t right_gb; - uint16_t right_af_far; - uint16_t right_af_mid; - uint16_t right_af_short; - uint16_t right_af_5um; - uint16_t right_af_50up; - uint16_t right_af_50down; -}; -struct sensor_init_cfg { - uint8_t prev_res; - uint8_t pict_res; -}; - -struct sensor_calib_data { - /* Color Related Measurements */ - uint16_t r_over_g; - uint16_t b_over_g; - uint16_t gr_over_gb; - - /* Lens Related Measurements */ - uint16_t macro_2_inf; - uint16_t inf_2_macro; - uint16_t stroke_amt; - uint16_t af_pos_1m; - uint16_t af_pos_inf; -}; - -enum msm_sensor_resolution_t { - MSM_SENSOR_RES_FULL, - MSM_SENSOR_RES_QTR, - MSM_SENSOR_RES_2, - MSM_SENSOR_RES_3, - MSM_SENSOR_RES_4, - MSM_SENSOR_RES_5, - MSM_SENSOR_RES_6, - MSM_SENSOR_RES_7, - MSM_SENSOR_INVALID_RES, -}; - -struct msm_sensor_output_info_t { - uint16_t x_output; - uint16_t y_output; - uint16_t line_length_pclk; - uint16_t frame_length_lines; - uint32_t vt_pixel_clk; - uint32_t op_pixel_clk; - uint16_t binning_factor; -}; - -struct sensor_output_info_t { - struct msm_sensor_output_info_t *output_info; - uint16_t num_info; -}; - -struct msm_sensor_exp_gain_info_t { - uint16_t coarse_int_time_addr; - uint16_t global_gain_addr; - uint16_t vert_offset; -}; - -struct msm_sensor_output_reg_addr_t { - uint16_t x_output; - uint16_t y_output; - uint16_t line_length_pclk; - uint16_t frame_length_lines; -}; - -struct sensor_driver_params_type { - struct msm_camera_i2c_reg_setting *init_settings; - uint16_t init_settings_size; - struct msm_camera_i2c_reg_setting *mode_settings; - uint16_t mode_settings_size; - struct msm_sensor_output_reg_addr_t *sensor_output_reg_addr; - struct msm_camera_i2c_reg_setting *start_settings; - struct msm_camera_i2c_reg_setting *stop_settings; - struct msm_camera_i2c_reg_setting *groupon_settings; - struct msm_camera_i2c_reg_setting *groupoff_settings; - struct msm_sensor_exp_gain_info_t *sensor_exp_gain_info; - struct msm_sensor_output_info_t *output_info; -}; - -struct mirror_flip { - int32_t x_mirror; - int32_t y_flip; -}; - -struct cord { - uint32_t x; - uint32_t y; -}; - -struct msm_eeprom_data_t { - void *eeprom_data; - uint16_t index; -}; - -struct msm_camera_csid_vc_cfg { - uint8_t cid; - uint8_t dt; - uint8_t decode_format; -}; - -struct csi_lane_params_t { - uint16_t csi_lane_assign; - uint8_t csi_lane_mask; - uint8_t csi_if; - uint8_t csid_core[2]; - uint8_t csi_phy_sel; -}; - -struct msm_camera_csid_lut_params { - uint8_t num_cid; - struct msm_camera_csid_vc_cfg *vc_cfg; -}; - -struct msm_camera_csid_params { - uint8_t lane_cnt; - uint16_t lane_assign; - uint8_t phy_sel; - struct msm_camera_csid_lut_params lut_params; -}; - -struct msm_camera_csiphy_params { - uint8_t lane_cnt; - uint8_t settle_cnt; - uint16_t lane_mask; - uint8_t combo_mode; - uint8_t csid_core; - uint64_t data_rate; -}; - -struct msm_camera_csi2_params { - struct msm_camera_csid_params csid_params; - struct msm_camera_csiphy_params csiphy_params; -}; - -enum msm_camera_csi_data_format { - CSI_8BIT, - CSI_10BIT, - CSI_12BIT, -}; - -struct msm_camera_csi_params { - enum msm_camera_csi_data_format data_format; - uint8_t lane_cnt; - uint8_t lane_assign; - uint8_t settle_cnt; - uint8_t dpcm_scheme; -}; - -enum csic_cfg_type_t { - CSIC_INIT, - CSIC_CFG, -}; - -struct csic_cfg_data { - enum csic_cfg_type_t cfgtype; - struct msm_camera_csi_params *csic_params; -}; - -enum csid_cfg_type_t { - CSID_INIT, - CSID_CFG, -}; - -struct csid_cfg_data { - enum csid_cfg_type_t cfgtype; - union { - uint32_t csid_version; - struct msm_camera_csid_params *csid_params; - } cfg; -}; - -enum csiphy_cfg_type_t { - CSIPHY_INIT, - CSIPHY_CFG, -}; - -struct csiphy_cfg_data { - enum csiphy_cfg_type_t cfgtype; - struct msm_camera_csiphy_params *csiphy_params; -}; - -#define CSI_EMBED_DATA 0x12 -#define CSI_RESERVED_DATA_0 0x13 -#define CSI_YUV422_8 0x1E -#define CSI_RAW8 0x2A -#define CSI_RAW10 0x2B -#define CSI_RAW12 0x2C - -#define CSI_DECODE_6BIT 0 -#define CSI_DECODE_8BIT 1 -#define CSI_DECODE_10BIT 2 -#define CSI_DECODE_DPCM_10_8_10 5 - -#define ISPIF_STREAM(intf, action, vfe) (((intf)<<ISPIF_S_STREAM_SHIFT)+\ - (action)+((vfe)<<ISPIF_VFE_INTF_SHIFT)) -#define ISPIF_ON_FRAME_BOUNDARY (0x01 << 0) -#define ISPIF_OFF_FRAME_BOUNDARY (0x01 << 1) -#define ISPIF_OFF_IMMEDIATELY (0x01 << 2) -#define ISPIF_S_STREAM_SHIFT 4 -#define ISPIF_VFE_INTF_SHIFT 12 - -#define PIX_0 (0x01 << 0) -#define RDI_0 (0x01 << 1) -#define PIX_1 (0x01 << 2) -#define RDI_1 (0x01 << 3) -#define RDI_2 (0x01 << 4) - -enum msm_ispif_vfe_intf { - VFE0, - VFE1, - VFE_MAX, -}; - -enum msm_ispif_intftype { - PIX0, - RDI0, - PIX1, - RDI1, - RDI2, - INTF_MAX, -}; - -enum msm_ispif_vc { - VC0, - VC1, - VC2, - VC3, -}; - -enum msm_ispif_cid { - CID0, - CID1, - CID2, - CID3, - CID4, - CID5, - CID6, - CID7, - CID8, - CID9, - CID10, - CID11, - CID12, - CID13, - CID14, - CID15, -}; - -struct msm_ispif_params { - uint8_t intftype; - uint16_t cid_mask; - uint8_t csid; - uint8_t vfe_intf; -}; - -struct msm_ispif_params_list { - uint32_t len; - struct msm_ispif_params params[4]; -}; - -enum ispif_cfg_type_t { - ISPIF_INIT, - ISPIF_SET_CFG, - ISPIF_SET_ON_FRAME_BOUNDARY, - ISPIF_SET_OFF_FRAME_BOUNDARY, - ISPIF_SET_OFF_IMMEDIATELY, - ISPIF_RELEASE, -}; - -struct ispif_cfg_data { - enum ispif_cfg_type_t cfgtype; - union { - uint32_t csid_version; - int cmd; - struct msm_ispif_params_list ispif_params; - } cfg; -}; - -enum msm_camera_i2c_reg_addr_type { - MSM_CAMERA_I2C_BYTE_ADDR = 1, - MSM_CAMERA_I2C_WORD_ADDR, - MSM_CAMERA_I2C_3B_ADDR, - MSM_CAMERA_I2C_DWORD_ADDR, -}; -#define MSM_CAMERA_I2C_DWORD_ADDR MSM_CAMERA_I2C_DWORD_ADDR - -struct msm_camera_i2c_reg_array { - uint16_t reg_addr; - uint16_t reg_data; -}; - -enum msm_camera_i2c_data_type { - MSM_CAMERA_I2C_BYTE_DATA = 1, - MSM_CAMERA_I2C_WORD_DATA, - MSM_CAMERA_I2C_SET_BYTE_MASK, - MSM_CAMERA_I2C_UNSET_BYTE_MASK, - MSM_CAMERA_I2C_SET_WORD_MASK, - MSM_CAMERA_I2C_UNSET_WORD_MASK, - MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA, -}; - -struct msm_camera_i2c_reg_setting { - struct msm_camera_i2c_reg_array *reg_setting; - uint16_t size; - enum msm_camera_i2c_reg_addr_type addr_type; - enum msm_camera_i2c_data_type data_type; - uint16_t delay; -}; - -enum oem_setting_type { - I2C_READ = 1, - I2C_WRITE, - GPIO_OP, - EEPROM_READ, - VREG_SET, - CLK_SET, -}; - -struct sensor_oem_setting { - enum oem_setting_type type; - void *data; -}; - -enum camera_vreg_type { - REG_LDO, - REG_VS, - REG_GPIO, -}; - -enum msm_camera_vreg_name_t { - CAM_VDIG, - CAM_VIO, - CAM_VANA, - CAM_VAF, - CAM_VREG_MAX, -}; - -struct msm_camera_csi_lane_params { - uint16_t csi_lane_assign; - uint16_t csi_lane_mask; -}; - -struct camera_vreg_t { - const char *reg_name; - int min_voltage; - int max_voltage; - int op_mode; - uint32_t delay; -}; - -struct msm_camera_vreg_setting { - struct camera_vreg_t *cam_vreg; - uint16_t num_vreg; - uint8_t enable; -}; - -struct msm_cam_clk_info { - const char *clk_name; - long clk_rate; - uint32_t delay; -}; - -struct msm_cam_clk_setting { - struct msm_cam_clk_info *clk_info; - uint16_t num_clk_info; - uint8_t enable; -}; - -struct sensor_cfg_data { - int cfgtype; - int mode; - int rs; - uint8_t max_steps; - - union { - int8_t effect; - uint8_t lens_shading; - uint16_t prevl_pf; - uint16_t prevp_pl; - uint16_t pictl_pf; - uint16_t pictp_pl; - uint32_t pict_max_exp_lc; - uint16_t p_fps; - uint8_t iso_type; - struct sensor_init_cfg init_info; - struct sensor_pict_fps gfps; - struct exp_gain_cfg exp_gain; - struct focus_cfg focus; - struct fps_cfg fps; - struct wb_info_cfg wb_info; - struct sensor_3d_exp_cfg sensor_3d_exp; - struct sensor_calib_data calib_info; - struct sensor_output_info_t output_info; - struct msm_eeprom_data_t eeprom_data; - struct csi_lane_params_t csi_lane_params; - /* QRD */ - uint16_t antibanding; - uint8_t contrast; - uint8_t saturation; - uint8_t sharpness; - int8_t brightness; - int ae_mode; - uint8_t wb_val; - int8_t exp_compensation; - uint32_t pclk; - struct cord aec_cord; - int is_autoflash; - struct mirror_flip mirror_flip; - void *setting; - } cfg; -}; - -enum gpio_operation_type { - GPIO_REQUEST, - GPIO_FREE, - GPIO_SET_DIRECTION_OUTPUT, - GPIO_SET_DIRECTION_INPUT, - GPIO_GET_VALUE, - GPIO_SET_VALUE, -}; - -struct msm_cam_gpio_operation { - enum gpio_operation_type op_type; - unsigned int address; - int value; - const char *tag; -}; - -struct damping_params_t { - uint32_t damping_step; - uint32_t damping_delay; - uint32_t hw_params; -}; - -enum actuator_type { - ACTUATOR_VCM, - ACTUATOR_PIEZO, - ACTUATOR_HVCM, - ACTUATOR_BIVCM, -}; - -enum msm_actuator_data_type { - MSM_ACTUATOR_BYTE_DATA = 1, - MSM_ACTUATOR_WORD_DATA, -}; - -enum msm_actuator_addr_type { - MSM_ACTUATOR_BYTE_ADDR = 1, - MSM_ACTUATOR_WORD_ADDR, -}; - -enum msm_actuator_write_type { - MSM_ACTUATOR_WRITE_HW_DAMP, - MSM_ACTUATOR_WRITE_DAC, - MSM_ACTUATOR_WRITE, - MSM_ACTUATOR_WRITE_DIR_REG, - MSM_ACTUATOR_POLL, - MSM_ACTUATOR_READ_WRITE, -}; - -struct msm_actuator_reg_params_t { - enum msm_actuator_write_type reg_write_type; - uint32_t hw_mask; - uint16_t reg_addr; - uint16_t hw_shift; - uint16_t data_type; - uint16_t addr_type; - uint16_t reg_data; - uint16_t delay; -}; - -struct reg_settings_t { - uint16_t reg_addr; - uint16_t reg_data; -}; - -struct region_params_t { - /* [0] = ForwardDirection Macro boundary - * [1] = ReverseDirection Inf boundary - */ - uint16_t step_bound[2]; - uint16_t code_per_step; -}; - -struct msm_actuator_move_params_t { - int8_t dir; - int8_t sign_dir; - int16_t dest_step_pos; - int32_t num_steps; - struct damping_params_t *ringing_params; -}; - -struct msm_actuator_tuning_params_t { - int16_t initial_code; - uint16_t pwd_step; - uint16_t region_size; - uint32_t total_steps; - struct region_params_t *region_params; -}; - -struct msm_actuator_params_t { - enum actuator_type act_type; - uint8_t reg_tbl_size; - uint16_t data_size; - uint16_t init_setting_size; - uint32_t i2c_addr; - enum msm_actuator_addr_type i2c_addr_type; - enum msm_actuator_data_type i2c_data_type; - struct msm_actuator_reg_params_t *reg_tbl_params; - struct reg_settings_t *init_settings; -}; - -struct msm_actuator_set_info_t { - struct msm_actuator_params_t actuator_params; - struct msm_actuator_tuning_params_t af_tuning_params; -}; - -struct msm_actuator_get_info_t { - uint32_t focal_length_num; - uint32_t focal_length_den; - uint32_t f_number_num; - uint32_t f_number_den; - uint32_t f_pix_num; - uint32_t f_pix_den; - uint32_t total_f_dist_num; - uint32_t total_f_dist_den; - uint32_t hor_view_angle_num; - uint32_t hor_view_angle_den; - uint32_t ver_view_angle_num; - uint32_t ver_view_angle_den; -}; - -enum af_camera_name { - ACTUATOR_MAIN_CAM_0, - ACTUATOR_MAIN_CAM_1, - ACTUATOR_MAIN_CAM_2, - ACTUATOR_MAIN_CAM_3, - ACTUATOR_MAIN_CAM_4, - ACTUATOR_MAIN_CAM_5, - ACTUATOR_WEB_CAM_0, - ACTUATOR_WEB_CAM_1, - ACTUATOR_WEB_CAM_2, -}; - -struct msm_actuator_cfg_data { - int cfgtype; - uint8_t is_af_supported; - union { - struct msm_actuator_move_params_t move; - struct msm_actuator_set_info_t set_info; - struct msm_actuator_get_info_t get_info; - enum af_camera_name cam_name; - } cfg; -}; - -struct msm_eeprom_support { - uint16_t is_supported; - uint16_t size; - uint16_t index; - uint16_t qvalue; -}; - -struct msm_calib_wb { - uint16_t r_over_g; - uint16_t b_over_g; - uint16_t gr_over_gb; -}; - -struct msm_calib_af { - uint16_t macro_dac; - uint16_t inf_dac; - uint16_t start_dac; -}; - -struct msm_calib_lsc { - uint16_t r_gain[221]; - uint16_t b_gain[221]; - uint16_t gr_gain[221]; - uint16_t gb_gain[221]; -}; - -struct pixel_t { - int x; - int y; -}; - -struct msm_calib_dpc { - uint16_t validcount; - struct pixel_t snapshot_coord[128]; - struct pixel_t preview_coord[128]; - struct pixel_t video_coord[128]; -}; - -struct msm_calib_raw { - uint8_t *data; - uint32_t size; -}; - -struct msm_camera_eeprom_info_t { - struct msm_eeprom_support af; - struct msm_eeprom_support wb; - struct msm_eeprom_support lsc; - struct msm_eeprom_support dpc; - struct msm_eeprom_support raw; -}; - -struct msm_eeprom_cfg_data { - int cfgtype; - uint8_t is_eeprom_supported; - union { - struct msm_eeprom_data_t get_data; - struct msm_camera_eeprom_info_t get_info; - } cfg; -}; - -struct sensor_large_data { - int cfgtype; - union { - struct sensor_3d_cali_data_t sensor_3d_cali_data; - } data; -}; - -enum sensor_type_t { - BAYER, - YUV, - JPEG_SOC, -}; - -enum flash_type { - LED_FLASH, - STROBE_FLASH, -}; - -enum strobe_flash_ctrl_type { - STROBE_FLASH_CTRL_INIT, - STROBE_FLASH_CTRL_CHARGE, - STROBE_FLASH_CTRL_RELEASE -}; - -struct strobe_flash_ctrl_data { - enum strobe_flash_ctrl_type type; - int charge_en; -}; - -struct msm_camera_info { - int num_cameras; - uint8_t has_3d_support[MSM_MAX_CAMERA_SENSORS]; - uint8_t is_internal_cam[MSM_MAX_CAMERA_SENSORS]; - uint32_t s_mount_angle[MSM_MAX_CAMERA_SENSORS]; - const char *video_dev_name[MSM_MAX_CAMERA_SENSORS]; - enum sensor_type_t sensor_type[MSM_MAX_CAMERA_SENSORS]; -}; - -struct msm_cam_config_dev_info { - int num_config_nodes; - const char *config_dev_name[MSM_MAX_CAMERA_CONFIGS]; - int config_dev_id[MSM_MAX_CAMERA_CONFIGS]; -}; - -struct msm_mctl_node_info { - int num_mctl_nodes; - const char *mctl_node_name[MSM_MAX_CAMERA_SENSORS]; -}; - -struct flash_ctrl_data { - int flashtype; - union { - int led_state; - struct strobe_flash_ctrl_data strobe_ctrl; - } ctrl_data; -}; - -#define GET_NAME 0 -#define GET_PREVIEW_LINE_PER_FRAME 1 -#define GET_PREVIEW_PIXELS_PER_LINE 2 -#define GET_SNAPSHOT_LINE_PER_FRAME 3 -#define GET_SNAPSHOT_PIXELS_PER_LINE 4 -#define GET_SNAPSHOT_FPS 5 -#define GET_SNAPSHOT_MAX_EP_LINE_CNT 6 - -struct msm_camsensor_info { - char name[MAX_SENSOR_NAME]; - uint8_t flash_enabled; - uint8_t strobe_flash_enabled; - uint8_t actuator_enabled; - uint8_t ispif_supported; - int8_t total_steps; - uint8_t support_3d; - enum flash_type flashtype; - enum sensor_type_t sensor_type; - uint32_t pxlcode; /* enum v4l2_mbus_pixelcode */ - uint32_t camera_type; /* msm_camera_type */ - int mount_angle; - uint32_t max_width; - uint32_t max_height; -}; - -#define V4L2_SINGLE_PLANE 0 -#define V4L2_MULTI_PLANE_Y 0 -#define V4L2_MULTI_PLANE_CBCR 1 -#define V4L2_MULTI_PLANE_CB 1 -#define V4L2_MULTI_PLANE_CR 2 - -struct plane_data { - int plane_id; - uint32_t offset; - unsigned long size; -}; - -struct img_plane_info { - uint32_t width; - uint32_t height; - uint32_t pixelformat; - uint8_t buffer_type; /*Single/Multi planar*/ - uint8_t output_port; - uint32_t ext_mode; - uint8_t num_planes; - struct plane_data plane[MAX_PLANES]; - uint32_t sp_y_offset; - uint32_t inst_handle; -}; - -#define QCAMERA_NAME "qcamera" -#define QCAMERA_SERVER_NAME "qcamera_server" -#define QCAMERA_VNODE_GROUP_ID MEDIA_ENT_F_IO_V4L - -enum msm_cam_subdev_type { - CSIPHY_DEV, - CSID_DEV, - CSIC_DEV, - ISPIF_DEV, - VFE_DEV, - AXI_DEV, - VPE_DEV, - SENSOR_DEV, - ACTUATOR_DEV, - EEPROM_DEV, - GESTURE_DEV, - IRQ_ROUTER_DEV, - CPP_DEV, - CCI_DEV, - FLASH_DEV, -}; - -struct msm_mctl_set_sdev_data { - uint32_t revision; - enum msm_cam_subdev_type sdev_type; -}; - -#define MSM_CAM_V4L2_IOCTL_GET_CAMERA_INFO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) - -#define MSM_CAM_V4L2_IOCTL_GET_CONFIG_INFO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) - -#define MSM_CAM_V4L2_IOCTL_GET_MCTL_INFO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t) - -#define MSM_CAM_V4L2_IOCTL_CTRL_CMD_DONE \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t) - -#define MSM_CAM_V4L2_IOCTL_GET_EVENT_PAYLOAD \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t) - -#define MSM_CAM_IOCTL_SEND_EVENT \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct v4l2_event) - -#define MSM_CAM_V4L2_IOCTL_CFG_VPE \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_vpe_cfg_cmd) - -#define MSM_CAM_V4L2_IOCTL_PRIVATE_S_CTRL \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t) - -#define MSM_CAM_V4L2_IOCTL_PRIVATE_G_CTRL \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t) - -#define MSM_CAM_V4L2_IOCTL_PRIVATE_GENERAL \ - _IOW('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_VPE_INIT \ - _IO('V', BASE_VIDIOC_PRIVATE + 15) - -#define VIDIOC_MSM_VPE_RELEASE \ - _IO('V', BASE_VIDIOC_PRIVATE + 16) - -#define VIDIOC_MSM_VPE_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_mctl_pp_params *) - -#define VIDIOC_MSM_AXI_INIT \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 18, uint8_t *) - -#define VIDIOC_MSM_AXI_RELEASE \ - _IO('V', BASE_VIDIOC_PRIVATE + 19) - -#define VIDIOC_MSM_AXI_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 20, void *) - -#define VIDIOC_MSM_AXI_IRQ \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 21, void *) - -#define VIDIOC_MSM_AXI_BUF_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 22, void *) - -#define VIDIOC_MSM_AXI_RDI_COUNT_UPDATE \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 23, void *) - -#define VIDIOC_MSM_VFE_INIT \ - _IO('V', BASE_VIDIOC_PRIVATE + 24) - -#define VIDIOC_MSM_VFE_RELEASE \ - _IO('V', BASE_VIDIOC_PRIVATE + 25) - -struct msm_camera_v4l2_ioctl_t { - uint32_t id; - uint32_t len; - uint32_t trans_code; - void *ioctl_ptr; -}; - -struct msm_camera_vfe_params_t { - uint32_t operation_mode; - uint32_t capture_count; - uint8_t skip_reset; - uint8_t stop_immediately; - uint16_t port_info; - uint32_t inst_handle; - uint16_t cmd_type; -}; - -enum msm_camss_irq_idx { - CAMERA_SS_IRQ_0, - CAMERA_SS_IRQ_1, - CAMERA_SS_IRQ_2, - CAMERA_SS_IRQ_3, - CAMERA_SS_IRQ_4, - CAMERA_SS_IRQ_5, - CAMERA_SS_IRQ_6, - CAMERA_SS_IRQ_7, - CAMERA_SS_IRQ_8, - CAMERA_SS_IRQ_9, - CAMERA_SS_IRQ_10, - CAMERA_SS_IRQ_11, - CAMERA_SS_IRQ_12, - CAMERA_SS_IRQ_MAX -}; - -enum msm_cam_hw_idx { - MSM_CAM_HW_MICRO, - MSM_CAM_HW_CCI, - MSM_CAM_HW_CSI0, - MSM_CAM_HW_CSI1, - MSM_CAM_HW_CSI2, - MSM_CAM_HW_CSI3, - MSM_CAM_HW_ISPIF, - MSM_CAM_HW_CPP, - MSM_CAM_HW_VFE0, - MSM_CAM_HW_VFE1, - MSM_CAM_HW_JPEG0, - MSM_CAM_HW_JPEG1, - MSM_CAM_HW_JPEG2, - MSM_CAM_HW_MAX -}; - -struct msm_camera_irq_cfg { - /* Bit mask of all the camera hardwares that needs to - * be composited into a single IRQ to the MSM. - * Current usage: (may be updated based on hw changes) - * Bits 31:13 - Reserved. - * Bits 12:0 - * 12 - MSM_CAM_HW_JPEG2 - * 11 - MSM_CAM_HW_JPEG1 - * 10 - MSM_CAM_HW_JPEG0 - * 9 - MSM_CAM_HW_VFE1 - * 8 - MSM_CAM_HW_VFE0 - * 7 - MSM_CAM_HW_CPP - * 6 - MSM_CAM_HW_ISPIF - * 5 - MSM_CAM_HW_CSI3 - * 4 - MSM_CAM_HW_CSI2 - * 3 - MSM_CAM_HW_CSI1 - * 2 - MSM_CAM_HW_CSI0 - * 1 - MSM_CAM_HW_CCI - * 0 - MSM_CAM_HW_MICRO - */ - uint32_t cam_hw_mask; - uint8_t irq_idx; - uint8_t num_hwcore; -}; - -#define MSM_IRQROUTER_CFG_COMPIRQ \ - _IOWR('V', BASE_VIDIOC_PRIVATE, void *) - -#define MAX_NUM_CPP_STRIPS 8 - -enum msm_cpp_frame_type { - MSM_CPP_OFFLINE_FRAME, - MSM_CPP_REALTIME_FRAME, -}; - -struct msm_cpp_frame_info_t { - int32_t frame_id; - uint32_t inst_id; - uint32_t client_id; - enum msm_cpp_frame_type frame_type; - uint32_t num_strips; -}; - -struct msm_ver_num_info { - uint32_t main; - uint32_t minor; - uint32_t rev; -}; - -#define VIDIOC_MSM_CPP_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_GET_INST_INFO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) - -#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0) - -/* Instance Handle - inst_handle - * Data bundle containing the information about where - * to get a buffer for a particular camera instance. - * This is a bitmask containing the following data: - * Buffer Handle Bitmask: - * ------------------------------------ - * Bits : Purpose - * ------------------------------------ - * 31 : is Dev ID valid? - * 30 - 24 : Dev ID. - * 23 : is Image mode valid? - * 22 - 16 : Image mode. - * 15 : is MCTL PP inst idx valid? - * 14 - 8 : MCTL PP inst idx. - * 7 : is Video inst idx valid? - * 6 - 0 : Video inst idx. - */ -#define CLR_DEVID_MODE(handle) (handle &= 0x00FFFFFF) -#define SET_DEVID_MODE(handle, data) \ - (handle |= ((0x1 << 31) | ((data & 0x7F) << 24))) -#define GET_DEVID_MODE(handle) \ - ((handle & 0x80000000) ? ((handle & 0x7F000000) >> 24) : 0xFF) - -#define CLR_IMG_MODE(handle) (handle &= 0xFF00FFFF) -#define SET_IMG_MODE(handle, data) \ - (handle |= ((0x1 << 23) | ((data & 0x7F) << 16))) -#define GET_IMG_MODE(handle) \ - ((handle & 0x800000) ? ((handle & 0x7F0000) >> 16) : 0xFF) - -#define CLR_MCTLPP_INST_IDX(handle) (handle &= 0xFFFF00FF) -#define SET_MCTLPP_INST_IDX(handle, data) \ - (handle |= ((0x1 << 15) | ((data & 0x7F) << 8))) -#define GET_MCTLPP_INST_IDX(handle) \ - ((handle & 0x8000) ? ((handle & 0x7F00) >> 8) : 0xFF) - -#define CLR_VIDEO_INST_IDX(handle) (handle &= 0xFFFFFF00) -#define GET_VIDEO_INST_IDX(handle) \ - ((handle & 0x80) ? (handle & 0x7F) : 0xFF) -#define SET_VIDEO_INST_IDX(handle, data) \ - (handle |= (0x1 << 7) | (data & 0x7F)) -#endif diff --git a/sdm710/original-kernel-headers/media/msm_camsensor_sdk.h b/sdm710/original-kernel-headers/media/msm_camsensor_sdk.h deleted file mode 100644 index 6d25967d..00000000 --- a/sdm710/original-kernel-headers/media/msm_camsensor_sdk.h +++ /dev/null @@ -1,432 +0,0 @@ -#ifndef __UAPI_LINUX_MSM_CAMSENSOR_SDK_H -#define __UAPI_LINUX_MSM_CAMSENSOR_SDK_H - -#include <linux/videodev2.h> - -#define KVERSION 0x1 - -#define MAX_POWER_CONFIG 12 -#define GPIO_OUT_LOW (0 << 1) -#define GPIO_OUT_HIGH (1 << 1) -#define CSI_EMBED_DATA 0x12 -#define CSI_RESERVED_DATA_0 0x13 -#define CSI_YUV422_8 0x1E -#define CSI_RAW8 0x2A -#define CSI_RAW10 0x2B -#define CSI_RAW12 0x2C -#define CSI_DECODE_6BIT 0 -#define CSI_DECODE_8BIT 1 -#define CSI_DECODE_10BIT 2 -#define CSI_DECODE_12BIT 3 -#define CSI_DECODE_DPCM_10_6_10 4 -#define CSI_DECODE_DPCM_10_8_10 5 -#define MAX_CID 16 -#define I2C_SEQ_REG_DATA_MAX 1024 -#define I2C_REG_DATA_MAX (8*1024) - -#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */ -#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') - /* 14 BGBG.. GRGR.. */ -#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') - /* 14 GBGB.. RGRG.. */ -#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') - /* 14 GRGR.. BGBG.. */ -#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') - /* 14 RGRG.. GBGB.. */ - -#define MAX_ACTUATOR_REG_TBL_SIZE 8 -#define MAX_ACTUATOR_REGION 5 -#define NUM_ACTUATOR_DIR 2 -#define MAX_ACTUATOR_SCENARIO 8 -#define MAX_ACT_MOD_NAME_SIZE 32 -#define MAX_ACT_NAME_SIZE 32 -#define MAX_ACTUATOR_INIT_SET 120 -#define MAX_I2C_REG_SET 12 - -#define MAX_LED_TRIGGERS 3 - -#define MSM_EEPROM_MEMORY_MAP_MAX_SIZE 80 -#define MSM_EEPROM_MAX_MEM_MAP_CNT 8 - -#define MSM_SENSOR_BYPASS_VIDEO_NODE 1 - -enum msm_sensor_camera_id_t { - CAMERA_0, - CAMERA_1, - CAMERA_2, - CAMERA_3, - MAX_CAMERAS, -}; - -enum i2c_freq_mode_t { - I2C_STANDARD_MODE, - I2C_FAST_MODE, - I2C_CUSTOM_MODE, - I2C_FAST_PLUS_MODE, - I2C_MAX_MODES, -}; - -enum camb_position_t { - BACK_CAMERA_B, - FRONT_CAMERA_B, - AUX_CAMERA_B = 0x100, - INVALID_CAMERA_B, -}; - -enum msm_sensor_power_seq_type_t { - SENSOR_CLK, - SENSOR_GPIO, - SENSOR_VREG, - SENSOR_I2C_MUX, - SENSOR_I2C, -}; - -enum msm_camera_i2c_reg_addr_type { - MSM_CAMERA_I2C_BYTE_ADDR = 1, - MSM_CAMERA_I2C_WORD_ADDR, - MSM_CAMERA_I2C_3B_ADDR, - MSM_CAMERA_I2C_DWORD_ADDR, - MSM_CAMERA_I2C_ADDR_TYPE_MAX, -}; -#define MSM_CAMERA_I2C_DWORD_ADDR MSM_CAMERA_I2C_DWORD_ADDR - -enum msm_camera_i2c_data_type { - MSM_CAMERA_I2C_BYTE_DATA = 1, - MSM_CAMERA_I2C_WORD_DATA, - MSM_CAMERA_I2C_DWORD_DATA, - MSM_CAMERA_I2C_SET_BYTE_MASK, - MSM_CAMERA_I2C_UNSET_BYTE_MASK, - MSM_CAMERA_I2C_SET_WORD_MASK, - MSM_CAMERA_I2C_UNSET_WORD_MASK, - MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA, - MSM_CAMERA_I2C_DATA_TYPE_MAX, -}; - -enum msm_sensor_power_seq_gpio_t { - SENSOR_GPIO_RESET, - SENSOR_GPIO_STANDBY, - SENSOR_GPIO_AF_PWDM, - SENSOR_GPIO_VIO, - SENSOR_GPIO_VANA, - SENSOR_GPIO_VDIG, - SENSOR_GPIO_VAF, - SENSOR_GPIO_FL_EN, - SENSOR_GPIO_FL_NOW, - SENSOR_GPIO_FL_RESET, - SENSOR_GPIO_CUSTOM1, - SENSOR_GPIO_CUSTOM2, - SENSOR_GPIO_CUSTOM3, - SENSOR_GPIO_MAX, -}; -#define SENSOR_GPIO_CUSTOM3 SENSOR_GPIO_CUSTOM3 - -enum msm_ir_cut_filter_gpio_t { - IR_CUT_FILTER_GPIO_P = 0, - IR_CUT_FILTER_GPIO_M, - IR_CUT_FILTER_GPIO_MAX, -}; -#define IR_CUT_FILTER_GPIO_P IR_CUT_FILTER_GPIO_P -#define IR_CUT_FILTER_GPIO_M IR_CUT_FILTER_GPIO_M -#define R_CUT_FILTER_GPIO_MAX IR_CUT_FILTER_GPIO_MAX - -enum msm_camera_vreg_name_t { - CAM_VDIG, - CAM_VIO, - CAM_VANA, - CAM_VAF, - CAM_V_CUSTOM1, - CAM_V_CUSTOM2, - CAM_VREG_MAX, -}; - -enum msm_sensor_clk_type_t { - SENSOR_CAM_MCLK, - SENSOR_CAM_CLK, - SENSOR_CAM_CLK_MAX, -}; - -enum camerab_mode_t { - CAMERA_MODE_2D_B = (1<<0), - CAMERA_MODE_3D_B = (1<<1), - CAMERA_MODE_INVALID = (1<<2), -}; - -enum msm_actuator_data_type { - MSM_ACTUATOR_BYTE_DATA = 1, - MSM_ACTUATOR_WORD_DATA, -}; - -enum msm_actuator_addr_type { - MSM_ACTUATOR_BYTE_ADDR = 1, - MSM_ACTUATOR_WORD_ADDR, -}; - -enum msm_actuator_write_type { - MSM_ACTUATOR_WRITE_HW_DAMP, - MSM_ACTUATOR_WRITE_DAC, - MSM_ACTUATOR_WRITE, - MSM_ACTUATOR_WRITE_DIR_REG, - MSM_ACTUATOR_POLL, - MSM_ACTUATOR_READ_WRITE, -}; - -enum msm_actuator_i2c_operation { - MSM_ACT_WRITE = 0, - MSM_ACT_POLL, -}; - -enum actuator_type { - ACTUATOR_VCM, - ACTUATOR_PIEZO, - ACTUATOR_HVCM, - ACTUATOR_BIVCM, -}; - -enum msm_flash_driver_type { - FLASH_DRIVER_PMIC, - FLASH_DRIVER_I2C, - FLASH_DRIVER_GPIO, - FLASH_DRIVER_DEFAULT -}; - -enum msm_flash_cfg_type_t { - CFG_FLASH_INIT, - CFG_FLASH_RELEASE, - CFG_FLASH_OFF, - CFG_FLASH_LOW, - CFG_FLASH_HIGH, -}; - -enum msm_ir_led_cfg_type_t { - CFG_IR_LED_INIT = 0, - CFG_IR_LED_RELEASE, - CFG_IR_LED_OFF, - CFG_IR_LED_ON, -}; -#define CFG_IR_LED_INIT CFG_IR_LED_INIT -#define CFG_IR_LED_RELEASE CFG_IR_LED_RELEASE -#define CFG_IR_LED_OFF CFG_IR_LED_OFF -#define CFG_IR_LED_ON CFG_IR_LED_ON - -enum msm_laser_led_cfg_type_t { - CFG_LASER_LED_INIT, - CFG_LASER_LED_CONTROL, -}; -#define CFG_LASER_LED_INIT CFG_LASER_LED_INIT -#define CFG_LASER_LED_CONTROL CFG_LASER_LED_CONTROL - -enum msm_ir_cut_cfg_type_t { - CFG_IR_CUT_INIT = 0, - CFG_IR_CUT_RELEASE, - CFG_IR_CUT_OFF, - CFG_IR_CUT_ON, -}; -#define CFG_IR_CUT_INIT CFG_IR_CUT_INIT -#define CFG_IR_CUT_RELEASE CFG_IR_CUT_RELEASE -#define CFG_IR_CUT_OFF CFG_IR_CUT_OFF -#define CFG_IR_CUT_ON CFG_IR_CUT_ON - -enum msm_sensor_output_format_t { - MSM_SENSOR_BAYER, - MSM_SENSOR_YCBCR, - MSM_SENSOR_META, -}; - -struct msm_sensor_power_setting { - enum msm_sensor_power_seq_type_t seq_type; - unsigned short seq_val; - long config_val; - unsigned short delay; - void *data[10]; -}; - -struct msm_sensor_power_setting_array { - struct msm_sensor_power_setting power_setting_a[MAX_POWER_CONFIG]; - struct msm_sensor_power_setting *power_setting; - unsigned short size; - struct msm_sensor_power_setting power_down_setting_a[MAX_POWER_CONFIG]; - struct msm_sensor_power_setting *power_down_setting; - unsigned short size_down; -}; - -enum msm_camera_i2c_operation { - MSM_CAM_WRITE = 0, - MSM_CAM_POLL, - MSM_CAM_READ, -}; - -struct msm_sensor_i2c_sync_params { - unsigned int cid; - int csid; - unsigned short line; - unsigned short delay; -}; - -struct msm_camera_reg_settings_t { - uint16_t reg_addr; - enum msm_camera_i2c_reg_addr_type addr_type; - uint16_t reg_data; - enum msm_camera_i2c_data_type data_type; - enum msm_camera_i2c_operation i2c_operation; - uint16_t delay; -}; - -struct msm_eeprom_mem_map_t { - int slave_addr; - struct msm_camera_reg_settings_t - mem_settings[MSM_EEPROM_MEMORY_MAP_MAX_SIZE]; - int memory_map_size; -}; - -struct msm_eeprom_memory_map_array { - struct msm_eeprom_mem_map_t memory_map[MSM_EEPROM_MAX_MEM_MAP_CNT]; - uint32_t msm_size_of_max_mappings; -}; - -struct msm_sensor_init_params { - /* mask of modes supported: 2D, 3D */ - int modes_supported; - /* sensor position: front, back */ - enum camb_position_t position; - /* sensor mount angle */ - unsigned int sensor_mount_angle; -}; - -struct msm_sensor_id_info_t { - unsigned short sensor_id_reg_addr; - unsigned short sensor_id; - unsigned short sensor_id_mask; -}; - -struct msm_camera_sensor_slave_info { - char sensor_name[32]; - char eeprom_name[32]; - char actuator_name[32]; - char ois_name[32]; - char flash_name[32]; - enum msm_sensor_camera_id_t camera_id; - unsigned short slave_addr; - enum i2c_freq_mode_t i2c_freq_mode; - enum msm_camera_i2c_reg_addr_type addr_type; - struct msm_sensor_id_info_t sensor_id_info; - struct msm_sensor_power_setting_array power_setting_array; - unsigned char is_init_params_valid; - struct msm_sensor_init_params sensor_init_params; - enum msm_sensor_output_format_t output_format; - uint8_t bypass_video_node_creation; -}; - -struct msm_camera_i2c_reg_array { - unsigned short reg_addr; - unsigned short reg_data; - unsigned int delay; -}; - -struct msm_camera_i2c_reg_setting { - struct msm_camera_i2c_reg_array *reg_setting; - unsigned short size; - enum msm_camera_i2c_reg_addr_type addr_type; - enum msm_camera_i2c_data_type data_type; - unsigned short delay; -}; - -struct msm_camera_csid_vc_cfg { - unsigned char cid; - unsigned char dt; - unsigned char decode_format; -}; - -struct msm_camera_csid_lut_params { - unsigned char num_cid; - struct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID]; - struct msm_camera_csid_vc_cfg *vc_cfg[MAX_CID]; -}; - -struct msm_camera_csid_params { - unsigned char lane_cnt; - unsigned short lane_assign; - unsigned char phy_sel; - unsigned int csi_clk; - struct msm_camera_csid_lut_params lut_params; - unsigned char csi_3p_sel; -}; - -struct msm_camera_csid_testmode_parms { - unsigned int num_bytes_per_line; - unsigned int num_lines; - unsigned int h_blanking_count; - unsigned int v_blanking_count; - unsigned int payload_mode; -}; - -struct msm_camera_csiphy_params { - unsigned char lane_cnt; - unsigned char settle_cnt; - unsigned short lane_mask; - unsigned char combo_mode; - unsigned char csid_core; - unsigned int csiphy_clk; - unsigned char csi_3phase; - uint64_t data_rate; -}; - -struct msm_camera_i2c_seq_reg_array { - unsigned short reg_addr; - unsigned char reg_data[I2C_SEQ_REG_DATA_MAX]; - unsigned short reg_data_size; -}; - -struct msm_camera_i2c_seq_reg_setting { - struct msm_camera_i2c_seq_reg_array *reg_setting; - unsigned short size; - enum msm_camera_i2c_reg_addr_type addr_type; - unsigned short delay; -}; - -struct msm_actuator_reg_params_t { - enum msm_actuator_write_type reg_write_type; - unsigned int hw_mask; - unsigned short reg_addr; - unsigned short hw_shift; - unsigned short data_shift; - unsigned short data_type; - unsigned short addr_type; - unsigned short reg_data; - unsigned short delay; -}; - - -struct damping_params_t { - unsigned int damping_step; - unsigned int damping_delay; - unsigned int hw_params; -}; - -struct region_params_t { - /* [0] = ForwardDirection Macro boundary - * [1] = ReverseDirection Inf boundary - */ - unsigned short step_bound[2]; - unsigned short code_per_step; - /* qvalue for converting float type numbers to integer format */ - unsigned int qvalue; -}; - -struct reg_settings_t { - unsigned short reg_addr; - enum msm_camera_i2c_reg_addr_type addr_type; - unsigned short reg_data; - enum msm_camera_i2c_data_type data_type; - enum msm_actuator_i2c_operation i2c_operation; - unsigned int delay; -}; - -struct msm_camera_i2c_reg_setting_array { - struct msm_camera_i2c_reg_array reg_setting_a[MAX_I2C_REG_SET]; - unsigned short size; - enum msm_camera_i2c_reg_addr_type addr_type; - enum msm_camera_i2c_data_type data_type; - unsigned short delay; -}; - -#endif diff --git a/sdm710/original-kernel-headers/media/msm_fd.h b/sdm710/original-kernel-headers/media/msm_fd.h deleted file mode 100644 index 8afc1363..00000000 --- a/sdm710/original-kernel-headers/media/msm_fd.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef __UAPI_MSM_FD__ -#define __UAPI_MSM_FD__ - -#include <linux/videodev2.h> -#include <linux/types.h> - -/* - * struct msm_fd_event - Structure contain event info. - * @buf_index: Buffer index. - * @frame_id: Frame id. - * @face_cnt: Detected faces. - */ -struct msm_fd_event { - __u32 buf_index; - __u32 frame_id; - __u32 face_cnt; -}; - -/* - * enum msm_fd_pose - Face pose. - */ -enum msm_fd_pose { - MSM_FD_POSE_FRONT, - MSM_FD_POSE_RIGHT_DIAGONAL, - MSM_FD_POSE_RIGHT, - MSM_FD_POSE_LEFT_DIAGONAL, - MSM_FD_POSE_LEFT, -}; - -/* - * struct msm_fd_face_data - Structure contain detected face data. - * @pose: refer to enum msm_fd_pose. - * @angle: Face angle - * @confidence: Face confidence level. - * @reserved: Reserved data for future use. - * @face: Face rectangle. - */ -struct msm_fd_face_data { - __u32 pose; - __u32 angle; - __u32 confidence; - __u32 reserved; - struct v4l2_rect face; -}; - -/* - * struct msm_fd_result - Structure contain detected faces result. - * @frame_id: Frame id of requested result. - * @face_cnt: Number of result faces, driver can modify this value (to smaller) - * @face_data: Pointer to array of face data structures. - * Array size should not be smaller then face_cnt. - */ -struct msm_fd_result { - __u32 frame_id; - __u32 face_cnt; - struct msm_fd_face_data *face_data; -}; - -/* MSM FD private ioctl ID */ -#define VIDIOC_MSM_FD_GET_RESULT \ - _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_fd_result) - -/* MSM FD event ID */ -#define MSM_EVENT_FD (V4L2_EVENT_PRIVATE_START) - -/* MSM FD control ID's */ -#define V4L2_CID_FD_SPEED (V4L2_CID_PRIVATE_BASE) -#define V4L2_CID_FD_FACE_ANGLE (V4L2_CID_PRIVATE_BASE + 1) -#define V4L2_CID_FD_MIN_FACE_SIZE (V4L2_CID_PRIVATE_BASE + 2) -#define V4L2_CID_FD_FACE_DIRECTION (V4L2_CID_PRIVATE_BASE + 3) -#define V4L2_CID_FD_DETECTION_THRESHOLD (V4L2_CID_PRIVATE_BASE + 4) -#define V4L2_CID_FD_WORK_MEMORY_SIZE (V4L2_CID_PRIVATE_BASE + 5) -#define V4L2_CID_FD_WORK_MEMORY_FD (V4L2_CID_PRIVATE_BASE + 6) - -#endif - diff --git a/sdm710/original-kernel-headers/media/msm_gemini.h b/sdm710/original-kernel-headers/media/msm_gemini.h deleted file mode 100644 index 0b41b384..00000000 --- a/sdm710/original-kernel-headers/media/msm_gemini.h +++ /dev/null @@ -1,123 +0,0 @@ -#ifndef __UAPI_MSM_GEMINI_H -#define __UAPI_MSM_GEMINI_H - -#include <linux/types.h> -#include <linux/ioctl.h> - -#define MSM_GMN_IOCTL_MAGIC 'g' - -#define MSM_GMN_IOCTL_GET_HW_VERSION \ - _IOW(MSM_GMN_IOCTL_MAGIC, 1, struct msm_gemini_hw_cmd *) - -#define MSM_GMN_IOCTL_RESET \ - _IOW(MSM_GMN_IOCTL_MAGIC, 2, struct msm_gemini_ctrl_cmd *) - -#define MSM_GMN_IOCTL_STOP \ - _IOW(MSM_GMN_IOCTL_MAGIC, 3, struct msm_gemini_hw_cmds *) - -#define MSM_GMN_IOCTL_START \ - _IOW(MSM_GMN_IOCTL_MAGIC, 4, struct msm_gemini_hw_cmds *) - -#define MSM_GMN_IOCTL_INPUT_BUF_ENQUEUE \ - _IOW(MSM_GMN_IOCTL_MAGIC, 5, struct msm_gemini_buf *) - -#define MSM_GMN_IOCTL_INPUT_GET \ - _IOW(MSM_GMN_IOCTL_MAGIC, 6, struct msm_gemini_buf *) - -#define MSM_GMN_IOCTL_INPUT_GET_UNBLOCK \ - _IOW(MSM_GMN_IOCTL_MAGIC, 7, int) - -#define MSM_GMN_IOCTL_OUTPUT_BUF_ENQUEUE \ - _IOW(MSM_GMN_IOCTL_MAGIC, 8, struct msm_gemini_buf *) - -#define MSM_GMN_IOCTL_OUTPUT_GET \ - _IOW(MSM_GMN_IOCTL_MAGIC, 9, struct msm_gemini_buf *) - -#define MSM_GMN_IOCTL_OUTPUT_GET_UNBLOCK \ - _IOW(MSM_GMN_IOCTL_MAGIC, 10, int) - -#define MSM_GMN_IOCTL_EVT_GET \ - _IOW(MSM_GMN_IOCTL_MAGIC, 11, struct msm_gemini_ctrl_cmd *) - -#define MSM_GMN_IOCTL_EVT_GET_UNBLOCK \ - _IOW(MSM_GMN_IOCTL_MAGIC, 12, int) - -#define MSM_GMN_IOCTL_HW_CMD \ - _IOW(MSM_GMN_IOCTL_MAGIC, 13, struct msm_gemini_hw_cmd *) - -#define MSM_GMN_IOCTL_HW_CMDS \ - _IOW(MSM_GMN_IOCTL_MAGIC, 14, struct msm_gemini_hw_cmds *) - -#define MSM_GMN_IOCTL_TEST_DUMP_REGION \ - _IOW(MSM_GMN_IOCTL_MAGIC, 15, unsigned long) - -#define MSM_GMN_IOCTL_SET_MODE \ - _IOW(MSM_GMN_IOCTL_MAGIC, 16, enum msm_gmn_out_mode) - -#define MSM_GEMINI_MODE_REALTIME_ENCODE 0 -#define MSM_GEMINI_MODE_OFFLINE_ENCODE 1 -#define MSM_GEMINI_MODE_REALTIME_ROTATION 2 -#define MSM_GEMINI_MODE_OFFLINE_ROTATION 3 - -enum msm_gmn_out_mode { - MSM_GMN_OUTMODE_FRAGMENTED, - MSM_GMN_OUTMODE_SINGLE -}; - -struct msm_gemini_ctrl_cmd { - uint32_t type; - uint32_t len; - void *value; -}; - -#define MSM_GEMINI_EVT_RESET 0 -#define MSM_GEMINI_EVT_FRAMEDONE 1 -#define MSM_GEMINI_EVT_ERR 2 - -struct msm_gemini_buf { - uint32_t type; - int fd; - - void *vaddr; - - uint32_t y_off; - uint32_t y_len; - uint32_t framedone_len; - - uint32_t cbcr_off; - uint32_t cbcr_len; - - uint32_t num_of_mcu_rows; - uint32_t offset; -}; - -#define MSM_GEMINI_HW_CMD_TYPE_READ 0 -#define MSM_GEMINI_HW_CMD_TYPE_WRITE 1 -#define MSM_GEMINI_HW_CMD_TYPE_WRITE_OR 2 -#define MSM_GEMINI_HW_CMD_TYPE_UWAIT 3 -#define MSM_GEMINI_HW_CMD_TYPE_MWAIT 4 -#define MSM_GEMINI_HW_CMD_TYPE_MDELAY 5 -#define MSM_GEMINI_HW_CMD_TYPE_UDELAY 6 -struct msm_gemini_hw_cmd { - - uint32_t type:4; - - /* n microseconds of timeout for WAIT */ - /* n microseconds of time for DELAY */ - /* repeat n times for READ/WRITE */ - /* max is 0xFFF, 4095 */ - uint32_t n:12; - uint32_t offset:16; - uint32_t mask; - union { - uint32_t data; /* for single READ/WRITE/WAIT, n = 1 */ - uint32_t *pdata; /* for multiple READ/WRITE/WAIT, n > 1 */ - }; -}; - -struct msm_gemini_hw_cmds { - uint32_t m; /* number of elements in the hw_cmd array */ - struct msm_gemini_hw_cmd hw_cmd[1]; -}; - -#endif /* __UAPI_MSM_GEMINI_H */ diff --git a/sdm710/original-kernel-headers/media/msm_gestures.h b/sdm710/original-kernel-headers/media/msm_gestures.h deleted file mode 100644 index 2d6d8f2e..00000000 --- a/sdm710/original-kernel-headers/media/msm_gestures.h +++ /dev/null @@ -1,54 +0,0 @@ -#ifndef __UAPI_MSM_GESTURES_H -#define __UAPI_MSM_GESTURES_H - -#include <linux/types.h> -#include <linux/ioctl.h> -#include <media/msm_camera.h> - -#define MSM_GES_IOCTL_CTRL_COMMAND \ - _IOW('V', BASE_VIDIOC_PRIVATE + 20, struct v4l2_control) - -#define VIDIOC_MSM_GESTURE_EVT \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 21, struct v4l2_event) - -#define MSM_GES_GET_EVT_PAYLOAD \ - _IOW('V', BASE_VIDIOC_PRIVATE + 22, struct msm_ges_evt) - -#define VIDIOC_MSM_GESTURE_CAM_EVT \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 23, int) - -#define MSM_GES_RESP_V4L2 MSM_CAM_RESP_MAX -#define MSM_GES_RESP_MAX (MSM_GES_RESP_V4L2 + 1) - -#define MSM_SVR_RESP_MAX MSM_GES_RESP_MAX - - -#define MSM_V4L2_GES_BASE 100 -#define MSM_V4L2_GES_OPEN (MSM_V4L2_GES_BASE + 0) -#define MSM_V4L2_GES_CLOSE (MSM_V4L2_GES_BASE + 1) -#define MSM_V4L2_GES_CAM_OPEN (MSM_V4L2_GES_BASE + 2) -#define MSM_V4L2_GES_CAM_CLOSE (MSM_V4L2_GES_BASE + 3) - -#define MSM_GES_APP_EVT_MIN (V4L2_EVENT_PRIVATE_START + 0x14) -#define MSM_GES_APP_NOTIFY_EVENT (MSM_GES_APP_EVT_MIN + 0) -#define MSM_GES_APP_NOTIFY_ERROR_EVENT (MSM_GES_APP_EVT_MIN + 1) -#define MSM_GES_APP_EVT_MAX (MSM_GES_APP_EVT_MIN + 2) - -#define MSM_GESTURE_CID_CTRL_CMD V4L2_CID_BRIGHTNESS - -#define MAX_GES_EVENTS 25 - -struct msm_ges_ctrl_cmd { - int type; - void *value; - int len; - int fd; - uint32_t cookie; -}; - -struct msm_ges_evt { - void *evt_data; - int evt_len; -}; - -#endif /*__UAPI_MSM_GESTURES_H*/ diff --git a/sdm710/original-kernel-headers/media/msm_isp.h b/sdm710/original-kernel-headers/media/msm_isp.h deleted file mode 100644 index 90d87c24..00000000 --- a/sdm710/original-kernel-headers/media/msm_isp.h +++ /dev/null @@ -1,344 +0,0 @@ -#ifndef __UAPI_MSM_ISP_H__ -#define __UAPI_MSM_ISP_H__ - -#define BIT(nr) (1UL << (nr)) - -/* ISP message IDs */ -#define MSG_ID_RESET_ACK 0 -#define MSG_ID_START_ACK 1 -#define MSG_ID_STOP_ACK 2 -#define MSG_ID_UPDATE_ACK 3 -#define MSG_ID_OUTPUT_P 4 -#define MSG_ID_OUTPUT_T 5 -#define MSG_ID_OUTPUT_S 6 -#define MSG_ID_OUTPUT_V 7 -#define MSG_ID_SNAPSHOT_DONE 8 -#define MSG_ID_STATS_AEC 9 -#define MSG_ID_STATS_AF 10 -#define MSG_ID_STATS_AWB 11 -#define MSG_ID_STATS_RS 12 -#define MSG_ID_STATS_CS 13 -#define MSG_ID_STATS_IHIST 14 -#define MSG_ID_STATS_SKIN 15 -#define MSG_ID_EPOCH1 16 -#define MSG_ID_EPOCH2 17 -#define MSG_ID_SYNC_TIMER0_DONE 18 -#define MSG_ID_SYNC_TIMER1_DONE 19 -#define MSG_ID_SYNC_TIMER2_DONE 20 -#define MSG_ID_ASYNC_TIMER0_DONE 21 -#define MSG_ID_ASYNC_TIMER1_DONE 22 -#define MSG_ID_ASYNC_TIMER2_DONE 23 -#define MSG_ID_ASYNC_TIMER3_DONE 24 -#define MSG_ID_AE_OVERFLOW 25 -#define MSG_ID_AF_OVERFLOW 26 -#define MSG_ID_AWB_OVERFLOW 27 -#define MSG_ID_RS_OVERFLOW 28 -#define MSG_ID_CS_OVERFLOW 29 -#define MSG_ID_IHIST_OVERFLOW 30 -#define MSG_ID_SKIN_OVERFLOW 31 -#define MSG_ID_AXI_ERROR 32 -#define MSG_ID_CAMIF_OVERFLOW 33 -#define MSG_ID_VIOLATION 34 -#define MSG_ID_CAMIF_ERROR 35 -#define MSG_ID_BUS_OVERFLOW 36 -#define MSG_ID_SOF_ACK 37 -#define MSG_ID_STOP_REC_ACK 38 -#define MSG_ID_STATS_AWB_AEC 39 -#define MSG_ID_OUTPUT_PRIMARY 40 -#define MSG_ID_OUTPUT_SECONDARY 41 -#define MSG_ID_STATS_COMPOSITE 42 -#define MSG_ID_OUTPUT_TERTIARY1 43 -#define MSG_ID_STOP_LS_ACK 44 -#define MSG_ID_OUTPUT_TERTIARY2 45 -#define MSG_ID_STATS_BG 46 -#define MSG_ID_STATS_BF 47 -#define MSG_ID_STATS_BHIST 48 -#define MSG_ID_RDI0_UPDATE_ACK 49 -#define MSG_ID_RDI1_UPDATE_ACK 50 -#define MSG_ID_RDI2_UPDATE_ACK 51 -#define MSG_ID_PIX0_UPDATE_ACK 52 -#define MSG_ID_PREV_STOP_ACK 53 -#define MSG_ID_STATS_BE 54 - - -/* ISP command IDs */ -#define VFE_CMD_DUMMY_0 0 -#define VFE_CMD_SET_CLK 1 -#define VFE_CMD_RESET 2 -#define VFE_CMD_START 3 -#define VFE_CMD_TEST_GEN_START 4 -#define VFE_CMD_OPERATION_CFG 5 -#define VFE_CMD_AXI_OUT_CFG 6 -#define VFE_CMD_CAMIF_CFG 7 -#define VFE_CMD_AXI_INPUT_CFG 8 -#define VFE_CMD_BLACK_LEVEL_CFG 9 -#define VFE_CMD_MESH_ROLL_OFF_CFG 10 -#define VFE_CMD_DEMUX_CFG 11 -#define VFE_CMD_FOV_CFG 12 -#define VFE_CMD_MAIN_SCALER_CFG 13 -#define VFE_CMD_WB_CFG 14 -#define VFE_CMD_COLOR_COR_CFG 15 -#define VFE_CMD_RGB_G_CFG 16 -#define VFE_CMD_LA_CFG 17 -#define VFE_CMD_CHROMA_EN_CFG 18 -#define VFE_CMD_CHROMA_SUP_CFG 19 -#define VFE_CMD_MCE_CFG 20 -#define VFE_CMD_SK_ENHAN_CFG 21 -#define VFE_CMD_ASF_CFG 22 -#define VFE_CMD_S2Y_CFG 23 -#define VFE_CMD_S2CbCr_CFG 24 -#define VFE_CMD_CHROMA_SUBS_CFG 25 -#define VFE_CMD_OUT_CLAMP_CFG 26 -#define VFE_CMD_FRAME_SKIP_CFG 27 -#define VFE_CMD_DUMMY_1 28 -#define VFE_CMD_DUMMY_2 29 -#define VFE_CMD_DUMMY_3 30 -#define VFE_CMD_UPDATE 31 -#define VFE_CMD_BL_LVL_UPDATE 32 -#define VFE_CMD_DEMUX_UPDATE 33 -#define VFE_CMD_FOV_UPDATE 34 -#define VFE_CMD_MAIN_SCALER_UPDATE 35 -#define VFE_CMD_WB_UPDATE 36 -#define VFE_CMD_COLOR_COR_UPDATE 37 -#define VFE_CMD_RGB_G_UPDATE 38 -#define VFE_CMD_LA_UPDATE 39 -#define VFE_CMD_CHROMA_EN_UPDATE 40 -#define VFE_CMD_CHROMA_SUP_UPDATE 41 -#define VFE_CMD_MCE_UPDATE 42 -#define VFE_CMD_SK_ENHAN_UPDATE 43 -#define VFE_CMD_S2CbCr_UPDATE 44 -#define VFE_CMD_S2Y_UPDATE 45 -#define VFE_CMD_ASF_UPDATE 46 -#define VFE_CMD_FRAME_SKIP_UPDATE 47 -#define VFE_CMD_CAMIF_FRAME_UPDATE 48 -#define VFE_CMD_STATS_AF_UPDATE 49 -#define VFE_CMD_STATS_AE_UPDATE 50 -#define VFE_CMD_STATS_AWB_UPDATE 51 -#define VFE_CMD_STATS_RS_UPDATE 52 -#define VFE_CMD_STATS_CS_UPDATE 53 -#define VFE_CMD_STATS_SKIN_UPDATE 54 -#define VFE_CMD_STATS_IHIST_UPDATE 55 -#define VFE_CMD_DUMMY_4 56 -#define VFE_CMD_EPOCH1_ACK 57 -#define VFE_CMD_EPOCH2_ACK 58 -#define VFE_CMD_START_RECORDING 59 -#define VFE_CMD_STOP_RECORDING 60 -#define VFE_CMD_DUMMY_5 61 -#define VFE_CMD_DUMMY_6 62 -#define VFE_CMD_CAPTURE 63 -#define VFE_CMD_DUMMY_7 64 -#define VFE_CMD_STOP 65 -#define VFE_CMD_GET_HW_VERSION 66 -#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67 -#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68 -#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69 -#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70 -#define VFE_CMD_JPEG_OUT_BUF_ENQ 71 -#define VFE_CMD_RAW_OUT_BUF_ENQ 72 -#define VFE_CMD_RAW_IN_BUF_ENQ 73 -#define VFE_CMD_STATS_AF_ENQ 74 -#define VFE_CMD_STATS_AE_ENQ 75 -#define VFE_CMD_STATS_AWB_ENQ 76 -#define VFE_CMD_STATS_RS_ENQ 77 -#define VFE_CMD_STATS_CS_ENQ 78 -#define VFE_CMD_STATS_SKIN_ENQ 79 -#define VFE_CMD_STATS_IHIST_ENQ 80 -#define VFE_CMD_DUMMY_8 81 -#define VFE_CMD_JPEG_ENC_CFG 82 -#define VFE_CMD_DUMMY_9 83 -#define VFE_CMD_STATS_AF_START 84 -#define VFE_CMD_STATS_AF_STOP 85 -#define VFE_CMD_STATS_AE_START 86 -#define VFE_CMD_STATS_AE_STOP 87 -#define VFE_CMD_STATS_AWB_START 88 -#define VFE_CMD_STATS_AWB_STOP 89 -#define VFE_CMD_STATS_RS_START 90 -#define VFE_CMD_STATS_RS_STOP 91 -#define VFE_CMD_STATS_CS_START 92 -#define VFE_CMD_STATS_CS_STOP 93 -#define VFE_CMD_STATS_SKIN_START 94 -#define VFE_CMD_STATS_SKIN_STOP 95 -#define VFE_CMD_STATS_IHIST_START 96 -#define VFE_CMD_STATS_IHIST_STOP 97 -#define VFE_CMD_DUMMY_10 98 -#define VFE_CMD_SYNC_TIMER_SETTING 99 -#define VFE_CMD_ASYNC_TIMER_SETTING 100 -#define VFE_CMD_LIVESHOT 101 -#define VFE_CMD_LA_SETUP 102 -#define VFE_CMD_LINEARIZATION_CFG 103 -#define VFE_CMD_DEMOSAICV3 104 -#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105 -#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106 -#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107 -#define VFE_CMD_DEMOSAICV3_ABF_CFG 108 -#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109 -#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110 -#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111 -#define VFE_CMD_XBAR_CFG 112 -#define VFE_CMD_MODULE_CFG 113 -#define VFE_CMD_ZSL 114 -#define VFE_CMD_LINEARIZATION_UPDATE 115 -#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116 -#define VFE_CMD_CLF_CFG 117 -#define VFE_CMD_CLF_LUMA_UPDATE 118 -#define VFE_CMD_CLF_CHROMA_UPDATE 119 -#define VFE_CMD_PCA_ROLL_OFF_CFG 120 -#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121 -#define VFE_CMD_GET_REG_DUMP 122 -#define VFE_CMD_GET_LINEARIZATON_TABLE 123 -#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124 -#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125 -#define VFE_CMD_GET_RGB_G_TABLE 126 -#define VFE_CMD_GET_LA_TABLE 127 -#define VFE_CMD_DEMOSAICV3_UPDATE 128 -#define VFE_CMD_ACTIVE_REGION_CFG 129 -#define VFE_CMD_COLOR_PROCESSING_CONFIG 130 -#define VFE_CMD_STATS_WB_AEC_CONFIG 131 -#define VFE_CMD_STATS_WB_AEC_UPDATE 132 -#define VFE_CMD_Y_GAMMA_CONFIG 133 -#define VFE_CMD_SCALE_OUTPUT1_CONFIG 134 -#define VFE_CMD_SCALE_OUTPUT2_CONFIG 135 -#define VFE_CMD_CAPTURE_RAW 136 -#define VFE_CMD_STOP_LIVESHOT 137 -#define VFE_CMD_RECONFIG_VFE 138 -#define VFE_CMD_STATS_REQBUF 139 -#define VFE_CMD_STATS_ENQUEUEBUF 140 -#define VFE_CMD_STATS_FLUSH_BUFQ 141 -#define VFE_CMD_STATS_UNREGBUF 142 -#define VFE_CMD_STATS_BG_START 143 -#define VFE_CMD_STATS_BG_STOP 144 -#define VFE_CMD_STATS_BF_START 145 -#define VFE_CMD_STATS_BF_STOP 146 -#define VFE_CMD_STATS_BHIST_START 147 -#define VFE_CMD_STATS_BHIST_STOP 148 -#define VFE_CMD_RESET_2 149 -#define VFE_CMD_FOV_ENC_CFG 150 -#define VFE_CMD_FOV_VIEW_CFG 151 -#define VFE_CMD_FOV_ENC_UPDATE 152 -#define VFE_CMD_FOV_VIEW_UPDATE 153 -#define VFE_CMD_SCALER_ENC_CFG 154 -#define VFE_CMD_SCALER_VIEW_CFG 155 -#define VFE_CMD_SCALER_ENC_UPDATE 156 -#define VFE_CMD_SCALER_VIEW_UPDATE 157 -#define VFE_CMD_COLORXFORM_ENC_CFG 158 -#define VFE_CMD_COLORXFORM_VIEW_CFG 159 -#define VFE_CMD_COLORXFORM_ENC_UPDATE 160 -#define VFE_CMD_COLORXFORM_VIEW_UPDATE 161 -#define VFE_CMD_TEST_GEN_CFG 162 -#define VFE_CMD_STATS_BE_START 163 -#define VFE_CMD_STATS_BE_STOP 164 -struct msm_isp_cmd { - int32_t id; - uint16_t length; - void *value; -}; - -#define VPE_CMD_DUMMY_0 0 -#define VPE_CMD_INIT 1 -#define VPE_CMD_DEINIT 2 -#define VPE_CMD_ENABLE 3 -#define VPE_CMD_DISABLE 4 -#define VPE_CMD_RESET 5 -#define VPE_CMD_FLUSH 6 -#define VPE_CMD_OPERATION_MODE_CFG 7 -#define VPE_CMD_INPUT_PLANE_CFG 8 -#define VPE_CMD_OUTPUT_PLANE_CFG 9 -#define VPE_CMD_INPUT_PLANE_UPDATE 10 -#define VPE_CMD_SCALE_CFG_TYPE 11 -#define VPE_CMD_ZOOM 13 -#define VPE_CMD_MAX 14 - -#define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */ -#define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */ -#define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */ - -#define MCTL_CMD_DUMMY_0 0 /* not used */ -#define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */ -#define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */ -#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */ - -/* event typese sending to MCTL PP module */ -#define MCTL_PP_EVENT_NOTUSED 0 -#define MCTL_PP_EVENT_CMD_ACK 1 - -#define VPE_OPERATION_MODE_CFG_LEN 4 -#define VPE_INPUT_PLANE_CFG_LEN 24 -#define VPE_OUTPUT_PLANE_CFG_LEN 20 -#define VPE_INPUT_PLANE_UPDATE_LEN 12 -#define VPE_SCALER_CONFIG_LEN 260 -#define VPE_DIS_OFFSET_CFG_LEN 12 - - -#define CAPTURE_WIDTH 1280 -#define IMEM_Y_SIZE (CAPTURE_WIDTH*16) -#define IMEM_CBCR_SIZE (CAPTURE_WIDTH*8) - -#define IMEM_Y_PING_OFFSET 0x2E000000 -#define IMEM_CBCR_PING_OFFSET (IMEM_Y_PING_OFFSET + IMEM_Y_SIZE) - -#define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE) -#define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE) - - -struct msm_vpe_op_mode_cfg { - uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN]; -}; - -struct msm_vpe_input_plane_cfg { - uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN]; -}; - -struct msm_vpe_output_plane_cfg { - uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN]; -}; - -struct msm_vpe_input_plane_update_cfg { - uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN]; -}; - -struct msm_vpe_scaler_cfg { - uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN]; -}; - -struct msm_vpe_flush_frame_buffer { - uint32_t src_buf_handle; - uint32_t dest_buf_handle; - int path; -}; - -struct msm_mctl_pp_frame_buffer { - uint32_t buf_handle; - int path; -}; -struct msm_mctl_pp_divert_pp { - int path; - int enable; -}; -struct msm_vpe_clock_rate { - uint32_t rate; -}; - -#define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0) -#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1<<1) - -#define VFE_OUTPUTS_MAIN_AND_PREVIEW BIT(0) -#define VFE_OUTPUTS_MAIN_AND_VIDEO BIT(1) -#define VFE_OUTPUTS_MAIN_AND_THUMB BIT(2) -#define VFE_OUTPUTS_THUMB_AND_MAIN BIT(3) -#define VFE_OUTPUTS_PREVIEW_AND_VIDEO BIT(4) -#define VFE_OUTPUTS_VIDEO_AND_PREVIEW BIT(5) -#define VFE_OUTPUTS_PREVIEW BIT(6) -#define VFE_OUTPUTS_VIDEO BIT(7) -#define VFE_OUTPUTS_RAW BIT(8) -#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9) -#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10) -#define VFE_OUTPUTS_RDI0 BIT(11) -#define VFE_OUTPUTS_RDI1 BIT(12) - -struct msm_frame_info { - uint32_t inst_handle; - uint32_t path; -}; - -#endif /*__UAPI_MSM_ISP_H__*/ - diff --git a/sdm710/original-kernel-headers/media/msm_jpeg.h b/sdm710/original-kernel-headers/media/msm_jpeg.h deleted file mode 100644 index 897a1808..00000000 --- a/sdm710/original-kernel-headers/media/msm_jpeg.h +++ /dev/null @@ -1,125 +0,0 @@ -#ifndef __UAPI_LINUX_MSM_JPEG_H -#define __UAPI_LINUX_MSM_JPEG_H - -#include <linux/types.h> -#include <linux/ioctl.h> - -#define OUTPUT_H2V1 0 -#define OUTPUT_H2V2 1 -#define OUTPUT_BYTE 6 - -#define MSM_JPEG_IOCTL_MAGIC 'g' - -#define MSM_JPEG_IOCTL_GET_HW_VERSION \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 1, struct msm_jpeg_hw_cmd) - -#define MSM_JPEG_IOCTL_RESET \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 2, struct msm_jpeg_ctrl_cmd) - -#define MSM_JPEG_IOCTL_STOP \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 3, struct msm_jpeg_hw_cmds) - -#define MSM_JPEG_IOCTL_START \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 4, struct msm_jpeg_hw_cmds) - -#define MSM_JPEG_IOCTL_INPUT_BUF_ENQUEUE \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 5, struct msm_jpeg_buf) - -#define MSM_JPEG_IOCTL_INPUT_GET \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 6, struct msm_jpeg_buf) - -#define MSM_JPEG_IOCTL_INPUT_GET_UNBLOCK \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 7, int) - -#define MSM_JPEG_IOCTL_OUTPUT_BUF_ENQUEUE \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 8, struct msm_jpeg_buf) - -#define MSM_JPEG_IOCTL_OUTPUT_GET \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 9, struct msm_jpeg_buf) - -#define MSM_JPEG_IOCTL_OUTPUT_GET_UNBLOCK \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 10, int) - -#define MSM_JPEG_IOCTL_EVT_GET \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 11, struct msm_jpeg_ctrl_cmd) - -#define MSM_JPEG_IOCTL_EVT_GET_UNBLOCK \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 12, int) - -#define MSM_JPEG_IOCTL_HW_CMD \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 13, struct msm_jpeg_hw_cmd) - -#define MSM_JPEG_IOCTL_HW_CMDS \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 14, struct msm_jpeg_hw_cmds) - -#define MSM_JPEG_IOCTL_TEST_DUMP_REGION \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 15, unsigned long) - -#define MSM_JPEG_IOCTL_SET_CLK_RATE \ - _IOW(MSM_JPEG_IOCTL_MAGIC, 16, unsigned int) - -#define MSM_JPEG_MODE_REALTIME_ENCODE 0 -#define MSM_JPEG_MODE_OFFLINE_ENCODE 1 -#define MSM_JPEG_MODE_REALTIME_ROTATION 2 -#define MSM_JPEG_MODE_OFFLINE_ROTATION 3 - -struct msm_jpeg_ctrl_cmd { - uint32_t type; - uint32_t len; - void *value; -}; - -#define MSM_JPEG_EVT_RESET 0 -#define MSM_JPEG_EVT_SESSION_DONE 1 -#define MSM_JPEG_EVT_ERR 2 - -struct msm_jpeg_buf { - uint32_t type; - int fd; - - void *vaddr; - - uint32_t y_off; - uint32_t y_len; - uint32_t framedone_len; - - uint32_t cbcr_off; - uint32_t cbcr_len; - - uint32_t num_of_mcu_rows; - uint32_t offset; - uint32_t pln2_off; - uint32_t pln2_len; -}; - -#define MSM_JPEG_HW_CMD_TYPE_READ 0 -#define MSM_JPEG_HW_CMD_TYPE_WRITE 1 -#define MSM_JPEG_HW_CMD_TYPE_WRITE_OR 2 -#define MSM_JPEG_HW_CMD_TYPE_UWAIT 3 -#define MSM_JPEG_HW_CMD_TYPE_MWAIT 4 -#define MSM_JPEG_HW_CMD_TYPE_MDELAY 5 -#define MSM_JPEG_HW_CMD_TYPE_UDELAY 6 -struct msm_jpeg_hw_cmd { - - uint32_t type:4; - - /* n microseconds of timeout for WAIT */ - /* n microseconds of time for DELAY */ - /* repeat n times for READ/WRITE */ - /* max is 0xFFF, 4095 */ - uint32_t n:12; - uint32_t offset:16; - uint32_t mask; - union { - uint32_t data; /* for single READ/WRITE/WAIT, n = 1 */ - uint32_t *pdata; /* for multiple READ/WRITE/WAIT, n > 1 */ - }; -}; - -struct msm_jpeg_hw_cmds { - uint32_t m; /* number of elements in the hw_cmd array */ - struct msm_jpeg_hw_cmd hw_cmd[1]; -}; - -#endif - diff --git a/sdm710/original-kernel-headers/media/msm_jpeg_dma.h b/sdm710/original-kernel-headers/media/msm_jpeg_dma.h deleted file mode 100644 index a3eab9fb..00000000 --- a/sdm710/original-kernel-headers/media/msm_jpeg_dma.h +++ /dev/null @@ -1,28 +0,0 @@ -/* Copyright (c) 2015-2016, 2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __UAPI_MSM_JPEG_DMA__ -#define __UAPI_MSM_JPEG_DMA__ - -#include <linux/videodev2.h> - -/* msm jpeg dma control ID's */ -#define V4L2_CID_JPEG_DMA_SPEED (V4L2_CID_PRIVATE_BASE) -#define V4L2_CID_JPEG_DMA_MAX_DOWN_SCALE (V4L2_CID_PRIVATE_BASE + 1) - -/* msm_jpeg_dma_buf */ -struct msm_jpeg_dma_buff { - int32_t fd; - uint32_t offset; -}; - -#endif /* __UAPI_MSM_JPEG_DMA__ */ diff --git a/sdm710/original-kernel-headers/media/msm_media_info.h b/sdm710/original-kernel-headers/media/msm_media_info.h deleted file mode 100644 index 0f4d7f75..00000000 --- a/sdm710/original-kernel-headers/media/msm_media_info.h +++ /dev/null @@ -1,1398 +0,0 @@ -#ifndef __MEDIA_INFO_H__ -#define __MEDIA_INFO_H__ - -#ifndef MSM_MEDIA_ALIGN -#define MSM_MEDIA_ALIGN(__sz, __align) (((__align) & ((__align) - 1)) ?\ - ((((__sz) + (__align) - 1) / (__align)) * (__align)) :\ - (((__sz) + (__align) - 1) & (~((__align) - 1)))) -#endif - -#ifndef MSM_MEDIA_ROUNDUP -#define MSM_MEDIA_ROUNDUP(__sz, __r) (((__sz) + ((__r) - 1)) / (__r)) -#endif - -#ifndef MSM_MEDIA_MAX -#define MSM_MEDIA_MAX(__a, __b) ((__a) > (__b)?(__a):(__b)) -#endif - -enum color_fmts { - /* Venus NV12: - * YUV 4:2:0 image with a plane of 8 bit Y samples followed - * by an interleaved U/V plane containing 8 bit 2x2 subsampled - * colour difference samples. - * - * <-------- Y/UV_Stride --------> - * <------- Width -------> - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * U V U V U V U V U V U V . . . . ^ - * U V U V U V U V U V U V . . . . | - * U V U V U V U V U V U V . . . . | - * U V U V U V U V U V U V . . . . UV_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . --> Buffer size alignment - * - * Y_Stride : Width aligned to 128 - * UV_Stride : Width aligned to 128 - * Y_Scanlines: Height aligned to 32 - * UV_Scanlines: Height/2 aligned to 16 - * Extradata: Arbitrary (software-imposed) padding - * Total size = align((Y_Stride * Y_Scanlines - * + UV_Stride * UV_Scanlines - * + max(Extradata, Y_Stride * 8), 4096) - */ - COLOR_FMT_NV12, - - /* Venus NV21: - * YUV 4:2:0 image with a plane of 8 bit Y samples followed - * by an interleaved V/U plane containing 8 bit 2x2 subsampled - * colour difference samples. - * - * <-------- Y/UV_Stride --------> - * <------- Width -------> - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * V U V U V U V U V U V U . . . . ^ - * V U V U V U V U V U V U . . . . | - * V U V U V U V U V U V U . . . . | - * V U V U V U V U V U V U . . . . UV_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . --> Padding & Buffer size alignment - * - * Y_Stride : Width aligned to 128 - * UV_Stride : Width aligned to 128 - * Y_Scanlines: Height aligned to 32 - * UV_Scanlines: Height/2 aligned to 16 - * Extradata: Arbitrary (software-imposed) padding - * Total size = align((Y_Stride * Y_Scanlines - * + UV_Stride * UV_Scanlines - * + max(Extradata, Y_Stride * 8), 4096) - */ - COLOR_FMT_NV21, - /* Venus NV12_MVTB: - * Two YUV 4:2:0 images/views one after the other - * in a top-bottom layout, same as NV12 - * with a plane of 8 bit Y samples followed - * by an interleaved U/V plane containing 8 bit 2x2 subsampled - * colour difference samples. - * - * - * <-------- Y/UV_Stride --------> - * <------- Width -------> - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^ - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | | - * . . . . . . . . . . . . . . . . | View_1 - * . . . . . . . . . . . . . . . . | | - * . . . . . . . . . . . . . . . . | | - * . . . . . . . . . . . . . . . . V | - * U V U V U V U V U V U V . . . . ^ | - * U V U V U V U V U V U V . . . . | | - * U V U V U V U V U V U V . . . . | | - * U V U V U V U V U V U V . . . . UV_Scanlines | - * . . . . . . . . . . . . . . . . | | - * . . . . . . . . . . . . . . . . V V - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^ - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | | - * . . . . . . . . . . . . . . . . | View_2 - * . . . . . . . . . . . . . . . . | | - * . . . . . . . . . . . . . . . . | | - * . . . . . . . . . . . . . . . . V | - * U V U V U V U V U V U V . . . . ^ | - * U V U V U V U V U V U V . . . . | | - * U V U V U V U V U V U V . . . . | | - * U V U V U V U V U V U V . . . . UV_Scanlines | - * . . . . . . . . . . . . . . . . | | - * . . . . . . . . . . . . . . . . V V - * . . . . . . . . . . . . . . . . --> Buffer size alignment - * - * Y_Stride : Width aligned to 128 - * UV_Stride : Width aligned to 128 - * Y_Scanlines: Height aligned to 32 - * UV_Scanlines: Height/2 aligned to 16 - * View_1 begin at: 0 (zero) - * View_2 begin at: Y_Stride * Y_Scanlines + UV_Stride * UV_Scanlines - * Extradata: Arbitrary (software-imposed) padding - * Total size = align((2*(Y_Stride * Y_Scanlines) - * + 2*(UV_Stride * UV_Scanlines) + Extradata), 4096) - */ - COLOR_FMT_NV12_MVTB, - /* - * The buffer can be of 2 types: - * (1) Venus NV12 UBWC Progressive - * (2) Venus NV12 UBWC Interlaced - * - * (1) Venus NV12 UBWC Progressive Buffer Format: - * Compressed Macro-tile format for NV12. - * Contains 4 planes in the following order - - * (A) Y_Meta_Plane - * (B) Y_UBWC_Plane - * (C) UV_Meta_Plane - * (D) UV_UBWC_Plane - * - * Y_Meta_Plane consists of meta information to decode compressed - * tile data in Y_UBWC_Plane. - * Y_UBWC_Plane consists of Y data in compressed macro-tile format. - * UBWC decoder block will use the Y_Meta_Plane data together with - * Y_UBWC_Plane data to produce loss-less uncompressed 8 bit Y samples. - * - * UV_Meta_Plane consists of meta information to decode compressed - * tile data in UV_UBWC_Plane. - * UV_UBWC_Plane consists of UV data in compressed macro-tile format. - * UBWC decoder block will use UV_Meta_Plane data together with - * UV_UBWC_Plane data to produce loss-less uncompressed 8 bit 2x2 - * subsampled color difference samples. - * - * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable - * and randomly accessible. There is no dependency between tiles. - * - * <----- Y_Meta_Stride ----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Height | - * M M M M M M M M M M M M . . | Meta_Y_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <--Compressed tile Y Stride---> - * <------- Width -------> - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * <----- UV_Meta_Stride ----> - * M M M M M M M M M M M M . . ^ - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . M_UV_Scanlines - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * <--Compressed tile UV Stride---> - * U* V* U* V* U* V* U* V* . . . . ^ - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . UV_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * - * Y_Stride = align(Width, 128) - * UV_Stride = align(Width, 128) - * Y_Scanlines = align(Height, 32) - * UV_Scanlines = align(Height/2, 16) - * Y_UBWC_Plane_size = align(Y_Stride * Y_Scanlines, 4096) - * UV_UBWC_Plane_size = align(UV_Stride * UV_Scanlines, 4096) - * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) - * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16) - * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096) - * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) - * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16) - * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align( Y_UBWC_Plane_size + UV_UBWC_Plane_size + - * Y_Meta_Plane_size + UV_Meta_Plane_size - * + max(Extradata, Y_Stride * 48), 4096) - * - * - * (2) Venus NV12 UBWC Interlaced Buffer Format: - * Compressed Macro-tile format for NV12 interlaced. - * Contains 8 planes in the following order - - * (A) Y_Meta_Top_Field_Plane - * (B) Y_UBWC_Top_Field_Plane - * (C) UV_Meta_Top_Field_Plane - * (D) UV_UBWC_Top_Field_Plane - * (E) Y_Meta_Bottom_Field_Plane - * (F) Y_UBWC_Bottom_Field_Plane - * (G) UV_Meta_Bottom_Field_Plane - * (H) UV_UBWC_Bottom_Field_Plane - * Y_Meta_Top_Field_Plane consists of meta information to decode - * compressed tile data for Y_UBWC_Top_Field_Plane. - * Y_UBWC_Top_Field_Plane consists of Y data in compressed macro-tile - * format for top field of an interlaced frame. - * UBWC decoder block will use the Y_Meta_Top_Field_Plane data together - * with Y_UBWC_Top_Field_Plane data to produce loss-less uncompressed - * 8 bit Y samples for top field of an interlaced frame. - * - * UV_Meta_Top_Field_Plane consists of meta information to decode - * compressed tile data in UV_UBWC_Top_Field_Plane. - * UV_UBWC_Top_Field_Plane consists of UV data in compressed macro-tile - * format for top field of an interlaced frame. - * UBWC decoder block will use UV_Meta_Top_Field_Plane data together - * with UV_UBWC_Top_Field_Plane data to produce loss-less uncompressed - * 8 bit subsampled color difference samples for top field of an - * interlaced frame. - * - * Each tile in Y_UBWC_Top_Field_Plane/UV_UBWC_Top_Field_Plane is - * independently decodable and randomly accessible. There is no - * dependency between tiles. - * - * Y_Meta_Bottom_Field_Plane consists of meta information to decode - * compressed tile data for Y_UBWC_Bottom_Field_Plane. - * Y_UBWC_Bottom_Field_Plane consists of Y data in compressed macro-tile - * format for bottom field of an interlaced frame. - * UBWC decoder block will use the Y_Meta_Bottom_Field_Plane data - * together with Y_UBWC_Bottom_Field_Plane data to produce loss-less - * uncompressed 8 bit Y samples for bottom field of an interlaced frame. - * - * UV_Meta_Bottom_Field_Plane consists of meta information to decode - * compressed tile data in UV_UBWC_Bottom_Field_Plane. - * UV_UBWC_Bottom_Field_Plane consists of UV data in compressed - * macro-tile format for bottom field of an interlaced frame. - * UBWC decoder block will use UV_Meta_Bottom_Field_Plane data together - * with UV_UBWC_Bottom_Field_Plane data to produce loss-less - * uncompressed 8 bit subsampled color difference samples for bottom - * field of an interlaced frame. - * - * Each tile in Y_UBWC_Bottom_Field_Plane/UV_UBWC_Bottom_Field_Plane is - * independently decodable and randomly accessible. There is no - * dependency between tiles. - * - * <-----Y_TF_Meta_Stride----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Half_height | - * M M M M M M M M M M M M . . | Meta_Y_TF_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <-Compressed tile Y_TF Stride-> - * <------- Width -------> - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Half_height | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_TF_Scanlines - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * <----UV_TF_Meta_Stride----> - * M M M M M M M M M M M M . . ^ - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . M_UV_TF_Scanlines - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * <-Compressed tile UV_TF Stride-> - * U* V* U* V* U* V* U* V* . . . . ^ - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . UV_TF_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * <-----Y_BF_Meta_Stride----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Half_height | - * M M M M M M M M M M M M . . | Meta_Y_BF_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <-Compressed tile Y_BF Stride-> - * <------- Width -------> - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Half_height | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_BF_Scanlines - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * <----UV_BF_Meta_Stride----> - * M M M M M M M M M M M M . . ^ - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . M_UV_BF_Scanlines - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * <-Compressed tile UV_BF Stride-> - * U* V* U* V* U* V* U* V* . . . . ^ - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . UV_BF_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * - * Half_height = (Height+1)>>1 - * Y_TF_Stride = align(Width, 128) - * UV_TF_Stride = align(Width, 128) - * Y_TF_Scanlines = align(Half_height, 32) - * UV_TF_Scanlines = align((Half_height+1)/2, 32) - * Y_UBWC_TF_Plane_size = align(Y_TF_Stride * Y_TF_Scanlines, 4096) - * UV_UBWC_TF_Plane_size = align(UV_TF_Stride * UV_TF_Scanlines, 4096) - * Y_TF_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) - * Y_TF_Meta_Scanlines = align(roundup(Half_height, Y_TileHeight), 16) - * Y_TF_Meta_Plane_size = - * align(Y_TF_Meta_Stride * Y_TF_Meta_Scanlines, 4096) - * UV_TF_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) - * UV_TF_Meta_Scanlines = align(roundup(Half_height, UV_TileHeight), 16) - * UV_TF_Meta_Plane_size = - * align(UV_TF_Meta_Stride * UV_TF_Meta_Scanlines, 4096) - * Y_BF_Stride = align(Width, 128) - * UV_BF_Stride = align(Width, 128) - * Y_BF_Scanlines = align(Half_height, 32) - * UV_BF_Scanlines = align((Half_height+1)/2, 32) - * Y_UBWC_BF_Plane_size = align(Y_BF_Stride * Y_BF_Scanlines, 4096) - * UV_UBWC_BF_Plane_size = align(UV_BF_Stride * UV_BF_Scanlines, 4096) - * Y_BF_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) - * Y_BF_Meta_Scanlines = align(roundup(Half_height, Y_TileHeight), 16) - * Y_BF_Meta_Plane_size = - * align(Y_BF_Meta_Stride * Y_BF_Meta_Scanlines, 4096) - * UV_BF_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) - * UV_BF_Meta_Scanlines = align(roundup(Half_height, UV_TileHeight), 16) - * UV_BF_Meta_Plane_size = - * align(UV_BF_Meta_Stride * UV_BF_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align( Y_UBWC_TF_Plane_size + UV_UBWC_TF_Plane_size + - * Y_TF_Meta_Plane_size + UV_TF_Meta_Plane_size + - * Y_UBWC_BF_Plane_size + UV_UBWC_BF_Plane_size + - * Y_BF_Meta_Plane_size + UV_BF_Meta_Plane_size + - * + max(Extradata, Y_TF_Stride * 48), 4096) - */ - COLOR_FMT_NV12_UBWC, - /* Venus NV12 10-bit UBWC: - * Compressed Macro-tile format for NV12. - * Contains 4 planes in the following order - - * (A) Y_Meta_Plane - * (B) Y_UBWC_Plane - * (C) UV_Meta_Plane - * (D) UV_UBWC_Plane - * - * Y_Meta_Plane consists of meta information to decode compressed - * tile data in Y_UBWC_Plane. - * Y_UBWC_Plane consists of Y data in compressed macro-tile format. - * UBWC decoder block will use the Y_Meta_Plane data together with - * Y_UBWC_Plane data to produce loss-less uncompressed 10 bit Y samples. - * - * UV_Meta_Plane consists of meta information to decode compressed - * tile data in UV_UBWC_Plane. - * UV_UBWC_Plane consists of UV data in compressed macro-tile format. - * UBWC decoder block will use UV_Meta_Plane data together with - * UV_UBWC_Plane data to produce loss-less uncompressed 10 bit 2x2 - * subsampled color difference samples. - * - * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable - * and randomly accessible. There is no dependency between tiles. - * - * <----- Y_Meta_Stride -----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Height | - * M M M M M M M M M M M M . . | Meta_Y_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <--Compressed tile Y Stride---> - * <------- Width -------> - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * <----- UV_Meta_Stride ----> - * M M M M M M M M M M M M . . ^ - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . M_UV_Scanlines - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * <--Compressed tile UV Stride---> - * U* V* U* V* U* V* U* V* . . . . ^ - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . UV_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * - * - * Y_Stride = align(Width * 4/3, 128) - * UV_Stride = align(Width * 4/3, 128) - * Y_Scanlines = align(Height, 32) - * UV_Scanlines = align(Height/2, 16) - * Y_UBWC_Plane_Size = align(Y_Stride * Y_Scanlines, 4096) - * UV_UBWC_Plane_Size = align(UV_Stride * UV_Scanlines, 4096) - * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) - * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16) - * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096) - * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) - * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16) - * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align(Y_UBWC_Plane_size + UV_UBWC_Plane_size + - * Y_Meta_Plane_size + UV_Meta_Plane_size - * + max(Extradata, Y_Stride * 48), 4096) - */ - COLOR_FMT_NV12_BPP10_UBWC, - /* Venus RGBA8888 format: - * Contains 1 plane in the following order - - * (A) RGBA plane - * - * <-------- RGB_Stride --------> - * <------- Width -------> - * R R R R R R R R R R R R . . . . ^ ^ - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . Height | - * R R R R R R R R R R R R . . . . | RGB_Scanlines - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * - * RGB_Stride = align(Width * 4, 128) - * RGB_Scanlines = align(Height, 32) - * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align(RGB_Plane_size + Extradata, 4096) - */ - COLOR_FMT_RGBA8888, - /* Venus RGBA8888 UBWC format: - * Contains 2 planes in the following order - - * (A) Meta plane - * (B) RGBA plane - * - * <--- RGB_Meta_Stride ----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Height | - * M M M M M M M M M M M M . . | Meta_RGB_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <-------- RGB_Stride --------> - * <------- Width -------> - * R R R R R R R R R R R R . . . . ^ ^ - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . Height | - * R R R R R R R R R R R R . . . . | RGB_Scanlines - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * - * RGB_Stride = align(Width * 4, 128) - * RGB_Scanlines = align(Height, 32) - * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096) - * RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64) - * RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16) - * RGB_Meta_Plane_size = align(RGB_Meta_Stride * - * RGB_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align(RGB_Meta_Plane_size + RGB_Plane_size + - * Extradata, 4096) - */ - COLOR_FMT_RGBA8888_UBWC, - /* Venus RGBA1010102 UBWC format: - * Contains 2 planes in the following order - - * (A) Meta plane - * (B) RGBA plane - * - * <--- RGB_Meta_Stride ----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Height | - * M M M M M M M M M M M M . . | Meta_RGB_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <-------- RGB_Stride --------> - * <------- Width -------> - * R R R R R R R R R R R R . . . . ^ ^ - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . Height | - * R R R R R R R R R R R R . . . . | RGB_Scanlines - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * - * RGB_Stride = align(Width * 4, 256) - * RGB_Scanlines = align(Height, 16) - * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096) - * RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64) - * RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16) - * RGB_Meta_Plane_size = align(RGB_Meta_Stride * - * RGB_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align(RGB_Meta_Plane_size + RGB_Plane_size + - * Extradata, 4096) - */ - COLOR_FMT_RGBA1010102_UBWC, - /* Venus RGB565 UBWC format: - * Contains 2 planes in the following order - - * (A) Meta plane - * (B) RGB plane - * - * <--- RGB_Meta_Stride ----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Height | - * M M M M M M M M M M M M . . | Meta_RGB_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <-------- RGB_Stride --------> - * <------- Width -------> - * R R R R R R R R R R R R . . . . ^ ^ - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . Height | - * R R R R R R R R R R R R . . . . | RGB_Scanlines - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . | | - * R R R R R R R R R R R R . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * - * RGB_Stride = align(Width * 2, 128) - * RGB_Scanlines = align(Height, 16) - * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096) - * RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64) - * RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16) - * RGB_Meta_Plane_size = align(RGB_Meta_Stride * - * RGB_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align(RGB_Meta_Plane_size + RGB_Plane_size + - * Extradata, 4096) - */ - COLOR_FMT_RGB565_UBWC, - /* P010 UBWC: - * Compressed Macro-tile format for NV12. - * Contains 4 planes in the following order - - * (A) Y_Meta_Plane - * (B) Y_UBWC_Plane - * (C) UV_Meta_Plane - * (D) UV_UBWC_Plane - * - * Y_Meta_Plane consists of meta information to decode compressed - * tile data in Y_UBWC_Plane. - * Y_UBWC_Plane consists of Y data in compressed macro-tile format. - * UBWC decoder block will use the Y_Meta_Plane data together with - * Y_UBWC_Plane data to produce loss-less uncompressed 10 bit Y samples. - * - * UV_Meta_Plane consists of meta information to decode compressed - * tile data in UV_UBWC_Plane. - * UV_UBWC_Plane consists of UV data in compressed macro-tile format. - * UBWC decoder block will use UV_Meta_Plane data together with - * UV_UBWC_Plane data to produce loss-less uncompressed 10 bit 2x2 - * subsampled color difference samples. - * - * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable - * and randomly accessible. There is no dependency between tiles. - * - * <----- Y_Meta_Stride -----> - * <-------- Width ------> - * M M M M M M M M M M M M . . ^ ^ - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . Height | - * M M M M M M M M M M M M . . | Meta_Y_Scanlines - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . | | - * M M M M M M M M M M M M . . V | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . V - * <--Compressed tile Y Stride---> - * <------- Width -------> - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | - * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * . . . . . . . . . . . . . . . . V - * <----- UV_Meta_Stride ----> - * M M M M M M M M M M M M . . ^ - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . | - * M M M M M M M M M M M M . . M_UV_Scanlines - * . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * <--Compressed tile UV Stride---> - * U* V* U* V* U* V* U* V* . . . . ^ - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . | - * U* V* U* V* U* V* U* V* . . . . UV_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k - * - * - * Y_Stride = align(Width * 2, 256) - * UV_Stride = align(Width * 2, 256) - * Y_Scanlines = align(Height, 16) - * UV_Scanlines = align(Height/2, 16) - * Y_UBWC_Plane_Size = align(Y_Stride * Y_Scanlines, 4096) - * UV_UBWC_Plane_Size = align(UV_Stride * UV_Scanlines, 4096) - * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) - * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16) - * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096) - * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) - * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16) - * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096) - * Extradata = 8k - * - * Total size = align(Y_UBWC_Plane_size + UV_UBWC_Plane_size + - * Y_Meta_Plane_size + UV_Meta_Plane_size - * + max(Extradata, Y_Stride * 48), 4096) - */ - COLOR_FMT_P010_UBWC, - /* Venus P010: - * YUV 4:2:0 image with a plane of 10 bit Y samples followed - * by an interleaved U/V plane containing 10 bit 2x2 subsampled - * colour difference samples. - * - * <-------- Y/UV_Stride --------> - * <------- Width -------> - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | - * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * U V U V U V U V U V U V . . . . ^ - * U V U V U V U V U V U V . . . . | - * U V U V U V U V U V U V . . . . | - * U V U V U V U V U V U V . . . . UV_Scanlines - * . . . . . . . . . . . . . . . . | - * . . . . . . . . . . . . . . . . V - * . . . . . . . . . . . . . . . . --> Buffer size alignment - * - * Y_Stride : Width * 2 aligned to 128 - * UV_Stride : Width * 2 aligned to 128 - * Y_Scanlines: Height aligned to 32 - * UV_Scanlines: Height/2 aligned to 16 - * Extradata: Arbitrary (software-imposed) padding - * Total size = align((Y_Stride * Y_Scanlines - * + UV_Stride * UV_Scanlines - * + max(Extradata, Y_Stride * 8), 4096) - */ - COLOR_FMT_P010, -}; - -#define COLOR_FMT_RGBA1010102_UBWC COLOR_FMT_RGBA1010102_UBWC -#define COLOR_FMT_RGB565_UBWC COLOR_FMT_RGB565_UBWC -#define COLOR_FMT_P010_UBWC COLOR_FMT_P010_UBWC -#define COLOR_FMT_P010 COLOR_FMT_P010 - -static __inline__ unsigned int VENUS_EXTRADATA_SIZE(int width, int height) -{ - (void)height; - (void)width; - - /* - * In the future, calculate the size based on the w/h but just - * hardcode it for now since 16K satisfies all current usecases. - */ - return 16 * 1024; -} - -/* - * Function arguments: - * @color_fmt - * @width - * Progressive: width - * Interlaced: width - */ -static __inline__ unsigned int VENUS_Y_STRIDE(int color_fmt, int width) -{ - unsigned int alignment, stride = 0; - - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - case COLOR_FMT_NV12_MVTB: - case COLOR_FMT_NV12_UBWC: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width, alignment); - break; - case COLOR_FMT_NV12_BPP10_UBWC: - alignment = 256; - stride = MSM_MEDIA_ALIGN(width, 192); - stride = MSM_MEDIA_ALIGN(stride * 4/3, alignment); - break; - case COLOR_FMT_P010_UBWC: - alignment = 256; - stride = MSM_MEDIA_ALIGN(width * 2, alignment); - break; - case COLOR_FMT_P010: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width*2, alignment); - break; - default: - break; - } -invalid_input: - return stride; -} - -/* - * Function arguments: - * @color_fmt - * @width - * Progressive: width - * Interlaced: width - */ -static __inline__ unsigned int VENUS_UV_STRIDE(int color_fmt, int width) -{ - unsigned int alignment, stride = 0; - - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - case COLOR_FMT_NV12_MVTB: - case COLOR_FMT_NV12_UBWC: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width, alignment); - break; - case COLOR_FMT_NV12_BPP10_UBWC: - alignment = 256; - stride = MSM_MEDIA_ALIGN(width, 192); - stride = MSM_MEDIA_ALIGN(stride * 4/3, alignment); - break; - case COLOR_FMT_P010_UBWC: - alignment = 256; - stride = MSM_MEDIA_ALIGN(width * 2, alignment); - break; - case COLOR_FMT_P010: - alignment = 128; - stride = MSM_MEDIA_ALIGN(width*2, alignment); - break; - default: - break; - } -invalid_input: - return stride; -} - -/* - * Function arguments: - * @color_fmt - * @height - * Progressive: height - * Interlaced: (height+1)>>1 - */ -static __inline__ unsigned int VENUS_Y_SCANLINES(int color_fmt, int height) -{ - unsigned int alignment, sclines = 0; - - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - case COLOR_FMT_NV12_MVTB: - case COLOR_FMT_NV12_UBWC: - case COLOR_FMT_P010: - alignment = 32; - break; - case COLOR_FMT_NV12_BPP10_UBWC: - case COLOR_FMT_P010_UBWC: - alignment = 16; - break; - default: - return 0; - } - sclines = MSM_MEDIA_ALIGN(height, alignment); -invalid_input: - return sclines; -} - -/* - * Function arguments: - * @color_fmt - * @height - * Progressive: height - * Interlaced: (height+1)>>1 - */ -static __inline__ unsigned int VENUS_UV_SCANLINES(int color_fmt, int height) -{ - unsigned int alignment, sclines = 0; - - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - case COLOR_FMT_NV12_MVTB: - case COLOR_FMT_NV12_BPP10_UBWC: - case COLOR_FMT_P010_UBWC: - case COLOR_FMT_P010: - alignment = 16; - break; - case COLOR_FMT_NV12_UBWC: - alignment = 32; - break; - default: - goto invalid_input; - } - - sclines = MSM_MEDIA_ALIGN((height+1)>>1, alignment); - -invalid_input: - return sclines; -} - -/* - * Function arguments: - * @color_fmt - * @width - * Progressive: width - * Interlaced: width - */ -static __inline__ unsigned int VENUS_Y_META_STRIDE(int color_fmt, int width) -{ - int y_tile_width = 0, y_meta_stride = 0; - - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV12_UBWC: - case COLOR_FMT_P010_UBWC: - y_tile_width = 32; - break; - case COLOR_FMT_NV12_BPP10_UBWC: - y_tile_width = 48; - break; - default: - goto invalid_input; - } - - y_meta_stride = MSM_MEDIA_ROUNDUP(width, y_tile_width); - y_meta_stride = MSM_MEDIA_ALIGN(y_meta_stride, 64); - -invalid_input: - return y_meta_stride; -} - -/* - * Function arguments: - * @color_fmt - * @height - * Progressive: height - * Interlaced: (height+1)>>1 - */ -static __inline__ unsigned int VENUS_Y_META_SCANLINES(int color_fmt, int height) -{ - int y_tile_height = 0, y_meta_scanlines = 0; - - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV12_UBWC: - y_tile_height = 8; - break; - case COLOR_FMT_NV12_BPP10_UBWC: - case COLOR_FMT_P010_UBWC: - y_tile_height = 4; - break; - default: - goto invalid_input; - } - - y_meta_scanlines = MSM_MEDIA_ROUNDUP(height, y_tile_height); - y_meta_scanlines = MSM_MEDIA_ALIGN(y_meta_scanlines, 16); - -invalid_input: - return y_meta_scanlines; -} - -/* - * Function arguments: - * @color_fmt - * @width - * Progressive: width - * Interlaced: width - */ -static __inline__ unsigned int VENUS_UV_META_STRIDE(int color_fmt, int width) -{ - int uv_tile_width = 0, uv_meta_stride = 0; - - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV12_UBWC: - case COLOR_FMT_P010_UBWC: - uv_tile_width = 16; - break; - case COLOR_FMT_NV12_BPP10_UBWC: - uv_tile_width = 24; - break; - default: - goto invalid_input; - } - - uv_meta_stride = MSM_MEDIA_ROUNDUP((width+1)>>1, uv_tile_width); - uv_meta_stride = MSM_MEDIA_ALIGN(uv_meta_stride, 64); - -invalid_input: - return uv_meta_stride; -} - -/* - * Function arguments: - * @color_fmt - * @height - * Progressive: height - * Interlaced: (height+1)>>1 - */ -static __inline__ unsigned int VENUS_UV_META_SCANLINES(int color_fmt, int height) -{ - int uv_tile_height = 0, uv_meta_scanlines = 0; - - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_NV12_UBWC: - uv_tile_height = 8; - break; - case COLOR_FMT_NV12_BPP10_UBWC: - case COLOR_FMT_P010_UBWC: - uv_tile_height = 4; - break; - default: - goto invalid_input; - } - - uv_meta_scanlines = MSM_MEDIA_ROUNDUP((height+1)>>1, uv_tile_height); - uv_meta_scanlines = MSM_MEDIA_ALIGN(uv_meta_scanlines, 16); - -invalid_input: - return uv_meta_scanlines; -} - -static __inline__ unsigned int VENUS_RGB_STRIDE(int color_fmt, int width) -{ - unsigned int alignment = 0, stride = 0, bpp = 4; - - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_RGBA8888: - alignment = 128; - break; - case COLOR_FMT_RGB565_UBWC: - alignment = 256; - bpp = 2; - break; - case COLOR_FMT_RGBA8888_UBWC: - case COLOR_FMT_RGBA1010102_UBWC: - alignment = 256; - break; - default: - goto invalid_input; - } - - stride = MSM_MEDIA_ALIGN(width * bpp, alignment); - -invalid_input: - return stride; -} - -static __inline__ unsigned int VENUS_RGB_SCANLINES(int color_fmt, int height) -{ - unsigned int alignment = 0, scanlines = 0; - - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_RGBA8888: - alignment = 32; - break; - case COLOR_FMT_RGBA8888_UBWC: - case COLOR_FMT_RGBA1010102_UBWC: - case COLOR_FMT_RGB565_UBWC: - alignment = 16; - break; - default: - goto invalid_input; - } - - scanlines = MSM_MEDIA_ALIGN(height, alignment); - -invalid_input: - return scanlines; -} - -static __inline__ unsigned int VENUS_RGB_META_STRIDE(int color_fmt, int width) -{ - int rgb_tile_width = 0, rgb_meta_stride = 0; - - if (!width) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_RGBA8888_UBWC: - case COLOR_FMT_RGBA1010102_UBWC: - case COLOR_FMT_RGB565_UBWC: - rgb_tile_width = 16; - break; - default: - goto invalid_input; - } - - rgb_meta_stride = MSM_MEDIA_ROUNDUP(width, rgb_tile_width); - rgb_meta_stride = MSM_MEDIA_ALIGN(rgb_meta_stride, 64); - -invalid_input: - return rgb_meta_stride; -} - -static __inline__ unsigned int VENUS_RGB_META_SCANLINES(int color_fmt, int height) -{ - int rgb_tile_height = 0, rgb_meta_scanlines = 0; - - if (!height) - goto invalid_input; - - switch (color_fmt) { - case COLOR_FMT_RGBA8888_UBWC: - case COLOR_FMT_RGBA1010102_UBWC: - case COLOR_FMT_RGB565_UBWC: - rgb_tile_height = 4; - break; - default: - goto invalid_input; - } - - rgb_meta_scanlines = MSM_MEDIA_ROUNDUP(height, rgb_tile_height); - rgb_meta_scanlines = MSM_MEDIA_ALIGN(rgb_meta_scanlines, 16); - -invalid_input: - return rgb_meta_scanlines; -} - -/* - * Function arguments: - * @color_fmt - * @width - * Progressive: width - * Interlaced: width - * @height - * Progressive: height - * Interlaced: height - */ -static __inline__ unsigned int VENUS_BUFFER_SIZE( - int color_fmt, int width, int height) -{ - const unsigned int extra_size = VENUS_EXTRADATA_SIZE(width, height); - unsigned int uv_alignment = 0, size = 0; - unsigned int w_alignment = 512; - unsigned int y_plane, uv_plane, y_stride, - uv_stride, y_sclines, uv_sclines; - unsigned int y_ubwc_plane = 0, uv_ubwc_plane = 0; - unsigned int y_meta_stride = 0, y_meta_scanlines = 0; - unsigned int uv_meta_stride = 0, uv_meta_scanlines = 0; - unsigned int y_meta_plane = 0, uv_meta_plane = 0; - unsigned int rgb_stride = 0, rgb_scanlines = 0; - unsigned int rgb_plane = 0, rgb_ubwc_plane = 0, rgb_meta_plane = 0; - unsigned int rgb_meta_stride = 0, rgb_meta_scanlines = 0; - - if (!width || !height) - goto invalid_input; - - y_stride = VENUS_Y_STRIDE(color_fmt, width); - uv_stride = VENUS_UV_STRIDE(color_fmt, width); - y_sclines = VENUS_Y_SCANLINES(color_fmt, height); - uv_sclines = VENUS_UV_SCANLINES(color_fmt, height); - rgb_stride = VENUS_RGB_STRIDE(color_fmt, width); - rgb_scanlines = VENUS_RGB_SCANLINES(color_fmt, height); - - switch (color_fmt) { - case COLOR_FMT_NV21: - case COLOR_FMT_NV12: - uv_alignment = 4096; - y_plane = y_stride * y_sclines; - uv_plane = uv_stride * uv_sclines + uv_alignment; - size = y_plane + uv_plane + - MSM_MEDIA_MAX(extra_size, 8 * y_stride); - size = MSM_MEDIA_ALIGN(size, 4096); - - /* Additional size to cover last row of non-aligned frame */ - if (width >= 2400 && height >= 2400) { - size += MSM_MEDIA_ALIGN(width, w_alignment) * - w_alignment; - size = MSM_MEDIA_ALIGN(size, 4096); - } - break; - case COLOR_FMT_P010: - uv_alignment = 4096; - y_plane = y_stride * y_sclines; - uv_plane = uv_stride * uv_sclines + uv_alignment; - size = y_plane + uv_plane + - MSM_MEDIA_MAX(extra_size, 8 * y_stride); - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_NV12_MVTB: - uv_alignment = 4096; - y_plane = y_stride * y_sclines; - uv_plane = uv_stride * uv_sclines + uv_alignment; - size = y_plane + uv_plane; - size = 2 * size + extra_size; - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_NV12_UBWC: - y_sclines = VENUS_Y_SCANLINES(color_fmt, (height+1)>>1); - y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); - uv_sclines = VENUS_UV_SCANLINES(color_fmt, (height+1)>>1); - uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); - y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); - y_meta_scanlines = - VENUS_Y_META_SCANLINES(color_fmt, (height+1)>>1); - y_meta_plane = MSM_MEDIA_ALIGN( - y_meta_stride * y_meta_scanlines, 4096); - uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); - uv_meta_scanlines = - VENUS_UV_META_SCANLINES(color_fmt, (height+1)>>1); - uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * - uv_meta_scanlines, 4096); - - size = (y_ubwc_plane + uv_ubwc_plane + y_meta_plane + - uv_meta_plane)*2 + - MSM_MEDIA_MAX(extra_size + 8192, 48 * y_stride); - size = MSM_MEDIA_ALIGN(size, 4096); - - /* Additional size to cover last row of non-aligned frame */ - if (width >= 2400 && height >= 2400) { - size += MSM_MEDIA_ALIGN(width, w_alignment) * - w_alignment; - size = MSM_MEDIA_ALIGN(size, 4096); - } - break; - case COLOR_FMT_NV12_BPP10_UBWC: - y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); - uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); - y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); - y_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt, height); - y_meta_plane = MSM_MEDIA_ALIGN( - y_meta_stride * y_meta_scanlines, 4096); - uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); - uv_meta_scanlines = VENUS_UV_META_SCANLINES(color_fmt, height); - uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * - uv_meta_scanlines, 4096); - - size = y_ubwc_plane + uv_ubwc_plane + y_meta_plane + - uv_meta_plane + - MSM_MEDIA_MAX(extra_size + 8192, 48 * y_stride); - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_P010_UBWC: - y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); - uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); - y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); - y_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt, height); - y_meta_plane = MSM_MEDIA_ALIGN( - y_meta_stride * y_meta_scanlines, 4096); - uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); - uv_meta_scanlines = VENUS_UV_META_SCANLINES(color_fmt, height); - uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * - uv_meta_scanlines, 4096); - - size = y_ubwc_plane + uv_ubwc_plane + y_meta_plane + - uv_meta_plane; - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_RGBA8888: - rgb_plane = MSM_MEDIA_ALIGN(rgb_stride * rgb_scanlines, 4096); - size = rgb_plane; - size = MSM_MEDIA_ALIGN(size, 4096); - break; - case COLOR_FMT_RGBA8888_UBWC: - case COLOR_FMT_RGBA1010102_UBWC: - case COLOR_FMT_RGB565_UBWC: - rgb_ubwc_plane = MSM_MEDIA_ALIGN(rgb_stride * rgb_scanlines, - 4096); - rgb_meta_stride = VENUS_RGB_META_STRIDE(color_fmt, width); - rgb_meta_scanlines = VENUS_RGB_META_SCANLINES(color_fmt, - height); - rgb_meta_plane = MSM_MEDIA_ALIGN(rgb_meta_stride * - rgb_meta_scanlines, 4096); - size = rgb_ubwc_plane + rgb_meta_plane; - size = MSM_MEDIA_ALIGN(size, 4096); - break; - default: - break; - } -invalid_input: - return size; -} - -static __inline__ unsigned int VENUS_VIEW2_OFFSET( - int color_fmt, int width, int height) -{ - unsigned int offset = 0; - unsigned int y_plane, uv_plane, y_stride, - uv_stride, y_sclines, uv_sclines; - if (!width || !height) - goto invalid_input; - - y_stride = VENUS_Y_STRIDE(color_fmt, width); - uv_stride = VENUS_UV_STRIDE(color_fmt, width); - y_sclines = VENUS_Y_SCANLINES(color_fmt, height); - uv_sclines = VENUS_UV_SCANLINES(color_fmt, height); - switch (color_fmt) { - case COLOR_FMT_NV12_MVTB: - y_plane = y_stride * y_sclines; - uv_plane = uv_stride * uv_sclines; - offset = y_plane + uv_plane; - break; - default: - break; - } -invalid_input: - return offset; -} - -#endif diff --git a/sdm710/original-kernel-headers/media/msm_mercury.h b/sdm710/original-kernel-headers/media/msm_mercury.h deleted file mode 100644 index 607a8c8d..00000000 --- a/sdm710/original-kernel-headers/media/msm_mercury.h +++ /dev/null @@ -1,119 +0,0 @@ -#ifndef __UAPI_MSM_MERCURY_H -#define __UAPI_MSM_MERCURY_H - -#include <linux/types.h> -#include <linux/ioctl.h> - -#define MSM_MERCURY_HW_VERSION_REG 0x0004/* this offset does not exist in HW*/ - -#define OUTPUT_H2V1 0 -#define OUTPUT_H2V2 1 -#define OUTPUT_BYTE 6 - -#define MSM_MERCURY_MODE_REALTIME_ENCODE 0 -#define MSM_MERCURY_MODE_OFFLINE_ENCODE 1 -#define MSM_MERCURY_MODE_REALTIME_ROTATION 2 -#define MSM_MERCURY_MODE_OFFLINE_ROTATION 3 - -#define MSM_MERCURY_EVT_RESET 1 -#define MSM_MERCURY_EVT_FRAMEDONE 2 -#define MSM_MERCURY_EVT_ERR 3 -#define MSM_MERCURY_EVT_UNBLOCK 4 - -#define MSM_MERCURY_HW_CMD_TYPE_READ 0 -#define MSM_MERCURY_HW_CMD_TYPE_WRITE 1 -#define MSM_MERCURY_HW_CMD_TYPE_WRITE_OR 2 -#define MSM_MERCURY_HW_CMD_TYPE_UWAIT 3 -#define MSM_MERCURY_HW_CMD_TYPE_MWAIT 4 -#define MSM_MERCURY_HW_CMD_TYPE_MDELAY 5 -#define MSM_MERCURY_HW_CMD_TYPE_UDELAY 6 - -#define MSM_MCR_IOCTL_MAGIC 'g' - -#define MSM_MCR_IOCTL_GET_HW_VERSION \ - _IOW(MSM_MCR_IOCTL_MAGIC, 1, struct msm_mercury_hw_cmd *) - -#define MSM_MCR_IOCTL_RESET \ - _IOW(MSM_MCR_IOCTL_MAGIC, 2, struct msm_mercury_ctrl_cmd *) - -#define MSM_MCR_IOCTL_STOP \ - _IOW(MSM_MCR_IOCTL_MAGIC, 3, struct msm_mercury_hw_cmds *) - -#define MSM_MCR_IOCTL_START \ - _IOW(MSM_MCR_IOCTL_MAGIC, 4, struct msm_mercury_hw_cmds *) - -#define MSM_MCR_IOCTL_INPUT_BUF_CFG \ - _IOW(MSM_MCR_IOCTL_MAGIC, 5, struct msm_mercury_buf *) - -#define MSM_MCR_IOCTL_INPUT_GET \ - _IOW(MSM_MCR_IOCTL_MAGIC, 6, struct msm_mercury_buf *) - -#define MSM_MCR_IOCTL_INPUT_GET_UNBLOCK \ - _IOW(MSM_MCR_IOCTL_MAGIC, 7, int) - -#define MSM_MCR_IOCTL_OUTPUT_BUF_CFG \ - _IOW(MSM_MCR_IOCTL_MAGIC, 8, struct msm_mercury_buf *) - -#define MSM_MCR_IOCTL_OUTPUT_GET \ - _IOW(MSM_MCR_IOCTL_MAGIC, 9, struct msm_mercury_buf *) - -#define MSM_MCR_IOCTL_OUTPUT_GET_UNBLOCK \ - _IOW(MSM_MCR_IOCTL_MAGIC, 10, int) - -#define MSM_MCR_IOCTL_EVT_GET \ - _IOW(MSM_MCR_IOCTL_MAGIC, 11, struct msm_mercury_ctrl_cmd *) - -#define MSM_MCR_IOCTL_EVT_GET_UNBLOCK \ - _IOW(MSM_MCR_IOCTL_MAGIC, 12, int) - -#define MSM_MCR_IOCTL_HW_CMD \ - _IOW(MSM_MCR_IOCTL_MAGIC, 13, struct msm_mercury_hw_cmd *) - -#define MSM_MCR_IOCTL_HW_CMDS \ - _IOW(MSM_MCR_IOCTL_MAGIC, 14, struct msm_mercury_hw_cmds *) - -#define MSM_MCR_IOCTL_TEST_DUMP_REGION \ - _IOW(MSM_MCR_IOCTL_MAGIC, 15, unsigned long) - -struct msm_mercury_ctrl_cmd { - uint32_t type; - uint32_t len; - void *value; -}; - -struct msm_mercury_buf { - uint32_t type; - int fd; - void *vaddr; - uint32_t y_off; - uint32_t y_len; - uint32_t framedone_len; - uint32_t cbcr_off; - uint32_t cbcr_len; - uint32_t num_of_mcu_rows; - uint32_t offset; -}; - -struct msm_mercury_hw_cmd { - - uint32_t type:4; - /* n microseconds of timeout for WAIT */ - /* n microseconds of time for DELAY */ - /* repeat n times for READ/WRITE */ - /* max is 0xFFF, 4095 */ - uint32_t n:12; - uint32_t offset:16; - uint32_t mask; - union { - /* for single READ/WRITE/WAIT, n = 1 */ - uint32_t data; - uint32_t *pdata;/* for multiple READ/WRITE/WAIT, n > 1 */ - }; -}; - -struct msm_mercury_hw_cmds { - uint32_t m; /* number of elements in the hw_cmd array */ - struct msm_mercury_hw_cmd hw_cmd[1]; -}; - -#endif /* __UAPI_MSM_MERCURY_H */ diff --git a/sdm710/original-kernel-headers/media/msm_sde_rotator.h b/sdm710/original-kernel-headers/media/msm_sde_rotator.h deleted file mode 100644 index dcdbb85b..00000000 --- a/sdm710/original-kernel-headers/media/msm_sde_rotator.h +++ /dev/null @@ -1,117 +0,0 @@ -#ifndef __UAPI_MSM_SDE_ROTATOR_H__ -#define __UAPI_MSM_SDE_ROTATOR_H__ - -#include <linux/videodev2.h> -#include <linux/types.h> -#include <linux/ioctl.h> - -/* SDE Rotator pixel format definitions */ -#define SDE_PIX_FMT_XRGB_8888 V4L2_PIX_FMT_XBGR32 -#define SDE_PIX_FMT_ARGB_8888 V4L2_PIX_FMT_ABGR32 -#define SDE_PIX_FMT_ABGR_8888 V4L2_PIX_FMT_SDE_ABGR_8888 -#define SDE_PIX_FMT_RGBA_8888 V4L2_PIX_FMT_SDE_RGBA_8888 -#define SDE_PIX_FMT_BGRA_8888 V4L2_PIX_FMT_ARGB32 -#define SDE_PIX_FMT_RGBX_8888 V4L2_PIX_FMT_SDE_RGBX_8888 -#define SDE_PIX_FMT_BGRX_8888 V4L2_PIX_FMT_XRGB32 -#define SDE_PIX_FMT_XBGR_8888 V4L2_PIX_FMT_SDE_XBGR_8888 -#define SDE_PIX_FMT_RGBA_5551 V4L2_PIX_FMT_SDE_RGBA_5551 -#define SDE_PIX_FMT_ARGB_1555 V4L2_PIX_FMT_ARGB555 -#define SDE_PIX_FMT_ABGR_1555 V4L2_PIX_FMT_SDE_ABGR_1555 -#define SDE_PIX_FMT_BGRA_5551 V4L2_PIX_FMT_SDE_BGRA_5551 -#define SDE_PIX_FMT_BGRX_5551 V4L2_PIX_FMT_SDE_BGRX_5551 -#define SDE_PIX_FMT_RGBX_5551 V4L2_PIX_FMT_SDE_RGBX_5551 -#define SDE_PIX_FMT_XBGR_1555 V4L2_PIX_FMT_SDE_XBGR_1555 -#define SDE_PIX_FMT_XRGB_1555 V4L2_PIX_FMT_XRGB555 -#define SDE_PIX_FMT_ARGB_4444 V4L2_PIX_FMT_ARGB444 -#define SDE_PIX_FMT_RGBA_4444 V4L2_PIX_FMT_SDE_RGBA_4444 -#define SDE_PIX_FMT_BGRA_4444 V4L2_PIX_FMT_SDE_BGRA_4444 -#define SDE_PIX_FMT_ABGR_4444 V4L2_PIX_FMT_SDE_ABGR_4444 -#define SDE_PIX_FMT_RGBX_4444 V4L2_PIX_FMT_SDE_RGBX_4444 -#define SDE_PIX_FMT_XRGB_4444 V4L2_PIX_FMT_XRGB444 -#define SDE_PIX_FMT_BGRX_4444 V4L2_PIX_FMT_SDE_BGRX_4444 -#define SDE_PIX_FMT_XBGR_4444 V4L2_PIX_FMT_SDE_XBGR_4444 -#define SDE_PIX_FMT_RGB_888 V4L2_PIX_FMT_RGB24 -#define SDE_PIX_FMT_BGR_888 V4L2_PIX_FMT_BGR24 -#define SDE_PIX_FMT_RGB_565 V4L2_PIX_FMT_RGB565 -#define SDE_PIX_FMT_BGR_565 V4L2_PIX_FMT_SDE_BGR_565 -#define SDE_PIX_FMT_Y_CB_CR_H2V2 V4L2_PIX_FMT_YUV420 -#define SDE_PIX_FMT_Y_CR_CB_H2V2 V4L2_PIX_FMT_YVU420 -#define SDE_PIX_FMT_Y_CR_CB_GH2V2 V4L2_PIX_FMT_SDE_Y_CR_CB_GH2V2 -#define SDE_PIX_FMT_Y_CBCR_H2V2 V4L2_PIX_FMT_NV12 -#define SDE_PIX_FMT_Y_CRCB_H2V2 V4L2_PIX_FMT_NV21 -#define SDE_PIX_FMT_Y_CBCR_H1V2 V4L2_PIX_FMT_SDE_Y_CBCR_H1V2 -#define SDE_PIX_FMT_Y_CRCB_H1V2 V4L2_PIX_FMT_SDE_Y_CRCB_H1V2 -#define SDE_PIX_FMT_Y_CBCR_H2V1 V4L2_PIX_FMT_NV16 -#define SDE_PIX_FMT_Y_CRCB_H2V1 V4L2_PIX_FMT_NV61 -#define SDE_PIX_FMT_YCBYCR_H2V1 V4L2_PIX_FMT_YUYV -#define SDE_PIX_FMT_Y_CBCR_H2V2_VENUS V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_VENUS -#define SDE_PIX_FMT_Y_CRCB_H2V2_VENUS V4L2_PIX_FMT_SDE_Y_CRCB_H2V2_VENUS -#define SDE_PIX_FMT_RGBA_8888_UBWC V4L2_PIX_FMT_RGBA8888_UBWC -#define SDE_PIX_FMT_RGBX_8888_UBWC V4L2_PIX_FMT_SDE_RGBX_8888_UBWC -#define SDE_PIX_FMT_RGB_565_UBWC V4L2_PIX_FMT_SDE_RGB_565_UBWC -#define SDE_PIX_FMT_Y_CBCR_H2V2_UBWC V4L2_PIX_FMT_NV12_UBWC -#define SDE_PIX_FMT_RGBA_1010102 V4L2_PIX_FMT_SDE_RGBA_1010102 -#define SDE_PIX_FMT_RGBX_1010102 V4L2_PIX_FMT_SDE_RGBX_1010102 -#define SDE_PIX_FMT_ARGB_2101010 V4L2_PIX_FMT_SDE_ARGB_2101010 -#define SDE_PIX_FMT_XRGB_2101010 V4L2_PIX_FMT_SDE_XRGB_2101010 -#define SDE_PIX_FMT_BGRA_1010102 V4L2_PIX_FMT_SDE_BGRA_1010102 -#define SDE_PIX_FMT_BGRX_1010102 V4L2_PIX_FMT_SDE_BGRX_1010102 -#define SDE_PIX_FMT_ABGR_2101010 V4L2_PIX_FMT_SDE_ABGR_2101010 -#define SDE_PIX_FMT_XBGR_2101010 V4L2_PIX_FMT_SDE_XBGR_2101010 -#define SDE_PIX_FMT_RGBA_1010102_UBWC V4L2_PIX_FMT_SDE_RGBA_1010102_UBWC -#define SDE_PIX_FMT_RGBX_1010102_UBWC V4L2_PIX_FMT_SDE_RGBX_1010102_UBWC -#define SDE_PIX_FMT_Y_CBCR_H2V2_P010 V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010 -#define SDE_PIX_FMT_Y_CBCR_H2V2_P010_VENUS \ - V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010_VENUS -#define SDE_PIX_FMT_Y_CBCR_H2V2_TP10 V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_TP10 -#define SDE_PIX_FMT_Y_CBCR_H2V2_TP10_UBWC V4L2_PIX_FMT_NV12_TP10_UBWC -#define SDE_PIX_FMT_Y_CBCR_H2V2_P010_UBWC V4L2_PIX_FMT_NV12_P010_UBWC - -/* - * struct msm_sde_rotator_fence - v4l2 buffer fence info - * @index: id number of the buffer - * @type: enum v4l2_buf_type; buffer type - * @fd: file descriptor of the fence associated with this buffer - */ -struct msm_sde_rotator_fence { - __u32 index; - __u32 type; - __s32 fd; - __u32 reserved[5]; -}; - -/* - * struct msm_sde_rotator_comp_ratio - v4l2 buffer compression ratio - * @index: id number of the buffer - * @type: enum v4l2_buf_type; buffer type - * @numer: numerator of the ratio - * @denom: denominator of the ratio - */ -struct msm_sde_rotator_comp_ratio { - __u32 index; - __u32 type; - __u32 numer; - __u32 denom; - __u32 reserved[4]; -}; - -/* SDE Rotator private ioctl ID */ -#define VIDIOC_G_SDE_ROTATOR_FENCE \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_sde_rotator_fence) -#define VIDIOC_S_SDE_ROTATOR_FENCE \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_sde_rotator_fence) -#define VIDIOC_G_SDE_ROTATOR_COMP_RATIO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_sde_rotator_comp_ratio) -#define VIDIOC_S_SDE_ROTATOR_COMP_RATIO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_sde_rotator_comp_ratio) - -/* SDE Rotator private control ID's */ -#define V4L2_CID_SDE_ROTATOR_SECURE (V4L2_CID_USER_BASE + 0x1000) - -/* - * This control Id indicates this context is associated with the - * secure camera. - */ -#define V4L2_CID_SDE_ROTATOR_SECURE_CAMERA (V4L2_CID_USER_BASE + 0x2000) - -#endif /* __UAPI_MSM_SDE_ROTATOR_H__ */ diff --git a/sdm710/original-kernel-headers/media/msm_vidc.h b/sdm710/original-kernel-headers/media/msm_vidc.h deleted file mode 100644 index cac2b326..00000000 --- a/sdm710/original-kernel-headers/media/msm_vidc.h +++ /dev/null @@ -1,423 +0,0 @@ -#ifndef __MSM_VIDC_H__ -#define __MSM_VIDC_H__ - -#include <linux/types.h> - -#define MSM_VIDC_HAL_INTERLACE_COLOR_FORMAT_NV12 0x2 -#define MSM_VIDC_HAL_INTERLACE_COLOR_FORMAT_NV12_UBWC 0x8002 -#define MSM_VIDC_4x_1 0x1 -#define MSM_VIDC_EXTRADATA_FRAME_QP_ADV 0x1 - -struct msm_vidc_extradata_header { - unsigned int size; - unsigned int:32; /** Keeping binary compatibility */ - unsigned int:32; /* with firmware and OpenMAX IL **/ - unsigned int type; /* msm_vidc_extradata_type */ - unsigned int data_size; - unsigned char data[1]; -}; - -struct msm_vidc_interlace_payload { - unsigned int format; - unsigned int color_format; -}; - -struct msm_vidc_framerate_payload { - unsigned int frame_rate; -}; - -struct msm_vidc_ts_payload { - unsigned int timestamp_lo; - unsigned int timestamp_hi; -}; - -struct msm_vidc_concealmb_payload { - unsigned int num_mbs; -}; - -struct msm_vidc_recoverysei_payload { - unsigned int flags; -}; - -struct msm_vidc_aspect_ratio_payload { - unsigned int size; - unsigned int version; - unsigned int port_index; - unsigned int aspect_width; - unsigned int aspect_height; -}; - -struct msm_vidc_mpeg2_seqdisp_payload { - unsigned int video_format; - unsigned int color_descp; - unsigned int color_primaries; - unsigned int transfer_char; - unsigned int matrix_coeffs; - unsigned int disp_width; - unsigned int disp_height; -}; - -struct msm_vidc_vc1_seqdisp_payload { - unsigned int prog_seg_format; - unsigned int uv_sampl_fmt; - unsigned int color_format; - unsigned int color_primaries; - unsigned int transfer_char; - unsigned int matrix_coeffs; - unsigned int aspect_ratio; - unsigned int aspect_horiz; - unsigned int aspect_vert; -}; - -struct msm_vidc_input_crop_payload { - unsigned int size; - unsigned int version; - unsigned int port_index; - unsigned int left; - unsigned int top; - unsigned int width; - unsigned int height; -}; - -struct msm_vidc_misr_info { - unsigned int misr_dpb_luma; - unsigned int misr_dpb_chroma; - unsigned int misr_opb_luma; - unsigned int misr_opb_chroma; -}; -struct msm_vidc_output_crop_payload { - unsigned int size; - unsigned int version; - unsigned int port_index; - unsigned int left; - unsigned int top; - unsigned int display_width; - unsigned int display_height; - unsigned int width; - unsigned int height; - unsigned int frame_num; - unsigned int bit_depth_y; - unsigned int bit_depth_c; - struct msm_vidc_misr_info misr_info[2]; -}; - - -struct msm_vidc_digital_zoom_payload { - unsigned int size; - unsigned int version; - unsigned int port_index; - unsigned int zoom_width; - unsigned int zoom_height; -}; - -struct msm_vidc_extradata_index { - unsigned int type; - union { - struct msm_vidc_input_crop_payload input_crop; - struct msm_vidc_digital_zoom_payload digital_zoom; - struct msm_vidc_aspect_ratio_payload aspect_ratio; - }; -}; - -struct msm_vidc_panscan_window { - unsigned int panscan_height_offset; - unsigned int panscan_width_offset; - unsigned int panscan_window_width; - unsigned int panscan_window_height; -}; - -struct msm_vidc_panscan_window_payload { - unsigned int num_panscan_windows; - struct msm_vidc_panscan_window wnd[1]; -}; - -struct msm_vidc_stream_userdata_payload { - unsigned int type; - unsigned int data[1]; -}; - -struct msm_vidc_frame_qp_payload { - unsigned int frame_qp; - unsigned int qp_sum; - unsigned int skip_qp_sum; - unsigned int skip_num_blocks; - unsigned int total_num_blocks; -}; - -struct msm_vidc_frame_bits_info_payload { - unsigned int frame_bits; - unsigned int header_bits; -}; - -struct msm_vidc_s3d_frame_packing_payload { - unsigned int fpa_id; - unsigned int cancel_flag; - unsigned int fpa_type; - unsigned int quin_cunx_flag; - unsigned int content_interprtation_type; - unsigned int spatial_flipping_flag; - unsigned int frame0_flipped_flag; - unsigned int field_views_flag; - unsigned int current_frame_is_frame0_flag; - unsigned int frame0_self_contained_flag; - unsigned int frame1_self_contained_flag; - unsigned int frame0_graid_pos_x; - unsigned int frame0_graid_pos_y; - unsigned int frame1_graid_pos_x; - unsigned int frame1_graid_pos_y; - unsigned int fpa_reserved_byte; - unsigned int fpa_repetition_period; - unsigned int fpa_extension_flag; -}; - -struct msm_vidc_vqzip_sei_payload { - unsigned int size; - unsigned int data[1]; -}; - -struct msm_vidc_ubwc_cr_stats_info { - unsigned int stats_tile_32; - unsigned int stats_tile_64; - unsigned int stats_tile_96; - unsigned int stats_tile_128; - unsigned int stats_tile_160; - unsigned int stats_tile_192; - unsigned int stats_tile_256; -}; - -struct msm_vidc_yuv_stats_payload { - unsigned int frame_qp; - unsigned int texture; - unsigned int luma_in_q16; - unsigned int frame_difference; -}; - -struct msm_vidc_vpx_colorspace_payload { - unsigned int color_space; - unsigned int yuv_range_flag; - unsigned int sumsampling_x; - unsigned int sumsampling_y; -}; - -struct msm_vidc_roi_qp_payload { - int upper_qp_offset; - int lower_qp_offset; - unsigned int b_roi_info; - int mbi_info_size; - unsigned int data[1]; -}; - -struct msm_vidc_mastering_display_colour_sei_payload { - unsigned int nDisplayPrimariesX[3]; - unsigned int nDisplayPrimariesY[3]; - unsigned int nWhitePointX; - unsigned int nWhitePointY; - unsigned int nMaxDisplayMasteringLuminance; - unsigned int nMinDisplayMasteringLuminance; -}; - -struct msm_vidc_content_light_level_sei_payload { - unsigned int nMaxContentLight; - unsigned int nMaxPicAverageLight; -}; - -struct msm_vidc_vui_display_info_payload { - unsigned int video_signal_present_flag; - unsigned int video_format; - unsigned int bit_depth_y; - unsigned int bit_depth_c; - unsigned int video_full_range_flag; - unsigned int color_description_present_flag; - unsigned int color_primaries; - unsigned int transfer_characteristics; - unsigned int matrix_coefficients; - unsigned int chroma_location_info_present_flag; - unsigned int chroma_format_idc; - unsigned int separate_color_plane_flag; - unsigned int chroma_sample_loc_type_top_field; - unsigned int chroma_sample_loc_type_bottom_field; -}; - -enum msm_vidc_extradata_type { - MSM_VIDC_EXTRADATA_NONE = 0x00000000, - MSM_VIDC_EXTRADATA_MB_QUANTIZATION = 0x00000001, - MSM_VIDC_EXTRADATA_INTERLACE_VIDEO = 0x00000002, - MSM_VIDC_EXTRADATA_VC1_FRAMEDISP = 0x00000003, - MSM_VIDC_EXTRADATA_VC1_SEQDISP = 0x00000004, - MSM_VIDC_EXTRADATA_TIMESTAMP = 0x00000005, - MSM_VIDC_EXTRADATA_S3D_FRAME_PACKING = 0x00000006, - MSM_VIDC_EXTRADATA_FRAME_RATE = 0x00000007, - MSM_VIDC_EXTRADATA_PANSCAN_WINDOW = 0x00000008, - MSM_VIDC_EXTRADATA_RECOVERY_POINT_SEI = 0x00000009, - MSM_VIDC_EXTRADATA_MPEG2_SEQDISP = 0x0000000D, - MSM_VIDC_EXTRADATA_STREAM_USERDATA = 0x0000000E, - MSM_VIDC_EXTRADATA_FRAME_QP = 0x0000000F, - MSM_VIDC_EXTRADATA_FRAME_BITS_INFO = 0x00000010, - MSM_VIDC_EXTRADATA_VQZIP_SEI = 0x00000011, - MSM_VIDC_EXTRADATA_ROI_QP = 0x00000013, -#define MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO \ - MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO - MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO = 0x00000014, -#define MSM_VIDC_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI \ - MSM_VIDC_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI - MSM_VIDC_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI = 0x00000015, -#define MSM_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI \ - MSM_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI - MSM_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI = 0x00000016, -#define MSM_VIDC_EXTRADATA_PQ_INFO \ - MSM_VIDC_EXTRADATA_PQ_INFO - MSM_VIDC_EXTRADATA_PQ_INFO = 0x00000017, -#define MSM_VIDC_EXTRADATA_COLOUR_REMAPPING_INFO_SEI \ - MSM_VIDC_EXTRADATA_COLOUR_REMAPPING_INFO_SEI - MSM_VIDC_EXTRADATA_COLOUR_REMAPPING_INFO_SEI = 0x00000018, -#define MSM_VIDC_EXTRADATA_UBWC_CR_STAT_INFO \ - MSM_VIDC_EXTRADATA_UBWC_CR_STAT_INFO - MSM_VIDC_EXTRADATA_UBWC_CR_STAT_INFO = 0x00000019, - MSM_VIDC_EXTRADATA_INPUT_CROP = 0x0700000E, -#define MSM_VIDC_EXTRADATA_OUTPUT_CROP \ - MSM_VIDC_EXTRADATA_OUTPUT_CROP - MSM_VIDC_EXTRADATA_OUTPUT_CROP = 0x0700000F, - MSM_VIDC_EXTRADATA_DIGITAL_ZOOM = 0x07000010, - MSM_VIDC_EXTRADATA_MULTISLICE_INFO = 0x7F100000, - MSM_VIDC_EXTRADATA_NUM_CONCEALED_MB = 0x7F100001, - MSM_VIDC_EXTRADATA_INDEX = 0x7F100002, - MSM_VIDC_EXTRADATA_ASPECT_RATIO = 0x7F100003, - MSM_VIDC_EXTRADATA_METADATA_LTR = 0x7F100004, - MSM_VIDC_EXTRADATA_METADATA_FILLER = 0x7FE00002, - MSM_VIDC_EXTRADATA_METADATA_MBI = 0x7F100005, -#define MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO \ - MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO - MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO = 0x7F100006, - MSM_VIDC_EXTRADATA_YUVSTATS_INFO = 0x7F100007, -}; -enum msm_vidc_interlace_type { - MSM_VIDC_INTERLACE_FRAME_PROGRESSIVE = 0x01, - MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_TOPFIELDFIRST = 0x02, - MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_BOTTOMFIELDFIRST = 0x04, - MSM_VIDC_INTERLACE_FRAME_TOPFIELDFIRST = 0x08, - MSM_VIDC_INTERLACE_FRAME_BOTTOMFIELDFIRST = 0x10, -#define MSM_VIDC_INTERLACE_FRAME_MBAFF \ - MSM_VIDC_INTERLACE_FRAME_MBAFF - MSM_VIDC_INTERLACE_FRAME_MBAFF = 0x20, -}; - -/* enum msm_vidc_framepack_type */ -#define MSM_VIDC_FRAMEPACK_CHECKERBOARD 0x00 -#define MSM_VIDC_FRAMEPACK_COLUMN_INTERLEAVE 0x01 -#define MSM_VIDC_FRAMEPACK_ROW_INTERLEAVE 0x02 -#define MSM_VIDC_FRAMEPACK_SIDE_BY_SIDE 0x03 -#define MSM_VIDC_FRAMEPACK_TOP_BOTTOM 0x04 -#define MSM_VIDC_FRAMEPACK_TEMPORAL_INTERLEAVE 0x05 - -enum msm_vidc_recovery_sei { - MSM_VIDC_FRAME_RECONSTRUCTION_INCORRECT = 0x0, - MSM_VIDC_FRAME_RECONSTRUCTION_CORRECT = 0x01, - MSM_VIDC_FRAME_RECONSTRUCTION_APPROXIMATELY_CORRECT = 0x02, -}; -enum msm_vidc_userdata_type { - MSM_VIDC_USERDATA_TYPE_FRAME = 0x1, - MSM_VIDC_USERDATA_TYPE_TOP_FIELD = 0x2, - MSM_VIDC_USERDATA_TYPE_BOTTOM_FIELD = 0x3, -}; - -/* See colour_primaries of ISO/IEC 14496 for significance */ -enum msm_vidc_h264_color_primaries_values { - MSM_VIDC_RESERVED_1 = 0, - MSM_VIDC_BT709_5 = 1, - MSM_VIDC_UNSPECIFIED = 2, - MSM_VIDC_RESERVED_2 = 3, - MSM_VIDC_BT470_6_M = 4, - MSM_VIDC_BT601_6_625 = 5, - MSM_VIDC_BT470_6_BG = MSM_VIDC_BT601_6_625, - MSM_VIDC_BT601_6_525 = 6, - MSM_VIDC_SMPTE_240M = 7, - MSM_VIDC_GENERIC_FILM = 8, - MSM_VIDC_BT2020 = 9, -}; - -enum msm_vidc_vp9_color_primaries_values { - MSM_VIDC_CS_UNKNOWN, - MSM_VIDC_CS_BT_601, - MSM_VIDC_CS_BT_709, - MSM_VIDC_CS_SMPTE_170, - MSM_VIDC_CS_SMPTE_240, - MSM_VIDC_CS_BT_2020, - MSM_VIDC_CS_RESERVED, - MSM_VIDC_CS_RGB, -}; - -enum msm_vidc_h264_matrix_coeff_values { - MSM_VIDC_MATRIX_RGB = 0, - MSM_VIDC_MATRIX_BT_709_5 = 1, - MSM_VIDC_MATRIX_UNSPECIFIED = 2, - MSM_VIDC_MATRIX_RESERVED = 3, - MSM_VIDC_MATRIX_FCC_47 = 4, - MSM_VIDC_MATRIX_601_6_625 = 5, - MSM_VIDC_MATRIX_BT470_BG = MSM_VIDC_MATRIX_601_6_625, - MSM_VIDC_MATRIX_601_6_525 = 6, - MSM_VIDC_MATRIX_SMPTE_170M = MSM_VIDC_MATRIX_601_6_525, - MSM_VIDC_MATRIX_SMPTE_240M = 7, - MSM_VIDC_MATRIX_Y_CG_CO = 8, - MSM_VIDC_MATRIX_BT_2020 = 9, - MSM_VIDC_MATRIX_BT_2020_CONST = 10, -}; - -enum msm_vidc_h264_transfer_chars_values { - MSM_VIDC_TRANSFER_RESERVED_1 = 0, - MSM_VIDC_TRANSFER_BT709_5 = 1, - MSM_VIDC_TRANSFER_UNSPECIFIED = 2, - MSM_VIDC_TRANSFER_RESERVED_2 = 3, - MSM_VIDC_TRANSFER_BT_470_6_M = 4, - MSM_VIDC_TRANSFER_BT_470_6_BG = 5, - MSM_VIDC_TRANSFER_601_6_625 = 6, - MSM_VIDC_TRANSFER_601_6_525 = MSM_VIDC_TRANSFER_601_6_625, - MSM_VIDC_TRANSFER_SMPTE_240M = 7, - MSM_VIDC_TRANSFER_LINEAR = 8, - MSM_VIDC_TRANSFER_LOG_100_1 = 9, - MSM_VIDC_TRANSFER_LOG_100_SQRT10_1 = 10, - MSM_VIDC_TRANSFER_IEC_61966 = 11, - MSM_VIDC_TRANSFER_BT_1361 = 12, - MSM_VIDC_TRANSFER_SRGB = 13, - MSM_VIDC_TRANSFER_BT_2020_10 = 14, - MSM_VIDC_TRANSFER_BT_2020_12 = 15, -#define MSM_VIDC_TRANSFER_SMPTE_ST2084 \ - MSM_VIDC_TRANSFER_SMPTE_ST2084 - MSM_VIDC_TRANSFER_SMPTE_ST2084 = 16, -#define MSM_VIDC_TRANSFER_SMPTE_ST428_1 \ - MSM_VIDC_TRANSFER_SMPTE_ST428_1 - MSM_VIDC_TRANSFER_SMPTE_ST428_1 = 17, -#define MSM_VIDC_TRANSFER_HLG \ - MSM_VIDC_TRANSFER_HLG - MSM_VIDC_TRANSFER_HLG = 18, -}; - -enum msm_vidc_pixel_depth { - MSM_VIDC_BIT_DEPTH_8, - MSM_VIDC_BIT_DEPTH_10, - MSM_VIDC_BIT_DEPTH_UNSUPPORTED = 0XFFFFFFFF, -}; - -enum msm_vidc_video_format { - MSM_VIDC_COMPONENT, - MSM_VIDC_PAL, - MSM_VIDC_NTSC, - MSM_VIDC_SECAM, - MSM_VIDC_MAC, - MSM_VIDC_UNSPECIFIED_FORMAT, - MSM_VIDC_RESERVED_1_FORMAT, - MSM_VIDC_RESERVED_2_FORMAT, -}; - -enum msm_vidc_color_desc_flag { - MSM_VIDC_COLOR_DESC_NOT_PRESENT, - MSM_VIDC_COLOR_DESC_PRESENT, -}; - -/*enum msm_vidc_pic_struct */ -#define MSM_VIDC_PIC_STRUCT_MAYBE_INTERLACED 0x0 -#define MSM_VIDC_PIC_STRUCT_PROGRESSIVE 0x1 -#define MSM_VIDC_PIC_STRUCT_UNKNOWN 0XFFFFFFFF -/*default when layer ID isn't specified*/ -#define MSM_VIDC_ALL_LAYER_ID 0xFF - -#endif diff --git a/sdm710/original-kernel-headers/media/msm_vpu.h b/sdm710/original-kernel-headers/media/msm_vpu.h deleted file mode 100644 index b7733050..00000000 --- a/sdm710/original-kernel-headers/media/msm_vpu.h +++ /dev/null @@ -1,475 +0,0 @@ -#ifndef _H_MSM_VPU_H_ -#define _H_MSM_VPU_H_ - -#include <linux/videodev2.h> - -/* - * V 4 L 2 E X T E N S I O N S B Y V P U - */ - -/* - * v4l2_buffer: - * - * VPU uses standard V4L2 buffer flags, and defines some custom - * flags (used in v4l2_buffer.flags field): - * V4L2_QCOM_BUF_FLAG_EOS: buffer flag indicating end of stream - * V4L2_BUF_FLAG_CDS_ENABLE: buffer flag to enable chroma down-sampling - */ -#define V4L2_BUF_FLAG_CDS_ENABLE 0x10000000 - -/* - * VPU uses multi-plane v4l2_buffer in the following manner: - * each plane can be a separate ION buffer, or all planes are from the - * same ION buffer (under this case all planes have the same fd, but different - * offset). - * - * For struct v4l2_plane - * fd: ION fd representing the ION buffer this plane is from - * reserved[0]: offset of this plane from the start of the ION buffer in - * bytes. Needed when all planes are from the same ION buffer. - */ -#define V4L2_PLANE_MEM_OFFSET 0 - -/* - * struct v4l2_format: - * always use v4l2_pix_format_mplane, even when there is only one plane - * - * v4l2_pix_format_mplane: - * - * VPU uses v4l2_pix_format_mplane for pixel format configuration - * The following members of this structure is either extended or changed: - * pixelformat: extended, a few more private formats added - * colorspace: possible values are enum vpu_colorspace - * field: when it is V4L2_FIELD_ALTERNATE, flags from vpu format extension - * specifies which field first. - * reserved[]: VPU format extension. struct v4l2_format_vpu_extension - */ -enum vpu_colorspace { - VPU_CS_MIN = 0, - /* RGB with full range*/ - VPU_CS_RGB_FULL = 1, - /* RGB with limited range*/ - VPU_CS_RGB_LIMITED = 2, - /* REC 601 with full range */ - VPU_CS_REC601_FULL = 3, - /* REC 601 with limited range */ - VPU_CS_REC601_LIMITED = 4, - /* REC 709 with full range */ - VPU_CS_REC709_FULL = 5, - /* REC 709 with limited range */ - VPU_CS_REC709_LIMITED = 6, - /* SMPTE 240 with full range */ - VPU_CS_SMPTE240_FULL = 7, - /* SMPTE 240 with limited range */ - VPU_CS_SMPTE240_LIMITED = 8, - VPU_CS_MAX = 9, -}; - - -#define VPU_FMT_EXT_FLAG_BT 1 /* bottom field first */ -#define VPU_FMT_EXT_FLAG_TB 2 /* top field first */ -#define VPU_FMT_EXT_FLAG_3D 4 /* 3D format */ -struct v4l2_format_vpu_extension { - __u8 flag; - __u8 gap_in_lines; -}; - -/* - * Supported pixel formats: - * - * VPU supported pixel format fourcc codes (use in s_fmt pixelformat field). - * Can be enumerated using VIDIOC_ENUM_FMT - * - * Standard V4L2 formats, defined in videodev2.h : - * - * V4L2_PIX_FMT_RGB24 24 bit RGB-8-8-8 - * V4L2_PIX_FMT_RGB32 32 bit XRGB-8-8-8-8 - * V4L2_PIX_FMT_BGR24 24 bit BGR-8-8-8 - * V4L2_PIX_FMT_BGR32 32 bit BGRX-8-8-8-8 - * - * V4L2_PIX_FMT_NV12 12 bit YUV 4:2:0 semi-planar NV12 - * V4L2_PIX_FMT_NV21 12 bit YUV 4:2:0 semi-planar NV21 - * V4L2_PIX_FMT_YUYV 16 bit YUYV 4:2:2 interleaved - * V4L2_PIX_FMT_YVYU 16 bit YVYU 4:2:2 interleaved - * V4L2_PIX_FMT_UYVY 16 bit UYVY 4:2:2 interleaved - * V4L2_PIX_FMT_VYUY 16 bit VYUY 4:2:2 interleaved - * - * - * Private VPU formats, defined here : - * - * V4L2_PIX_FMT_XRGB2 32 bit XRGB-2-10-10-10 - * V4L2_PIX_FMT_XBGR2 32 bit XBGR-2-10-10-10 - * - * V4L2_PIX_FMT_YUYV10 24 bit YUYV 4:2:2 10 bit per component loose - * V4L2_PIX_FMT_YUV8 24 bit YUV 4:4:4 8 bit per component - * V4L2_PIX_FMT_YUV10 32 bit YUV 4:4:4 10 bit per component loose - * V4L2_PIX_FMT_YUYV10BWC 10 bit YUYV 4:2:2 compressed, for output only - */ -#define V4L2_PIX_FMT_XRGB2 v4l2_fourcc('X', 'R', 'G', '2') -#define V4L2_PIX_FMT_XBGR2 v4l2_fourcc('X', 'B', 'G', '2') -#define V4L2_PIX_FMT_YUYV10 v4l2_fourcc('Y', 'U', 'Y', 'L') -#define V4L2_PIX_FMT_YUV8 v4l2_fourcc('Y', 'U', 'V', '8') -#define V4L2_PIX_FMT_YUV10 v4l2_fourcc('Y', 'U', 'V', 'L') -#define V4L2_PIX_FMT_YUYV10BWC v4l2_fourcc('Y', 'B', 'W', 'C') - -/* - * VIDIOC_S_INPUT/VIDIOC_S_OUTPUT - * - * The single integer passed by these commands specifies port type in the - * lower 16 bits, and pipe bit mask in the higher 16 bits. - */ -/* input / output types */ -#define VPU_INPUT_TYPE_HOST 0 -#define VPU_INPUT_TYPE_VCAP 1 -#define VPU_OUTPUT_TYPE_HOST 0 -#define VPU_OUTPUT_TYPE_DISPLAY 1 - -/* input / output pipe bit fields */ -#define VPU_PIPE_VCAP0 (1 << 16) -#define VPU_PIPE_VCAP1 (1 << 17) -#define VPU_PIPE_DISPLAY0 (1 << 18) -#define VPU_PIPE_DISPLAY1 (1 << 19) -#define VPU_PIPE_DISPLAY2 (1 << 20) -#define VPU_PIPE_DISPLAY3 (1 << 21) - -/* - * V P U E V E N T S : I D s A N D D A T A P A Y L O A D S - */ - -/* - * Event ID: set in type field of struct v4l2_event - * payload: returned in u.data array of struct v4l2_event - * - * - * VPU_EVENT_FLUSH_DONE: Done flushing buffers after VPU_FLUSH_BUFS ioctl - * payload data: enum v4l2_buf_type (buffer type of flushed port) - * - * VPU_EVENT_ACTIVE_REGION_CHANGED: New Active Region Detected - * payload data: struct v4l2_rect (new active region rectangle) - * - * VPU_EVENT_SESSION_TIMESTAMP: New Session timestamp - * payload data: vpu_frame_timestamp_info - * - * VPU_EVENT_SESSION_CREATED: New session has been created - * payload data: int (number of the attached session) - * - * VPU_EVENT_SESSION_FREED: Session is detached and free - * payload data: int (number of the detached session) - * - * VPU_EVENT_SESSION_CLIENT_EXITED: Indicates that clients of current - * session have exited. - * payload data: int (number of all remaining clients for this session) - * - * VPU_EVENT_HW_ERROR: a hardware error occurred in VPU - * payload data: NULL - * - * VPU_EVENT_INVALID_CONFIG: invalid VPU session configuration - * payload data: NULL - * - * VPU_EVENT_FAILED_SESSION_STREAMING: Failed to stream session - * payload data: NULL - */ -#define VPU_PRIVATE_EVENT_BASE (V4L2_EVENT_PRIVATE_START + 6 * 1000) -enum VPU_PRIVATE_EVENT { - VPU_EVENT_START = VPU_PRIVATE_EVENT_BASE, - - VPU_EVENT_FLUSH_DONE = VPU_EVENT_START + 1, - VPU_EVENT_ACTIVE_REGION_CHANGED = VPU_EVENT_START + 2, - VPU_EVENT_SESSION_TIMESTAMP = VPU_EVENT_START + 3, - VPU_EVENT_SESSION_CREATED = VPU_EVENT_START + 4, - VPU_EVENT_SESSION_FREED = VPU_EVENT_START + 5, - VPU_EVENT_SESSION_CLIENT_EXITED = VPU_EVENT_START + 6, - - VPU_EVENT_HW_ERROR = VPU_EVENT_START + 11, - VPU_EVENT_INVALID_CONFIG = VPU_EVENT_START + 12, - VPU_EVENT_FAILED_SESSION_STREAMING = VPU_EVENT_START + 13, - - VPU_EVENT_END -}; - - -/* - * V P U CO N T R O L S : S T R U C T S A N D I D s - * - * Controls are video processing parameters - */ - -/* - * Standard VPU Controls - */ -struct vpu_ctrl_standard { - __u32 enable; /* boolean: 0=disable, else=enable */ - __s32 value; -}; - -struct vpu_ctrl_auto_manual { - __u32 enable; /* boolean: 0=disable, else=enable */ - __u32 auto_mode; /* boolean: 0=manual, else=automatic */ - __s32 value; -}; - -struct vpu_ctrl_range_mapping { - __u32 enable; /* boolean: 0=disable, else=enable */ - __u32 y_range; /* the range mapping set for Y [0, 7] */ - __u32 uv_range; /* the range mapping set for UV [0, 7] */ -}; - -#define VPU_ACTIVE_REGION_N_EXCLUSIONS 1 -struct vpu_ctrl_active_region_param { - __u32 enable; /* boolean: 0=disable, else=enable */ - /* number of exclusion regions */ - __u32 num_exclusions; - /* roi where active region detection is applied */ - struct v4l2_rect detection_region; - /* roi(s) excluded from active region detection*/ - struct v4l2_rect excluded_regions[VPU_ACTIVE_REGION_N_EXCLUSIONS]; -}; - -struct vpu_ctrl_deinterlacing_mode { - __u32 field_polarity; - __u32 mvp_mode; -}; - -struct vpu_ctrl_hqv { - __u32 enable; - /* strength control of all sharpening features [0, 100] */ - __u32 sharpen_strength; - /* strength control of Auto NR feature [0, 100] */ - __u32 auto_nr_strength; -}; - -struct vpu_info_frame_timestamp { - /* presentation timestamp of the frame */ - __u32 pts_low; - __u32 pts_high; - /* qtimer snapshot */ - __u32 qtime_low; - __u32 qtime_high; -}; - -struct vpu_control { - __u32 control_id; - union control_data { - __s32 value; - struct vpu_ctrl_standard standard; - struct vpu_ctrl_auto_manual auto_manual; - struct vpu_ctrl_range_mapping range_mapping; - struct vpu_ctrl_active_region_param active_region_param; - struct v4l2_rect active_region_result; - struct vpu_ctrl_deinterlacing_mode deinterlacing_mode; - struct vpu_ctrl_hqv hqv; - struct vpu_info_frame_timestamp timestamp; - __u8 reserved[124]; - } data; -}; - -/* - * IDs for standard controls (use in control_id field of struct vpu_control) - * - * VPU_CTRL_NOISE_REDUCTION: noise reduction level, data: auto_manual, - * value: [0, 100] (step in increments of 25). - * - * VPU_CTRL_IMAGE_ENHANCEMENT: image enhancement level, data: auto_manual, - * value: [-100, 100] (step in increments of 1). - * - * VPU_CTRL_ANAMORPHIC_SCALING: anamorphic scaling config, data: standard, - * value: [0, 100] (step in increments of 1). - * - * VPU_CTRL_DIRECTIONAL_INTERPOLATION: directional interpolation config - * data: standard, value: [0, 100] (step in increments of 1). - * - * VPU_CTRL_BACKGROUND_COLOR: , data: value, - * value: red[0:7] green[8:15] blue[16:23] alpha[24:31] - * - * VPU_CTRL_RANGE_MAPPING: Y/UV range mapping, data: range_mapping, - * y_range: [0, 7], uv_range: [0, 7] (step in increments of 1). - * - * VPU_CTRL_DEINTERLACING_MODE: deinterlacing mode, data: deinterlacing_mode, - * field_polarity: [0, 2], mvp_mode: [0, 2] (step in increments of 1). - * - * VPU_CTRL_ACTIVE_REGION_PARAM: active region detection parameters (set only) - * data: active_region_param, - * - * VPU_CTRL_ACTIVE_REGION_RESULT: detected active region roi (get only) - * data: active_region_result - * - * VPU_CTRL_PRIORITY: Session priority, data: value, - * value: high 100, normal 50 - * - * VPU_CTRL_CONTENT_PROTECTION: input content protection status, data: value, - * value: secure 1, non-secure 0 - * - * VPU_CTRL_DISPLAY_REFRESH_RATE: display refresh rate (set only) - * data: value (set to __u32 16.16 format) - * - * VPU_CTRL_HQV: hqv block config, data: hqv, - * sharpen_strength: [0, 100] (step in increments of 25), - * auto_nr_strength: [0, 100] (step in increments of 1). - * - * VPU_CTRL_HQV_SHARPEN: , data: value, - * sharpen_strength: [0, 100] (step in increments of 1). - * - * VPU_CTRL_HQV_AUTONR: , data: value, - * auto_nr_strength: [0, 100] (step in increments of 1). - * - * VPU_CTRL_ACE: , data: value - * - * VPU_CTRL_ACE_BRIGHTNESS: , data: value, - * value: [-100, 100] (step in increments of 1). - * - * VPU_CTRL_ACE_CONTRAST: , data: value, - * value: [-100, 100] (step in increments of 1). - * - * VPU_CTRL_2D3D: , data: value, - * value: 1 enabled, 0 disabled - * - * VPU_CTRL_2D3D_DEPTH: , data: value, - * value: [0, 100] (step in increments of 1). - * - * VPU_CTRL_TIMESTAMP_INFO_MODE: timestamp reporting mode, - * data: value specifying how frequent a timestamp reporting info, value - * is in frames - * - * VPU_INFO_TIMESTAMP: timestamp information (get only) - * data: struct vpu_frame_timestamp_info - * - * VPU_CTRL_FRC: enable/disable FRC, data: value, - * value: 1 enable, 0 disable - * - * VPU_CTRL_FRC_MOTION_SMOOTHNESS: , data: value, - * value: [0, 100] (step in increments of 1). - * - * VPU_CTRL_FRC_MOTION_CLEAR: , data: value, - * value: [0, 100] (step in increments of 1). - * - * VPU_CTRL_LATENCY: session latency, data: value in us - * - * VPU_CTRL_LATENCY_MODE: data: value (ultra low, low, etc.) - * - * VPU_INFO_STATISTICS: frames dropped, etc (get only), - * data: reserved - */ -#define VPU_CTRL_ID_MIN 0 - -#define VPU_CTRL_NOISE_REDUCTION 1 -#define VPU_CTRL_IMAGE_ENHANCEMENT 2 -#define VPU_CTRL_ANAMORPHIC_SCALING 3 -#define VPU_CTRL_DIRECTIONAL_INTERPOLATION 4 -#define VPU_CTRL_BACKGROUND_COLOR 5 -#define VPU_CTRL_RANGE_MAPPING 6 -#define VPU_CTRL_DEINTERLACING_MODE 7 -#define VPU_CTRL_ACTIVE_REGION_PARAM 8 -#define VPU_CTRL_ACTIVE_REGION_RESULT 9 -#define VPU_CTRL_PRIORITY 10 -#define VPU_CTRL_CONTENT_PROTECTION 11 -#define VPU_CTRL_DISPLAY_REFRESH_RATE 12 - -#define VPU_CTRL_HQV 20 -#define VPU_CTRL_HQV_SHARPEN 21 -#define VPU_CTRL_HQV_AUTONR 22 -#define VPU_CTRL_ACE 23 -#define VPU_CTRL_ACE_BRIGHTNESS 24 -#define VPU_CTRL_ACE_CONTRAST 25 -#define VPU_CTRL_2D3D 26 -#define VPU_CTRL_2D3D_DEPTH 27 -#define VPU_CTRL_FRC 28 -#define VPU_CTRL_FRC_MOTION_SMOOTHNESS 29 -#define VPU_CTRL_FRC_MOTION_CLEAR 30 - -#define VPU_INFO_TIMESTAMP 35 -#define VPU_CTRL_TIMESTAMP_INFO_MODE 36 -#define VPU_INFO_STATISTICS 37 -#define VPU_CTRL_LATENCY 38 -#define VPU_CTRL_LATENCY_MODE 39 - -#define VPU_CTRL_ID_MAX 40 - - -/* - * Extended VPU Controls (large data payloads) - */ -#define VPU_MAX_EXT_DATA_SIZE 720 -struct vpu_control_extended { - /* - * extended control type - * 0: system - * 1: session - */ - __u32 type; - - /* - * size and ptr of the data to send - * maximum VPU_MAX_EXT_DATA_SIZE bytes - */ - __u32 data_len; - void *data_ptr; - - /* - * size and ptr of the buffer to recv data - * maximum VPU_MAX_EXT_DATA_SIZE bytes - */ - __u32 buf_size; - void *buf_ptr; -}; - -/* - * Port specific controls - */ -struct vpu_control_port { - __u32 control_id; - __u32 port; /* 0: INPUT, 1: OUTPUT */ - union control_port_data { - __u32 framerate; - } data; -}; - -/* - * IDs for port controls (use in control_id field of struct vpu_control_port) - * - * VPU_CTRL_FPS: set frame rate, data: __u32, 16.16 format - */ -#define VPU_CTRL_FPS 1000 - - -/* - * V P U D E V I C E P R I V A T E I O C T L C O D E S - */ - -/* VPU Session ioctls (deprecated) */ -#define VPU_ATTACH_TO_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 1), int) - -/* VPU Session ioctls */ -#define VPU_QUERY_SESSIONS _IOR('V', (BASE_VIDIOC_PRIVATE + 0), int) -#define VPU_CREATE_SESSION _IOR('V', (BASE_VIDIOC_PRIVATE + 2), int) -#define VPU_JOIN_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 3), int) - -/* Enable second VPU output port and use with current client */ -#define VPU_CREATE_OUTPUT2 _IO('V', (BASE_VIDIOC_PRIVATE + 5)) - -/* Explicit commit of session configuration */ -#define VPU_COMMIT_CONFIGURATION _IO('V', (BASE_VIDIOC_PRIVATE + 10)) - -/* Flush all buffers of given type (port) */ -#define VPU_FLUSH_BUFS _IOW('V', (BASE_VIDIOC_PRIVATE + 15), \ - enum v4l2_buf_type) - -/* VPU controls get/set ioctls (for most controls with small data) */ -#define VPU_G_CONTROL _IOWR('V', (BASE_VIDIOC_PRIVATE + 20), \ - struct vpu_control) -#define VPU_S_CONTROL _IOW('V', (BASE_VIDIOC_PRIVATE + 21), \ - struct vpu_control) - -/* extended control set/get ioctls (large data payloads) */ -#define VPU_G_CONTROL_EXTENDED _IOWR('V', (BASE_VIDIOC_PRIVATE + 22), \ - struct vpu_control_extended) -#define VPU_S_CONTROL_EXTENDED _IOW('V', (BASE_VIDIOC_PRIVATE + 23), \ - struct vpu_control_extended) - -/* VPU port (input/output) specific controls get/set ioctls */ -#define VPU_G_CONTROL_PORT _IOWR('V', (BASE_VIDIOC_PRIVATE + 24), \ - struct vpu_control_port) -#define VPU_S_CONTROL_PORT _IOW('V', (BASE_VIDIOC_PRIVATE + 25), \ - struct vpu_control_port) - -#endif /* _H_MSM_VPU_H_ */ - diff --git a/sdm710/original-kernel-headers/media/msmb_camera.h b/sdm710/original-kernel-headers/media/msmb_camera.h deleted file mode 100644 index 8bb2f8c4..00000000 --- a/sdm710/original-kernel-headers/media/msmb_camera.h +++ /dev/null @@ -1,234 +0,0 @@ -#ifndef __UAPI_LINUX_MSMB_CAMERA_H -#define __UAPI_LINUX_MSMB_CAMERA_H - -#include <linux/videodev2.h> -#include <linux/types.h> -#include <linux/ioctl.h> -#include <linux/media.h> - -#define MSM_CAM_LOGSYNC_FILE_NAME "logsync" -#define MSM_CAM_LOGSYNC_FILE_BASEDIR "camera" - -#define MSM_CAM_V4L2_IOCTL_NOTIFY \ - _IOW('V', BASE_VIDIOC_PRIVATE + 30, struct msm_v4l2_event_data) - -#define MSM_CAM_V4L2_IOCTL_NOTIFY_META \ - _IOW('V', BASE_VIDIOC_PRIVATE + 31, struct msm_v4l2_event_data) - -#define MSM_CAM_V4L2_IOCTL_CMD_ACK \ - _IOW('V', BASE_VIDIOC_PRIVATE + 32, struct msm_v4l2_event_data) - -#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR \ - _IOW('V', BASE_VIDIOC_PRIVATE + 33, struct msm_v4l2_event_data) - -#define MSM_CAM_V4L2_IOCTL_NOTIFY_DEBUG \ - _IOW('V', BASE_VIDIOC_PRIVATE + 34, struct msm_v4l2_event_data) - -#define MSM_CAM_V4L2_IOCTL_DAEMON_DISABLED \ - _IOW('V', BASE_VIDIOC_PRIVATE + 35, struct msm_v4l2_event_data) - -#define QCAMERA_VNODE_GROUP_ID MEDIA_ENT_F_IO_V4L -#define MSM_CAMERA_NAME "msm_camera" -#define MSM_CONFIGURATION_NAME "msm_config" - -//#define MSM_CAMERA_SUBDEV_BASE (MEDIA_ENT_F_OLD_SUBDEV_BASE + 1) -#define MSM_CAMERA_SUBDEV_BASE (MEDIA_ENT_F_OLD_BASE + 0xF00) -#define MSM_CAMERA_SUBDEV_CSIPHY (MSM_CAMERA_SUBDEV_BASE + 0) -//#define MSM_CAMERA_SUBDEV_CSID (MSM_CAMERA_SUBDEV_BASE + 1) -#define MSM_CAMERA_SUBDEV_CSID (MSM_CAMERA_SUBDEV_BASE + 13) -#define MSM_CAMERA_SUBDEV_ISPIF (MSM_CAMERA_SUBDEV_BASE + 2) -#define MSM_CAMERA_SUBDEV_VFE (MSM_CAMERA_SUBDEV_BASE + 3) -#define MSM_CAMERA_SUBDEV_AXI (MSM_CAMERA_SUBDEV_BASE + 4) -#define MSM_CAMERA_SUBDEV_VPE (MSM_CAMERA_SUBDEV_BASE + 5) -#define MSM_CAMERA_SUBDEV_SENSOR (MSM_CAMERA_SUBDEV_BASE + 6) -#define MSM_CAMERA_SUBDEV_ACTUATOR (MSM_CAMERA_SUBDEV_BASE + 7) -#define MSM_CAMERA_SUBDEV_EEPROM (MSM_CAMERA_SUBDEV_BASE + 8) -#define MSM_CAMERA_SUBDEV_CPP (MSM_CAMERA_SUBDEV_BASE + 9) -#define MSM_CAMERA_SUBDEV_CCI (MSM_CAMERA_SUBDEV_BASE + 10) -#define MSM_CAMERA_SUBDEV_LED_FLASH (MSM_CAMERA_SUBDEV_BASE + 11) -#define MSM_CAMERA_SUBDEV_STROBE_FLASH (MSM_CAMERA_SUBDEV_BASE + 12) -#define MSM_CAMERA_SUBDEV_BUF_MNGR (MSM_CAMERA_SUBDEV_BASE + 1) -//#define MSM_CAMERA_SUBDEV_BUF_MNGR (MSM_CAMERA_SUBDEV_BASE + 13) -#define MSM_CAMERA_SUBDEV_SENSOR_INIT (MSM_CAMERA_SUBDEV_BASE + 14) -#define MSM_CAMERA_SUBDEV_OIS (MSM_CAMERA_SUBDEV_BASE + 15) -#define MSM_CAMERA_SUBDEV_FLASH (MSM_CAMERA_SUBDEV_BASE + 16) -#define MSM_CAMERA_SUBDEV_IR_LED (MSM_CAMERA_SUBDEV_BASE + 17) -#define MSM_CAMERA_SUBDEV_IR_CUT (MSM_CAMERA_SUBDEV_BASE + 18) -#define MSM_CAMERA_SUBDEV_EXT (MSM_CAMERA_SUBDEV_BASE + 19) -#define MSM_CAMERA_SUBDEV_TOF (MSM_CAMERA_SUBDEV_BASE + 20) -#define MSM_CAMERA_SUBDEV_LASER_LED (MSM_CAMERA_SUBDEV_BASE + 21) -#define MSM_MAX_CAMERA_SENSORS 5 - -/* The below macro is defined to put an upper limit on maximum - * number of buffer requested per stream. In case of extremely - * large value for number of buffer due to data structure corruption - * we return error to avoid integer overflow. Group processing - * can have max of 9 groups of 8 bufs each. This value may be - * configured in future - */ -#define MSM_CAMERA_MAX_STREAM_BUF 72 - -/* Max batch size of processing */ -#define MSM_CAMERA_MAX_USER_BUFF_CNT 16 - -/* featur base */ -#define MSM_CAMERA_FEATURE_BASE 0x00010000 -#define MSM_CAMERA_FEATURE_SHUTDOWN (MSM_CAMERA_FEATURE_BASE + 1) - -#define MSM_CAMERA_STATUS_BASE 0x00020000 -#define MSM_CAMERA_STATUS_FAIL (MSM_CAMERA_STATUS_BASE + 1) -#define MSM_CAMERA_STATUS_SUCCESS (MSM_CAMERA_STATUS_BASE + 2) - -/* event type */ -#define MSM_CAMERA_V4L2_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x00002000) - -/* event id */ -#define MSM_CAMERA_EVENT_MIN 0 -#define MSM_CAMERA_NEW_SESSION (MSM_CAMERA_EVENT_MIN + 1) -#define MSM_CAMERA_DEL_SESSION (MSM_CAMERA_EVENT_MIN + 2) -#define MSM_CAMERA_SET_PARM (MSM_CAMERA_EVENT_MIN + 3) -#define MSM_CAMERA_GET_PARM (MSM_CAMERA_EVENT_MIN + 4) -#define MSM_CAMERA_MAPPING_CFG (MSM_CAMERA_EVENT_MIN + 5) -#define MSM_CAMERA_MAPPING_SES (MSM_CAMERA_EVENT_MIN + 6) -#define MSM_CAMERA_MSM_NOTIFY (MSM_CAMERA_EVENT_MIN + 7) -#define MSM_CAMERA_EVENT_MAX (MSM_CAMERA_EVENT_MIN + 8) - -/* data.command */ -#define MSM_CAMERA_PRIV_S_CROP (V4L2_CID_PRIVATE_BASE + 1) -#define MSM_CAMERA_PRIV_G_CROP (V4L2_CID_PRIVATE_BASE + 2) -#define MSM_CAMERA_PRIV_G_FMT (V4L2_CID_PRIVATE_BASE + 3) -#define MSM_CAMERA_PRIV_S_FMT (V4L2_CID_PRIVATE_BASE + 4) -#define MSM_CAMERA_PRIV_TRY_FMT (V4L2_CID_PRIVATE_BASE + 5) -#define MSM_CAMERA_PRIV_METADATA (V4L2_CID_PRIVATE_BASE + 6) -#define MSM_CAMERA_PRIV_QUERY_CAP (V4L2_CID_PRIVATE_BASE + 7) -#define MSM_CAMERA_PRIV_STREAM_ON (V4L2_CID_PRIVATE_BASE + 8) -#define MSM_CAMERA_PRIV_STREAM_OFF (V4L2_CID_PRIVATE_BASE + 9) -#define MSM_CAMERA_PRIV_NEW_STREAM (V4L2_CID_PRIVATE_BASE + 10) -#define MSM_CAMERA_PRIV_DEL_STREAM (V4L2_CID_PRIVATE_BASE + 11) -#define MSM_CAMERA_PRIV_SHUTDOWN (V4L2_CID_PRIVATE_BASE + 12) -#define MSM_CAMERA_PRIV_STREAM_INFO_SYNC \ - (V4L2_CID_PRIVATE_BASE + 13) -#define MSM_CAMERA_PRIV_G_SESSION_ID (V4L2_CID_PRIVATE_BASE + 14) -#define MSM_CAMERA_PRIV_CMD_MAX 20 - -/* data.status - success */ -#define MSM_CAMERA_CMD_SUCCESS 0x00000001 -#define MSM_CAMERA_BUF_MAP_SUCCESS 0x00000002 - -/* data.status - error */ -#define MSM_CAMERA_ERR_EVT_BASE 0x00010000 -#define MSM_CAMERA_ERR_CMD_FAIL (MSM_CAMERA_ERR_EVT_BASE + 1) -#define MSM_CAMERA_ERR_MAPPING (MSM_CAMERA_ERR_EVT_BASE + 2) -#define MSM_CAMERA_ERR_DEVICE_BUSY (MSM_CAMERA_ERR_EVT_BASE + 3) - -/* The msm_v4l2_event_data structure should match the - * v4l2_event.u.data field. - * should not exceed 16 elements - */ -struct msm_v4l2_event_data { - /*word 0*/ - unsigned int command; - /*word 1*/ - unsigned int status; - /*word 2*/ - unsigned int session_id; - /*word 3*/ - unsigned int stream_id; - /*word 4*/ - unsigned int map_op; - /*word 5*/ - unsigned int map_buf_idx; - /*word 6*/ - unsigned int notify; - /*word 7*/ - unsigned int arg_value; - /*word 8*/ - unsigned int ret_value; - /*word 9*/ - unsigned int v4l2_event_type; - /*word 10*/ - unsigned int v4l2_event_id; - /*word 11*/ - unsigned int handle; - /*word 12*/ - unsigned int nop6; - /*word 13*/ - unsigned int nop7; - /*word 14*/ - unsigned int nop8; - /*word 15*/ - unsigned int nop9; -}; - -/* map to v4l2_format.fmt.raw_data */ -struct msm_v4l2_format_data { - enum v4l2_buf_type type; - unsigned int width; - unsigned int height; - unsigned int pixelformat; /* FOURCC */ - unsigned char num_planes; - unsigned int plane_sizes[VIDEO_MAX_PLANES]; -}; - -/* MSM Four-character-code (FOURCC) */ -#define msm_v4l2_fourcc(a, b, c, d)\ - ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) |\ - ((__u32)(d) << 24)) - -/* Composite stats */ -#define MSM_V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M') -/* AEC stats */ -#define MSM_V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E') -/* AF stats */ -#define MSM_V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F') -/* AWB stats */ -#define MSM_V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B') -/* IHIST stats */ -#define MSM_V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T') -/* Column count stats */ -#define MSM_V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S') -/* Row count stats */ -#define MSM_V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S') -/* Bayer Grid stats */ -#define MSM_V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G') -/* Bayer focus stats */ -#define MSM_V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F') -/* Bayer hist stats */ -#define MSM_V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T') - -enum smmu_attach_mode { - NON_SECURE_MODE = 0x01, - SECURE_MODE = 0x02, - MAX_PROTECTION_MODE = 0x03, -}; - -struct msm_camera_smmu_attach_type { - enum smmu_attach_mode attach; -}; - -struct msm_camera_user_buf_cont_t { - unsigned int buf_cnt; - unsigned int buf_idx[MSM_CAMERA_MAX_USER_BUFF_CNT]; -}; - -struct msm_camera_return_buf { - __u32 index; - __u32 reserved; -}; - -#define MSM_CAMERA_PRIV_IOCTL_ID_BASE 0 -#define MSM_CAMERA_PRIV_IOCTL_ID_RETURN_BUF 1 - -struct msm_camera_private_ioctl_arg { - __u32 id; - __u32 size; - __u32 result; - __u32 reserved; - __u64 ioctl_ptr; -}; - -#define VIDIOC_MSM_CAMERA_PRIVATE_IOCTL_CMD \ - _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_private_ioctl_arg) - -#endif - diff --git a/sdm710/original-kernel-headers/media/msmb_generic_buf_mgr.h b/sdm710/original-kernel-headers/media/msmb_generic_buf_mgr.h deleted file mode 100644 index 8dad9ae9..00000000 --- a/sdm710/original-kernel-headers/media/msmb_generic_buf_mgr.h +++ /dev/null @@ -1,68 +0,0 @@ -#ifndef __UAPI_MEDIA_MSMB_GENERIC_BUF_MGR_H__ -#define __UAPI_MEDIA_MSMB_GENERIC_BUF_MGR_H__ - -#include <media/msmb_camera.h> - -enum msm_camera_buf_mngr_cmd { - MSM_CAMERA_BUF_MNGR_CONT_MAP, - MSM_CAMERA_BUF_MNGR_CONT_UNMAP, - MSM_CAMERA_BUF_MNGR_CONT_MAX, -}; - -enum msm_camera_buf_mngr_buf_type { - MSM_CAMERA_BUF_MNGR_BUF_PLANAR, - MSM_CAMERA_BUF_MNGR_BUF_USER, - MSM_CAMERA_BUF_MNGR_BUF_INVALID, -}; - -struct msm_buf_mngr_info { - uint32_t session_id; - uint32_t stream_id; - uint32_t frame_id; - struct timeval timestamp; - uint32_t index; - uint32_t reserved; - enum msm_camera_buf_mngr_buf_type type; - struct msm_camera_user_buf_cont_t user_buf; -}; - -struct msm_buf_mngr_main_cont_info { - uint32_t session_id; - uint32_t stream_id; - enum msm_camera_buf_mngr_cmd cmd; - uint32_t cnt; - int32_t cont_fd; -}; - -#define MSM_CAMERA_BUF_MNGR_IOCTL_ID_BASE 0 -#define MSM_CAMERA_BUF_MNGR_IOCTL_ID_GET_BUF_BY_IDX 1 - -#define VIDIOC_MSM_BUF_MNGR_GET_BUF \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 33, struct msm_buf_mngr_info) - -#define VIDIOC_MSM_BUF_MNGR_PUT_BUF \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 34, struct msm_buf_mngr_info) - -#define VIDIOC_MSM_BUF_MNGR_BUF_DONE \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct msm_buf_mngr_info) - -#define VIDIOC_MSM_BUF_MNGR_CONT_CMD \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 36, struct msm_buf_mngr_main_cont_info) - -#define VIDIOC_MSM_BUF_MNGR_INIT \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 37, struct msm_buf_mngr_info) - -#define VIDIOC_MSM_BUF_MNGR_DEINIT \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 38, struct msm_buf_mngr_info) - -#define VIDIOC_MSM_BUF_MNGR_FLUSH \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 39, struct msm_buf_mngr_info) - -#define VIDIOC_MSM_BUF_MNGR_IOCTL_CMD \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 40, \ - struct msm_camera_private_ioctl_arg) - -#define VIDIOC_MSM_BUF_MNGR_BUF_ERROR \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 41, struct msm_buf_mngr_info) -#endif - diff --git a/sdm710/original-kernel-headers/media/msmb_isp.h b/sdm710/original-kernel-headers/media/msmb_isp.h deleted file mode 100644 index 0ec0e696..00000000 --- a/sdm710/original-kernel-headers/media/msmb_isp.h +++ /dev/null @@ -1,1046 +0,0 @@ -#ifndef __UAPI_MSMB_ISP__ -#define __UAPI_MSMB_ISP__ - -#include <linux/videodev2.h> -#include <media/msmb_camera.h> - -#define MAX_PLANES_PER_STREAM 3 -#define MAX_NUM_STREAM 7 - -#define ISP_VERSION_48 48 -#define ISP_VERSION_47 47 -#define ISP_VERSION_46 46 -#define ISP_VERSION_44 44 -#define ISP_VERSION_40 40 -#define ISP_VERSION_32 32 -#define ISP_NATIVE_BUF_BIT (0x10000 << 0) -#define ISP0_BIT (0x10000 << 1) -#define ISP1_BIT (0x10000 << 2) -#define ISP_META_CHANNEL_BIT (0x10000 << 3) -#define ISP_SCRATCH_BUF_BIT (0x10000 << 4) -#define ISP_OFFLINE_STATS_BIT (0x10000 << 5) -#define ISP_SVHDR_IN_BIT (0x10000 << 6) /* RDI hw stream for SVHDR */ -#define ISP_SVHDR_OUT_BIT (0x10000 << 7) /* SVHDR output bufq stream*/ - -#define ISP_STATS_STREAM_BIT 0x80000000 - -#define VFE_HW_LIMIT 1 - -struct msm_vfe_cfg_cmd_list; - -enum ISP_START_PIXEL_PATTERN { - ISP_BAYER_RGRGRG, - ISP_BAYER_GRGRGR, - ISP_BAYER_BGBGBG, - ISP_BAYER_GBGBGB, - ISP_YUV_YCbYCr, - ISP_YUV_YCrYCb, - ISP_YUV_CbYCrY, - ISP_YUV_CrYCbY, - ISP_PIX_PATTERN_MAX -}; - -enum msm_vfe_plane_fmt { - Y_PLANE, - CB_PLANE, - CR_PLANE, - CRCB_PLANE, - CBCR_PLANE, - VFE_PLANE_FMT_MAX -}; - -enum msm_vfe_input_src { - VFE_PIX_0, - VFE_RAW_0, - VFE_RAW_1, - VFE_RAW_2, - VFE_SRC_MAX, -}; - -enum msm_vfe_axi_stream_src { - PIX_ENCODER, - PIX_VIEWFINDER, - PIX_VIDEO, - CAMIF_RAW, - IDEAL_RAW, - RDI_INTF_0, - RDI_INTF_1, - RDI_INTF_2, - VFE_AXI_SRC_MAX -}; - -enum msm_vfe_frame_skip_pattern { - NO_SKIP, - EVERY_2FRAME, - EVERY_3FRAME, - EVERY_4FRAME, - EVERY_5FRAME, - EVERY_6FRAME, - EVERY_7FRAME, - EVERY_8FRAME, - EVERY_16FRAME, - EVERY_32FRAME, - SKIP_ALL, - SKIP_RANGE, - MAX_SKIP, -}; - -/* - * Define an unused period. When this period is set it means that the stream is - * stopped(i.e the pattern is 0). We don't track the current pattern, just the - * period defines what the pattern is, if period is this then pattern is 0 else - * pattern is 1 - */ -#define MSM_VFE_STREAM_STOP_PERIOD 15 - -enum msm_isp_stats_type { - MSM_ISP_STATS_AEC, /* legacy based AEC */ - MSM_ISP_STATS_AF, /* legacy based AF */ - MSM_ISP_STATS_AWB, /* legacy based AWB */ - MSM_ISP_STATS_RS, /* legacy based RS */ - MSM_ISP_STATS_CS, /* legacy based CS */ - MSM_ISP_STATS_IHIST, /* legacy based HIST */ - MSM_ISP_STATS_SKIN, /* legacy based SKIN */ - MSM_ISP_STATS_BG, /* Bayer Grids */ - MSM_ISP_STATS_BF, /* Bayer Focus */ - MSM_ISP_STATS_BE, /* Bayer Exposure*/ - MSM_ISP_STATS_BHIST, /* Bayer Hist */ - MSM_ISP_STATS_BF_SCALE, /* Bayer Focus scale */ - MSM_ISP_STATS_HDR_BE, /* HDR Bayer Exposure */ - MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */ - MSM_ISP_STATS_AEC_BG, /* AEC BG */ - MSM_ISP_STATS_MAX /* MAX */ -}; - -/* - * @stats_type_mask: Stats type mask (enum msm_isp_stats_type). - * @stream_src_mask: Stream src mask (enum msm_vfe_axi_stream_src) - * @skip_mode: skip pattern, if skip mode is range only then min/max is used - * @min_frame_id: minimum frame id (valid only if skip_mode = RANGE) - * @max_frame_id: maximum frame id (valid only if skip_mode = RANGE) - */ -struct msm_isp_sw_framskip { - uint32_t stats_type_mask; - uint32_t stream_src_mask; - enum msm_vfe_frame_skip_pattern skip_mode; - uint32_t min_frame_id; - uint32_t max_frame_id; -}; - -enum msm_vfe_testgen_color_pattern { - COLOR_BAR_8_COLOR, - UNICOLOR_WHITE, - UNICOLOR_YELLOW, - UNICOLOR_CYAN, - UNICOLOR_GREEN, - UNICOLOR_MAGENTA, - UNICOLOR_RED, - UNICOLOR_BLUE, - UNICOLOR_BLACK, - MAX_COLOR, -}; - -enum msm_vfe_camif_input { - CAMIF_DISABLED, - CAMIF_PAD_REG_INPUT, - CAMIF_MIDDI_INPUT, - CAMIF_MIPI_INPUT, -}; - -struct msm_vfe_fetch_engine_cfg { - uint32_t input_format; - uint32_t buf_width; - uint32_t buf_height; - uint32_t fetch_width; - uint32_t fetch_height; - uint32_t x_offset; - uint32_t y_offset; - uint32_t buf_stride; -}; - -enum msm_vfe_camif_output_format { - CAMIF_QCOM_RAW, - CAMIF_MIPI_RAW, - CAMIF_PLAIN_8, - CAMIF_PLAIN_16, - CAMIF_MAX_FORMAT, -}; - -/* - * Camif output general configuration - */ -struct msm_vfe_camif_subsample_cfg { - uint32_t irq_subsample_period; - uint32_t irq_subsample_pattern; - uint32_t sof_counter_step; - uint32_t pixel_skip; - uint32_t line_skip; - uint32_t first_line; - uint32_t last_line; - uint32_t first_pixel; - uint32_t last_pixel; - enum msm_vfe_camif_output_format output_format; -}; - -/* - * Camif frame and window configuration - */ -struct msm_vfe_camif_cfg { - uint32_t lines_per_frame; - uint32_t pixels_per_line; - uint32_t first_pixel; - uint32_t last_pixel; - uint32_t first_line; - uint32_t last_line; - uint32_t epoch_line0; - uint32_t epoch_line1; - uint32_t is_split; - enum msm_vfe_camif_input camif_input; - struct msm_vfe_camif_subsample_cfg subsample_cfg; -}; - -struct msm_vfe_testgen_cfg { - uint32_t lines_per_frame; - uint32_t pixels_per_line; - uint32_t v_blank; - uint32_t h_blank; - enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern; - uint32_t rotate_period; - enum msm_vfe_testgen_color_pattern color_bar_pattern; - uint32_t burst_num_frame; -}; - -enum msm_vfe_inputmux { - CAMIF, - TESTGEN, - EXTERNAL_READ, -}; - -enum msm_vfe_stats_composite_group { - STATS_COMPOSITE_GRP_NONE, - STATS_COMPOSITE_GRP_1, - STATS_COMPOSITE_GRP_2, - STATS_COMPOSITE_GRP_MAX, -}; - -enum msm_vfe_hvx_streaming_cmd { - HVX_DISABLE, - HVX_ONE_WAY, - HVX_ROUND_TRIP -}; - -struct msm_vfe_pix_cfg { - struct msm_vfe_camif_cfg camif_cfg; - struct msm_vfe_testgen_cfg testgen_cfg; - struct msm_vfe_fetch_engine_cfg fetch_engine_cfg; - enum msm_vfe_inputmux input_mux; - enum ISP_START_PIXEL_PATTERN pixel_pattern; - uint32_t input_format; - enum msm_vfe_hvx_streaming_cmd hvx_cmd; - uint32_t is_split; -}; - -struct msm_vfe_rdi_cfg { - uint8_t cid; - uint8_t frame_based; -}; - -struct msm_vfe_input_cfg { - union { - struct msm_vfe_pix_cfg pix_cfg; - struct msm_vfe_rdi_cfg rdi_cfg; - } d; - enum msm_vfe_input_src input_src; - uint32_t input_pix_clk; -}; - -struct msm_vfe_fetch_eng_start { - uint32_t session_id; - uint32_t stream_id; - uint32_t buf_idx; - uint8_t offline_mode; - uint32_t fd; - uint32_t buf_addr; - uint32_t frame_id; -}; - -enum msm_vfe_fetch_eng_pass { - OFFLINE_FIRST_PASS, - OFFLINE_SECOND_PASS, - OFFLINE_MAX_PASS, -}; - -struct msm_vfe_fetch_eng_multi_pass_start { - uint32_t session_id; - uint32_t stream_id; - uint32_t buf_idx; - uint8_t offline_mode; - uint32_t fd; - uint32_t buf_addr; - uint32_t frame_id; - uint32_t output_buf_idx; - uint32_t input_buf_offset; - enum msm_vfe_fetch_eng_pass offline_pass; - uint32_t output_stream_id; -}; - -struct msm_vfe_axi_plane_cfg { - uint32_t output_width; /*Include padding*/ - uint32_t output_height; - uint32_t output_stride; - uint32_t output_scan_lines; - uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/ - uint32_t plane_addr_offset; - uint8_t csid_src; /*RDI 0-2*/ - uint8_t rdi_cid;/*CID 1-16*/ -}; - -enum msm_stream_rdi_input_type { - MSM_CAMERA_RDI_MIN, - MSM_CAMERA_RDI_PDAF, - MSM_CAMERA_RDI_MAX, -}; - -struct msm_vfe_axi_stream_request_cmd { - uint32_t session_id; - uint32_t stream_id; - uint32_t vt_enable; - uint32_t output_format;/*Planar/RAW/Misc*/ - enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/ - struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; - - uint32_t burst_count; - uint32_t hfr_mode; - uint8_t frame_base; - - uint32_t init_frame_drop; /*MAX 31 Frames*/ - enum msm_vfe_frame_skip_pattern frame_skip_pattern; - uint8_t buf_divert; /* if TRUE no vb2 buf done. */ - /*Return values*/ - uint32_t axi_stream_handle; - uint32_t controllable_output; - uint32_t burst_len; - /* Flag indicating memory input stream */ - enum msm_stream_rdi_input_type rdi_input_type; -}; - -struct msm_vfe_axi_stream_release_cmd { - uint32_t stream_handle; -}; - -enum msm_vfe_axi_stream_cmd { - STOP_STREAM, - START_STREAM, - STOP_IMMEDIATELY, -}; - -struct msm_vfe_axi_stream_cfg_cmd { - uint8_t num_streams; - uint32_t stream_handle[VFE_AXI_SRC_MAX]; - enum msm_vfe_axi_stream_cmd cmd; - uint8_t sync_frame_id_src; -}; - -enum msm_vfe_axi_stream_update_type { - ENABLE_STREAM_BUF_DIVERT, - DISABLE_STREAM_BUF_DIVERT, - UPDATE_STREAM_FRAMEDROP_PATTERN, - UPDATE_STREAM_STATS_FRAMEDROP_PATTERN, - UPDATE_STREAM_AXI_CONFIG, - UPDATE_STREAM_REQUEST_FRAMES, - UPDATE_STREAM_ADD_BUFQ, - UPDATE_STREAM_REMOVE_BUFQ, - UPDATE_STREAM_SW_FRAME_DROP, - UPDATE_STREAM_REQUEST_FRAMES_VER2, - UPDATE_STREAM_OFFLINE_AXI_CONFIG, -}; -#define UPDATE_STREAM_REQUEST_FRAMES_VER2 UPDATE_STREAM_REQUEST_FRAMES_VER2 - -enum msm_vfe_iommu_type { - IOMMU_ATTACH, - IOMMU_DETACH, -}; - -enum msm_vfe_buff_queue_id { - VFE_BUF_QUEUE_DEFAULT, - VFE_BUF_QUEUE_SHARED, - VFE_BUF_QUEUE_MAX, -}; - -struct msm_vfe_axi_stream_cfg_update_info { - uint32_t stream_handle; - uint32_t output_format; - uint32_t user_stream_id; - uint32_t frame_id; - enum msm_vfe_frame_skip_pattern skip_pattern; - struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; - struct msm_isp_sw_framskip sw_skip_info; -}; - -struct msm_vfe_axi_stream_cfg_update_info_req_frm { - uint32_t stream_handle; - uint32_t user_stream_id; - uint32_t frame_id; - uint32_t buf_index; -}; - -struct msm_vfe_axi_halt_cmd { - uint32_t stop_camif; - uint32_t overflow_detected; - uint32_t blocking_halt; -}; - -struct msm_vfe_axi_reset_cmd { - uint32_t blocking; - uint32_t frame_id; -}; - -struct msm_vfe_axi_restart_cmd { - uint32_t enable_camif; -}; - -struct msm_vfe_axi_stream_update_cmd { - uint32_t num_streams; - enum msm_vfe_axi_stream_update_type update_type; - /* - * For backward compatibility, ensure 1st member of any struct - * in union below is uint32_t stream_handle. - */ - union { - struct msm_vfe_axi_stream_cfg_update_info - update_info[MSM_ISP_STATS_MAX]; - struct msm_vfe_axi_stream_cfg_update_info_req_frm req_frm_ver2; - }; -}; - -struct msm_vfe_smmu_attach_cmd { - uint32_t security_mode; - uint32_t iommu_attach_mode; -}; - -struct msm_vfe_stats_stream_request_cmd { - uint32_t session_id; - uint32_t stream_id; - enum msm_isp_stats_type stats_type; - uint32_t composite_flag; - uint32_t framedrop_pattern; - uint32_t init_frame_drop; /*MAX 31 Frames*/ - uint32_t irq_subsample_pattern; - uint32_t buffer_offset; - uint32_t stream_handle; -}; - -struct msm_vfe_stats_stream_release_cmd { - uint32_t stream_handle; -}; -struct msm_vfe_stats_stream_cfg_cmd { - uint8_t num_streams; - uint32_t stream_handle[MSM_ISP_STATS_MAX]; - uint8_t enable; - uint32_t stats_burst_len; -}; - -enum msm_vfe_reg_cfg_type { - VFE_WRITE, - VFE_WRITE_MB, - VFE_READ, - VFE_CFG_MASK, - VFE_WRITE_DMI_16BIT, - VFE_WRITE_DMI_32BIT, - VFE_WRITE_DMI_64BIT, - VFE_READ_DMI_16BIT, - VFE_READ_DMI_32BIT, - VFE_READ_DMI_64BIT, - GET_MAX_CLK_RATE, - GET_CLK_RATES, - GET_ISP_ID, - VFE_HW_UPDATE_LOCK, - VFE_HW_UPDATE_UNLOCK, - SET_WM_UB_SIZE, - SET_UB_POLICY, - GET_VFE_HW_LIMIT, -}; - -struct msm_vfe_cfg_cmd2 { - uint16_t num_cfg; - uint16_t cmd_len; - void *cfg_data; - void *cfg_cmd; -}; - -struct msm_vfe_cfg_cmd_list { - struct msm_vfe_cfg_cmd2 cfg_cmd; - struct msm_vfe_cfg_cmd_list *next; - uint32_t next_size; -}; - -struct msm_vfe_reg_rw_info { - uint32_t reg_offset; - uint32_t cmd_data_offset; - uint32_t len; -}; - -struct msm_vfe_reg_mask_info { - uint32_t reg_offset; - uint32_t mask; - uint32_t val; -}; - -struct msm_vfe_reg_dmi_info { - uint32_t hi_tbl_offset; /*Optional*/ - uint32_t lo_tbl_offset; /*Required*/ - uint32_t len; -}; - -struct msm_vfe_reg_cfg_cmd { - union { - struct msm_vfe_reg_rw_info rw_info; - struct msm_vfe_reg_mask_info mask_info; - struct msm_vfe_reg_dmi_info dmi_info; - } u; - - enum msm_vfe_reg_cfg_type cmd_type; -}; - -enum vfe_sd_type { - VFE_SD_0 = 0, - VFE_SD_1, - VFE_SD_COMMON, - VFE_SD_MAX, -}; - -/* When you change the value below, check for the sof event_data size. - * V4l2 limits payload to 64 bytes - */ -#define MS_NUM_SLAVE_MAX 1 - -/* Usecases when 2 HW need to be related or synced */ -enum msm_vfe_dual_hw_type { - DUAL_NONE = 0, - DUAL_HW_VFE_SPLIT = 1, - DUAL_HW_MASTER_SLAVE = 2, -}; - -/* Type for 2 INTF when used in Master-Slave mode */ -enum msm_vfe_dual_hw_ms_type { - MS_TYPE_NONE, - MS_TYPE_MASTER, - MS_TYPE_SLAVE, -}; - -struct msm_isp_set_dual_hw_ms_cmd { - uint8_t num_src; - /* Each session can be only one type but multiple intf if YUV cam */ - enum msm_vfe_dual_hw_ms_type dual_hw_ms_type; - /* Primary intf is mostly associated with preview. - * This primary intf SOF frame_id and timestamp is tracked - * and used to calculate delta - */ - enum msm_vfe_input_src primary_intf; - /* input_src array indicates other input INTF that may be Master/Slave. - * For these additional intf, frame_id and timestamp are not saved. - * However, if these are slaves then they will still get their - * frame_id from Master - */ - enum msm_vfe_input_src input_src[VFE_SRC_MAX]; - uint32_t sof_delta_threshold; /* In milliseconds. Sent for Master */ -}; - -enum msm_isp_buf_type { - ISP_PRIVATE_BUF, - ISP_SHARE_BUF, - MAX_ISP_BUF_TYPE, -}; - -struct msm_isp_unmap_buf_req { - uint32_t fd; -}; - -struct msm_isp_buf_request { - uint32_t session_id; - uint32_t stream_id; - uint8_t num_buf; - uint32_t handle; - enum msm_isp_buf_type buf_type; -}; - -struct msm_isp_buf_request_ver2 { - uint32_t session_id; - uint32_t stream_id; - uint8_t num_buf; - uint32_t handle; - enum msm_isp_buf_type buf_type; - enum smmu_attach_mode security_mode; - uint32_t reserved[4]; -}; - -struct msm_isp_qbuf_plane { - uint32_t addr; - uint32_t offset; - uint32_t length; -}; - -struct msm_isp_qbuf_buffer { - struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM]; - uint32_t num_planes; -}; - -struct msm_isp_qbuf_info { - uint32_t handle; - int32_t buf_idx; - /*Only used for prepare buffer*/ - struct msm_isp_qbuf_buffer buffer; - /*Only used for diverted buffer*/ - uint32_t dirty_buf; -}; - -struct msm_isp_clk_rates { - uint32_t svs_rate; - uint32_t nominal_rate; - uint32_t high_rate; -}; - -struct msm_vfe_axi_src_state { - enum msm_vfe_input_src input_src; - uint32_t src_active; - uint32_t src_frame_id; -}; - -enum msm_isp_event_mask_index { - ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0, - ISP_EVENT_MASK_INDEX_ERROR = 1, - ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2, - ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3, - ISP_EVENT_MASK_INDEX_REG_UPDATE = 4, - ISP_EVENT_MASK_INDEX_SOF = 5, - ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6, - ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7, - ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8, - ISP_EVENT_MASK_INDEX_BUF_DONE = 9, - ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING = 10, - ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH = 11, - ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR = 12, -}; - - -#define ISP_EVENT_SUBS_MASK_NONE 0 - -#define ISP_EVENT_SUBS_MASK_STATS_NOTIFY \ - (1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY) - -#define ISP_EVENT_SUBS_MASK_ERROR \ - (1 << ISP_EVENT_MASK_INDEX_ERROR) - -#define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT \ - (1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT) - -#define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE \ - (1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE) - -#define ISP_EVENT_SUBS_MASK_REG_UPDATE \ - (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE) - -#define ISP_EVENT_SUBS_MASK_SOF \ - (1 << ISP_EVENT_MASK_INDEX_SOF) - -#define ISP_EVENT_SUBS_MASK_BUF_DIVERT \ - (1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT) - -#define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY \ - (1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY) - -#define ISP_EVENT_SUBS_MASK_FE_READ_DONE \ - (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE) - -#define ISP_EVENT_SUBS_MASK_BUF_DONE \ - (1 << ISP_EVENT_MASK_INDEX_BUF_DONE) - -#define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING \ - (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING) - -#define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH \ - (1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH) - -#define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR \ - (1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR) - -enum msm_isp_event_idx { - ISP_REG_UPDATE = 0, - ISP_EPOCH_0 = 1, - ISP_EPOCH_1 = 2, - ISP_START_ACK = 3, - ISP_STOP_ACK = 4, - ISP_IRQ_VIOLATION = 5, - ISP_STATS_OVERFLOW = 6, - ISP_BUF_DONE = 7, - ISP_FE_RD_DONE = 8, - ISP_IOMMU_P_FAULT = 9, - ISP_ERROR = 10, - ISP_HW_FATAL_ERROR = 11, - ISP_PING_PONG_MISMATCH = 12, - ISP_REG_UPDATE_MISSING = 13, - ISP_BUF_FATAL_ERROR = 14, - ISP_EVENT_MAX = 15 -}; - -#define ISP_EVENT_OFFSET 8 -#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) -#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) -#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) -#define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET)) -#define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET)) -#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) -#define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0) -#define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1) -#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) -#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) -#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) -#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) -#define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR) -#define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE) -#define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1) -#define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE) -#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) -#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) -#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) -#define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE) -#define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT) -#define ISP_EVENT_HW_FATAL_ERROR (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR) -#define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH) -#define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING) -#define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR) -#define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE) - -/* The msm_v4l2_event_data structure should match the - * v4l2_event.u.data field. - * should not exceed 64 bytes - */ - -struct msm_isp_buf_event { - uint32_t session_id; - uint32_t stream_id; - uint32_t handle; - uint32_t output_format; - int8_t buf_idx; -}; -struct msm_isp_fetch_eng_event { - uint32_t session_id; - uint32_t stream_id; - uint32_t handle; - uint32_t fd; - int8_t buf_idx; - int8_t offline_mode; -}; -struct msm_isp_stats_event { - uint32_t stats_mask; /* 4 bytes */ - uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */ - uint8_t pd_stats_idx; -}; - -struct msm_isp_stream_ack { - uint32_t session_id; - uint32_t stream_id; - uint32_t handle; -}; - -enum msm_vfe_error_type { - ISP_ERROR_NONE, - ISP_ERROR_CAMIF, - ISP_ERROR_BUS_OVERFLOW, - ISP_ERROR_RETURN_EMPTY_BUFFER, - ISP_ERROR_FRAME_ID_MISMATCH, - ISP_ERROR_MAX, -}; - -struct msm_isp_error_info { - enum msm_vfe_error_type err_type; - uint32_t session_id; - uint32_t stream_id; - uint32_t stream_id_mask; -}; - -/* This structure reports delta between master and slave */ -struct msm_isp_ms_delta_info { - uint8_t num_delta_info; - uint32_t delta[MS_NUM_SLAVE_MAX]; -}; - -/* This is sent in EPOCH irq */ -struct msm_isp_output_info { - uint8_t regs_not_updated; - /* mask with bufq_handle for regs not updated or return empty */ - uint16_t output_err_mask; - /* mask with stream_idx for get_buf failed */ - uint8_t stream_framedrop_mask; - /* mask with stats stream_idx for get_buf failed */ - uint16_t stats_framedrop_mask; - /* delta between master and slave */ -}; - -/* This structure is piggybacked with SOF event */ -struct msm_isp_sof_info { - uint8_t regs_not_updated; - /* mask with bufq_handle for regs not updated */ - uint16_t reg_update_fail_mask; - /* mask with bufq_handle for get_buf failed */ - uint32_t stream_get_buf_fail_mask; - /* mask with stats stream_idx for get_buf failed */ - uint16_t stats_get_buf_fail_mask; - /* delta between master and slave */ - struct msm_isp_ms_delta_info ms_delta_info; - /* - * mask with AXI_SRC in paused state. In PAUSED - * state there is no Buffer output. So this mask is used - * to report drop. - */ - uint16_t axi_updating_mask; - /* extended mask with bufq_handle for regs not updated */ - uint32_t reg_update_fail_mask_ext; -}; -#define AXI_UPDATING_MASK 1 -#define REG_UPDATE_FAIL_MASK_EXT 1 - -struct msm_isp_event_data { - /*Wall clock except for buffer divert events - *which use monotonic clock - */ - struct timeval timestamp; - /* Monotonic timestamp since bootup */ - struct timeval mono_timestamp; - uint32_t frame_id; - union { - /* Sent for Stats_Done event */ - struct msm_isp_stats_event stats; - /* Sent for Buf_Divert event */ - struct msm_isp_buf_event buf_done; - /* Sent for offline fetch done event */ - struct msm_isp_fetch_eng_event fetch_done; - /* Sent for Error_Event */ - struct msm_isp_error_info error_info; - /* - * This struct needs to be removed once - * userspace switches to sof_info - */ - struct msm_isp_output_info output_info; - /* Sent for SOF event */ - struct msm_isp_sof_info sof_info; - } u; /* union can have max 52 bytes */ -}; - -enum msm_vfe_ahb_clk_vote { - MSM_ISP_CAMERA_AHB_SVS_VOTE = 1, - MSM_ISP_CAMERA_AHB_TURBO_VOTE = 2, - MSM_ISP_CAMERA_AHB_NOMINAL_VOTE = 3, - MSM_ISP_CAMERA_AHB_SUSPEND_VOTE = 4, -}; - -struct msm_isp_ahb_clk_cfg { - uint32_t vote; - uint32_t reserved[2]; -}; - -enum msm_vfe_dual_cam_sync_mode { - MSM_ISP_DUAL_CAM_ASYNC, - MSM_ISP_DUAL_CAM_SYNC, -}; - -struct msm_isp_dual_hw_master_slave_sync { - uint32_t sync_mode; - uint32_t reserved[2]; -}; - -struct msm_vfe_dual_lpm_mode { - enum msm_vfe_axi_stream_src stream_src[VFE_AXI_SRC_MAX]; - uint32_t num_src; - uint32_t lpm_mode; -}; -#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') -#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') -#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') -#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') -#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') -#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') -#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') -#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') -#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') -#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') -#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') -#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') -#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4') -#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4') -#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4') -#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4') -#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0') -#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0') -#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0') -#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0') -#define V4L2_PIX_FMT_P16BGGR12 v4l2_fourcc('P', 'B', 'G', '2') -#define V4L2_PIX_FMT_P16GBRG12 v4l2_fourcc('P', 'G', 'B', '2') -#define V4L2_PIX_FMT_P16GRBG12 v4l2_fourcc('P', 'G', 'R', '2') -#define V4L2_PIX_FMT_P16RGGB12 v4l2_fourcc('P', 'R', 'G', '2') -#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4') -#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1') -#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T') -#define V4L2_PIX_FMT_META10 v4l2_fourcc('Q', 'M', '1', '0') -#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.GRGR.*/ -#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.RGRG.*/ -#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') /* 14 GRGR.BGBG.*/ -#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.GBGB.*/ - -enum msm_isp_ioctl_cmd_code { - MSM_VFE_REG_CFG = BASE_VIDIOC_PRIVATE, - MSM_ISP_REQUEST_BUF, - MSM_ISP_ENQUEUE_BUF, - MSM_ISP_RELEASE_BUF, - MSM_ISP_REQUEST_STREAM, - MSM_ISP_CFG_STREAM, - MSM_ISP_RELEASE_STREAM, - MSM_ISP_INPUT_CFG, - MSM_ISP_SET_SRC_STATE, - MSM_ISP_REQUEST_STATS_STREAM, - MSM_ISP_CFG_STATS_STREAM, - MSM_ISP_RELEASE_STATS_STREAM, - MSM_ISP_REG_UPDATE_CMD, - MSM_ISP_UPDATE_STREAM, - MSM_VFE_REG_LIST_CFG, - MSM_ISP_SMMU_ATTACH, - MSM_ISP_UPDATE_STATS_STREAM, - MSM_ISP_AXI_HALT, - MSM_ISP_AXI_RESET, - MSM_ISP_AXI_RESTART, - MSM_ISP_FETCH_ENG_START, - MSM_ISP_DEQUEUE_BUF, - MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, - MSM_ISP_MAP_BUF_START_FE, - MSM_ISP_UNMAP_BUF, - MSM_ISP_AHB_CLK_CFG, - MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, - MSM_ISP_FETCH_ENG_MULTI_PASS_START, - MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, - MSM_ISP_REQUEST_BUF_VER2, - MSM_ISP_DUAL_HW_LPM_MODE, -}; - -#define VIDIOC_MSM_VFE_REG_CFG \ - _IOWR('V', MSM_VFE_REG_CFG, \ - struct msm_vfe_cfg_cmd2) - -#define VIDIOC_MSM_ISP_REQUEST_BUF \ - _IOWR('V', MSM_ISP_REQUEST_BUF, \ - struct msm_isp_buf_request) - -#define VIDIOC_MSM_ISP_ENQUEUE_BUF \ - _IOWR('V', MSM_ISP_ENQUEUE_BUF, \ - struct msm_isp_qbuf_info) - -#define VIDIOC_MSM_ISP_RELEASE_BUF \ - _IOWR('V', MSM_ISP_RELEASE_BUF, \ - struct msm_isp_buf_request) - -#define VIDIOC_MSM_ISP_REQUEST_STREAM \ - _IOWR('V', MSM_ISP_REQUEST_STREAM, \ - struct msm_vfe_axi_stream_request_cmd) - -#define VIDIOC_MSM_ISP_CFG_STREAM \ - _IOWR('V', MSM_ISP_CFG_STREAM, \ - struct msm_vfe_axi_stream_cfg_cmd) - -#define VIDIOC_MSM_ISP_RELEASE_STREAM \ - _IOWR('V', MSM_ISP_RELEASE_STREAM, \ - struct msm_vfe_axi_stream_release_cmd) - -#define VIDIOC_MSM_ISP_INPUT_CFG \ - _IOWR('V', MSM_ISP_INPUT_CFG, \ - struct msm_vfe_input_cfg) - -#define VIDIOC_MSM_ISP_SET_SRC_STATE \ - _IOWR('V', MSM_ISP_SET_SRC_STATE, \ - struct msm_vfe_axi_src_state) - -#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \ - _IOWR('V', MSM_ISP_REQUEST_STATS_STREAM, \ - struct msm_vfe_stats_stream_request_cmd) - -#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \ - _IOWR('V', MSM_ISP_CFG_STATS_STREAM, \ - struct msm_vfe_stats_stream_cfg_cmd) - -#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \ - _IOWR('V', MSM_ISP_RELEASE_STATS_STREAM, \ - struct msm_vfe_stats_stream_release_cmd) - -#define VIDIOC_MSM_ISP_REG_UPDATE_CMD \ - _IOWR('V', MSM_ISP_REG_UPDATE_CMD, \ - enum msm_vfe_input_src) - -#define VIDIOC_MSM_ISP_UPDATE_STREAM \ - _IOWR('V', MSM_ISP_UPDATE_STREAM, \ - struct msm_vfe_axi_stream_update_cmd) - -#define VIDIOC_MSM_VFE_REG_LIST_CFG \ - _IOWR('V', MSM_VFE_REG_LIST_CFG, \ - struct msm_vfe_cfg_cmd_list) - -#define VIDIOC_MSM_ISP_SMMU_ATTACH \ - _IOWR('V', MSM_ISP_SMMU_ATTACH, \ - struct msm_vfe_smmu_attach_cmd) - -#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \ - _IOWR('V', MSM_ISP_UPDATE_STATS_STREAM, \ - struct msm_vfe_axi_stream_update_cmd) - -#define VIDIOC_MSM_ISP_AXI_HALT \ - _IOWR('V', MSM_ISP_AXI_HALT, \ - struct msm_vfe_axi_halt_cmd) - -#define VIDIOC_MSM_ISP_AXI_RESET \ - _IOWR('V', MSM_ISP_AXI_RESET, \ - struct msm_vfe_axi_reset_cmd) - -#define VIDIOC_MSM_ISP_AXI_RESTART \ - _IOWR('V', MSM_ISP_AXI_RESTART, \ - struct msm_vfe_axi_restart_cmd) - -#define VIDIOC_MSM_ISP_FETCH_ENG_START \ - _IOWR('V', MSM_ISP_FETCH_ENG_START, \ - struct msm_vfe_fetch_eng_start) - -#define VIDIOC_MSM_ISP_DEQUEUE_BUF \ - _IOWR('V', MSM_ISP_DEQUEUE_BUF, \ - struct msm_isp_qbuf_info) - -#define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE \ - _IOWR('V', MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, \ - struct msm_isp_set_dual_hw_ms_cmd) - -#define VIDIOC_MSM_ISP_MAP_BUF_START_FE \ - _IOWR('V', MSM_ISP_MAP_BUF_START_FE, \ - struct msm_vfe_fetch_eng_start) - -#define VIDIOC_MSM_ISP_UNMAP_BUF \ - _IOWR('V', MSM_ISP_UNMAP_BUF, \ - struct msm_isp_unmap_buf_req) - -#define VIDIOC_MSM_ISP_AHB_CLK_CFG \ - _IOWR('V', MSM_ISP_AHB_CLK_CFG, struct msm_isp_ahb_clk_cfg) - -#define VIDIOC_MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC \ - _IOWR('V', MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, \ - struct msm_isp_dual_hw_master_slave_sync) - -#define VIDIOC_MSM_ISP_FETCH_ENG_MULTI_PASS_START \ - _IOWR('V', MSM_ISP_FETCH_ENG_MULTI_PASS_START, \ - struct msm_vfe_fetch_eng_multi_pass_start) - -#define VIDIOC_MSM_ISP_MAP_BUF_START_MULTI_PASS_FE \ - _IOWR('V', MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, \ - struct msm_vfe_fetch_eng_multi_pass_start) - -#define VIDIOC_MSM_ISP_REQUEST_BUF_VER2 \ - _IOWR('V', MSM_ISP_REQUEST_BUF_VER2, struct msm_isp_buf_request_ver2) - -#define VIDIOC_MSM_ISP_DUAL_HW_LPM_MODE \ - _IOWR('V', MSM_ISP_DUAL_HW_LPM_MODE, \ - struct msm_vfe_dual_lpm_mode) - -#endif /* __MSMB_ISP__ */ diff --git a/sdm710/original-kernel-headers/media/msmb_ispif.h b/sdm710/original-kernel-headers/media/msmb_ispif.h deleted file mode 100644 index 4d85ba52..00000000 --- a/sdm710/original-kernel-headers/media/msmb_ispif.h +++ /dev/null @@ -1,179 +0,0 @@ -#ifndef UAPI_MSMB_ISPIF_H -#define UAPI_MSMB_ISPIF_H - -#include <linux/types.h> -#include <linux/ioctl.h> -#include <linux/videodev2.h> - -#define CSID_VERSION_V20 0x02000011 -#define CSID_VERSION_V22 0x02001000 -#define CSID_VERSION_V30 0x30000000 -#define CSID_VERSION_V3 0x30000000 - -enum msm_ispif_vfe_intf { - VFE0, - VFE1, - VFE_MAX -}; -#define VFE0_MASK (1 << VFE0) -#define VFE1_MASK (1 << VFE1) - -enum msm_ispif_intftype { - PIX0, - RDI0, - PIX1, - RDI1, - RDI2, - INTF_MAX -}; -#define MAX_PARAM_ENTRIES (INTF_MAX * 2) -#define MAX_CID_CH 8 -#define MAX_CID_CH_PARAM_ENTRY 3 - -#define PIX0_MASK (1 << PIX0) -#define PIX1_MASK (1 << PIX1) -#define RDI0_MASK (1 << RDI0) -#define RDI1_MASK (1 << RDI1) -#define RDI2_MASK (1 << RDI2) - -enum msm_ispif_vc { - VC0, - VC1, - VC2, - VC3, - VC_MAX -}; - -enum msm_ispif_cid { - CID0, - CID1, - CID2, - CID3, - CID4, - CID5, - CID6, - CID7, - CID8, - CID9, - CID10, - CID11, - CID12, - CID13, - CID14, - CID15, - CID_MAX -}; - -enum msm_ispif_csid { - CSID0, - CSID1, - CSID2, - CSID3, - CSID_MAX -}; - -enum msm_ispif_pixel_odd_even { - PIX_EVEN, - PIX_ODD -}; - -enum msm_ispif_pixel_pack_mode { - PACK_BYTE, - PACK_PLAIN_PACK, - PACK_NV_P8, - PACK_NV_P16 -}; - -struct msm_ispif_pack_cfg { - int pixel_swap_en; - enum msm_ispif_pixel_odd_even even_odd_sel; - enum msm_ispif_pixel_pack_mode pack_mode; -}; - -struct msm_ispif_params_entry { - enum msm_ispif_vfe_intf vfe_intf; - enum msm_ispif_intftype intftype; - int num_cids; - enum msm_ispif_cid cids[MAX_CID_CH_PARAM_ENTRY]; - enum msm_ispif_csid csid; - int crop_enable; - uint16_t crop_start_pixel; - uint16_t crop_end_pixel; -}; - -struct msm_ispif_right_param_entry { - enum msm_ispif_cid cids[MAX_CID_CH_PARAM_ENTRY]; - enum msm_ispif_csid csid; -}; - -struct msm_ispif_param_data_ext { - uint32_t num; - struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES]; - struct msm_ispif_pack_cfg pack_cfg[CID_MAX]; - struct msm_ispif_right_param_entry right_entries[MAX_PARAM_ENTRIES]; - uint32_t stereo_enable; - uint16_t line_width[VFE_MAX]; -}; - -struct msm_ispif_param_data { - uint32_t num; - struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES]; -}; - -struct msm_isp_info { - uint32_t max_resolution; - uint32_t id; - uint32_t ver; -}; - -struct msm_ispif_vfe_info { - int num_vfe; - struct msm_isp_info info[VFE_MAX]; -}; - -enum ispif_cfg_type_t { - ISPIF_CLK_ENABLE, - ISPIF_CLK_DISABLE, - ISPIF_INIT, - ISPIF_CFG, - ISPIF_START_FRAME_BOUNDARY, - ISPIF_RESTART_FRAME_BOUNDARY, - ISPIF_STOP_FRAME_BOUNDARY, - ISPIF_STOP_IMMEDIATELY, - ISPIF_RELEASE, - ISPIF_ENABLE_REG_DUMP, - ISPIF_SET_VFE_INFO, - ISPIF_CFG2, - ISPIF_CFG_STEREO, -}; - -struct ispif_cfg_data { - enum ispif_cfg_type_t cfg_type; - union { - int reg_dump; /* ISPIF_ENABLE_REG_DUMP */ - uint32_t csid_version; /* ISPIF_INIT */ - struct msm_ispif_vfe_info vfe_info; /* ISPIF_SET_VFE_INFO */ - struct msm_ispif_param_data params; /* CFG, START, STOP */ - }; -}; - -struct ispif_cfg_data_ext { - enum ispif_cfg_type_t cfg_type; - void *data; - uint32_t size; -}; - -#define ISPIF_RDI_PACK_MODE_SUPPORT 1 - -#define ISPIF_3D_SUPPORT 1 - -#define ISPIF_LINE_WIDTH_SUPPORT 1 - -#define VIDIOC_MSM_ISPIF_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data) - -#define VIDIOC_MSM_ISPIF_CFG_EXT \ - _IOWR('V', BASE_VIDIOC_PRIVATE+1, struct ispif_cfg_data_ext) - -#endif - diff --git a/sdm710/original-kernel-headers/media/msmb_pproc.h b/sdm710/original-kernel-headers/media/msmb_pproc.h deleted file mode 100644 index 4ee9aba7..00000000 --- a/sdm710/original-kernel-headers/media/msmb_pproc.h +++ /dev/null @@ -1,255 +0,0 @@ -#ifndef __UAPI_MSMB_PPROC_H -#define __UAPI_MSMB_PPROC_H - -#include <linux/videodev2.h> -#include <linux/types.h> -#include <media/msmb_generic_buf_mgr.h> - -/* Should be same as VIDEO_MAX_PLANES in videodev2.h */ -#define MAX_PLANES VIDEO_MAX_PLANES -/* PARTIAL_FRAME_STRIPE_COUNT must be even */ -#define PARTIAL_FRAME_STRIPE_COUNT 4 - -#define MAX_NUM_CPP_STRIPS 8 -#define MSM_CPP_MAX_NUM_PLANES 3 -#define MSM_CPP_MIN_FRAME_LENGTH 13 -#define MSM_CPP_MAX_FRAME_LENGTH 4096 -#define MSM_CPP_MAX_FW_NAME_LEN 32 -#define MAX_FREQ_TBL 10 -#define MSM_OUTPUT_BUF_CNT 8 - -enum msm_cpp_frame_type { - MSM_CPP_OFFLINE_FRAME, - MSM_CPP_REALTIME_FRAME, -}; - -enum msm_vpe_frame_type { - MSM_VPE_OFFLINE_FRAME, - MSM_VPE_REALTIME_FRAME, -}; - -struct msm_cpp_buffer_info_t { - int32_t fd; - uint32_t index; - uint32_t offset; - uint8_t native_buff; - uint8_t processed_divert; - uint32_t identity; -}; - -struct msm_cpp_stream_buff_info_t { - uint32_t identity; - uint32_t num_buffs; - struct msm_cpp_buffer_info_t *buffer_info; -}; - -enum msm_cpp_batch_mode_t { - BATCH_MODE_NONE, - BATCH_MODE_VIDEO, - BATCH_MODE_PREVIEW -}; - -struct msm_cpp_batch_info_t { - enum msm_cpp_batch_mode_t batch_mode; - uint32_t batch_size; - uint32_t intra_plane_offset[MAX_PLANES]; - uint32_t pick_preview_idx; - uint32_t cont_idx; -}; - -struct msm_cpp_frame_info_t { - int32_t frame_id; - struct timeval timestamp; - uint32_t inst_id; - uint32_t identity; - uint32_t client_id; - enum msm_cpp_frame_type frame_type; - uint32_t num_strips; - uint32_t msg_len; - uint32_t *cpp_cmd_msg; - int src_fd; - int dst_fd; - struct timeval in_time, out_time; - void *cookie; - int32_t *status; - int32_t duplicate_output; - uint32_t duplicate_identity; - uint32_t feature_mask; - uint8_t we_disable; - struct msm_cpp_buffer_info_t input_buffer_info; - struct msm_cpp_buffer_info_t output_buffer_info[MSM_OUTPUT_BUF_CNT]; - struct msm_cpp_buffer_info_t duplicate_buffer_info; - struct msm_cpp_buffer_info_t tnr_scratch_buffer_info[2]; - uint32_t reserved; - uint8_t partial_frame_indicator; - /* the followings are used only for partial_frame type - * and is only used for offline frame processing and - * only if payload big enough and need to be split into partial_frame - * if first_payload, kernel acquires output buffer - * first payload must have the last stripe - * buffer addresses from 0 to last_stripe_index are updated. - * kernel updates payload with msg_len and stripe_info - * kernel sends top level, plane level, then only stripes - * starting with first_stripe_index and - * ends with last_stripe_index - * kernel then sends trailing flag at frame done, - * if last payload, kernel queues the output buffer to HAL - */ - uint8_t first_payload; - uint8_t last_payload; - uint32_t first_stripe_index; - uint32_t last_stripe_index; - uint32_t stripe_info_offset; - uint32_t stripe_info; - struct msm_cpp_batch_info_t batch_info; -}; - -struct msm_cpp_pop_stream_info_t { - int32_t frame_id; - uint32_t identity; -}; - -struct cpp_hw_info { - uint32_t cpp_hw_version; - uint32_t cpp_hw_caps; - unsigned long freq_tbl[MAX_FREQ_TBL]; - uint32_t freq_tbl_count; -}; - -struct msm_vpe_frame_strip_info { - uint32_t src_w; - uint32_t src_h; - uint32_t dst_w; - uint32_t dst_h; - uint32_t src_x; - uint32_t src_y; - uint32_t phase_step_x; - uint32_t phase_step_y; - uint32_t phase_init_x; - uint32_t phase_init_y; -}; - -struct msm_vpe_buffer_info_t { - int32_t fd; - uint32_t index; - uint32_t offset; - uint8_t native_buff; - uint8_t processed_divert; -}; - -struct msm_vpe_stream_buff_info_t { - uint32_t identity; - uint32_t num_buffs; - struct msm_vpe_buffer_info_t *buffer_info; -}; - -struct msm_vpe_frame_info_t { - int32_t frame_id; - struct timeval timestamp; - uint32_t inst_id; - uint32_t identity; - uint32_t client_id; - enum msm_vpe_frame_type frame_type; - struct msm_vpe_frame_strip_info strip_info; - unsigned long src_fd; - unsigned long dst_fd; - struct ion_handle *src_ion_handle; - struct ion_handle *dest_ion_handle; - unsigned long src_phyaddr; - unsigned long dest_phyaddr; - unsigned long src_chroma_plane_offset; - unsigned long dest_chroma_plane_offset; - struct timeval in_time, out_time; - void *cookie; - - struct msm_vpe_buffer_info_t input_buffer_info; - struct msm_vpe_buffer_info_t output_buffer_info; -}; - -struct msm_pproc_queue_buf_info { - struct msm_buf_mngr_info buff_mgr_info; - uint8_t is_buf_dirty; -}; - -struct msm_cpp_clock_settings_t { - unsigned long clock_rate; - uint64_t avg; - uint64_t inst; -}; - -#define VIDIOC_MSM_CPP_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_GET_INST_INFO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_LOAD_FIRMWARE \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_GET_HW_INFO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_FLUSH_QUEUE \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_ENQUEUE_STREAM_BUFF_INFO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_DEQUEUE_STREAM_BUFF_INFO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_VPE_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_VPE_TRANSACTION_SETUP \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_VPE_GET_EVENTPAYLOAD \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_VPE_GET_INST_INFO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_VPE_ENQUEUE_STREAM_BUFF_INFO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_VPE_DEQUEUE_STREAM_BUFF_INFO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_QUEUE_BUF \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_APPEND_STREAM_BUFF_INFO \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_SET_CLOCK \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_POP_STREAM_BUFFER \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_IOMMU_ATTACH \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 18, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_IOMMU_DETACH \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 19, struct msm_camera_v4l2_ioctl_t) - -#define VIDIOC_MSM_CPP_DELETE_STREAM_BUFF\ - _IOWR('V', BASE_VIDIOC_PRIVATE + 20, struct msm_camera_v4l2_ioctl_t) - - -#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0) -#define V4L2_EVENT_VPE_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 1) - -struct msm_camera_v4l2_ioctl_t { - uint32_t id; - size_t len; - int32_t trans_code; - void *ioctl_ptr; -}; - -#endif - diff --git a/sdm710/original-kernel-headers/scsi/ufs/ioctl.h b/sdm710/original-kernel-headers/scsi/ufs/ioctl.h deleted file mode 100644 index 56b2f461..00000000 --- a/sdm710/original-kernel-headers/scsi/ufs/ioctl.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef UAPI_UFS_IOCTL_H_ -#define UAPI_UFS_IOCTL_H_ - -#include <linux/types.h> - -/* - * IOCTL opcode for ufs queries has the following opcode after - * SCSI_IOCTL_GET_PCI - */ -#define UFS_IOCTL_QUERY 0x5388 - -/** - * struct ufs_ioctl_query_data - used to transfer data to and from user via ioctl - * @opcode: type of data to query (descriptor/attribute/flag) - * @idn: id of the data structure - * @buf_size: number of allocated bytes/data size on return - * @buffer: data location - * - * Received: buffer and buf_size (available space for transfered data) - * Submitted: opcode, idn, length, buf_size - */ -struct ufs_ioctl_query_data { - /* - * User should select one of the opcode defined in "enum query_opcode". - * Please check include/uapi/scsi/ufs/ufs.h for the definition of it. - * Note that only UPIU_QUERY_OPCODE_READ_DESC, - * UPIU_QUERY_OPCODE_READ_ATTR & UPIU_QUERY_OPCODE_READ_FLAG are - * supported as of now. All other query_opcode would be considered - * invalid. - * As of now only read query operations are supported. - */ - __u32 opcode; - /* - * User should select one of the idn from "enum flag_idn" or "enum - * attr_idn" or "enum desc_idn" based on whether opcode above is - * attribute, flag or descriptor. - * Please check include/uapi/scsi/ufs/ufs.h for the definition of it. - */ - __u8 idn; - /* - * User should specify the size of the buffer (buffer[0] below) where - * it wants to read the query data (attribute/flag/descriptor). - * As we might end up reading less data then what is specified in - * buf_size. So we are updating buf_size to what exactly we have read. - */ - __u16 buf_size; - /* - * placeholder for the start of the data buffer where kernel will copy - * the query data (attribute/flag/descriptor) read from the UFS device - * Note: - * For Read/Write Attribute you will have to allocate 4 bytes - * For Read/Write Flag you will have to allocate 1 byte - */ - __u8 buffer[0]; -}; - -#endif /* UAPI_UFS_IOCTL_H_ */ diff --git a/sdm710/original-kernel-headers/scsi/ufs/ufs.h b/sdm710/original-kernel-headers/scsi/ufs/ufs.h deleted file mode 100644 index 6d8ef803..00000000 --- a/sdm710/original-kernel-headers/scsi/ufs/ufs.h +++ /dev/null @@ -1,85 +0,0 @@ -#ifndef UAPI_UFS_H_ -#define UAPI_UFS_H_ - -#define MAX_QUERY_IDN 0x18 - -/* Flag idn for Query Requests*/ -enum flag_idn { - QUERY_FLAG_IDN_FDEVICEINIT = 0x01, - QUERY_FLAG_IDN_PERMANENT_WPE = 0x02, - QUERY_FLAG_IDN_PWR_ON_WPE = 0x03, - QUERY_FLAG_IDN_BKOPS_EN = 0x04, - QUERY_FLAG_IDN_RESERVED1 = 0x05, - QUERY_FLAG_IDN_PURGE_ENABLE = 0x06, - QUERY_FLAG_IDN_RESERVED2 = 0x07, - QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08, - QUERY_FLAG_IDN_BUSY_RTC = 0x09, - /* use one reserved bit */ - QUERY_FLAG_IDN_MANUAL_GC_CONT = 0x0E, -}; - -/* Attribute idn for Query requests */ -enum attr_idn { - QUERY_ATTR_IDN_BOOT_LU_EN = 0x00, - QUERY_ATTR_IDN_RESERVED = 0x01, - QUERY_ATTR_IDN_POWER_MODE = 0x02, - QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03, - QUERY_ATTR_IDN_OOO_DATA_EN = 0x04, - QUERY_ATTR_IDN_BKOPS_STATUS = 0x05, - QUERY_ATTR_IDN_PURGE_STATUS = 0x06, - QUERY_ATTR_IDN_MAX_DATA_IN = 0x07, - QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08, - QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09, - QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A, - QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B, - QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C, - QUERY_ATTR_IDN_EE_CONTROL = 0x0D, - QUERY_ATTR_IDN_EE_STATUS = 0x0E, - QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F, - QUERY_ATTR_IDN_CNTX_CONF = 0x10, - QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11, - /* use one reserved bit */ - QUERY_ATTR_IDN_MANUAL_GC_STATUS = 0x17, -}; - -#define QUERY_ATTR_IDN_BOOT_LU_EN_MAX 0x02 - -/* Descriptor idn for Query requests */ -enum desc_idn { - QUERY_DESC_IDN_DEVICE = 0x0, - QUERY_DESC_IDN_CONFIGURAION = 0x1, - QUERY_DESC_IDN_UNIT = 0x2, - QUERY_DESC_IDN_RFU_0 = 0x3, - QUERY_DESC_IDN_INTERCONNECT = 0x4, - QUERY_DESC_IDN_STRING = 0x5, - QUERY_DESC_IDN_RFU_1 = 0x6, - QUERY_DESC_IDN_GEOMETRY = 0x7, - QUERY_DESC_IDN_POWER = 0x8, - QUERY_DESC_IDN_HEALTH = 0x9, - QUERY_DESC_IDN_RFU_2 = 0xA, - QUERY_DESC_IDN_MAX, -}; - -/* UTP QUERY Transaction Specific Fields OpCode */ -enum query_opcode { - UPIU_QUERY_OPCODE_NOP = 0x0, - UPIU_QUERY_OPCODE_READ_DESC = 0x1, - UPIU_QUERY_OPCODE_WRITE_DESC = 0x2, - UPIU_QUERY_OPCODE_READ_ATTR = 0x3, - UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4, - UPIU_QUERY_OPCODE_READ_FLAG = 0x5, - UPIU_QUERY_OPCODE_SET_FLAG = 0x6, - UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7, - UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8, - UPIU_QUERY_OPCODE_MAX, -}; - -/* - * high 16 bits for HPB. E.g., - * opcode = (UFS_IOCTL_QUERY_OPCODE << 16) | UPIU_QUERY_OPCODE_READ_DESC - */ -#define UPIU_QUERY_OPCODE_HIGH_HPB 0x5500 -#define UPIU_QUERY_OPCODE_HIGH(opcode) ((opcode) >> 16) -#define UPIU_QUERY_OPCODE_LOW(opcode) ((opcode) & 0xffff) - -#endif /* UAPI_UFS_H_ */ diff --git a/sdm710/original-kernel-headers/sound/asound.h b/sdm710/original-kernel-headers/sound/asound.h deleted file mode 100644 index 9c85bf7d..00000000 --- a/sdm710/original-kernel-headers/sound/asound.h +++ /dev/null @@ -1,1022 +0,0 @@ -/* - * Advanced Linux Sound Architecture - ALSA - Driver - * Copyright (c) 1994-2003 by Jaroslav Kysela <perex@perex.cz>, - * Abramo Bagnara <abramo@alsa-project.org> - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __SOUND_ASOUND_H -#define __SOUND_ASOUND_H - -#if defined(__KERNEL__) || defined(__linux__) -#include <linux/types.h> -#else -#include <sys/ioctl.h> -#endif - -#include <stdlib.h> - -/* - * protocol version - */ - -#define SNDRV_PROTOCOL_VERSION(major, minor, subminor) (((major)<<16)|((minor)<<8)|(subminor)) -#define SNDRV_PROTOCOL_MAJOR(version) (((version)>>16)&0xffff) -#define SNDRV_PROTOCOL_MINOR(version) (((version)>>8)&0xff) -#define SNDRV_PROTOCOL_MICRO(version) ((version)&0xff) -#define SNDRV_PROTOCOL_INCOMPATIBLE(kversion, uversion) \ - (SNDRV_PROTOCOL_MAJOR(kversion) != SNDRV_PROTOCOL_MAJOR(uversion) || \ - (SNDRV_PROTOCOL_MAJOR(kversion) == SNDRV_PROTOCOL_MAJOR(uversion) && \ - SNDRV_PROTOCOL_MINOR(kversion) != SNDRV_PROTOCOL_MINOR(uversion))) - -/**************************************************************************** - * * - * Digital audio interface * - * * - ****************************************************************************/ - -struct snd_aes_iec958 { - unsigned char status[24]; /* AES/IEC958 channel status bits */ - unsigned char subcode[147]; /* AES/IEC958 subcode bits */ - unsigned char pad; /* nothing */ - unsigned char dig_subframe[4]; /* AES/IEC958 subframe bits */ -}; - -/**************************************************************************** - * * - * CEA-861 Audio InfoFrame. Used in HDMI and DisplayPort * - * * - ****************************************************************************/ - -struct snd_cea_861_aud_if { - unsigned char db1_ct_cc; /* coding type and channel count */ - unsigned char db2_sf_ss; /* sample frequency and size */ - unsigned char db3; /* not used, all zeros */ - unsigned char db4_ca; /* channel allocation code */ - unsigned char db5_dminh_lsv; /* downmix inhibit & level-shit values */ -}; - -/**************************************************************************** - * * - * Section for driver hardware dependent interface - /dev/snd/hw? * - * * - ****************************************************************************/ - -#define SNDRV_HWDEP_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1) - -enum { - SNDRV_HWDEP_IFACE_OPL2 = 0, - SNDRV_HWDEP_IFACE_OPL3, - SNDRV_HWDEP_IFACE_OPL4, - SNDRV_HWDEP_IFACE_SB16CSP, /* Creative Signal Processor */ - SNDRV_HWDEP_IFACE_EMU10K1, /* FX8010 processor in EMU10K1 chip */ - SNDRV_HWDEP_IFACE_YSS225, /* Yamaha FX processor */ - SNDRV_HWDEP_IFACE_ICS2115, /* Wavetable synth */ - SNDRV_HWDEP_IFACE_SSCAPE, /* Ensoniq SoundScape ISA card (MC68EC000) */ - SNDRV_HWDEP_IFACE_VX, /* Digigram VX cards */ - SNDRV_HWDEP_IFACE_MIXART, /* Digigram miXart cards */ - SNDRV_HWDEP_IFACE_USX2Y, /* Tascam US122, US224 & US428 usb */ - SNDRV_HWDEP_IFACE_EMUX_WAVETABLE, /* EmuX wavetable */ - SNDRV_HWDEP_IFACE_BLUETOOTH, /* Bluetooth audio */ - SNDRV_HWDEP_IFACE_USX2Y_PCM, /* Tascam US122, US224 & US428 rawusb pcm */ - SNDRV_HWDEP_IFACE_PCXHR, /* Digigram PCXHR */ - SNDRV_HWDEP_IFACE_SB_RC, /* SB Extigy/Audigy2NX remote control */ - SNDRV_HWDEP_IFACE_HDA, /* HD-audio */ - SNDRV_HWDEP_IFACE_USB_STREAM, /* direct access to usb stream */ - SNDRV_HWDEP_IFACE_FW_DICE, /* TC DICE FireWire device */ - SNDRV_HWDEP_IFACE_FW_FIREWORKS, /* Echo Audio Fireworks based device */ - SNDRV_HWDEP_IFACE_FW_BEBOB, /* BridgeCo BeBoB based device */ - SNDRV_HWDEP_IFACE_FW_OXFW, /* Oxford OXFW970/971 based device */ - SNDRV_HWDEP_IFACE_FW_DIGI00X, /* Digidesign Digi 002/003 family */ - SNDRV_HWDEP_IFACE_FW_TASCAM, /* TASCAM FireWire series */ - SNDRV_HWDEP_IFACE_LINE6, /* Line6 USB processors */ - SNDRV_HWDEP_IFACE_AUDIO_BE, /* Backend Audio Control */ - SNDRV_HWDEP_IFACE_AUDIO_CODEC, /* codec Audio Control */ - - /* Don't forget to change the following: */ - SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_AUDIO_CODEC -}; - -struct snd_hwdep_info { - unsigned int device; /* WR: device number */ - int card; /* R: card number */ - unsigned char id[64]; /* ID (user selectable) */ - unsigned char name[80]; /* hwdep name */ - int iface; /* hwdep interface */ - unsigned char reserved[64]; /* reserved for future */ -}; - -/* generic DSP loader */ -struct snd_hwdep_dsp_status { - unsigned int version; /* R: driver-specific version */ - unsigned char id[32]; /* R: driver-specific ID string */ - unsigned int num_dsps; /* R: number of DSP images to transfer */ - unsigned int dsp_loaded; /* R: bit flags indicating the loaded DSPs */ - unsigned int chip_ready; /* R: 1 = initialization finished */ - unsigned char reserved[16]; /* reserved for future use */ -}; - -struct snd_hwdep_dsp_image { - unsigned int index; /* W: DSP index */ - unsigned char name[64]; /* W: ID (e.g. file name) */ - unsigned char *image; /* W: binary image */ - size_t length; /* W: size of image in bytes */ - unsigned long driver_data; /* W: driver-specific data */ -}; - -#define SNDRV_HWDEP_IOCTL_PVERSION _IOR ('H', 0x00, int) -#define SNDRV_HWDEP_IOCTL_INFO _IOR ('H', 0x01, struct snd_hwdep_info) -#define SNDRV_HWDEP_IOCTL_DSP_STATUS _IOR('H', 0x02, struct snd_hwdep_dsp_status) -#define SNDRV_HWDEP_IOCTL_DSP_LOAD _IOW('H', 0x03, struct snd_hwdep_dsp_image) - -/***************************************************************************** - * * - * Digital Audio (PCM) interface - /dev/snd/pcm?? * - * * - *****************************************************************************/ - -#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 13) - -typedef unsigned long snd_pcm_uframes_t; -typedef signed long snd_pcm_sframes_t; - -enum { - SNDRV_PCM_CLASS_GENERIC = 0, /* standard mono or stereo device */ - SNDRV_PCM_CLASS_MULTI, /* multichannel device */ - SNDRV_PCM_CLASS_MODEM, /* software modem class */ - SNDRV_PCM_CLASS_DIGITIZER, /* digitizer class */ - /* Don't forget to change the following: */ - SNDRV_PCM_CLASS_LAST = SNDRV_PCM_CLASS_DIGITIZER, -}; - -enum { - SNDRV_PCM_SUBCLASS_GENERIC_MIX = 0, /* mono or stereo subdevices are mixed together */ - SNDRV_PCM_SUBCLASS_MULTI_MIX, /* multichannel subdevices are mixed together */ - /* Don't forget to change the following: */ - SNDRV_PCM_SUBCLASS_LAST = SNDRV_PCM_SUBCLASS_MULTI_MIX, -}; - -enum { - SNDRV_PCM_STREAM_PLAYBACK = 0, - SNDRV_PCM_STREAM_CAPTURE, - SNDRV_PCM_STREAM_LAST = SNDRV_PCM_STREAM_CAPTURE, -}; - -typedef int __bitwise snd_pcm_access_t; -#define SNDRV_PCM_ACCESS_MMAP_INTERLEAVED ((snd_pcm_access_t) 0) /* interleaved mmap */ -#define SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED ((snd_pcm_access_t) 1) /* noninterleaved mmap */ -#define SNDRV_PCM_ACCESS_MMAP_COMPLEX ((snd_pcm_access_t) 2) /* complex mmap */ -#define SNDRV_PCM_ACCESS_RW_INTERLEAVED ((snd_pcm_access_t) 3) /* readi/writei */ -#define SNDRV_PCM_ACCESS_RW_NONINTERLEAVED ((snd_pcm_access_t) 4) /* readn/writen */ -#define SNDRV_PCM_ACCESS_LAST SNDRV_PCM_ACCESS_RW_NONINTERLEAVED - -typedef int __bitwise snd_pcm_format_t; -#define SNDRV_PCM_FORMAT_S8 ((snd_pcm_format_t) 0) -#define SNDRV_PCM_FORMAT_U8 ((snd_pcm_format_t) 1) -#define SNDRV_PCM_FORMAT_S16_LE ((snd_pcm_format_t) 2) -#define SNDRV_PCM_FORMAT_S16_BE ((snd_pcm_format_t) 3) -#define SNDRV_PCM_FORMAT_U16_LE ((snd_pcm_format_t) 4) -#define SNDRV_PCM_FORMAT_U16_BE ((snd_pcm_format_t) 5) -#define SNDRV_PCM_FORMAT_S24_LE ((snd_pcm_format_t) 6) /* low three bytes */ -#define SNDRV_PCM_FORMAT_S24_BE ((snd_pcm_format_t) 7) /* low three bytes */ -#define SNDRV_PCM_FORMAT_U24_LE ((snd_pcm_format_t) 8) /* low three bytes */ -#define SNDRV_PCM_FORMAT_U24_BE ((snd_pcm_format_t) 9) /* low three bytes */ -#define SNDRV_PCM_FORMAT_S32_LE ((snd_pcm_format_t) 10) -#define SNDRV_PCM_FORMAT_S32_BE ((snd_pcm_format_t) 11) -#define SNDRV_PCM_FORMAT_U32_LE ((snd_pcm_format_t) 12) -#define SNDRV_PCM_FORMAT_U32_BE ((snd_pcm_format_t) 13) -#define SNDRV_PCM_FORMAT_FLOAT_LE ((snd_pcm_format_t) 14) /* 4-byte float, IEEE-754 32-bit, range -1.0 to 1.0 */ -#define SNDRV_PCM_FORMAT_FLOAT_BE ((snd_pcm_format_t) 15) /* 4-byte float, IEEE-754 32-bit, range -1.0 to 1.0 */ -#define SNDRV_PCM_FORMAT_FLOAT64_LE ((snd_pcm_format_t) 16) /* 8-byte float, IEEE-754 64-bit, range -1.0 to 1.0 */ -#define SNDRV_PCM_FORMAT_FLOAT64_BE ((snd_pcm_format_t) 17) /* 8-byte float, IEEE-754 64-bit, range -1.0 to 1.0 */ -#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE ((snd_pcm_format_t) 18) /* IEC-958 subframe, Little Endian */ -#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE ((snd_pcm_format_t) 19) /* IEC-958 subframe, Big Endian */ -#define SNDRV_PCM_FORMAT_MU_LAW ((snd_pcm_format_t) 20) -#define SNDRV_PCM_FORMAT_A_LAW ((snd_pcm_format_t) 21) -#define SNDRV_PCM_FORMAT_IMA_ADPCM ((snd_pcm_format_t) 22) -#define SNDRV_PCM_FORMAT_MPEG ((snd_pcm_format_t) 23) -#define SNDRV_PCM_FORMAT_GSM ((snd_pcm_format_t) 24) -#define SNDRV_PCM_FORMAT_SPECIAL ((snd_pcm_format_t) 31) -#define SNDRV_PCM_FORMAT_S24_3LE ((snd_pcm_format_t) 32) /* in three bytes */ -#define SNDRV_PCM_FORMAT_S24_3BE ((snd_pcm_format_t) 33) /* in three bytes */ -#define SNDRV_PCM_FORMAT_U24_3LE ((snd_pcm_format_t) 34) /* in three bytes */ -#define SNDRV_PCM_FORMAT_U24_3BE ((snd_pcm_format_t) 35) /* in three bytes */ -#define SNDRV_PCM_FORMAT_S20_3LE ((snd_pcm_format_t) 36) /* in three bytes */ -#define SNDRV_PCM_FORMAT_S20_3BE ((snd_pcm_format_t) 37) /* in three bytes */ -#define SNDRV_PCM_FORMAT_U20_3LE ((snd_pcm_format_t) 38) /* in three bytes */ -#define SNDRV_PCM_FORMAT_U20_3BE ((snd_pcm_format_t) 39) /* in three bytes */ -#define SNDRV_PCM_FORMAT_S18_3LE ((snd_pcm_format_t) 40) /* in three bytes */ -#define SNDRV_PCM_FORMAT_S18_3BE ((snd_pcm_format_t) 41) /* in three bytes */ -#define SNDRV_PCM_FORMAT_U18_3LE ((snd_pcm_format_t) 42) /* in three bytes */ -#define SNDRV_PCM_FORMAT_U18_3BE ((snd_pcm_format_t) 43) /* in three bytes */ -#define SNDRV_PCM_FORMAT_G723_24 ((snd_pcm_format_t) 44) /* 8 samples in 3 bytes */ -#define SNDRV_PCM_FORMAT_G723_24_1B ((snd_pcm_format_t) 45) /* 1 sample in 1 byte */ -#define SNDRV_PCM_FORMAT_G723_40 ((snd_pcm_format_t) 46) /* 8 Samples in 5 bytes */ -#define SNDRV_PCM_FORMAT_G723_40_1B ((snd_pcm_format_t) 47) /* 1 sample in 1 byte */ -#define SNDRV_PCM_FORMAT_DSD_U8 ((snd_pcm_format_t) 48) /* DSD, 1-byte samples DSD (x8) */ -#define SNDRV_PCM_FORMAT_DSD_U16_LE ((snd_pcm_format_t) 49) /* DSD, 2-byte samples DSD (x16), little endian */ -#define SNDRV_PCM_FORMAT_DSD_U32_LE ((snd_pcm_format_t) 50) /* DSD, 4-byte samples DSD (x32), little endian */ -#define SNDRV_PCM_FORMAT_DSD_U16_BE ((snd_pcm_format_t) 51) /* DSD, 2-byte samples DSD (x16), big endian */ -#define SNDRV_PCM_FORMAT_DSD_U32_BE ((snd_pcm_format_t) 52) /* DSD, 4-byte samples DSD (x32), big endian */ -#define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_DSD_U32_BE - -#ifdef SNDRV_LITTLE_ENDIAN -#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_LE -#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_LE -#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_LE -#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_LE -#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_LE -#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_LE -#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE -#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE -#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE -#endif -#ifdef SNDRV_BIG_ENDIAN -#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE -#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_BE -#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_BE -#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_BE -#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_BE -#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_BE -#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE -#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE -#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE -#endif - -typedef int __bitwise snd_pcm_subformat_t; -#define SNDRV_PCM_SUBFORMAT_STD ((snd_pcm_subformat_t) 0) -#define SNDRV_PCM_SUBFORMAT_LAST SNDRV_PCM_SUBFORMAT_STD - -#define SNDRV_PCM_INFO_MMAP 0x00000001 /* hardware supports mmap */ -#define SNDRV_PCM_INFO_MMAP_VALID 0x00000002 /* period data are valid during transfer */ -#define SNDRV_PCM_INFO_DOUBLE 0x00000004 /* Double buffering needed for PCM start/stop */ -#define SNDRV_PCM_INFO_BATCH 0x00000010 /* double buffering */ -#define SNDRV_PCM_INFO_INTERLEAVED 0x00000100 /* channels are interleaved */ -#define SNDRV_PCM_INFO_NONINTERLEAVED 0x00000200 /* channels are not interleaved */ -#define SNDRV_PCM_INFO_COMPLEX 0x00000400 /* complex frame organization (mmap only) */ -#define SNDRV_PCM_INFO_BLOCK_TRANSFER 0x00010000 /* hardware transfer block of samples */ -#define SNDRV_PCM_INFO_OVERRANGE 0x00020000 /* hardware supports ADC (capture) overrange detection */ -#define SNDRV_PCM_INFO_RESUME 0x00040000 /* hardware supports stream resume after suspend */ -#define SNDRV_PCM_INFO_PAUSE 0x00080000 /* pause ioctl is supported */ -#define SNDRV_PCM_INFO_HALF_DUPLEX 0x00100000 /* only half duplex */ -#define SNDRV_PCM_INFO_JOINT_DUPLEX 0x00200000 /* playback and capture stream are somewhat correlated */ -#define SNDRV_PCM_INFO_SYNC_START 0x00400000 /* pcm support some kind of sync go */ -#define SNDRV_PCM_INFO_NO_PERIOD_WAKEUP 0x00800000 /* period wakeup can be disabled */ -#define SNDRV_PCM_INFO_HAS_WALL_CLOCK 0x01000000 /* (Deprecated)has audio wall clock for audio/system time sync */ -#define SNDRV_PCM_INFO_HAS_LINK_ATIME 0x01000000 /* report hardware link audio time, reset on startup */ -#define SNDRV_PCM_INFO_HAS_LINK_ABSOLUTE_ATIME 0x02000000 /* report absolute hardware link audio time, not reset on startup */ -#define SNDRV_PCM_INFO_HAS_LINK_ESTIMATED_ATIME 0x04000000 /* report estimated link audio time */ -#define SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 0x08000000 /* report synchronized audio/system time */ - -#define SNDRV_PCM_INFO_DRAIN_TRIGGER 0x40000000 /* internal kernel flag - trigger in drain */ -#define SNDRV_PCM_INFO_FIFO_IN_FRAMES 0x80000000 /* internal kernel flag - FIFO size is in frames */ - - - -typedef int __bitwise snd_pcm_state_t; -#define SNDRV_PCM_STATE_OPEN ((snd_pcm_state_t) 0) /* stream is open */ -#define SNDRV_PCM_STATE_SETUP ((snd_pcm_state_t) 1) /* stream has a setup */ -#define SNDRV_PCM_STATE_PREPARED ((snd_pcm_state_t) 2) /* stream is ready to start */ -#define SNDRV_PCM_STATE_RUNNING ((snd_pcm_state_t) 3) /* stream is running */ -#define SNDRV_PCM_STATE_XRUN ((snd_pcm_state_t) 4) /* stream reached an xrun */ -#define SNDRV_PCM_STATE_DRAINING ((snd_pcm_state_t) 5) /* stream is draining */ -#define SNDRV_PCM_STATE_PAUSED ((snd_pcm_state_t) 6) /* stream is paused */ -#define SNDRV_PCM_STATE_SUSPENDED ((snd_pcm_state_t) 7) /* hardware is suspended */ -#define SNDRV_PCM_STATE_DISCONNECTED ((snd_pcm_state_t) 8) /* hardware is disconnected */ -#define SNDRV_PCM_STATE_LAST SNDRV_PCM_STATE_DISCONNECTED - -enum { - SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000, - SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000, - SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000, -}; - -union snd_pcm_sync_id { - unsigned char id[16]; - unsigned short id16[8]; - unsigned int id32[4]; -}; - -struct snd_pcm_info { - unsigned int device; /* RO/WR (control): device number */ - unsigned int subdevice; /* RO/WR (control): subdevice number */ - int stream; /* RO/WR (control): stream direction */ - int card; /* R: card number */ - unsigned char id[64]; /* ID (user selectable) */ - unsigned char name[80]; /* name of this device */ - unsigned char subname[32]; /* subdevice name */ - int dev_class; /* SNDRV_PCM_CLASS_* */ - int dev_subclass; /* SNDRV_PCM_SUBCLASS_* */ - unsigned int subdevices_count; - unsigned int subdevices_avail; - union snd_pcm_sync_id sync; /* hardware synchronization ID */ - unsigned char reserved[64]; /* reserved for future... */ -}; - -typedef int snd_pcm_hw_param_t; -#define SNDRV_PCM_HW_PARAM_ACCESS 0 /* Access type */ -#define SNDRV_PCM_HW_PARAM_FORMAT 1 /* Format */ -#define SNDRV_PCM_HW_PARAM_SUBFORMAT 2 /* Subformat */ -#define SNDRV_PCM_HW_PARAM_FIRST_MASK SNDRV_PCM_HW_PARAM_ACCESS -#define SNDRV_PCM_HW_PARAM_LAST_MASK SNDRV_PCM_HW_PARAM_SUBFORMAT - -#define SNDRV_PCM_HW_PARAM_SAMPLE_BITS 8 /* Bits per sample */ -#define SNDRV_PCM_HW_PARAM_FRAME_BITS 9 /* Bits per frame */ -#define SNDRV_PCM_HW_PARAM_CHANNELS 10 /* Channels */ -#define SNDRV_PCM_HW_PARAM_RATE 11 /* Approx rate */ -#define SNDRV_PCM_HW_PARAM_PERIOD_TIME 12 /* Approx distance between - * interrupts in us - */ -#define SNDRV_PCM_HW_PARAM_PERIOD_SIZE 13 /* Approx frames between - * interrupts - */ -#define SNDRV_PCM_HW_PARAM_PERIOD_BYTES 14 /* Approx bytes between - * interrupts - */ -#define SNDRV_PCM_HW_PARAM_PERIODS 15 /* Approx interrupts per - * buffer - */ -#define SNDRV_PCM_HW_PARAM_BUFFER_TIME 16 /* Approx duration of buffer - * in us - */ -#define SNDRV_PCM_HW_PARAM_BUFFER_SIZE 17 /* Size of buffer in frames */ -#define SNDRV_PCM_HW_PARAM_BUFFER_BYTES 18 /* Size of buffer in bytes */ -#define SNDRV_PCM_HW_PARAM_TICK_TIME 19 /* Approx tick duration in us */ -#define SNDRV_PCM_HW_PARAM_FIRST_INTERVAL SNDRV_PCM_HW_PARAM_SAMPLE_BITS -#define SNDRV_PCM_HW_PARAM_LAST_INTERVAL SNDRV_PCM_HW_PARAM_TICK_TIME - -#define SNDRV_PCM_HW_PARAMS_NORESAMPLE (1<<0) /* avoid rate resampling */ -#define SNDRV_PCM_HW_PARAMS_EXPORT_BUFFER (1<<1) /* export buffer */ -#define SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP (1<<2) /* disable period wakeups */ - -struct snd_interval { - unsigned int min, max; - unsigned int openmin:1, - openmax:1, - integer:1, - empty:1; -}; - -#define SNDRV_MASK_MAX 256 - -struct snd_mask { - __u32 bits[(SNDRV_MASK_MAX+31)/32]; -}; - -struct snd_pcm_hw_params { - unsigned int flags; - struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK - - SNDRV_PCM_HW_PARAM_FIRST_MASK + 1]; - struct snd_mask mres[5]; /* reserved masks */ - struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL - - SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1]; - struct snd_interval ires[9]; /* reserved intervals */ - unsigned int rmask; /* W: requested masks */ - unsigned int cmask; /* R: changed masks */ - unsigned int info; /* R: Info flags for returned setup */ - unsigned int msbits; /* R: used most significant bits */ - unsigned int rate_num; /* R: rate numerator */ - unsigned int rate_den; /* R: rate denominator */ - snd_pcm_uframes_t fifo_size; /* R: chip FIFO size in frames */ - unsigned char reserved[64]; /* reserved for future */ -}; - -enum { - SNDRV_PCM_TSTAMP_NONE = 0, - SNDRV_PCM_TSTAMP_ENABLE, - SNDRV_PCM_TSTAMP_LAST = SNDRV_PCM_TSTAMP_ENABLE, -}; - -struct snd_pcm_sw_params { - int tstamp_mode; /* timestamp mode */ - unsigned int period_step; - unsigned int sleep_min; /* min ticks to sleep */ - snd_pcm_uframes_t avail_min; /* min avail frames for wakeup */ - snd_pcm_uframes_t xfer_align; /* obsolete: xfer size need to be a multiple */ - snd_pcm_uframes_t start_threshold; /* min hw_avail frames for automatic start */ - snd_pcm_uframes_t stop_threshold; /* min avail frames for automatic stop */ - snd_pcm_uframes_t silence_threshold; /* min distance from noise for silence filling */ - snd_pcm_uframes_t silence_size; /* silence block size */ - snd_pcm_uframes_t boundary; /* pointers wrap point */ - unsigned int proto; /* protocol version */ - unsigned int tstamp_type; /* timestamp type (req. proto >= 2.0.12) */ - unsigned char reserved[56]; /* reserved for future */ -}; - -struct snd_pcm_channel_info { - unsigned int channel; - __kernel_off_t offset; /* mmap offset */ - unsigned int first; /* offset to first sample in bits */ - unsigned int step; /* samples distance in bits */ -}; - -enum { - /* - * first definition for backwards compatibility only, - * maps to wallclock/link time for HDAudio playback and DEFAULT/DMA time for everything else - */ - SNDRV_PCM_AUDIO_TSTAMP_TYPE_COMPAT = 0, - - /* timestamp definitions */ - SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT = 1, /* DMA time, reported as per hw_ptr */ - SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK = 2, /* link time reported by sample or wallclock counter, reset on startup */ - SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ABSOLUTE = 3, /* link time reported by sample or wallclock counter, not reset on startup */ - SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ESTIMATED = 4, /* link time estimated indirectly */ - SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED = 5, /* link time synchronized with system time */ - SNDRV_PCM_AUDIO_TSTAMP_TYPE_LAST = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED -}; - -struct snd_pcm_status { - snd_pcm_state_t state; /* stream state */ - struct timespec trigger_tstamp; /* time when stream was started/stopped/paused */ - struct timespec tstamp; /* reference timestamp */ - snd_pcm_uframes_t appl_ptr; /* appl ptr */ - snd_pcm_uframes_t hw_ptr; /* hw ptr */ - snd_pcm_sframes_t delay; /* current delay in frames */ - snd_pcm_uframes_t avail; /* number of frames available */ - snd_pcm_uframes_t avail_max; /* max frames available on hw since last status */ - snd_pcm_uframes_t overrange; /* count of ADC (capture) overrange detections from last status */ - snd_pcm_state_t suspended_state; /* suspended stream state */ - __u32 audio_tstamp_data; /* needed for 64-bit alignment, used for configs/report to/from userspace */ - struct timespec audio_tstamp; /* sample counter, wall clock, PHC or on-demand sync'ed */ - struct timespec driver_tstamp; /* useful in case reference system tstamp is reported with delay */ - __u32 audio_tstamp_accuracy; /* in ns units, only valid if indicated in audio_tstamp_data */ - unsigned char reserved[52-2*sizeof(struct timespec)]; /* must be filled with zero */ -}; - -struct snd_pcm_mmap_status { - snd_pcm_state_t state; /* RO: state - SNDRV_PCM_STATE_XXXX */ - int pad1; /* Needed for 64 bit alignment */ - snd_pcm_uframes_t hw_ptr; /* RO: hw ptr (0...boundary-1) */ - struct timespec tstamp; /* Timestamp */ - snd_pcm_state_t suspended_state; /* RO: suspended stream state */ - struct timespec audio_tstamp; /* from sample counter or wall clock */ -}; - -struct snd_pcm_mmap_control { - snd_pcm_uframes_t appl_ptr; /* RW: appl ptr (0...boundary-1) */ - snd_pcm_uframes_t avail_min; /* RW: min available frames for wakeup */ -}; - -#define SNDRV_PCM_SYNC_PTR_HWSYNC (1<<0) /* execute hwsync */ -#define SNDRV_PCM_SYNC_PTR_APPL (1<<1) /* get appl_ptr from driver (r/w op) */ -#define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1<<2) /* get avail_min from driver */ - -struct snd_pcm_sync_ptr { - unsigned int flags; - union { - struct snd_pcm_mmap_status status; - unsigned char reserved[64]; - } s; - union { - struct snd_pcm_mmap_control control; - unsigned char reserved[64]; - } c; -}; - -struct snd_xferi { - snd_pcm_sframes_t result; - void *buf; - snd_pcm_uframes_t frames; -}; - -struct snd_xfern { - snd_pcm_sframes_t result; - void * *bufs; - snd_pcm_uframes_t frames; -}; - -enum { - SNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0, /* gettimeofday equivalent */ - SNDRV_PCM_TSTAMP_TYPE_MONOTONIC, /* posix_clock_monotonic equivalent */ - SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW, /* monotonic_raw (no NTP) */ - SNDRV_PCM_TSTAMP_TYPE_LAST = SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW, -}; - -/* channel positions */ -enum { - SNDRV_CHMAP_UNKNOWN = 0, - SNDRV_CHMAP_NA, /* N/A, silent */ - SNDRV_CHMAP_MONO, /* mono stream */ - /* this follows the alsa-lib mixer channel value + 3 */ - SNDRV_CHMAP_FL, /* front left */ - SNDRV_CHMAP_FR, /* front right */ - SNDRV_CHMAP_RL, /* rear left */ - SNDRV_CHMAP_RR, /* rear right */ - SNDRV_CHMAP_FC, /* front center */ - SNDRV_CHMAP_LFE, /* LFE */ - SNDRV_CHMAP_SL, /* side left */ - SNDRV_CHMAP_SR, /* side right */ - SNDRV_CHMAP_RC, /* rear center */ - /* new definitions */ - SNDRV_CHMAP_FLC, /* front left center */ - SNDRV_CHMAP_FRC, /* front right center */ - SNDRV_CHMAP_RLC, /* rear left center */ - SNDRV_CHMAP_RRC, /* rear right center */ - SNDRV_CHMAP_FLW, /* front left wide */ - SNDRV_CHMAP_FRW, /* front right wide */ - SNDRV_CHMAP_FLH, /* front left high */ - SNDRV_CHMAP_FCH, /* front center high */ - SNDRV_CHMAP_FRH, /* front right high */ - SNDRV_CHMAP_TC, /* top center */ - SNDRV_CHMAP_TFL, /* top front left */ - SNDRV_CHMAP_TFR, /* top front right */ - SNDRV_CHMAP_TFC, /* top front center */ - SNDRV_CHMAP_TRL, /* top rear left */ - SNDRV_CHMAP_TRR, /* top rear right */ - SNDRV_CHMAP_TRC, /* top rear center */ - /* new definitions for UAC2 */ - SNDRV_CHMAP_TFLC, /* top front left center */ - SNDRV_CHMAP_TFRC, /* top front right center */ - SNDRV_CHMAP_TSL, /* top side left */ - SNDRV_CHMAP_TSR, /* top side right */ - SNDRV_CHMAP_LLFE, /* left LFE */ - SNDRV_CHMAP_RLFE, /* right LFE */ - SNDRV_CHMAP_BC, /* bottom center */ - SNDRV_CHMAP_BLC, /* bottom left center */ - SNDRV_CHMAP_BRC, /* bottom right center */ - SNDRV_CHMAP_LAST = SNDRV_CHMAP_BRC, -}; - -#define SNDRV_CHMAP_POSITION_MASK 0xffff -#define SNDRV_CHMAP_PHASE_INVERSE (0x01 << 16) -#define SNDRV_CHMAP_DRIVER_SPEC (0x02 << 16) - -#define SNDRV_PCM_IOCTL_PVERSION _IOR('A', 0x00, int) -#define SNDRV_PCM_IOCTL_INFO _IOR('A', 0x01, struct snd_pcm_info) -#define SNDRV_PCM_IOCTL_TSTAMP _IOW('A', 0x02, int) -#define SNDRV_PCM_IOCTL_TTSTAMP _IOW('A', 0x03, int) -#define SNDRV_PCM_IOCTL_HW_REFINE _IOWR('A', 0x10, struct snd_pcm_hw_params) -#define SNDRV_PCM_IOCTL_HW_PARAMS _IOWR('A', 0x11, struct snd_pcm_hw_params) -#define SNDRV_PCM_IOCTL_HW_FREE _IO('A', 0x12) -#define SNDRV_PCM_IOCTL_SW_PARAMS _IOWR('A', 0x13, struct snd_pcm_sw_params) -#define SNDRV_PCM_IOCTL_STATUS _IOR('A', 0x20, struct snd_pcm_status) -#define SNDRV_PCM_IOCTL_DELAY _IOR('A', 0x21, snd_pcm_sframes_t) -#define SNDRV_PCM_IOCTL_HWSYNC _IO('A', 0x22) -#define SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct snd_pcm_sync_ptr) -#define SNDRV_PCM_IOCTL_STATUS_EXT _IOWR('A', 0x24, struct snd_pcm_status) -#define SNDRV_PCM_IOCTL_CHANNEL_INFO _IOR('A', 0x32, struct snd_pcm_channel_info) -#define SNDRV_PCM_IOCTL_PREPARE _IO('A', 0x40) -#define SNDRV_PCM_IOCTL_RESET _IO('A', 0x41) -#define SNDRV_PCM_IOCTL_START _IO('A', 0x42) -#define SNDRV_PCM_IOCTL_DROP _IO('A', 0x43) -#define SNDRV_PCM_IOCTL_DRAIN _IO('A', 0x44) -#define SNDRV_PCM_IOCTL_PAUSE _IOW('A', 0x45, int) -#define SNDRV_PCM_IOCTL_REWIND _IOW('A', 0x46, snd_pcm_uframes_t) -#define SNDRV_PCM_IOCTL_RESUME _IO('A', 0x47) -#define SNDRV_PCM_IOCTL_XRUN _IO('A', 0x48) -#define SNDRV_PCM_IOCTL_FORWARD _IOW('A', 0x49, snd_pcm_uframes_t) -#define SNDRV_PCM_IOCTL_WRITEI_FRAMES _IOW('A', 0x50, struct snd_xferi) -#define SNDRV_PCM_IOCTL_READI_FRAMES _IOR('A', 0x51, struct snd_xferi) -#define SNDRV_PCM_IOCTL_WRITEN_FRAMES _IOW('A', 0x52, struct snd_xfern) -#define SNDRV_PCM_IOCTL_READN_FRAMES _IOR('A', 0x53, struct snd_xfern) -#define SNDRV_PCM_IOCTL_LINK _IOW('A', 0x60, int) -#define SNDRV_PCM_IOCTL_UNLINK _IO('A', 0x61) - -/***************************************************************************** - * * - * MIDI v1.0 interface * - * * - *****************************************************************************/ - -/* - * Raw MIDI section - /dev/snd/midi?? - */ - -#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0) - -enum { - SNDRV_RAWMIDI_STREAM_OUTPUT = 0, - SNDRV_RAWMIDI_STREAM_INPUT, - SNDRV_RAWMIDI_STREAM_LAST = SNDRV_RAWMIDI_STREAM_INPUT, -}; - -#define SNDRV_RAWMIDI_INFO_OUTPUT 0x00000001 -#define SNDRV_RAWMIDI_INFO_INPUT 0x00000002 -#define SNDRV_RAWMIDI_INFO_DUPLEX 0x00000004 - -struct snd_rawmidi_info { - unsigned int device; /* RO/WR (control): device number */ - unsigned int subdevice; /* RO/WR (control): subdevice number */ - int stream; /* WR: stream */ - int card; /* R: card number */ - unsigned int flags; /* SNDRV_RAWMIDI_INFO_XXXX */ - unsigned char id[64]; /* ID (user selectable) */ - unsigned char name[80]; /* name of device */ - unsigned char subname[32]; /* name of active or selected subdevice */ - unsigned int subdevices_count; - unsigned int subdevices_avail; - unsigned char reserved[64]; /* reserved for future use */ -}; - -struct snd_rawmidi_params { - int stream; - size_t buffer_size; /* queue size in bytes */ - size_t avail_min; /* minimum avail bytes for wakeup */ - unsigned int no_active_sensing: 1; /* do not send active sensing byte in close() */ - unsigned char reserved[16]; /* reserved for future use */ -}; - -struct snd_rawmidi_status { - int stream; - struct timespec tstamp; /* Timestamp */ - size_t avail; /* available bytes */ - size_t xruns; /* count of overruns since last status (in bytes) */ - unsigned char reserved[16]; /* reserved for future use */ -}; - -#define SNDRV_RAWMIDI_IOCTL_PVERSION _IOR('W', 0x00, int) -#define SNDRV_RAWMIDI_IOCTL_INFO _IOR('W', 0x01, struct snd_rawmidi_info) -#define SNDRV_RAWMIDI_IOCTL_PARAMS _IOWR('W', 0x10, struct snd_rawmidi_params) -#define SNDRV_RAWMIDI_IOCTL_STATUS _IOWR('W', 0x20, struct snd_rawmidi_status) -#define SNDRV_RAWMIDI_IOCTL_DROP _IOW('W', 0x30, int) -#define SNDRV_RAWMIDI_IOCTL_DRAIN _IOW('W', 0x31, int) - -/* - * Timer section - /dev/snd/timer - */ - -#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 6) - -enum { - SNDRV_TIMER_CLASS_NONE = -1, - SNDRV_TIMER_CLASS_SLAVE = 0, - SNDRV_TIMER_CLASS_GLOBAL, - SNDRV_TIMER_CLASS_CARD, - SNDRV_TIMER_CLASS_PCM, - SNDRV_TIMER_CLASS_LAST = SNDRV_TIMER_CLASS_PCM, -}; - -/* slave timer classes */ -enum { - SNDRV_TIMER_SCLASS_NONE = 0, - SNDRV_TIMER_SCLASS_APPLICATION, - SNDRV_TIMER_SCLASS_SEQUENCER, /* alias */ - SNDRV_TIMER_SCLASS_OSS_SEQUENCER, /* alias */ - SNDRV_TIMER_SCLASS_LAST = SNDRV_TIMER_SCLASS_OSS_SEQUENCER, -}; - -/* global timers (device member) */ -#define SNDRV_TIMER_GLOBAL_SYSTEM 0 -#define SNDRV_TIMER_GLOBAL_RTC 1 /* unused */ -#define SNDRV_TIMER_GLOBAL_HPET 2 -#define SNDRV_TIMER_GLOBAL_HRTIMER 3 - -/* info flags */ -#define SNDRV_TIMER_FLG_SLAVE (1<<0) /* cannot be controlled */ - -struct snd_timer_id { - int dev_class; - int dev_sclass; - int card; - int device; - int subdevice; -}; - -struct snd_timer_ginfo { - struct snd_timer_id tid; /* requested timer ID */ - unsigned int flags; /* timer flags - SNDRV_TIMER_FLG_* */ - int card; /* card number */ - unsigned char id[64]; /* timer identification */ - unsigned char name[80]; /* timer name */ - unsigned long reserved0; /* reserved for future use */ - unsigned long resolution; /* average period resolution in ns */ - unsigned long resolution_min; /* minimal period resolution in ns */ - unsigned long resolution_max; /* maximal period resolution in ns */ - unsigned int clients; /* active timer clients */ - unsigned char reserved[32]; -}; - -struct snd_timer_gparams { - struct snd_timer_id tid; /* requested timer ID */ - unsigned long period_num; /* requested precise period duration (in seconds) - numerator */ - unsigned long period_den; /* requested precise period duration (in seconds) - denominator */ - unsigned char reserved[32]; -}; - -struct snd_timer_gstatus { - struct snd_timer_id tid; /* requested timer ID */ - unsigned long resolution; /* current period resolution in ns */ - unsigned long resolution_num; /* precise current period resolution (in seconds) - numerator */ - unsigned long resolution_den; /* precise current period resolution (in seconds) - denominator */ - unsigned char reserved[32]; -}; - -struct snd_timer_select { - struct snd_timer_id id; /* bind to timer ID */ - unsigned char reserved[32]; /* reserved */ -}; - -struct snd_timer_info { - unsigned int flags; /* timer flags - SNDRV_TIMER_FLG_* */ - int card; /* card number */ - unsigned char id[64]; /* timer identificator */ - unsigned char name[80]; /* timer name */ - unsigned long reserved0; /* reserved for future use */ - unsigned long resolution; /* average period resolution in ns */ - unsigned char reserved[64]; /* reserved */ -}; - -#define SNDRV_TIMER_PSFLG_AUTO (1<<0) /* auto start, otherwise one-shot */ -#define SNDRV_TIMER_PSFLG_EXCLUSIVE (1<<1) /* exclusive use, precise start/stop/pause/continue */ -#define SNDRV_TIMER_PSFLG_EARLY_EVENT (1<<2) /* write early event to the poll queue */ - -struct snd_timer_params { - unsigned int flags; /* flags - SNDRV_MIXER_PSFLG_* */ - unsigned int ticks; /* requested resolution in ticks */ - unsigned int queue_size; /* total size of queue (32-1024) */ - unsigned int reserved0; /* reserved, was: failure locations */ - unsigned int filter; /* event filter (bitmask of SNDRV_TIMER_EVENT_*) */ - unsigned char reserved[60]; /* reserved */ -}; - -struct snd_timer_status { - struct timespec tstamp; /* Timestamp - last update */ - unsigned int resolution; /* current period resolution in ns */ - unsigned int lost; /* counter of master tick lost */ - unsigned int overrun; /* count of read queue overruns */ - unsigned int queue; /* used queue size */ - unsigned char reserved[64]; /* reserved */ -}; - -#define SNDRV_TIMER_IOCTL_PVERSION _IOR('T', 0x00, int) -#define SNDRV_TIMER_IOCTL_NEXT_DEVICE _IOWR('T', 0x01, struct snd_timer_id) -#define SNDRV_TIMER_IOCTL_TREAD _IOW('T', 0x02, int) -#define SNDRV_TIMER_IOCTL_GINFO _IOWR('T', 0x03, struct snd_timer_ginfo) -#define SNDRV_TIMER_IOCTL_GPARAMS _IOW('T', 0x04, struct snd_timer_gparams) -#define SNDRV_TIMER_IOCTL_GSTATUS _IOWR('T', 0x05, struct snd_timer_gstatus) -#define SNDRV_TIMER_IOCTL_SELECT _IOW('T', 0x10, struct snd_timer_select) -#define SNDRV_TIMER_IOCTL_INFO _IOR('T', 0x11, struct snd_timer_info) -#define SNDRV_TIMER_IOCTL_PARAMS _IOW('T', 0x12, struct snd_timer_params) -#define SNDRV_TIMER_IOCTL_STATUS _IOR('T', 0x14, struct snd_timer_status) -/* The following four ioctls are changed since 1.0.9 due to confliction */ -#define SNDRV_TIMER_IOCTL_START _IO('T', 0xa0) -#define SNDRV_TIMER_IOCTL_STOP _IO('T', 0xa1) -#define SNDRV_TIMER_IOCTL_CONTINUE _IO('T', 0xa2) -#define SNDRV_TIMER_IOCTL_PAUSE _IO('T', 0xa3) - -struct snd_timer_read { - unsigned int resolution; - unsigned int ticks; -}; - -enum { - SNDRV_TIMER_EVENT_RESOLUTION = 0, /* val = resolution in ns */ - SNDRV_TIMER_EVENT_TICK, /* val = ticks */ - SNDRV_TIMER_EVENT_START, /* val = resolution in ns */ - SNDRV_TIMER_EVENT_STOP, /* val = 0 */ - SNDRV_TIMER_EVENT_CONTINUE, /* val = resolution in ns */ - SNDRV_TIMER_EVENT_PAUSE, /* val = 0 */ - SNDRV_TIMER_EVENT_EARLY, /* val = 0, early event */ - SNDRV_TIMER_EVENT_SUSPEND, /* val = 0 */ - SNDRV_TIMER_EVENT_RESUME, /* val = resolution in ns */ - /* master timer events for slave timer instances */ - SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10, - SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10, - SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10, - SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10, - SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10, - SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10, -}; - -struct snd_timer_tread { - int event; - struct timespec tstamp; - unsigned int val; -}; - -/**************************************************************************** - * * - * Section for driver control interface - /dev/snd/control? * - * * - ****************************************************************************/ - -#define SNDRV_CTL_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 7) - -struct snd_ctl_card_info { - int card; /* card number */ - int pad; /* reserved for future (was type) */ - unsigned char id[16]; /* ID of card (user selectable) */ - unsigned char driver[16]; /* Driver name */ - unsigned char name[32]; /* Short name of soundcard */ - unsigned char longname[80]; /* name + info text about soundcard */ - unsigned char reserved_[16]; /* reserved for future (was ID of mixer) */ - unsigned char mixername[80]; /* visual mixer identification */ - unsigned char components[128]; /* card components / fine identification, delimited with one space (AC97 etc..) */ -}; - -typedef int __bitwise snd_ctl_elem_type_t; -#define SNDRV_CTL_ELEM_TYPE_NONE ((snd_ctl_elem_type_t) 0) /* invalid */ -#define SNDRV_CTL_ELEM_TYPE_BOOLEAN ((snd_ctl_elem_type_t) 1) /* boolean type */ -#define SNDRV_CTL_ELEM_TYPE_INTEGER ((snd_ctl_elem_type_t) 2) /* integer type */ -#define SNDRV_CTL_ELEM_TYPE_ENUMERATED ((snd_ctl_elem_type_t) 3) /* enumerated type */ -#define SNDRV_CTL_ELEM_TYPE_BYTES ((snd_ctl_elem_type_t) 4) /* byte array */ -#define SNDRV_CTL_ELEM_TYPE_IEC958 ((snd_ctl_elem_type_t) 5) /* IEC958 (S/PDIF) setup */ -#define SNDRV_CTL_ELEM_TYPE_INTEGER64 ((snd_ctl_elem_type_t) 6) /* 64-bit integer type */ -#define SNDRV_CTL_ELEM_TYPE_LAST SNDRV_CTL_ELEM_TYPE_INTEGER64 - -typedef int __bitwise snd_ctl_elem_iface_t; -#define SNDRV_CTL_ELEM_IFACE_CARD ((snd_ctl_elem_iface_t) 0) /* global control */ -#define SNDRV_CTL_ELEM_IFACE_HWDEP ((snd_ctl_elem_iface_t) 1) /* hardware dependent device */ -#define SNDRV_CTL_ELEM_IFACE_MIXER ((snd_ctl_elem_iface_t) 2) /* virtual mixer device */ -#define SNDRV_CTL_ELEM_IFACE_PCM ((snd_ctl_elem_iface_t) 3) /* PCM device */ -#define SNDRV_CTL_ELEM_IFACE_RAWMIDI ((snd_ctl_elem_iface_t) 4) /* RawMidi device */ -#define SNDRV_CTL_ELEM_IFACE_TIMER ((snd_ctl_elem_iface_t) 5) /* timer device */ -#define SNDRV_CTL_ELEM_IFACE_SEQUENCER ((snd_ctl_elem_iface_t) 6) /* sequencer client */ -#define SNDRV_CTL_ELEM_IFACE_LAST SNDRV_CTL_ELEM_IFACE_SEQUENCER - -#define SNDRV_CTL_ELEM_ACCESS_READ (1<<0) -#define SNDRV_CTL_ELEM_ACCESS_WRITE (1<<1) -#define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE) -#define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1<<2) /* control value may be changed without a notification */ -#define SNDRV_CTL_ELEM_ACCESS_TIMESTAMP (1<<3) /* when was control changed */ -#define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1<<4) /* TLV read is possible */ -#define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1<<5) /* TLV write is possible */ -#define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ|SNDRV_CTL_ELEM_ACCESS_TLV_WRITE) -#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1<<6) /* TLV command is possible */ -#define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1<<8) /* control does actually nothing, but may be updated */ -#define SNDRV_CTL_ELEM_ACCESS_LOCK (1<<9) /* write lock */ -#define SNDRV_CTL_ELEM_ACCESS_OWNER (1<<10) /* write lock owner */ -#define SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK (1<<28) /* kernel use a TLV callback */ -#define SNDRV_CTL_ELEM_ACCESS_USER (1<<29) /* user space element */ -/* bits 30 and 31 are obsoleted (for indirect access) */ - -/* for further details see the ACPI and PCI power management specification */ -#define SNDRV_CTL_POWER_D0 0x0000 /* full On */ -#define SNDRV_CTL_POWER_D1 0x0100 /* partial On */ -#define SNDRV_CTL_POWER_D2 0x0200 /* partial On */ -#define SNDRV_CTL_POWER_D3 0x0300 /* Off */ -#define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3|0x0000) /* Off, with power */ -#define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3|0x0001) /* Off, without power */ - -#define SNDRV_CTL_ELEM_ID_NAME_MAXLEN 44 - -struct snd_ctl_elem_id { - unsigned int numid; /* numeric identifier, zero = invalid */ - snd_ctl_elem_iface_t iface; /* interface identifier */ - unsigned int device; /* device/client number */ - unsigned int subdevice; /* subdevice (substream) number */ - unsigned char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; /* ASCII name of item */ - unsigned int index; /* index of item */ -}; - -struct snd_ctl_elem_list { - unsigned int offset; /* W: first element ID to get */ - unsigned int space; /* W: count of element IDs to get */ - unsigned int used; /* R: count of element IDs set */ - unsigned int count; /* R: count of all elements */ - struct snd_ctl_elem_id *pids; /* R: IDs */ - unsigned char reserved[50]; -}; - -struct snd_ctl_elem_info { - struct snd_ctl_elem_id id; /* W: element ID */ - snd_ctl_elem_type_t type; /* R: value type - SNDRV_CTL_ELEM_TYPE_* */ - unsigned int access; /* R: value access (bitmask) - SNDRV_CTL_ELEM_ACCESS_* */ - unsigned int count; /* count of values */ - __kernel_pid_t owner; /* owner's PID of this control */ - union { - struct { - long min; /* R: minimum value */ - long max; /* R: maximum value */ - long step; /* R: step (0 variable) */ - } integer; - struct { - long long min; /* R: minimum value */ - long long max; /* R: maximum value */ - long long step; /* R: step (0 variable) */ - } integer64; - struct { - unsigned int items; /* R: number of items */ - unsigned int item; /* W: item number */ - char name[64]; /* R: value name */ - __u64 names_ptr; /* W: names list (ELEM_ADD only) */ - unsigned int names_length; - } enumerated; - unsigned char reserved[128]; - } value; - union { - unsigned short d[4]; /* dimensions */ - unsigned short *d_ptr; /* indirect - obsoleted */ - } dimen; - unsigned char reserved[64-4*sizeof(unsigned short)]; -}; - -struct snd_ctl_elem_value { - struct snd_ctl_elem_id id; /* W: element ID */ - unsigned int indirect: 1; /* W: indirect access - obsoleted */ - union { - union { - long value[128]; - long *value_ptr; /* obsoleted */ - } integer; - union { - long long value[64]; - long long *value_ptr; /* obsoleted */ - } integer64; - union { - unsigned int item[128]; - unsigned int *item_ptr; /* obsoleted */ - } enumerated; - union { - unsigned char data[512]; - unsigned char *data_ptr; /* obsoleted */ - } bytes; - struct snd_aes_iec958 iec958; - } value; /* RO */ - struct timespec tstamp; - unsigned char reserved[128-sizeof(struct timespec)]; -}; - -struct snd_ctl_tlv { - unsigned int numid; /* control element numeric identification */ - unsigned int length; /* in bytes aligned to 4 */ - unsigned int tlv[0]; /* first TLV */ -}; - -#define SNDRV_CTL_IOCTL_PVERSION _IOR('U', 0x00, int) -#define SNDRV_CTL_IOCTL_CARD_INFO _IOR('U', 0x01, struct snd_ctl_card_info) -#define SNDRV_CTL_IOCTL_ELEM_LIST _IOWR('U', 0x10, struct snd_ctl_elem_list) -#define SNDRV_CTL_IOCTL_ELEM_INFO _IOWR('U', 0x11, struct snd_ctl_elem_info) -#define SNDRV_CTL_IOCTL_ELEM_READ _IOWR('U', 0x12, struct snd_ctl_elem_value) -#define SNDRV_CTL_IOCTL_ELEM_WRITE _IOWR('U', 0x13, struct snd_ctl_elem_value) -#define SNDRV_CTL_IOCTL_ELEM_LOCK _IOW('U', 0x14, struct snd_ctl_elem_id) -#define SNDRV_CTL_IOCTL_ELEM_UNLOCK _IOW('U', 0x15, struct snd_ctl_elem_id) -#define SNDRV_CTL_IOCTL_SUBSCRIBE_EVENTS _IOWR('U', 0x16, int) -#define SNDRV_CTL_IOCTL_ELEM_ADD _IOWR('U', 0x17, struct snd_ctl_elem_info) -#define SNDRV_CTL_IOCTL_ELEM_REPLACE _IOWR('U', 0x18, struct snd_ctl_elem_info) -#define SNDRV_CTL_IOCTL_ELEM_REMOVE _IOWR('U', 0x19, struct snd_ctl_elem_id) -#define SNDRV_CTL_IOCTL_TLV_READ _IOWR('U', 0x1a, struct snd_ctl_tlv) -#define SNDRV_CTL_IOCTL_TLV_WRITE _IOWR('U', 0x1b, struct snd_ctl_tlv) -#define SNDRV_CTL_IOCTL_TLV_COMMAND _IOWR('U', 0x1c, struct snd_ctl_tlv) -#define SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE _IOWR('U', 0x20, int) -#define SNDRV_CTL_IOCTL_HWDEP_INFO _IOR('U', 0x21, struct snd_hwdep_info) -#define SNDRV_CTL_IOCTL_PCM_NEXT_DEVICE _IOR('U', 0x30, int) -#define SNDRV_CTL_IOCTL_PCM_INFO _IOWR('U', 0x31, struct snd_pcm_info) -#define SNDRV_CTL_IOCTL_PCM_PREFER_SUBDEVICE _IOW('U', 0x32, int) -#define SNDRV_CTL_IOCTL_RAWMIDI_NEXT_DEVICE _IOWR('U', 0x40, int) -#define SNDRV_CTL_IOCTL_RAWMIDI_INFO _IOWR('U', 0x41, struct snd_rawmidi_info) -#define SNDRV_CTL_IOCTL_RAWMIDI_PREFER_SUBDEVICE _IOW('U', 0x42, int) -#define SNDRV_CTL_IOCTL_POWER _IOWR('U', 0xd0, int) -#define SNDRV_CTL_IOCTL_POWER_STATE _IOR('U', 0xd1, int) - -/* - * Read interface. - */ - -enum sndrv_ctl_event_type { - SNDRV_CTL_EVENT_ELEM = 0, - SNDRV_CTL_EVENT_LAST = SNDRV_CTL_EVENT_ELEM, -}; - -#define SNDRV_CTL_EVENT_MASK_VALUE (1<<0) /* element value was changed */ -#define SNDRV_CTL_EVENT_MASK_INFO (1<<1) /* element info was changed */ -#define SNDRV_CTL_EVENT_MASK_ADD (1<<2) /* element was added */ -#define SNDRV_CTL_EVENT_MASK_TLV (1<<3) /* element TLV tree was changed */ -#define SNDRV_CTL_EVENT_MASK_REMOVE (~0U) /* element was removed */ - -struct snd_ctl_event { - int type; /* event type - SNDRV_CTL_EVENT_* */ - union { - struct { - unsigned int mask; - struct snd_ctl_elem_id id; - } elem; - unsigned char data8[60]; - } data; -}; - -/* - * Control names - */ - -#define SNDRV_CTL_NAME_NONE "" -#define SNDRV_CTL_NAME_PLAYBACK "Playback " -#define SNDRV_CTL_NAME_CAPTURE "Capture " - -#define SNDRV_CTL_NAME_IEC958_NONE "" -#define SNDRV_CTL_NAME_IEC958_SWITCH "Switch" -#define SNDRV_CTL_NAME_IEC958_VOLUME "Volume" -#define SNDRV_CTL_NAME_IEC958_DEFAULT "Default" -#define SNDRV_CTL_NAME_IEC958_MASK "Mask" -#define SNDRV_CTL_NAME_IEC958_CON_MASK "Con Mask" -#define SNDRV_CTL_NAME_IEC958_PRO_MASK "Pro Mask" -#define SNDRV_CTL_NAME_IEC958_PCM_STREAM "PCM Stream" -#define SNDRV_CTL_NAME_IEC958(expl,direction,what) "IEC958 " expl SNDRV_CTL_NAME_##direction SNDRV_CTL_NAME_IEC958_##what - -#endif /* __SOUND_ASOUND_H */ diff --git a/sdm710/original-kernel-headers/sound/audio_effects.h b/sdm710/original-kernel-headers/sound/audio_effects.h deleted file mode 100644 index 0ac887cd..00000000 --- a/sdm710/original-kernel-headers/sound/audio_effects.h +++ /dev/null @@ -1,361 +0,0 @@ -#ifndef _AUDIO_EFFECTS_H -#define _AUDIO_EFFECTS_H - -/** AUDIO EFFECTS **/ - - -/* CONFIG GET/SET */ -#define CONFIG_CACHE 0 -#define CONFIG_SET 1 -#define CONFIG_GET 2 - -/* CONFIG HEADER */ -/* - * MODULE_ID, - * DEVICE, - * NUM_COMMANDS, - * COMMAND_ID_1, - * CONFIG_CACHE/SET/GET, - * OFFSET_1, - * LENGTH_1, - * VALUES_1, - * ..., - * ..., - * COMMAND_ID_2, - * CONFIG_CACHE/SET/GET, - * OFFSET_2, - * LENGTH_2, - * VALUES_2, - * ..., - * ..., - * COMMAND_ID_3, - * ... - */ - - -/* CONFIG PARAM IDs */ -#define VIRTUALIZER_MODULE 0x00001000 -#define VIRTUALIZER_ENABLE 0x00001001 -#define VIRTUALIZER_STRENGTH 0x00001002 -#define VIRTUALIZER_OUT_TYPE 0x00001003 -#define VIRTUALIZER_GAIN_ADJUST 0x00001004 -#define VIRTUALIZER_ENABLE_PARAM_LEN 1 -#define VIRTUALIZER_STRENGTH_PARAM_LEN 1 -#define VIRTUALIZER_OUT_TYPE_PARAM_LEN 1 -#define VIRTUALIZER_GAIN_ADJUST_PARAM_LEN 1 - -#define REVERB_MODULE 0x00002000 -#define REVERB_ENABLE 0x00002001 -#define REVERB_MODE 0x00002002 -#define REVERB_PRESET 0x00002003 -#define REVERB_WET_MIX 0x00002004 -#define REVERB_GAIN_ADJUST 0x00002005 -#define REVERB_ROOM_LEVEL 0x00002006 -#define REVERB_ROOM_HF_LEVEL 0x00002007 -#define REVERB_DECAY_TIME 0x00002008 -#define REVERB_DECAY_HF_RATIO 0x00002009 -#define REVERB_REFLECTIONS_LEVEL 0x0000200a -#define REVERB_REFLECTIONS_DELAY 0x0000200b -#define REVERB_LEVEL 0x0000200c -#define REVERB_DELAY 0x0000200d -#define REVERB_DIFFUSION 0x0000200e -#define REVERB_DENSITY 0x0000200f -#define REVERB_ENABLE_PARAM_LEN 1 -#define REVERB_MODE_PARAM_LEN 1 -#define REVERB_PRESET_PARAM_LEN 1 -#define REVERB_WET_MIX_PARAM_LEN 1 -#define REVERB_GAIN_ADJUST_PARAM_LEN 1 -#define REVERB_ROOM_LEVEL_PARAM_LEN 1 -#define REVERB_ROOM_HF_LEVEL_PARAM_LEN 1 -#define REVERB_DECAY_TIME_PARAM_LEN 1 -#define REVERB_DECAY_HF_RATIO_PARAM_LEN 1 -#define REVERB_REFLECTIONS_LEVEL_PARAM_LEN 1 -#define REVERB_REFLECTIONS_DELAY_PARAM_LEN 1 -#define REVERB_LEVEL_PARAM_LEN 1 -#define REVERB_DELAY_PARAM_LEN 1 -#define REVERB_DIFFUSION_PARAM_LEN 1 -#define REVERB_DENSITY_PARAM_LEN 1 - -#define BASS_BOOST_MODULE 0x00003000 -#define BASS_BOOST_ENABLE 0x00003001 -#define BASS_BOOST_MODE 0x00003002 -#define BASS_BOOST_STRENGTH 0x00003003 -#define BASS_BOOST_ENABLE_PARAM_LEN 1 -#define BASS_BOOST_MODE_PARAM_LEN 1 -#define BASS_BOOST_STRENGTH_PARAM_LEN 1 - -#define EQ_MODULE 0x00004000 -#define EQ_ENABLE 0x00004001 -#define EQ_CONFIG 0x00004002 -#define EQ_NUM_BANDS 0x00004003 -#define EQ_BAND_LEVELS 0x00004004 -#define EQ_BAND_LEVEL_RANGE 0x00004005 -#define EQ_BAND_FREQS 0x00004006 -#define EQ_SINGLE_BAND_FREQ_RANGE 0x00004007 -#define EQ_SINGLE_BAND_FREQ 0x00004008 -#define EQ_BAND_INDEX 0x00004009 -#define EQ_PRESET_ID 0x0000400a -#define EQ_NUM_PRESETS 0x0000400b -#define EQ_PRESET_NAME 0x0000400c -#define EQ_ENABLE_PARAM_LEN 1 -#define EQ_CONFIG_PARAM_LEN 3 -#define EQ_CONFIG_PER_BAND_PARAM_LEN 5 -#define EQ_NUM_BANDS_PARAM_LEN 1 -#define EQ_BAND_LEVELS_PARAM_LEN 13 -#define EQ_BAND_LEVEL_RANGE_PARAM_LEN 2 -#define EQ_BAND_FREQS_PARAM_LEN 13 -#define EQ_SINGLE_BAND_FREQ_RANGE_PARAM_LEN 2 -#define EQ_SINGLE_BAND_FREQ_PARAM_LEN 1 -#define EQ_BAND_INDEX_PARAM_LEN 1 -#define EQ_PRESET_ID_PARAM_LEN 1 -#define EQ_NUM_PRESETS_PARAM_LEN 1 -#define EQ_PRESET_NAME_PARAM_LEN 32 - -#define EQ_TYPE_NONE 0 -#define EQ_BASS_BOOST 1 -#define EQ_BASS_CUT 2 -#define EQ_TREBLE_BOOST 3 -#define EQ_TREBLE_CUT 4 -#define EQ_BAND_BOOST 5 -#define EQ_BAND_CUT 6 - -#define SOFT_VOLUME_MODULE 0x00006000 -#define SOFT_VOLUME_ENABLE 0x00006001 -#define SOFT_VOLUME_GAIN_2CH 0x00006002 -#define SOFT_VOLUME_GAIN_MASTER 0x00006003 -#define SOFT_VOLUME_ENABLE_PARAM_LEN 1 -#define SOFT_VOLUME_GAIN_2CH_PARAM_LEN 2 -#define SOFT_VOLUME_GAIN_MASTER_PARAM_LEN 1 - -#define SOFT_VOLUME2_MODULE 0x00007000 -#define SOFT_VOLUME2_ENABLE 0x00007001 -#define SOFT_VOLUME2_GAIN_2CH 0x00007002 -#define SOFT_VOLUME2_GAIN_MASTER 0x00007003 -#define SOFT_VOLUME2_ENABLE_PARAM_LEN SOFT_VOLUME_ENABLE_PARAM_LEN -#define SOFT_VOLUME2_GAIN_2CH_PARAM_LEN SOFT_VOLUME_GAIN_2CH_PARAM_LEN -#define SOFT_VOLUME2_GAIN_MASTER_PARAM_LEN \ - SOFT_VOLUME_GAIN_MASTER_PARAM_LEN - -#define PBE_CONF_MODULE_ID 0x00010C2A -#define PBE_CONF_PARAM_ID 0x00010C49 - -#define PBE_MODULE 0x00008000 -#define PBE_ENABLE 0x00008001 -#define PBE_CONFIG 0x00008002 -#define PBE_ENABLE_PARAM_LEN 1 -#define PBE_CONFIG_PARAM_LEN 28 - -#define COMMAND_PAYLOAD_LEN 3 -#define COMMAND_PAYLOAD_SZ (COMMAND_PAYLOAD_LEN * sizeof(uint32_t)) -#define MAX_INBAND_PARAM_SZ 4096 -#define Q27_UNITY (1 << 27) -#define Q8_UNITY (1 << 8) -#define CUSTOM_OPENSL_PRESET 18 - -#define VIRTUALIZER_ENABLE_PARAM_SZ \ - (VIRTUALIZER_ENABLE_PARAM_LEN*sizeof(uint32_t)) -#define VIRTUALIZER_STRENGTH_PARAM_SZ \ - (VIRTUALIZER_STRENGTH_PARAM_LEN*sizeof(uint32_t)) -#define VIRTUALIZER_OUT_TYPE_PARAM_SZ \ - (VIRTUALIZER_OUT_TYPE_PARAM_LEN*sizeof(uint32_t)) -#define VIRTUALIZER_GAIN_ADJUST_PARAM_SZ \ - (VIRTUALIZER_GAIN_ADJUST_PARAM_LEN*sizeof(uint32_t)) -struct virtualizer_params { - uint32_t device; - uint32_t enable_flag; - uint32_t strength; - uint32_t out_type; - int32_t gain_adjust; -}; - -#define NUM_OSL_REVERB_PRESETS_SUPPORTED 6 -#define REVERB_ENABLE_PARAM_SZ \ - (REVERB_ENABLE_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_MODE_PARAM_SZ \ - (REVERB_MODE_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_PRESET_PARAM_SZ \ - (REVERB_PRESET_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_WET_MIX_PARAM_SZ \ - (REVERB_WET_MIX_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_GAIN_ADJUST_PARAM_SZ \ - (REVERB_GAIN_ADJUST_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_ROOM_LEVEL_PARAM_SZ \ - (REVERB_ROOM_LEVEL_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_ROOM_HF_LEVEL_PARAM_SZ \ - (REVERB_ROOM_HF_LEVEL_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_DECAY_TIME_PARAM_SZ \ - (REVERB_DECAY_TIME_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_DECAY_HF_RATIO_PARAM_SZ \ - (REVERB_DECAY_HF_RATIO_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_REFLECTIONS_LEVEL_PARAM_SZ \ - (REVERB_REFLECTIONS_LEVEL_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_REFLECTIONS_DELAY_PARAM_SZ \ - (REVERB_REFLECTIONS_DELAY_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_LEVEL_PARAM_SZ \ - (REVERB_LEVEL_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_DELAY_PARAM_SZ \ - (REVERB_DELAY_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_DIFFUSION_PARAM_SZ \ - (REVERB_DIFFUSION_PARAM_LEN*sizeof(uint32_t)) -#define REVERB_DENSITY_PARAM_SZ \ - (REVERB_DENSITY_PARAM_LEN*sizeof(uint32_t)) -struct reverb_params { - uint32_t device; - uint32_t enable_flag; - uint32_t mode; - uint32_t preset; - uint32_t wet_mix; - int32_t gain_adjust; - int32_t room_level; - int32_t room_hf_level; - uint32_t decay_time; - uint32_t decay_hf_ratio; - int32_t reflections_level; - uint32_t reflections_delay; - int32_t level; - uint32_t delay; - uint32_t diffusion; - uint32_t density; -}; - -#define BASS_BOOST_ENABLE_PARAM_SZ \ - (BASS_BOOST_ENABLE_PARAM_LEN*sizeof(uint32_t)) -#define BASS_BOOST_MODE_PARAM_SZ \ - (BASS_BOOST_MODE_PARAM_LEN*sizeof(uint32_t)) -#define BASS_BOOST_STRENGTH_PARAM_SZ \ - (BASS_BOOST_STRENGTH_PARAM_LEN*sizeof(uint32_t)) -struct bass_boost_params { - uint32_t device; - uint32_t enable_flag; - uint32_t mode; - uint32_t strength; -}; - - -#define MAX_EQ_BANDS 12 -#define MAX_OSL_EQ_BANDS 5 -#define EQ_ENABLE_PARAM_SZ \ - (EQ_ENABLE_PARAM_LEN*sizeof(uint32_t)) -#define EQ_CONFIG_PARAM_SZ \ - (EQ_CONFIG_PARAM_LEN*sizeof(uint32_t)) -#define EQ_CONFIG_PER_BAND_PARAM_SZ \ - (EQ_CONFIG_PER_BAND_PARAM_LEN*sizeof(uint32_t)) -#define EQ_CONFIG_PARAM_MAX_LEN (EQ_CONFIG_PARAM_LEN+\ - MAX_EQ_BANDS*EQ_CONFIG_PER_BAND_PARAM_LEN) -#define EQ_CONFIG_PARAM_MAX_SZ \ - (EQ_CONFIG_PARAM_MAX_LEN*sizeof(uint32_t)) -#define EQ_NUM_BANDS_PARAM_SZ \ - (EQ_NUM_BANDS_PARAM_LEN*sizeof(uint32_t)) -#define EQ_BAND_LEVELS_PARAM_SZ \ - (EQ_BAND_LEVELS_PARAM_LEN*sizeof(uint32_t)) -#define EQ_BAND_LEVEL_RANGE_PARAM_SZ \ - (EQ_BAND_LEVEL_RANGE_PARAM_LEN*sizeof(uint32_t)) -#define EQ_BAND_FREQS_PARAM_SZ \ - (EQ_BAND_FREQS_PARAM_LEN*sizeof(uint32_t)) -#define EQ_SINGLE_BAND_FREQ_RANGE_PARAM_SZ \ - (EQ_SINGLE_BAND_FREQ_RANGE_PARAM_LEN*sizeof(uint32_t)) -#define EQ_SINGLE_BAND_FREQ_PARAM_SZ \ - (EQ_SINGLE_BAND_FREQ_PARAM_LEN*sizeof(uint32_t)) -#define EQ_BAND_INDEX_PARAM_SZ \ - (EQ_BAND_INDEX_PARAM_LEN*sizeof(uint32_t)) -#define EQ_PRESET_ID_PARAM_SZ \ - (EQ_PRESET_ID_PARAM_LEN*sizeof(uint32_t)) -#define EQ_NUM_PRESETS_PARAM_SZ \ - (EQ_NUM_PRESETS_PARAM_LEN*sizeof(uint8_t)) -struct eq_config_t { - int32_t eq_pregain; - int32_t preset_id; - uint32_t num_bands; -}; -struct eq_per_band_config_t { - int32_t band_idx; - uint32_t filter_type; - uint32_t freq_millihertz; - int32_t gain_millibels; - uint32_t quality_factor; -}; -struct eq_per_band_freq_range_t { - uint32_t band_index; - uint32_t min_freq_millihertz; - uint32_t max_freq_millihertz; -}; - -struct eq_params { - uint32_t device; - uint32_t enable_flag; - struct eq_config_t config; - struct eq_per_band_config_t per_band_cfg[MAX_EQ_BANDS]; - struct eq_per_band_freq_range_t per_band_freq_range[MAX_EQ_BANDS]; - uint32_t band_index; - uint32_t freq_millihertz; -}; - -#define PBE_ENABLE_PARAM_SZ \ - (PBE_ENABLE_PARAM_LEN*sizeof(uint32_t)) -#define PBE_CONFIG_PARAM_SZ \ - (PBE_CONFIG_PARAM_LEN*sizeof(uint16_t)) -struct pbe_config_t { - int16_t real_bass_mix; - int16_t bass_color_control; - uint16_t main_chain_delay; - uint16_t xover_filter_order; - uint16_t bandpass_filter_order; - int16_t drc_delay; - uint16_t rms_tav; - int16_t exp_threshold; - uint16_t exp_slope; - int16_t comp_threshold; - uint16_t comp_slope; - uint16_t makeup_gain; - uint32_t comp_attack; - uint32_t comp_release; - uint32_t exp_attack; - uint32_t exp_release; - int16_t limiter_bass_threshold; - int16_t limiter_high_threshold; - int16_t limiter_bass_makeup_gain; - int16_t limiter_high_makeup_gain; - int16_t limiter_bass_gc; - int16_t limiter_high_gc; - int16_t limiter_delay; - uint16_t reserved; - /* place holder for filter coeffs to be followed */ - int32_t p1LowPassCoeffs[5*2]; - int32_t p1HighPassCoeffs[5*2]; - int32_t p1BandPassCoeffs[5*3]; - int32_t p1BassShelfCoeffs[5]; - int32_t p1TrebleShelfCoeffs[5]; -} __attribute__((packed)); - -struct pbe_params { - uint32_t device; - uint32_t enable_flag; - uint32_t cfg_len; - struct pbe_config_t config; -}; - -#define SOFT_VOLUME_ENABLE_PARAM_SZ \ - (SOFT_VOLUME_ENABLE_PARAM_LEN*sizeof(uint32_t)) -#define SOFT_VOLUME_GAIN_MASTER_PARAM_SZ \ - (SOFT_VOLUME_GAIN_MASTER_PARAM_LEN*sizeof(uint32_t)) -#define SOFT_VOLUME_GAIN_2CH_PARAM_SZ \ - (SOFT_VOLUME_GAIN_2CH_PARAM_LEN*sizeof(uint16_t)) -struct soft_volume_params { - uint32_t device; - uint32_t enable_flag; - uint32_t master_gain; - uint32_t left_gain; - uint32_t right_gain; -}; - -struct msm_nt_eff_all_config { - struct bass_boost_params bass_boost; - struct pbe_params pbe; - struct virtualizer_params virtualizer; - struct reverb_params reverb; - struct eq_params equalizer; - struct soft_volume_params saplus_vol; - struct soft_volume_params topo_switch_vol; -}; - -#endif /*_MSM_AUDIO_EFFECTS_H*/ diff --git a/sdm710/original-kernel-headers/sound/compress_offload.h b/sdm710/original-kernel-headers/sound/compress_offload.h deleted file mode 100644 index 866ec3d2..00000000 --- a/sdm710/original-kernel-headers/sound/compress_offload.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - * compress_offload.h - compress offload header definations - * - * Copyright (C) 2011 Intel Corporation - * Authors: Vinod Koul <vinod.koul@linux.intel.com> - * Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. - * - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - */ -#ifndef __COMPRESS_OFFLOAD_H -#define __COMPRESS_OFFLOAD_H - -#include <linux/types.h> -#include <sound/asound.h> -#include <sound/compress_params.h> - - -#define SNDRV_COMPRESS_VERSION SNDRV_PROTOCOL_VERSION(0, 1, 2) -/** - * struct snd_compressed_buffer - compressed buffer - * @fragment_size: size of buffer fragment in bytes - * @fragments: number of such fragments - */ -struct snd_compressed_buffer { - __u32 fragment_size; - __u32 fragments; -} __attribute__((packed, aligned(4))); - -/** - * struct snd_compr_params - compressed stream params - * @buffer: buffer description - * @codec: codec parameters - * @no_wake_mode: dont wake on fragment elapsed - */ -struct snd_compr_params { - struct snd_compressed_buffer buffer; - struct snd_codec codec; - __u8 no_wake_mode; -} __attribute__((packed, aligned(4))); - -/** - * struct snd_compr_tstamp - timestamp descriptor - * @byte_offset: Byte offset in ring buffer to DSP - * @copied_total: Total number of bytes copied from/to ring buffer to/by DSP - * @pcm_frames: Frames decoded or encoded by DSP. This field will evolve by - * large steps and should only be used to monitor encoding/decoding - * progress. It shall not be used for timing estimates. - * @pcm_io_frames: Frames rendered or received by DSP into a mixer or an audio - * output/input. This field should be used for A/V sync or time estimates. - * @sampling_rate: sampling rate of audio - */ -struct snd_compr_tstamp { - __u32 byte_offset; - __u64 copied_total; - __u32 pcm_frames; - __u32 pcm_io_frames; - __u32 sampling_rate; - __u64 timestamp; -} __attribute__((packed, aligned(4))); - -/** - * struct snd_compr_avail - avail descriptor - * @avail: Number of bytes available in ring buffer for writing/reading - * @tstamp: timestamp information - */ -struct snd_compr_avail { - __u64 avail; - struct snd_compr_tstamp tstamp; -} __attribute__((packed, aligned(4))); - -enum snd_compr_direction { - SND_COMPRESS_PLAYBACK = 0, - SND_COMPRESS_CAPTURE -}; - -/** - * struct snd_compr_caps - caps descriptor - * @codecs: pointer to array of codecs - * @direction: direction supported. Of type snd_compr_direction - * @min_fragment_size: minimum fragment supported by DSP - * @max_fragment_size: maximum fragment supported by DSP - * @min_fragments: min fragments supported by DSP - * @max_fragments: max fragments supported by DSP - * @num_codecs: number of codecs supported - * @reserved: reserved field - */ -struct snd_compr_caps { - __u32 num_codecs; - __u32 direction; - __u32 min_fragment_size; - __u32 max_fragment_size; - __u32 min_fragments; - __u32 max_fragments; - __u32 codecs[MAX_NUM_CODECS]; - __u32 reserved[11]; -} __attribute__((packed, aligned(4))); - -/** - * struct snd_compr_codec_caps - query capability of codec - * @codec: codec for which capability is queried - * @num_descriptors: number of codec descriptors - * @descriptor: array of codec capability descriptor - */ -struct snd_compr_codec_caps { - __u32 codec; - __u32 num_descriptors; - struct snd_codec_desc descriptor[MAX_NUM_CODEC_DESCRIPTORS]; -} __attribute__((packed, aligned(4))); - -/** - * struct snd_compr_audio_info: compressed input audio information - * @frame_size: legth of the encoded frame with valid data - * @reserved: reserved for furture use - */ -struct snd_compr_audio_info { - __u32 frame_size; - __u32 reserved[15]; -} __attribute__((packed, aligned(4))); - -#define SNDRV_COMPRESS_RENDER_MODE_AUDIO_MASTER 0 -#define SNDRV_COMPRESS_RENDER_MODE_STC_MASTER 1 - -#define SNDRV_COMPRESS_CLK_REC_MODE_NONE 0 -#define SNDRV_COMPRESS_CLK_REC_MODE_AUTO 1 - -/** - * enum sndrv_compress_encoder - * @SNDRV_COMPRESS_ENCODER_PADDING: no of samples appended by the encoder at the - * end of the track - * @SNDRV_COMPRESS_ENCODER_DELAY: no of samples inserted by the encoder at the - * beginning of the track - * @SNDRV_COMPRESS_PATH_DELAY: dsp path delay in microseconds - * @SNDRV_COMPRESS_RENDER_MODE: dsp render mode (audio master or stc) - * @SNDRV_COMPRESS_CLK_REC_MODE: clock recovery mode ( none or auto) - * @SNDRV_COMPRESS_RENDER_WINDOW: render window - * @SNDRV_COMPRESS_START_DELAY: start delay - * @SNDRV_COMPRESS_ENABLE_ADJUST_SESSION_CLOCK: enable dsp drift correction - * @SNDRV_COMPRESS_ADJUST_SESSION_CLOCK: set drift correction value - */ -enum sndrv_compress_encoder { - SNDRV_COMPRESS_ENCODER_PADDING = 1, - SNDRV_COMPRESS_ENCODER_DELAY = 2, - SNDRV_COMPRESS_MIN_BLK_SIZE = 3, - SNDRV_COMPRESS_MAX_BLK_SIZE = 4, - SNDRV_COMPRESS_PATH_DELAY = 5, - SNDRV_COMPRESS_RENDER_MODE = 6, - SNDRV_COMPRESS_CLK_REC_MODE = 7, - SNDRV_COMPRESS_RENDER_WINDOW = 8, - SNDRV_COMPRESS_START_DELAY = 9, - SNDRV_COMPRESS_ENABLE_ADJUST_SESSION_CLOCK = 10, - SNDRV_COMPRESS_ADJUST_SESSION_CLOCK = 11, -}; - -#define SNDRV_COMPRESS_PATH_DELAY SNDRV_COMPRESS_PATH_DELAY -#define SNDRV_COMPRESS_RENDER_MODE SNDRV_COMPRESS_RENDER_MODE -#define SNDRV_COMPRESS_CLK_REC_MODE SNDRV_COMPRESS_CLK_REC_MODE -#define SNDRV_COMPRESS_RENDER_WINDOW SNDRV_COMPRESS_RENDER_WINDOW -#define SNDRV_COMPRESS_START_DELAY SNDRV_COMPRESS_START_DELAY -#define SNDRV_COMPRESS_ENABLE_ADJUST_SESSION_CLOCK \ - SNDRV_COMPRESS_ENABLE_ADJUST_SESSION_CLOCK -#define SNDRV_COMPRESS_ADJUST_SESSION_CLOCK SNDRV_COMPRESS_ADJUST_SESSION_CLOCK - -/** - * struct snd_compr_metadata - compressed stream metadata - * @key: key id - * @value: key value - */ -struct snd_compr_metadata { - __u32 key; - __u32 value[8]; -} __attribute__((packed, aligned(4))); - -/** - * compress path ioctl definitions - * SNDRV_COMPRESS_GET_CAPS: Query capability of DSP - * SNDRV_COMPRESS_GET_CODEC_CAPS: Query capability of a codec - * SNDRV_COMPRESS_SET_PARAMS: Set codec and stream parameters - * Note: only codec params can be changed runtime and stream params cant be - * SNDRV_COMPRESS_GET_PARAMS: Query codec params - * SNDRV_COMPRESS_TSTAMP: get the current timestamp value - * SNDRV_COMPRESS_AVAIL: get the current buffer avail value. - * This also queries the tstamp properties - * SNDRV_COMPRESS_PAUSE: Pause the running stream - * SNDRV_COMPRESS_RESUME: resume a paused stream - * SNDRV_COMPRESS_START: Start a stream - * SNDRV_COMPRESS_STOP: stop a running stream, discarding ring buffer content - * and the buffers currently with DSP - * SNDRV_COMPRESS_DRAIN: Play till end of buffers and stop after that - * SNDRV_COMPRESS_SET_NEXT_TRACK_PARAM: send codec specific data for the next - * track in gapless - * SNDRV_COMPRESS_IOCTL_VERSION: Query the API version - */ -#define SNDRV_COMPRESS_IOCTL_VERSION _IOR('C', 0x00, int) -#define SNDRV_COMPRESS_GET_CAPS _IOWR('C', 0x10, struct snd_compr_caps) -#define SNDRV_COMPRESS_GET_CODEC_CAPS _IOWR('C', 0x11,\ - struct snd_compr_codec_caps) -#define SNDRV_COMPRESS_SET_PARAMS _IOW('C', 0x12, struct snd_compr_params) -#define SNDRV_COMPRESS_GET_PARAMS _IOR('C', 0x13, struct snd_codec) -#define SNDRV_COMPRESS_SET_METADATA _IOW('C', 0x14,\ - struct snd_compr_metadata) -#define SNDRV_COMPRESS_GET_METADATA _IOWR('C', 0x15,\ - struct snd_compr_metadata) -#define SNDRV_COMPRESS_TSTAMP _IOR('C', 0x20, struct snd_compr_tstamp) -#define SNDRV_COMPRESS_AVAIL _IOR('C', 0x21, struct snd_compr_avail) -#define SNDRV_COMPRESS_PAUSE _IO('C', 0x30) -#define SNDRV_COMPRESS_RESUME _IO('C', 0x31) -#define SNDRV_COMPRESS_START _IO('C', 0x32) -#define SNDRV_COMPRESS_STOP _IO('C', 0x33) -#define SNDRV_COMPRESS_DRAIN _IO('C', 0x34) -#define SNDRV_COMPRESS_NEXT_TRACK _IO('C', 0x35) -#define SNDRV_COMPRESS_PARTIAL_DRAIN _IO('C', 0x36) -#define SNDRV_COMPRESS_SET_NEXT_TRACK_PARAM\ - _IOW('C', 0x80, union snd_codec_options) -/* - * TODO - * 1. add mmap support - * - */ -#define SND_COMPR_TRIGGER_DRAIN 7 /*FIXME move this to pcm.h */ -#define SND_COMPR_TRIGGER_NEXT_TRACK 8 -#define SND_COMPR_TRIGGER_PARTIAL_DRAIN 9 -#endif diff --git a/sdm710/original-kernel-headers/sound/compress_params.h b/sdm710/original-kernel-headers/sound/compress_params.h deleted file mode 100644 index 278bf12b..00000000 --- a/sdm710/original-kernel-headers/sound/compress_params.h +++ /dev/null @@ -1,524 +0,0 @@ -/* - * compress_params.h - codec types and parameters for compressed data - * streaming interface - * - * Copyright (C) 2011 Intel Corporation - * Authors: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> - * Vinod Koul <vinod.koul@linux.intel.com> - * - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. - * - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * The definitions in this file are derived from the OpenMAX AL version 1.1 - * and OpenMAX IL v 1.1.2 header files which contain the copyright notice below. - * - * Copyright (c) 2007-2010 The Khronos Group Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and/or associated documentation files (the - * "Materials "), to deal in the Materials without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Materials, and to - * permit persons to whom the Materials are furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Materials. - * - * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. - * - */ -#ifndef __SND_COMPRESS_PARAMS_H -#define __SND_COMPRESS_PARAMS_H - -#include <linux/types.h> - -#define SND_DEC_DDP_MAX_PARAMS 18 - -/* AUDIO CODECS SUPPORTED */ -#define MAX_NUM_CODECS 32 -#define MAX_NUM_CODEC_DESCRIPTORS 32 -#define MAX_NUM_BITRATES 32 -#define MAX_NUM_SAMPLE_RATES 32 - -/* compressed TX */ -#define MAX_NUM_FRAMES_PER_BUFFER 1 -#define COMPRESSED_META_DATA_MODE 0x10 -#define META_DATA_LEN_BYTES 36 -#define Q6_AC3_DECODER 0x00010BF6 -#define Q6_EAC3_DECODER 0x00010C3C -#define Q6_DTS 0x00010D88 -#define Q6_DTS_LBR 0x00010DBB - -/* Timestamp flsg */ -/* Bit-0 - 1 : Enable Timestamp mode */ -/* Bit-0 - 0 : Disable Timestamp mode */ -#define COMPRESSED_TIMESTAMP_FLAG 0x0001 - -/* Codecs are listed linearly to allow for extensibility */ -#define SND_AUDIOCODEC_PCM ((__u32) 0x00000001) -#define SND_AUDIOCODEC_MP3 ((__u32) 0x00000002) -#define SND_AUDIOCODEC_AMR ((__u32) 0x00000003) -#define SND_AUDIOCODEC_AMRWB ((__u32) 0x00000004) -#define SND_AUDIOCODEC_AMRWBPLUS ((__u32) 0x00000005) -#define SND_AUDIOCODEC_AAC ((__u32) 0x00000006) -#define SND_AUDIOCODEC_WMA ((__u32) 0x00000007) -#define SND_AUDIOCODEC_REAL ((__u32) 0x00000008) -#define SND_AUDIOCODEC_VORBIS ((__u32) 0x00000009) -#define SND_AUDIOCODEC_FLAC ((__u32) 0x0000000A) -#define SND_AUDIOCODEC_IEC61937 ((__u32) 0x0000000B) -#define SND_AUDIOCODEC_G723_1 ((__u32) 0x0000000C) -#define SND_AUDIOCODEC_G729 ((__u32) 0x0000000D) -#define SND_AUDIOCODEC_BESPOKE ((__u32) 0x0000000E) -#define SND_AUDIOCODEC_DTS_PASS_THROUGH ((__u32) 0x0000000F) -#define SND_AUDIOCODEC_DTS_LBR ((__u32) 0x00000010) -#define SND_AUDIOCODEC_DTS_TRANSCODE_LOOPBACK ((__u32) 0x00000011) -#define SND_AUDIOCODEC_PASS_THROUGH ((__u32) 0x00000012) -#define SND_AUDIOCODEC_MP2 ((__u32) 0x00000013) -#define SND_AUDIOCODEC_DTS_LBR_PASS_THROUGH ((__u32) 0x00000014) -#define SND_AUDIOCODEC_AC3 ((__u32) 0x00000015) -#define SND_AUDIOCODEC_AC3_PASS_THROUGH ((__u32) 0x00000016) -#define SND_AUDIOCODEC_WMA_PRO ((__u32) 0x00000017) -#define SND_AUDIOCODEC_DTS ((__u32) 0x00000018) -#define SND_AUDIOCODEC_EAC3 ((__u32) 0x00000019) -#define SND_AUDIOCODEC_ALAC ((__u32) 0x00000020) -#define SND_AUDIOCODEC_APE ((__u32) 0x00000021) -#define SND_AUDIOCODEC_DSD ((__u32) 0x00000022) -#define SND_AUDIOCODEC_APTX ((__u32) 0x00000023) -#define SND_AUDIOCODEC_TRUEHD ((__u32) 0x00000024) -#define SND_AUDIOCODEC_MAX SND_AUDIOCODEC_TRUEHD - -/* - * Profile and modes are listed with bit masks. This allows for a - * more compact representation of fields that will not evolve - * (in contrast to the list of codecs) - */ - -#define SND_AUDIOPROFILE_PCM ((__u32) 0x00000001) - -/* MP3 modes are only useful for encoders */ -#define SND_AUDIOCHANMODE_MP3_MONO ((__u32) 0x00000001) -#define SND_AUDIOCHANMODE_MP3_STEREO ((__u32) 0x00000002) -#define SND_AUDIOCHANMODE_MP3_JOINTSTEREO ((__u32) 0x00000004) -#define SND_AUDIOCHANMODE_MP3_DUAL ((__u32) 0x00000008) - -#define SND_AUDIOPROFILE_AMR ((__u32) 0x00000001) - -/* AMR modes are only useful for encoders */ -#define SND_AUDIOMODE_AMR_DTX_OFF ((__u32) 0x00000001) -#define SND_AUDIOMODE_AMR_VAD1 ((__u32) 0x00000002) -#define SND_AUDIOMODE_AMR_VAD2 ((__u32) 0x00000004) - -#define SND_AUDIOSTREAMFORMAT_UNDEFINED ((__u32) 0x00000000) -#define SND_AUDIOSTREAMFORMAT_CONFORMANCE ((__u32) 0x00000001) -#define SND_AUDIOSTREAMFORMAT_IF1 ((__u32) 0x00000002) -#define SND_AUDIOSTREAMFORMAT_IF2 ((__u32) 0x00000004) -#define SND_AUDIOSTREAMFORMAT_FSF ((__u32) 0x00000008) -#define SND_AUDIOSTREAMFORMAT_RTPPAYLOAD ((__u32) 0x00000010) -#define SND_AUDIOSTREAMFORMAT_ITU ((__u32) 0x00000020) - -#define SND_AUDIOPROFILE_AMRWB ((__u32) 0x00000001) - -/* AMRWB modes are only useful for encoders */ -#define SND_AUDIOMODE_AMRWB_DTX_OFF ((__u32) 0x00000001) -#define SND_AUDIOMODE_AMRWB_VAD1 ((__u32) 0x00000002) -#define SND_AUDIOMODE_AMRWB_VAD2 ((__u32) 0x00000004) - -#define SND_AUDIOPROFILE_AMRWBPLUS ((__u32) 0x00000001) - -#define SND_AUDIOPROFILE_AAC ((__u32) 0x00000001) - -/* AAC modes are required for encoders and decoders */ -#define SND_AUDIOMODE_AAC_MAIN ((__u32) 0x00000001) -#define SND_AUDIOMODE_AAC_LC ((__u32) 0x00000002) -#define SND_AUDIOMODE_AAC_SSR ((__u32) 0x00000004) -#define SND_AUDIOMODE_AAC_LTP ((__u32) 0x00000008) -#define SND_AUDIOMODE_AAC_HE ((__u32) 0x00000010) -#define SND_AUDIOMODE_AAC_SCALABLE ((__u32) 0x00000020) -#define SND_AUDIOMODE_AAC_ERLC ((__u32) 0x00000040) -#define SND_AUDIOMODE_AAC_LD ((__u32) 0x00000080) -#define SND_AUDIOMODE_AAC_HE_PS ((__u32) 0x00000100) -#define SND_AUDIOMODE_AAC_HE_MPS ((__u32) 0x00000200) - -/* AAC formats are required for encoders and decoders */ -#define SND_AUDIOSTREAMFORMAT_MP2ADTS ((__u32) 0x00000001) -#define SND_AUDIOSTREAMFORMAT_MP4ADTS ((__u32) 0x00000002) -#define SND_AUDIOSTREAMFORMAT_MP4LOAS ((__u32) 0x00000004) -#define SND_AUDIOSTREAMFORMAT_MP4LATM ((__u32) 0x00000008) -#define SND_AUDIOSTREAMFORMAT_ADIF ((__u32) 0x00000010) -#define SND_AUDIOSTREAMFORMAT_MP4FF ((__u32) 0x00000020) -#define SND_AUDIOSTREAMFORMAT_RAW ((__u32) 0x00000040) - -#define SND_AUDIOPROFILE_WMA7 ((__u32) 0x00000001) -#define SND_AUDIOPROFILE_WMA8 ((__u32) 0x00000002) -#define SND_AUDIOPROFILE_WMA9 ((__u32) 0x00000004) -#define SND_AUDIOPROFILE_WMA10 ((__u32) 0x00000008) - -#define SND_AUDIOMODE_WMA_LEVEL1 ((__u32) 0x00000001) -#define SND_AUDIOMODE_WMA_LEVEL2 ((__u32) 0x00000002) -#define SND_AUDIOMODE_WMA_LEVEL3 ((__u32) 0x00000004) -#define SND_AUDIOMODE_WMA_LEVEL4 ((__u32) 0x00000008) -#define SND_AUDIOMODE_WMAPRO_LEVELM0 ((__u32) 0x00000010) -#define SND_AUDIOMODE_WMAPRO_LEVELM1 ((__u32) 0x00000020) -#define SND_AUDIOMODE_WMAPRO_LEVELM2 ((__u32) 0x00000040) -#define SND_AUDIOMODE_WMAPRO_LEVELM3 ((__u32) 0x00000080) - -#define SND_AUDIOSTREAMFORMAT_WMA_ASF ((__u32) 0x00000001) -/* - * Some implementations strip the ASF header and only send ASF packets - * to the DSP - */ -#define SND_AUDIOSTREAMFORMAT_WMA_NOASF_HDR ((__u32) 0x00000002) - -#define SND_AUDIOPROFILE_REALAUDIO ((__u32) 0x00000001) - -#define SND_AUDIOMODE_REALAUDIO_G2 ((__u32) 0x00000001) -#define SND_AUDIOMODE_REALAUDIO_8 ((__u32) 0x00000002) -#define SND_AUDIOMODE_REALAUDIO_10 ((__u32) 0x00000004) -#define SND_AUDIOMODE_REALAUDIO_SURROUND ((__u32) 0x00000008) - -#define SND_AUDIOPROFILE_VORBIS ((__u32) 0x00000001) - -#define SND_AUDIOMODE_VORBIS ((__u32) 0x00000001) - -#define SND_AUDIOPROFILE_FLAC ((__u32) 0x00000001) - -/* - * Define quality levels for FLAC encoders, from LEVEL0 (fast) - * to LEVEL8 (best) - */ -#define SND_AUDIOMODE_FLAC_LEVEL0 ((__u32) 0x00000001) -#define SND_AUDIOMODE_FLAC_LEVEL1 ((__u32) 0x00000002) -#define SND_AUDIOMODE_FLAC_LEVEL2 ((__u32) 0x00000004) -#define SND_AUDIOMODE_FLAC_LEVEL3 ((__u32) 0x00000008) -#define SND_AUDIOMODE_FLAC_LEVEL4 ((__u32) 0x00000010) -#define SND_AUDIOMODE_FLAC_LEVEL5 ((__u32) 0x00000020) -#define SND_AUDIOMODE_FLAC_LEVEL6 ((__u32) 0x00000040) -#define SND_AUDIOMODE_FLAC_LEVEL7 ((__u32) 0x00000080) -#define SND_AUDIOMODE_FLAC_LEVEL8 ((__u32) 0x00000100) - -#define SND_AUDIOSTREAMFORMAT_FLAC ((__u32) 0x00000001) -#define SND_AUDIOSTREAMFORMAT_FLAC_OGG ((__u32) 0x00000002) - -/* IEC61937 payloads without CUVP and preambles */ -#define SND_AUDIOPROFILE_IEC61937 ((__u32) 0x00000001) -/* IEC61937 with S/PDIF preambles+CUVP bits in 32-bit containers */ -#define SND_AUDIOPROFILE_IEC61937_SPDIF ((__u32) 0x00000002) - -/* - * IEC modes are mandatory for decoders. Format autodetection - * will only happen on the DSP side with mode 0. The PCM mode should - * not be used, the PCM codec should be used instead. - */ -#define SND_AUDIOMODE_IEC_REF_STREAM_HEADER ((__u32) 0x00000000) -#define SND_AUDIOMODE_IEC_LPCM ((__u32) 0x00000001) -#define SND_AUDIOMODE_IEC_AC3 ((__u32) 0x00000002) -#define SND_AUDIOMODE_IEC_MPEG1 ((__u32) 0x00000004) -#define SND_AUDIOMODE_IEC_MP3 ((__u32) 0x00000008) -#define SND_AUDIOMODE_IEC_MPEG2 ((__u32) 0x00000010) -#define SND_AUDIOMODE_IEC_AACLC ((__u32) 0x00000020) -#define SND_AUDIOMODE_IEC_DTS ((__u32) 0x00000040) -#define SND_AUDIOMODE_IEC_ATRAC ((__u32) 0x00000080) -#define SND_AUDIOMODE_IEC_SACD ((__u32) 0x00000100) -#define SND_AUDIOMODE_IEC_EAC3 ((__u32) 0x00000200) -#define SND_AUDIOMODE_IEC_DTS_HD ((__u32) 0x00000400) -#define SND_AUDIOMODE_IEC_MLP ((__u32) 0x00000800) -#define SND_AUDIOMODE_IEC_DST ((__u32) 0x00001000) -#define SND_AUDIOMODE_IEC_WMAPRO ((__u32) 0x00002000) -#define SND_AUDIOMODE_IEC_REF_CXT ((__u32) 0x00004000) -#define SND_AUDIOMODE_IEC_HE_AAC ((__u32) 0x00008000) -#define SND_AUDIOMODE_IEC_HE_AAC2 ((__u32) 0x00010000) -#define SND_AUDIOMODE_IEC_MPEG_SURROUND ((__u32) 0x00020000) - -#define SND_AUDIOPROFILE_G723_1 ((__u32) 0x00000001) - -#define SND_AUDIOMODE_G723_1_ANNEX_A ((__u32) 0x00000001) -#define SND_AUDIOMODE_G723_1_ANNEX_B ((__u32) 0x00000002) -#define SND_AUDIOMODE_G723_1_ANNEX_C ((__u32) 0x00000004) - -#define SND_AUDIOPROFILE_G729 ((__u32) 0x00000001) - -#define SND_AUDIOMODE_G729_ANNEX_A ((__u32) 0x00000001) -#define SND_AUDIOMODE_G729_ANNEX_B ((__u32) 0x00000002) - -/* <FIXME: multichannel encoders aren't supported for now. Would need - an additional definition of channel arrangement> */ - -/* VBR/CBR definitions */ -#define SND_RATECONTROLMODE_CONSTANTBITRATE ((__u32) 0x00000001) -#define SND_RATECONTROLMODE_VARIABLEBITRATE ((__u32) 0x00000002) - -/* Encoder options */ - -struct snd_enc_wma { - __u32 super_block_align; /* WMA Type-specific data */ - __u32 bits_per_sample; - __u32 channelmask; - __u32 encodeopt; - __u32 encodeopt1; - __u32 encodeopt2; - __u32 avg_bit_rate; -}; - - -/** - * struct snd_enc_vorbis - * @quality: Sets encoding quality to n, between -1 (low) and 10 (high). - * In the default mode of operation, the quality level is 3. - * Normal quality range is 0 - 10. - * @managed: Boolean. Set bitrate management mode. This turns off the - * normal VBR encoding, but allows hard or soft bitrate constraints to be - * enforced by the encoder. This mode can be slower, and may also be - * lower quality. It is primarily useful for streaming. - * @max_bit_rate: Enabled only if managed is TRUE - * @min_bit_rate: Enabled only if managed is TRUE - * @downmix: Boolean. Downmix input from stereo to mono (has no effect on - * non-stereo streams). Useful for lower-bitrate encoding. - * - * These options were extracted from the OpenMAX IL spec and Gstreamer vorbisenc - * properties - * - * For best quality users should specify VBR mode and set quality levels. - */ - -struct snd_enc_vorbis { - __s32 quality; - __u32 managed; - __u32 max_bit_rate; - __u32 min_bit_rate; - __u32 downmix; -} __attribute__((packed, aligned(4))); - - -/** - * struct snd_enc_real - * @quant_bits: number of coupling quantization bits in the stream - * @start_region: coupling start region in the stream - * @num_regions: number of regions value - * - * These options were extracted from the OpenMAX IL spec - */ - -struct snd_enc_real { - __u32 quant_bits; - __u32 start_region; - __u32 num_regions; -} __attribute__((packed, aligned(4))); - -/** - * struct snd_enc_flac - * @num: serial number, valid only for OGG formats - * needs to be set by application - * @gain: Add replay gain tags - * - * These options were extracted from the FLAC online documentation - * at http://flac.sourceforge.net/documentation_tools_flac.html - * - * To make the API simpler, it is assumed that the user will select quality - * profiles. Additional options that affect encoding quality and speed can - * be added at a later stage if needed. - * - * By default the Subset format is used by encoders. - * - * TAGS such as pictures, etc, cannot be handled by an offloaded encoder and are - * not supported in this API. - */ - -struct snd_enc_flac { - __u32 num; - __u32 gain; -} __attribute__((packed, aligned(4))); - -struct snd_enc_generic { - __u32 bw; /* encoder bandwidth */ - __s32 reserved[15]; /* Can be used for SND_AUDIOCODEC_BESPOKE */ -} __attribute__((packed, aligned(4))); - -struct snd_dec_ddp { - __u32 params_length; - __u32 params_id[SND_DEC_DDP_MAX_PARAMS]; - __u32 params_value[SND_DEC_DDP_MAX_PARAMS]; -} __attribute__((packed, aligned(4))); - -struct snd_dec_flac { - __u16 sample_size; - __u16 min_blk_size; - __u16 max_blk_size; - __u16 min_frame_size; - __u16 max_frame_size; -} __attribute__((packed, aligned(4))); - -struct snd_dec_vorbis { - __u32 bit_stream_fmt; -}; - -struct snd_dec_alac { - __u32 frame_length; - __u8 compatible_version; - __u8 bit_depth; - __u8 pb; - __u8 mb; - __u8 kb; - __u8 num_channels; - __u16 max_run; - __u32 max_frame_bytes; - __u32 avg_bit_rate; - __u32 sample_rate; - __u32 channel_layout_tag; -}; - -struct snd_dec_ape { - __u16 compatible_version; - __u16 compression_level; - __u32 format_flags; - __u32 blocks_per_frame; - __u32 final_frame_blocks; - __u32 total_frames; - __u16 bits_per_sample; - __u16 num_channels; - __u32 sample_rate; - __u32 seek_table_present; -}; - -struct snd_dec_aptx { - __u32 lap; - __u32 uap; - __u32 nap; -}; - -struct snd_dec_amrwb_plus { - __u32 bit_stream_fmt; -}; - -union snd_codec_options { - struct snd_enc_wma wma; - struct snd_enc_vorbis vorbis; - struct snd_enc_real real; - struct snd_enc_flac flac; - struct snd_enc_generic generic; - struct snd_dec_ddp ddp; - struct snd_dec_flac flac_dec; - struct snd_dec_vorbis vorbis_dec; - struct snd_dec_alac alac; - struct snd_dec_ape ape; - struct snd_dec_aptx aptx_dec; - struct snd_dec_amrwb_plus amrwbplus; -}; - -/** struct snd_codec_desc - description of codec capabilities - * @max_ch: Maximum number of audio channels - * @sample_rates: Sampling rates in Hz, use values like 48000 for this - * @num_sample_rates: Number of valid values in sample_rates array - * @bit_rate: Indexed array containing supported bit rates - * @num_bitrates: Number of valid values in bit_rate array - * @rate_control: value is specified by SND_RATECONTROLMODE defines. - * @profiles: Supported profiles. See SND_AUDIOPROFILE defines. - * @modes: Supported modes. See SND_AUDIOMODE defines - * @formats: Supported formats. See SND_AUDIOSTREAMFORMAT defines - * @min_buffer: Minimum buffer size handled by codec implementation - * @reserved: reserved for future use - * - * This structure provides a scalar value for profiles, modes and stream - * format fields. - * If an implementation supports multiple combinations, they will be listed as - * codecs with different descriptors, for example there would be 2 descriptors - * for AAC-RAW and AAC-ADTS. - * This entails some redundancy but makes it easier to avoid invalid - * configurations. - * - */ - -struct snd_codec_desc { - __u32 max_ch; - __u32 sample_rates[MAX_NUM_SAMPLE_RATES]; - __u32 num_sample_rates; - __u32 bit_rate[MAX_NUM_BITRATES]; - __u32 num_bitrates; - __u32 rate_control; - __u32 profiles; - __u32 modes; - __u32 formats; - __u32 min_buffer; - __u32 reserved[15]; -} __attribute__((packed, aligned(4))); - -/** struct snd_codec - * @id: Identifies the supported audio encoder/decoder. - * See SND_AUDIOCODEC macros. - * @ch_in: Number of input audio channels - * @ch_out: Number of output channels. In case of contradiction between - * this field and the channelMode field, the channelMode field - * overrides. - * @sample_rate: Audio sample rate of input data in Hz, use values like 48000 - * for this. - * @bit_rate: Bitrate of encoded data. May be ignored by decoders - * @rate_control: Encoding rate control. See SND_RATECONTROLMODE defines. - * Encoders may rely on profiles for quality levels. - * May be ignored by decoders. - * @profile: Mandatory for encoders, can be mandatory for specific - * decoders as well. See SND_AUDIOPROFILE defines. - * @level: Supported level (Only used by WMA at the moment) - * @ch_mode: Channel mode for encoder. See SND_AUDIOCHANMODE defines - * @format: Format of encoded bistream. Mandatory when defined. - * See SND_AUDIOSTREAMFORMAT defines. - * @align: Block alignment in bytes of an audio sample. - * Only required for PCM or IEC formats. - * @options: encoder-specific settings - * @reserved: reserved for future use - */ - -struct snd_codec { - __u32 id; - __u32 ch_in; - __u32 ch_out; - __u32 sample_rate; - __u32 bit_rate; - __u32 rate_control; - __u32 profile; - __u32 level; - __u32 ch_mode; - __u32 format; - __u32 align; - __u32 compr_passthr; - union snd_codec_options options; - __u32 flags; - __u32 reserved[2]; -} __attribute__((packed, aligned(4))); - - -/** struct snd_codec_metadata - * @length: Length of the encoded buffer. - * @offset: Offset from the buffer address to the first byte of the first - * encoded frame. All encoded frames are consecutive starting - * from this offset. - * @timestamp: Session time in microseconds of the first sample in the buffer. - * @reserved: Reserved for future use. - */ -struct snd_codec_metadata { - __u32 length; - __u32 offset; - __u64 timestamp; - __u32 reserved[4]; -}; - -#endif diff --git a/sdm710/original-kernel-headers/sound/devdep_params.h b/sdm710/original-kernel-headers/sound/devdep_params.h deleted file mode 100644 index b4a185f7..00000000 --- a/sdm710/original-kernel-headers/sound/devdep_params.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef _DEV_DEP_H -#define _DEV_DEP_H - -struct dolby_param_data { - int32_t version; - int32_t device_id; - int32_t be_id; - int32_t param_id; - int32_t length; - int32_t *data; -}; - -struct dolby_param_license { - int32_t dmid; - int32_t license_key; -}; - -#define SNDRV_DEVDEP_DAP_IOCTL_SET_PARAM\ - _IOWR('U', 0x10, struct dolby_param_data) -#define SNDRV_DEVDEP_DAP_IOCTL_GET_PARAM\ - _IOR('U', 0x11, struct dolby_param_data) -#define SNDRV_DEVDEP_DAP_IOCTL_DAP_COMMAND\ - _IOWR('U', 0x13, struct dolby_param_data) -#define SNDRV_DEVDEP_DAP_IOCTL_DAP_LICENSE\ - _IOWR('U', 0x14, struct dolby_param_license) -#define SNDRV_DEVDEP_DAP_IOCTL_GET_VISUALIZER\ - _IOR('U', 0x15, struct dolby_param_data) - -#define DTS_EAGLE_MODULE 0x00005000 -#define DTS_EAGLE_MODULE_ENABLE 0x00005001 -#define EAGLE_DRIVER_ID 0xF2 -#define DTS_EAGLE_IOCTL_GET_CACHE_SIZE _IOR(EAGLE_DRIVER_ID, 0, int) -#define DTS_EAGLE_IOCTL_SET_CACHE_SIZE _IOW(EAGLE_DRIVER_ID, 1, int) -#define DTS_EAGLE_IOCTL_GET_PARAM _IOR(EAGLE_DRIVER_ID, 2, void*) -#define DTS_EAGLE_IOCTL_SET_PARAM _IOW(EAGLE_DRIVER_ID, 3, void*) -#define DTS_EAGLE_IOCTL_SET_CACHE_BLOCK _IOW(EAGLE_DRIVER_ID, 4, void*) -#define DTS_EAGLE_IOCTL_SET_ACTIVE_DEVICE _IOW(EAGLE_DRIVER_ID, 5, void*) -#define DTS_EAGLE_IOCTL_GET_LICENSE _IOR(EAGLE_DRIVER_ID, 6, void*) -#define DTS_EAGLE_IOCTL_SET_LICENSE _IOW(EAGLE_DRIVER_ID, 7, void*) -#define DTS_EAGLE_IOCTL_SEND_LICENSE _IOW(EAGLE_DRIVER_ID, 8, int) -#define DTS_EAGLE_IOCTL_SET_VOLUME_COMMANDS _IOW(EAGLE_DRIVER_ID, 9, void*) -#define DTS_EAGLE_FLAG_IOCTL_PRE (1<<30) -#define DTS_EAGLE_FLAG_IOCTL_JUSTSETCACHE (1<<31) -#define DTS_EAGLE_FLAG_IOCTL_GETFROMCORE DTS_EAGLE_FLAG_IOCTL_JUSTSETCACHE -#define DTS_EAGLE_FLAG_IOCTL_MASK (~(DTS_EAGLE_FLAG_IOCTL_PRE | \ - DTS_EAGLE_FLAG_IOCTL_JUSTSETCACHE)) -#define DTS_EAGLE_FLAG_ALSA_GET (1<<31) - -struct dts_eagle_param_desc { - uint32_t id; - uint32_t size; - int32_t offset; - uint32_t device; -} __attribute__((packed)); - -#define HWDEP_FE_BASE 3000 /*unique base for FE hw dep nodes*/ -struct snd_pcm_mmap_fd { - int32_t dir; - int32_t fd; - int32_t size; - int32_t actual_size; -}; - -#define SNDRV_PCM_IOCTL_MMAP_DATA_FD _IOWR('U', 0xd2, struct snd_pcm_mmap_fd) - -#endif diff --git a/sdm710/original-kernel-headers/sound/lsm_params.h b/sdm710/original-kernel-headers/sound/lsm_params.h deleted file mode 100644 index 50ec97a0..00000000 --- a/sdm710/original-kernel-headers/sound/lsm_params.h +++ /dev/null @@ -1,200 +0,0 @@ -#ifndef _LSM_PARAMS_H__ -#define _LSM_PARAMS_H__ - -#define LSM_POLLING_ENABLE_SUPPORT -#define LSM_EVENT_TIMESTAMP_MODE_SUPPORT - -#include <linux/types.h> -#include <sound/asound.h> - -#define SNDRV_LSM_VERSION SNDRV_PROTOCOL_VERSION(0, 1, 0) - -#define LSM_OUT_FORMAT_PCM (0) -#define LSM_OUT_FORMAT_ADPCM (1 << 0) - -#define LSM_OUT_DATA_RAW (0) -#define LSM_OUT_DATA_PACKED (1) - -#define LSM_OUT_DATA_EVENTS_DISABLED (0) -#define LSM_OUT_DATA_EVENTS_ENABLED (1) - -#define LSM_OUT_TRANSFER_MODE_RT (0) -#define LSM_OUT_TRANSFER_MODE_FTRT (1) - -#define LSM_ENDPOINT_DETECT_THRESHOLD (0) -#define LSM_OPERATION_MODE (1) -#define LSM_GAIN (2) -#define LSM_MIN_CONFIDENCE_LEVELS (3) -#define LSM_REG_SND_MODEL (4) -#define LSM_DEREG_SND_MODEL (5) -#define LSM_CUSTOM_PARAMS (6) -#define LSM_POLLING_ENABLE (7) -#define LSM_PARAMS_MAX (LSM_POLLING_ENABLE + 1) - -#define LSM_EVENT_NON_TIME_STAMP_MODE (0) -#define LSM_EVENT_TIME_STAMP_MODE (1) - -enum lsm_app_id { - LSM_VOICE_WAKEUP_APP_ID = 1, - LSM_VOICE_WAKEUP_APP_ID_V2 = 2, -}; - -enum lsm_detection_mode { - LSM_MODE_KEYWORD_ONLY_DETECTION = 1, - LSM_MODE_USER_KEYWORD_DETECTION -}; - -enum lsm_vw_status { - LSM_VOICE_WAKEUP_STATUS_RUNNING = 1, - LSM_VOICE_WAKEUP_STATUS_DETECTED, - LSM_VOICE_WAKEUP_STATUS_END_SPEECH, - LSM_VOICE_WAKEUP_STATUS_REJECTED -}; - -/* - * Data for LSM_ENDPOINT_DETECT_THRESHOLD param_type - * @epd_begin: Begin threshold - * @epd_end: End threshold - */ -struct snd_lsm_ep_det_thres { - __u32 epd_begin; - __u32 epd_end; -}; - -/* - * Data for LSM_OPERATION_MODE param_type - * @mode: The detection mode to be used - * @detect_failure: Setting to enable failure detections. - */ -struct snd_lsm_detect_mode { - enum lsm_detection_mode mode; - bool detect_failure; -}; - -/* - * Data for LSM_GAIN param_type - * @gain: The gain to be applied on LSM - */ -struct snd_lsm_gain { - __u16 gain; -}; - -/* - * Data for LSM_POLLING_ENABLE param_type - * @poll_en: Polling enable or disable - */ -struct snd_lsm_poll_enable { - bool poll_en; -}; - - -struct snd_lsm_sound_model_v2 { - __u8 *data; - __u8 *confidence_level; - __u32 data_size; - enum lsm_detection_mode detection_mode; - __u8 num_confidence_levels; - bool detect_failure; -}; - -struct snd_lsm_session_data { - enum lsm_app_id app_id; -}; - -struct snd_lsm_event_status { - __u16 status; - __u16 payload_size; - __u8 payload[0]; -}; - -struct snd_lsm_event_status_v3 { - __u32 timestamp_lsw; - __u32 timestamp_msw; - __u16 status; - __u16 payload_size; - __u8 payload[0]; -}; - -struct snd_lsm_detection_params { - __u8 *conf_level; - enum lsm_detection_mode detect_mode; - __u8 num_confidence_levels; - bool detect_failure; - bool poll_enable; -}; - -/* - * Param info for each parameter type - * @module_id: Module to which parameter is to be set - * @param_id: Parameter that is to be set - * @param_size: size (in number of bytes) for the data - * in param_data. - * For confidence levels, this is num_conf_levels - * For REG_SND_MODEL, this is size of sound model - * For CUSTOM_PARAMS, this is size of the entire blob of data - * @param_data: Data for the parameter. - * For some param_types this is a structure defined, ex: LSM_GAIN - * For CONFIDENCE_LEVELS, this is array of confidence levels - * For REG_SND_MODEL, this is the sound model data - * For CUSTOM_PARAMS, this is the blob of custom data. - */ -struct lsm_params_info { - __u32 module_id; - __u32 param_id; - __u32 param_size; - __u8 *param_data; - uint32_t param_type; -}; - -/* - * Data passed to the SET_PARAM_V2 IOCTL - * @num_params: Number of params that are to be set - * should not be greater than LSM_PARAMS_MAX - * @params: Points to an array of lsm_params_info - * Each entry points to one parameter to set - * @data_size: size (in bytes) for params - * should be equal to - * num_params * sizeof(struct lsm_parms_info) - */ -struct snd_lsm_module_params { - __u8 *params; - __u32 num_params; - __u32 data_size; -}; - -/* - * Data passed to LSM_OUT_FORMAT_CFG IOCTL - * @format: The media format enum - * @packing: indicates the packing method used for data path - * @events: indicates whether data path events need to be enabled - * @transfer_mode: indicates whether FTRT mode or RT mode. - */ -struct snd_lsm_output_format_cfg { - __u8 format; - __u8 packing; - __u8 events; - __u8 mode; -}; - -#define SNDRV_LSM_DEREG_SND_MODEL _IOW('U', 0x01, int) -#define SNDRV_LSM_EVENT_STATUS _IOW('U', 0x02, struct snd_lsm_event_status) -#define SNDRV_LSM_ABORT_EVENT _IOW('U', 0x03, int) -#define SNDRV_LSM_START _IOW('U', 0x04, int) -#define SNDRV_LSM_STOP _IOW('U', 0x05, int) -#define SNDRV_LSM_SET_SESSION_DATA _IOW('U', 0x06, struct snd_lsm_session_data) -#define SNDRV_LSM_REG_SND_MODEL_V2 _IOW('U', 0x07,\ - struct snd_lsm_sound_model_v2) -#define SNDRV_LSM_LAB_CONTROL _IOW('U', 0x08, uint32_t) -#define SNDRV_LSM_STOP_LAB _IO('U', 0x09) -#define SNDRV_LSM_SET_PARAMS _IOW('U', 0x0A, \ - struct snd_lsm_detection_params) -#define SNDRV_LSM_SET_MODULE_PARAMS _IOW('U', 0x0B, \ - struct snd_lsm_module_params) -#define SNDRV_LSM_OUT_FORMAT_CFG _IOW('U', 0x0C, \ - struct snd_lsm_output_format_cfg) -#define SNDRV_LSM_SET_PORT _IO('U', 0x0D) -#define SNDRV_LSM_SET_FWK_MODE_CONFIG _IOW('U', 0x0E, uint32_t) -#define SNDRV_LSM_EVENT_STATUS_V3 _IOW('U', 0x0F, \ - struct snd_lsm_event_status_v3) - -#endif diff --git a/sdm710/original-kernel-headers/sound/msmcal-hwdep.h b/sdm710/original-kernel-headers/sound/msmcal-hwdep.h deleted file mode 100644 index abb66106..00000000 --- a/sdm710/original-kernel-headers/sound/msmcal-hwdep.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef _CALIB_HWDEP_H -#define _CALIB_HWDEP_H - -#define WCD9XXX_CODEC_HWDEP_NODE 1000 -enum wcd_cal_type { - WCD9XXX_MIN_CAL, - WCD9XXX_ANC_CAL = WCD9XXX_MIN_CAL, - WCD9XXX_MAD_CAL, - WCD9XXX_MBHC_CAL, - WCD9XXX_VBAT_CAL, - WCD9XXX_MAX_CAL, -}; - -struct wcdcal_ioctl_buffer { - __u32 size; - __u8 *buffer; - enum wcd_cal_type cal_type; -}; - -#define SNDRV_CTL_IOCTL_HWDEP_CAL_TYPE \ - _IOW('U', 0x1, struct wcdcal_ioctl_buffer) - -#endif /*_CALIB_HWDEP_H*/ diff --git a/sdm710/original-kernel-headers/sound/voice_params.h b/sdm710/original-kernel-headers/sound/voice_params.h deleted file mode 100644 index 43e3b9d0..00000000 --- a/sdm710/original-kernel-headers/sound/voice_params.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef __VOICE_PARAMS_H__ -#define __VOICE_PARAMS_H__ - -#include <linux/types.h> -#include <sound/asound.h> - -enum voice_lch_mode { - VOICE_LCH_START = 1, - VOICE_LCH_STOP -}; - -#define SNDRV_VOICE_IOCTL_LCH _IOW('U', 0x00, enum voice_lch_mode) - -#endif diff --git a/sdm710/original-kernel-headers/sound/voice_svc.h b/sdm710/original-kernel-headers/sound/voice_svc.h deleted file mode 100644 index 035053f0..00000000 --- a/sdm710/original-kernel-headers/sound/voice_svc.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef __VOICE_SVC_H__ -#define __VOICE_SVC_H__ - -#include <linux/types.h> -#include <linux/ioctl.h> - -#define VOICE_SVC_DRIVER_NAME "voice_svc" - -#define VOICE_SVC_MVM_STR "MVM" -#define VOICE_SVC_CVS_STR "CVS" -#define MAX_APR_SERVICE_NAME_LEN 64 - -#define MSG_REGISTER 0x1 -#define MSG_REQUEST 0x2 -#define MSG_RESPONSE 0x3 - -struct voice_svc_write_msg { - __u32 msg_type; - __u8 payload[0]; -}; - -struct voice_svc_register { - char svc_name[MAX_APR_SERVICE_NAME_LEN]; - __u32 src_port; - __u8 reg_flag; -}; - -struct voice_svc_cmd_response { - __u32 src_port; - __u32 dest_port; - __u32 token; - __u32 opcode; - __u32 payload_size; - __u8 payload[0]; -}; - -struct voice_svc_cmd_request { - char svc_name[MAX_APR_SERVICE_NAME_LEN]; - __u32 src_port; - __u32 dest_port; - __u32 token; - __u32 opcode; - __u32 payload_size; - __u8 payload[0]; -}; - -#endif diff --git a/sdm710/original-kernel-headers/sound/wcd-dsp-glink.h b/sdm710/original-kernel-headers/sound/wcd-dsp-glink.h deleted file mode 100644 index 39d128d3..00000000 --- a/sdm710/original-kernel-headers/sound/wcd-dsp-glink.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef _WCD_DSP_GLINK_H -#define _WCD_DSP_GLINK_H - -#include <linux/types.h> - -#define WDSP_CH_NAME_MAX_LEN 50 - -enum { - WDSP_REG_PKT = 1, - WDSP_CMD_PKT, - WDSP_READY_PKT, -}; -#define WDSP_READY_PKT WDSP_READY_PKT - -/* - * struct wdsp_reg_pkt - Glink channel information structure format - * @no_of_channels: Number of glink channels to open - * @payload[0]: Dynamic array contains all the glink channels information - */ -struct wdsp_reg_pkt { - __u8 no_of_channels; - __u8 payload[0]; -}; - -/* - * struct wdsp_cmd_pkt - WDSP command packet format - * @ch_name: Name of the glink channel - * @payload_size: Size of the payload - * @payload[0]: Actual data payload - */ -struct wdsp_cmd_pkt { - char ch_name[WDSP_CH_NAME_MAX_LEN]; - __u32 payload_size; - __u8 payload[0]; -}; - -/* - * struct wdsp_write_pkt - Format that userspace send the data to driver. - * @pkt_type: Type of the packet(REG or CMD PKT) - * @payload[0]: Payload is either cmd or reg pkt structure based on pkt type - */ -struct wdsp_write_pkt { - __u8 pkt_type; - __u8 payload[0]; -}; - -/* - * struct wdsp_glink_ch_cfg - Defines the glink channel configuration. - * @ch_name: Name of the glink channel - * @latency_in_us: Latency specified in micro seconds for QOS - * @no_of_intents: Number of intents prequeued - * @intents_size[0]: Dynamic array to specify size of each intent - */ -struct wdsp_glink_ch_cfg { - char name[WDSP_CH_NAME_MAX_LEN]; - __u32 latency_in_us; - __u32 no_of_intents; - __u32 intents_size[0]; -}; -#endif /* _WCD_DSP_GLINK_H */ diff --git a/sdm710/original-kernel-headers/video/msm_hdmi_modes.h b/sdm710/original-kernel-headers/video/msm_hdmi_modes.h deleted file mode 100644 index 7b2d6986..00000000 --- a/sdm710/original-kernel-headers/video/msm_hdmi_modes.h +++ /dev/null @@ -1,559 +0,0 @@ -#ifndef _MSM_HDMI_MODES_H__ -#define _MSM_HDMI_MODES_H__ -#include <linux/types.h> -#include <linux/errno.h> - -#define MSM_HDMI_RGB_888_24BPP_FORMAT (1 << 0) -#define MSM_HDMI_YUV_420_12BPP_FORMAT (1 << 1) - -enum aspect_ratio { - HDMI_RES_AR_INVALID, - HDMI_RES_AR_4_3, - HDMI_RES_AR_5_4, - HDMI_RES_AR_16_9, - HDMI_RES_AR_16_10, - HDMI_RES_AR_64_27, - HDMI_RES_AR_256_135, - HDMI_RES_AR_MAX, -}; - -enum msm_hdmi_s3d_mode { - HDMI_S3D_NONE, - HDMI_S3D_SIDE_BY_SIDE, - HDMI_S3D_TOP_AND_BOTTOM, - HDMI_S3D_FRAME_PACKING, - HDMI_S3D_MAX, -}; - -struct msm_hdmi_mode_timing_info { - uint32_t video_format; - uint32_t active_h; - uint32_t front_porch_h; - uint32_t pulse_width_h; - uint32_t back_porch_h; - uint32_t active_low_h; - uint32_t active_v; - uint32_t front_porch_v; - uint32_t pulse_width_v; - uint32_t back_porch_v; - uint32_t active_low_v; - /* Must divide by 1000 to get the actual frequency in MHZ */ - uint32_t pixel_freq; - /* Must divide by 1000 to get the actual frequency in HZ */ - uint32_t refresh_rate; - uint32_t interlaced; - uint32_t supported; - enum aspect_ratio ar; - /* Flags indicating support for specific pixel formats */ - uint32_t pixel_formats; -}; - -#define MSM_HDMI_INIT_RES_PAGE 1 - -#define MSM_HDMI_MODES_CEA (1 << 0) -#define MSM_HDMI_MODES_XTND (1 << 1) -#define MSM_HDMI_MODES_DVI (1 << 2) -#define MSM_HDMI_MODES_ALL (MSM_HDMI_MODES_CEA |\ - MSM_HDMI_MODES_XTND |\ - MSM_HDMI_MODES_DVI) - -/* all video formats defined by CEA 861D */ -#define HDMI_VFRMT_UNKNOWN 0 -#define HDMI_VFRMT_640x480p60_4_3 1 -#define HDMI_VFRMT_720x480p60_4_3 2 -#define HDMI_VFRMT_720x480p60_16_9 3 -#define HDMI_VFRMT_1280x720p60_16_9 4 -#define HDMI_VFRMT_1920x1080i60_16_9 5 -#define HDMI_VFRMT_720x480i60_4_3 6 -#define HDMI_VFRMT_1440x480i60_4_3 HDMI_VFRMT_720x480i60_4_3 -#define HDMI_VFRMT_720x480i60_16_9 7 -#define HDMI_VFRMT_1440x480i60_16_9 HDMI_VFRMT_720x480i60_16_9 -#define HDMI_VFRMT_720x240p60_4_3 8 -#define HDMI_VFRMT_1440x240p60_4_3 HDMI_VFRMT_720x240p60_4_3 -#define HDMI_VFRMT_720x240p60_16_9 9 -#define HDMI_VFRMT_1440x240p60_16_9 HDMI_VFRMT_720x240p60_16_9 -#define HDMI_VFRMT_2880x480i60_4_3 10 -#define HDMI_VFRMT_2880x480i60_16_9 11 -#define HDMI_VFRMT_2880x240p60_4_3 12 -#define HDMI_VFRMT_2880x240p60_16_9 13 -#define HDMI_VFRMT_1440x480p60_4_3 14 -#define HDMI_VFRMT_1440x480p60_16_9 15 -#define HDMI_VFRMT_1920x1080p60_16_9 16 -#define HDMI_VFRMT_720x576p50_4_3 17 -#define HDMI_VFRMT_720x576p50_16_9 18 -#define HDMI_VFRMT_1280x720p50_16_9 19 -#define HDMI_VFRMT_1920x1080i50_16_9 20 -#define HDMI_VFRMT_720x576i50_4_3 21 -#define HDMI_VFRMT_1440x576i50_4_3 HDMI_VFRMT_720x576i50_4_3 -#define HDMI_VFRMT_720x576i50_16_9 22 -#define HDMI_VFRMT_1440x576i50_16_9 HDMI_VFRMT_720x576i50_16_9 -#define HDMI_VFRMT_720x288p50_4_3 23 -#define HDMI_VFRMT_1440x288p50_4_3 HDMI_VFRMT_720x288p50_4_3 -#define HDMI_VFRMT_720x288p50_16_9 24 -#define HDMI_VFRMT_1440x288p50_16_9 HDMI_VFRMT_720x288p50_16_9 -#define HDMI_VFRMT_2880x576i50_4_3 25 -#define HDMI_VFRMT_2880x576i50_16_9 26 -#define HDMI_VFRMT_2880x288p50_4_3 27 -#define HDMI_VFRMT_2880x288p50_16_9 28 -#define HDMI_VFRMT_1440x576p50_4_3 29 -#define HDMI_VFRMT_1440x576p50_16_9 30 -#define HDMI_VFRMT_1920x1080p50_16_9 31 -#define HDMI_VFRMT_1920x1080p24_16_9 32 -#define HDMI_VFRMT_1920x1080p25_16_9 33 -#define HDMI_VFRMT_1920x1080p30_16_9 34 -#define HDMI_VFRMT_2880x480p60_4_3 35 -#define HDMI_VFRMT_2880x480p60_16_9 36 -#define HDMI_VFRMT_2880x576p50_4_3 37 -#define HDMI_VFRMT_2880x576p50_16_9 38 -#define HDMI_VFRMT_1920x1250i50_16_9 39 -#define HDMI_VFRMT_1920x1080i100_16_9 40 -#define HDMI_VFRMT_1280x720p100_16_9 41 -#define HDMI_VFRMT_720x576p100_4_3 42 -#define HDMI_VFRMT_720x576p100_16_9 43 -#define HDMI_VFRMT_720x576i100_4_3 44 -#define HDMI_VFRMT_1440x576i100_4_3 HDMI_VFRMT_720x576i100_4_3 -#define HDMI_VFRMT_720x576i100_16_9 45 -#define HDMI_VFRMT_1440x576i100_16_9 HDMI_VFRMT_720x576i100_16_9 -#define HDMI_VFRMT_1920x1080i120_16_9 46 -#define HDMI_VFRMT_1280x720p120_16_9 47 -#define HDMI_VFRMT_720x480p120_4_3 48 -#define HDMI_VFRMT_720x480p120_16_9 49 -#define HDMI_VFRMT_720x480i120_4_3 50 -#define HDMI_VFRMT_1440x480i120_4_3 HDMI_VFRMT_720x480i120_4_3 -#define HDMI_VFRMT_720x480i120_16_9 51 -#define HDMI_VFRMT_1440x480i120_16_9 HDMI_VFRMT_720x480i120_16_9 -#define HDMI_VFRMT_720x576p200_4_3 52 -#define HDMI_VFRMT_720x576p200_16_9 53 -#define HDMI_VFRMT_720x576i200_4_3 54 -#define HDMI_VFRMT_1440x576i200_4_3 HDMI_VFRMT_720x576i200_4_3 -#define HDMI_VFRMT_720x576i200_16_9 55 -#define HDMI_VFRMT_1440x576i200_16_9 HDMI_VFRMT_720x576i200_16_9 -#define HDMI_VFRMT_720x480p240_4_3 56 -#define HDMI_VFRMT_720x480p240_16_9 57 -#define HDMI_VFRMT_720x480i240_4_3 58 -#define HDMI_VFRMT_1440x480i240_4_3 HDMI_VFRMT_720x480i240_4_3 -#define HDMI_VFRMT_720x480i240_16_9 59 -#define HDMI_VFRMT_1440x480i240_16_9 HDMI_VFRMT_720x480i240_16_9 -#define HDMI_VFRMT_1280x720p24_16_9 60 -#define HDMI_VFRMT_1280x720p25_16_9 61 -#define HDMI_VFRMT_1280x720p30_16_9 62 -#define HDMI_VFRMT_1920x1080p120_16_9 63 -#define HDMI_VFRMT_1920x1080p100_16_9 64 -#define HDMI_VFRMT_1280x720p24_64_27 65 -#define HDMI_VFRMT_1280x720p25_64_27 66 -#define HDMI_VFRMT_1280x720p30_64_27 67 -#define HDMI_VFRMT_1280x720p50_64_27 68 -#define HDMI_VFRMT_1280x720p60_64_27 69 -#define HDMI_VFRMT_1280x720p100_64_27 70 -#define HDMI_VFRMT_1280x720p120_64_27 71 -#define HDMI_VFRMT_1920x1080p24_64_27 72 -#define HDMI_VFRMT_1920x1080p25_64_27 73 -#define HDMI_VFRMT_1920x1080p30_64_27 74 -#define HDMI_VFRMT_1920x1080p50_64_27 75 -#define HDMI_VFRMT_1920x1080p60_64_27 76 -#define HDMI_VFRMT_1920x1080p100_64_27 77 -#define HDMI_VFRMT_1920x1080p120_64_27 78 -#define HDMI_VFRMT_1680x720p24_64_27 79 -#define HDMI_VFRMT_1680x720p25_64_27 80 -#define HDMI_VFRMT_1680x720p30_64_27 81 -#define HDMI_VFRMT_1680x720p50_64_27 82 -#define HDMI_VFRMT_1680x720p60_64_27 83 -#define HDMI_VFRMT_1680x720p100_64_27 84 -#define HDMI_VFRMT_1680x720p120_64_27 85 -#define HDMI_VFRMT_2560x1080p24_64_27 86 -#define HDMI_VFRMT_2560x1080p25_64_27 87 -#define HDMI_VFRMT_2560x1080p30_64_27 88 -#define HDMI_VFRMT_2560x1080p50_64_27 89 -#define HDMI_VFRMT_2560x1080p60_64_27 90 -#define HDMI_VFRMT_2560x1080p100_64_27 91 -#define HDMI_VFRMT_2560x1080p120_64_27 92 -#define HDMI_VFRMT_3840x2160p24_16_9 93 -#define HDMI_VFRMT_3840x2160p25_16_9 94 -#define HDMI_VFRMT_3840x2160p30_16_9 95 -#define HDMI_VFRMT_3840x2160p50_16_9 96 -#define HDMI_VFRMT_3840x2160p60_16_9 97 -#define HDMI_VFRMT_4096x2160p24_256_135 98 -#define HDMI_VFRMT_4096x2160p25_256_135 99 -#define HDMI_VFRMT_4096x2160p30_256_135 100 -#define HDMI_VFRMT_4096x2160p50_256_135 101 -#define HDMI_VFRMT_4096x2160p60_256_135 102 -#define HDMI_VFRMT_3840x2160p24_64_27 103 -#define HDMI_VFRMT_3840x2160p25_64_27 104 -#define HDMI_VFRMT_3840x2160p30_64_27 105 -#define HDMI_VFRMT_3840x2160p50_64_27 106 -#define HDMI_VFRMT_3840x2160p60_64_27 107 - -/* Video Identification Codes from 107-127 are reserved for the future */ -#define HDMI_VFRMT_END 127 - -#define EVFRMT_OFF(x) (HDMI_VFRMT_END + x) - -/* extended video formats */ -#define HDMI_EVFRMT_3840x2160p30_16_9 EVFRMT_OFF(1) -#define HDMI_EVFRMT_3840x2160p25_16_9 EVFRMT_OFF(2) -#define HDMI_EVFRMT_3840x2160p24_16_9 EVFRMT_OFF(3) -#define HDMI_EVFRMT_4096x2160p24_16_9 EVFRMT_OFF(4) -#define HDMI_EVFRMT_END HDMI_EVFRMT_4096x2160p24_16_9 - -#define WQXGA_OFF(x) (HDMI_EVFRMT_END + x) - -/* WQXGA */ -#define HDMI_VFRMT_2560x1600p60_16_9 WQXGA_OFF(1) -#define HDMI_WQXGAFRMT_END HDMI_VFRMT_2560x1600p60_16_9 - -#define WXGA_OFF(x) (HDMI_WQXGAFRMT_END + x) - -/* WXGA */ -#define HDMI_VFRMT_1280x800p60_16_10 WXGA_OFF(1) -#define HDMI_VFRMT_1366x768p60_16_10 WXGA_OFF(2) -#define HDMI_WXGAFRMT_END HDMI_VFRMT_1366x768p60_16_10 - -#define ETI_OFF(x) (HDMI_WXGAFRMT_END + x) - -/* ESTABLISHED TIMINGS I */ -#define HDMI_VFRMT_800x600p60_4_3 ETI_OFF(1) -#define ETI_VFRMT_END HDMI_VFRMT_800x600p60_4_3 - -#define ETII_OFF(x) (ETI_VFRMT_END + x) - -/* ESTABLISHED TIMINGS II */ -#define HDMI_VFRMT_1024x768p60_4_3 ETII_OFF(1) -#define HDMI_VFRMT_1280x1024p60_5_4 ETII_OFF(2) -#define ETII_VFRMT_END HDMI_VFRMT_1280x1024p60_5_4 - -#define ETIII_OFF(x) (ETII_VFRMT_END + x) - -/* ESTABLISHED TIMINGS III */ -#define HDMI_VFRMT_848x480p60_16_9 ETIII_OFF(1) -#define HDMI_VFRMT_1280x960p60_4_3 ETIII_OFF(2) -#define HDMI_VFRMT_1360x768p60_16_9 ETIII_OFF(3) -#define HDMI_VFRMT_1440x900p60_16_10 ETIII_OFF(4) -#define HDMI_VFRMT_1400x1050p60_4_3 ETIII_OFF(5) -#define HDMI_VFRMT_1680x1050p60_16_10 ETIII_OFF(6) -#define HDMI_VFRMT_1600x1200p60_4_3 ETIII_OFF(7) -#define HDMI_VFRMT_1920x1200p60_16_10 ETIII_OFF(8) -#define ETIII_VFRMT_END HDMI_VFRMT_1920x1200p60_16_10 - -#define RESERVE_OFF(x) (ETIII_VFRMT_END + x) - -#define HDMI_VFRMT_RESERVE1 RESERVE_OFF(1) -#define HDMI_VFRMT_RESERVE2 RESERVE_OFF(2) -#define HDMI_VFRMT_RESERVE3 RESERVE_OFF(3) -#define HDMI_VFRMT_RESERVE4 RESERVE_OFF(4) -#define HDMI_VFRMT_RESERVE5 RESERVE_OFF(5) -#define HDMI_VFRMT_RESERVE6 RESERVE_OFF(6) -#define HDMI_VFRMT_RESERVE7 RESERVE_OFF(7) -#define HDMI_VFRMT_RESERVE8 RESERVE_OFF(8) -#define RESERVE_VFRMT_END HDMI_VFRMT_RESERVE8 - -#define HDMI_VFRMT_MAX (RESERVE_VFRMT_END + 1) - -/* Timing information for supported modes */ -#define VFRMT_NOT_SUPPORTED(VFRMT) \ - {VFRMT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, false, \ - HDMI_RES_AR_INVALID} - -#define HDMI_VFRMT_640x480p60_4_3_TIMING \ - {HDMI_VFRMT_640x480p60_4_3, 640, 16, 96, 48, true, \ - 480, 10, 2, 33, true, 25200, 60000, false, true, HDMI_RES_AR_4_3, 0} -#define HDMI_VFRMT_720x480p60_4_3_TIMING \ - {HDMI_VFRMT_720x480p60_4_3, 720, 16, 62, 60, true, \ - 480, 9, 6, 30, true, 27027, 60000, false, true, HDMI_RES_AR_4_3, 0} -#define HDMI_VFRMT_720x480p60_16_9_TIMING \ - {HDMI_VFRMT_720x480p60_16_9, 720, 16, 62, 60, true, \ - 480, 9, 6, 30, true, 27027, 60000, false, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_1280x720p60_16_9_TIMING \ - {HDMI_VFRMT_1280x720p60_16_9, 1280, 110, 40, 220, false, \ - 720, 5, 5, 20, false, 74250, 60000, false, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_1920x1080i60_16_9_TIMING \ - {HDMI_VFRMT_1920x1080i60_16_9, 1920, 88, 44, 148, false, \ - 540, 2, 5, 5, false, 74250, 60000, false, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_1440x480i60_4_3_TIMING \ - {HDMI_VFRMT_1440x480i60_4_3, 1440, 38, 124, 114, true, \ - 240, 4, 3, 15, true, 27000, 60000, true, true, HDMI_RES_AR_4_3, 0} -#define HDMI_VFRMT_1440x480i60_16_9_TIMING \ - {HDMI_VFRMT_1440x480i60_16_9, 1440, 38, 124, 114, true, \ - 240, 4, 3, 15, true, 27000, 60000, true, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_1920x1080p60_16_9_TIMING \ - {HDMI_VFRMT_1920x1080p60_16_9, 1920, 88, 44, 148, false, \ - 1080, 4, 5, 36, false, 148500, 60000, false, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_720x576p50_4_3_TIMING \ - {HDMI_VFRMT_720x576p50_4_3, 720, 12, 64, 68, true, \ - 576, 5, 5, 39, true, 27000, 50000, false, true, HDMI_RES_AR_4_3, 0} -#define HDMI_VFRMT_720x576p50_16_9_TIMING \ - {HDMI_VFRMT_720x576p50_16_9, 720, 12, 64, 68, true, \ - 576, 5, 5, 39, true, 27000, 50000, false, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_1280x720p50_16_9_TIMING \ - {HDMI_VFRMT_1280x720p50_16_9, 1280, 440, 40, 220, false, \ - 720, 5, 5, 20, false, 74250, 50000, false, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_1440x576i50_4_3_TIMING \ - {HDMI_VFRMT_1440x576i50_4_3, 1440, 24, 126, 138, true, \ - 288, 2, 3, 19, true, 27000, 50000, true, true, HDMI_RES_AR_4_3, 0} -#define HDMI_VFRMT_1440x576i50_16_9_TIMING \ - {HDMI_VFRMT_1440x576i50_16_9, 1440, 24, 126, 138, true, \ - 288, 2, 3, 19, true, 27000, 50000, true, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_1920x1080p50_16_9_TIMING \ - {HDMI_VFRMT_1920x1080p50_16_9, 1920, 528, 44, 148, false, \ - 1080, 4, 5, 36, false, 148500, 50000, false, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_1920x1080p24_16_9_TIMING \ - {HDMI_VFRMT_1920x1080p24_16_9, 1920, 638, 44, 148, false, \ - 1080, 4, 5, 36, false, 74250, 24000, false, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_1920x1080p25_16_9_TIMING \ - {HDMI_VFRMT_1920x1080p25_16_9, 1920, 528, 44, 148, false, \ - 1080, 4, 5, 36, false, 74250, 25000, false, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_1920x1080p30_16_9_TIMING \ - {HDMI_VFRMT_1920x1080p30_16_9, 1920, 88, 44, 148, false, \ - 1080, 4, 5, 36, false, 74250, 30000, false, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_1024x768p60_4_3_TIMING \ - {HDMI_VFRMT_1024x768p60_4_3, 1024, 24, 136, 160, false, \ - 768, 2, 6, 29, false, 65000, 60000, false, true, HDMI_RES_AR_4_3, 0} -#define HDMI_VFRMT_1280x1024p60_5_4_TIMING \ - {HDMI_VFRMT_1280x1024p60_5_4, 1280, 48, 112, 248, false, \ - 1024, 1, 3, 38, false, 108000, 60000, false, true, HDMI_RES_AR_5_4, 0} -#define HDMI_VFRMT_2560x1600p60_16_9_TIMING \ - {HDMI_VFRMT_2560x1600p60_16_9, 2560, 48, 32, 80, false, \ - 1600, 3, 6, 37, false, 268500, 60000, false, true, HDMI_RES_AR_16_9, 0} -#define HDMI_EVFRMT_3840x2160p30_16_9_TIMING \ - {HDMI_EVFRMT_3840x2160p30_16_9, 3840, 176, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 30000, false, true, \ - HDMI_RES_AR_16_9, 0} -#define HDMI_EVFRMT_3840x2160p25_16_9_TIMING \ - {HDMI_EVFRMT_3840x2160p25_16_9, 3840, 1056, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 25000, false, true, \ - HDMI_RES_AR_16_9, 0} -#define HDMI_EVFRMT_3840x2160p24_16_9_TIMING \ - {HDMI_EVFRMT_3840x2160p24_16_9, 3840, 1276, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 24000, false, true, \ - HDMI_RES_AR_16_9, 0} -#define HDMI_EVFRMT_4096x2160p24_16_9_TIMING \ - {HDMI_EVFRMT_4096x2160p24_16_9, 4096, 1020, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 24000, false, true, \ - HDMI_RES_AR_16_9, 0} - -#define HDMI_VFRMT_800x600p60_4_3_TIMING \ - {HDMI_VFRMT_800x600p60_4_3, 800, 40, 128, 88, false, \ - 600, 1, 4, 23, false, 40000, 60000, false, true, HDMI_RES_AR_4_3, 0} -#define HDMI_VFRMT_848x480p60_16_9_TIMING \ - {HDMI_VFRMT_848x480p60_16_9, 848, 16, 112, 112, false, \ - 480, 6, 8, 23, false, 33750, 60000, false, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_1280x960p60_4_3_TIMING\ - {HDMI_VFRMT_1280x960p60_4_3, 1280, 96, 112, 312, false, \ - 960, 1, 3, 36, false, 108000, 60000, false, true, HDMI_RES_AR_4_3, 0} -#define HDMI_VFRMT_1360x768p60_16_9_TIMING\ - {HDMI_VFRMT_1360x768p60_16_9, 1360, 64, 112, 256, false, \ - 768, 3, 6, 18, false, 85500, 60000, false, true, HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_1440x900p60_16_10_TIMING\ - {HDMI_VFRMT_1440x900p60_16_10, 1440, 48, 32, 80, false, \ - 900, 3, 6, 17, true, 88750, 60000, false, true, HDMI_RES_AR_16_10, 0} -#define HDMI_VFRMT_1400x1050p60_4_3_TIMING\ - {HDMI_VFRMT_1400x1050p60_4_3, 1400, 48, 32, 80, false, \ - 1050, 3, 4, 23, true, 101000, 60000, false, true, HDMI_RES_AR_4_3, 0} -#define HDMI_VFRMT_1680x1050p60_16_10_TIMING\ - {HDMI_VFRMT_1680x1050p60_16_10, 1680, 48, 32, 80, false, \ - 1050, 3, 6, 21, true, 119000, 60000, false, true, HDMI_RES_AR_16_10, 0} -#define HDMI_VFRMT_1600x1200p60_4_3_TIMING\ - {HDMI_VFRMT_1600x1200p60_4_3, 1600, 64, 192, 304, false, \ - 1200, 1, 3, 46, false, 162000, 60000, false, true, HDMI_RES_AR_4_3, 0} -#define HDMI_VFRMT_1920x1200p60_16_10_TIMING\ - {HDMI_VFRMT_1920x1200p60_16_10, 1920, 48, 32, 80, false,\ - 1200, 3, 6, 26, true, 154000, 60000, false, true, HDMI_RES_AR_16_10, 0} -#define HDMI_VFRMT_1366x768p60_16_10_TIMING\ - {HDMI_VFRMT_1366x768p60_16_10, 1366, 70, 143, 213, false,\ - 768, 3, 3, 24, false, 85500, 60000, false, true, HDMI_RES_AR_16_10, 0} -#define HDMI_VFRMT_1280x800p60_16_10_TIMING\ - {HDMI_VFRMT_1280x800p60_16_10, 1280, 72, 128, 200, true,\ - 800, 3, 6, 22, false, 83500, 60000, false, true, HDMI_RES_AR_16_10, 0} -#define HDMI_VFRMT_3840x2160p24_16_9_TIMING \ - {HDMI_VFRMT_3840x2160p24_16_9, 3840, 1276, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 24000, false, true, \ - HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_3840x2160p25_16_9_TIMING \ - {HDMI_VFRMT_3840x2160p25_16_9, 3840, 1056, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 25000, false, true, \ - HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_3840x2160p30_16_9_TIMING \ - {HDMI_VFRMT_3840x2160p30_16_9, 3840, 176, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 30000, false, true, \ - HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_3840x2160p50_16_9_TIMING \ - {HDMI_VFRMT_3840x2160p50_16_9, 3840, 1056, 88, 296, false, \ - 2160, 8, 10, 72, false, 594000, 50000, false, true, \ - HDMI_RES_AR_16_9, 0} -#define HDMI_VFRMT_3840x2160p60_16_9_TIMING \ - {HDMI_VFRMT_3840x2160p60_16_9, 3840, 176, 88, 296, false, \ - 2160, 8, 10, 72, false, 594000, 60000, false, true, \ - HDMI_RES_AR_16_9, 0} - -#define HDMI_VFRMT_4096x2160p24_256_135_TIMING \ - {HDMI_VFRMT_4096x2160p24_256_135, 4096, 1020, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 24000, false, true, \ - HDMI_RES_AR_256_135, 0} -#define HDMI_VFRMT_4096x2160p25_256_135_TIMING \ - {HDMI_VFRMT_4096x2160p25_256_135, 4096, 968, 88, 128, false, \ - 2160, 8, 10, 72, false, 297000, 25000, false, true, \ - HDMI_RES_AR_256_135, 0} -#define HDMI_VFRMT_4096x2160p30_256_135_TIMING \ - {HDMI_VFRMT_4096x2160p30_256_135, 4096, 88, 88, 128, false, \ - 2160, 8, 10, 72, false, 297000, 30000, false, true, \ - HDMI_RES_AR_256_135, 0} -#define HDMI_VFRMT_4096x2160p50_256_135_TIMING \ - {HDMI_VFRMT_4096x2160p50_256_135, 4096, 968, 88, 128, false, \ - 2160, 8, 10, 72, false, 594000, 50000, false, true, \ - HDMI_RES_AR_256_135, 0} -#define HDMI_VFRMT_4096x2160p60_256_135_TIMING \ - {HDMI_VFRMT_4096x2160p60_256_135, 4096, 88, 88, 128, false, \ - 2160, 8, 10, 72, false, 594000, 60000, false, true, \ - HDMI_RES_AR_256_135, 0} - -#define HDMI_VFRMT_3840x2160p24_64_27_TIMING \ - {HDMI_VFRMT_3840x2160p24_64_27, 3840, 1276, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 24000, false, true, \ - HDMI_RES_AR_64_27, 0} -#define HDMI_VFRMT_3840x2160p25_64_27_TIMING \ - {HDMI_VFRMT_3840x2160p25_64_27, 3840, 1056, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 25000, false, true, \ - HDMI_RES_AR_64_27, 0} -#define HDMI_VFRMT_3840x2160p30_64_27_TIMING \ - {HDMI_VFRMT_3840x2160p30_64_27, 3840, 176, 88, 296, false, \ - 2160, 8, 10, 72, false, 297000, 30000, false, true, \ - HDMI_RES_AR_64_27, 0} -#define HDMI_VFRMT_3840x2160p50_64_27_TIMING \ - {HDMI_VFRMT_3840x2160p50_64_27, 3840, 1056, 88, 296, false, \ - 2160, 8, 10, 72, false, 594000, 50000, false, true, \ - HDMI_RES_AR_64_27, 0} -#define HDMI_VFRMT_3840x2160p60_64_27_TIMING \ - {HDMI_VFRMT_3840x2160p60_64_27, 3840, 176, 88, 296, false, \ - 2160, 8, 10, 72, false, 594000, 60000, false, true, \ - HDMI_RES_AR_64_27, 0} - -#define MSM_HDMI_MODES_SET_TIMING(LUT, MODE) do { \ - struct msm_hdmi_mode_timing_info mode = MODE##_TIMING; \ - LUT[MODE] = mode;\ - } while (0) - -#define MSM_HDMI_MODES_INIT_TIMINGS(__lut) \ -do { \ - unsigned int i; \ - for (i = 0; i < HDMI_VFRMT_MAX; i++) { \ - struct msm_hdmi_mode_timing_info mode = \ - VFRMT_NOT_SUPPORTED(i); \ - (__lut)[i] = mode; \ - } \ -} while (0) - -#define MSM_HDMI_MODES_SET_SUPP_TIMINGS(__lut, __type) \ -do { \ - if (__type & MSM_HDMI_MODES_CEA) { \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_640x480p60_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_720x480p60_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_720x480p60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1280x720p60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1920x1080i60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1440x480i60_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1440x480i60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1920x1080p60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_720x576p50_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_720x576p50_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1280x720p50_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1440x576i50_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1440x576i50_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1920x1080p50_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1920x1080p24_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1920x1080p25_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1920x1080p30_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_3840x2160p24_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_3840x2160p25_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_3840x2160p30_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_3840x2160p50_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_3840x2160p60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_4096x2160p24_256_135);\ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_4096x2160p25_256_135);\ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_4096x2160p30_256_135);\ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_4096x2160p50_256_135);\ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_4096x2160p60_256_135);\ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_3840x2160p24_64_27); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_3840x2160p25_64_27); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_3840x2160p30_64_27); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_3840x2160p50_64_27); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_3840x2160p60_64_27); \ - } \ - if (__type & MSM_HDMI_MODES_XTND) { \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_EVFRMT_3840x2160p30_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_EVFRMT_3840x2160p25_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_EVFRMT_3840x2160p24_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_EVFRMT_4096x2160p24_16_9); \ - } \ - if (__type & MSM_HDMI_MODES_DVI) { \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1024x768p60_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1280x1024p60_5_4); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_2560x1600p60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_800x600p60_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_848x480p60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1280x960p60_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1360x768p60_16_9); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1440x900p60_16_10); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1400x1050p60_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1680x1050p60_16_10); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1600x1200p60_4_3); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1920x1200p60_16_10); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1366x768p60_16_10); \ - MSM_HDMI_MODES_SET_TIMING(__lut, \ - HDMI_VFRMT_1280x800p60_16_10); \ - } \ -} while (0) - -#define MSM_HDMI_MODES_GET_DETAILS(mode, MODE) do { \ - struct msm_hdmi_mode_timing_info info = MODE##_TIMING; \ - *mode = info; \ - } while (0) - -#endif /* _MSM_HDMI_MODES_H__ */ |