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authorGeorge Chang <georgekgchang@google.com>2018-11-20 14:19:37 +0000
committerGeorge Chang <georgekgchang@google.com>2018-11-20 14:19:37 +0000
commit30321fb50f5f371affbd5d8c2dfe1b327615c59f (patch)
tree19fe2f3ac725cc202be88ab10738e8da054b3990 /nfc
parenta5b9d5ed90a06862b3b3ac4182435cbb36b6c1fd (diff)
Update bonito NFC RF Configure
Bug: 117743441 Test: Nfc On/Off, Tag Read/Write, P2P, HCE Change-Id: I0ff579a7d7e48516d24c9c08f6c9b3bb2d024eb6
Diffstat (limited to 'nfc')
-rw-r--r--nfc/libnfc-nxp.bonito.conf17
-rw-r--r--nfc/libnfc-nxp.sargo.conf17
2 files changed, 26 insertions, 8 deletions
diff --git a/nfc/libnfc-nxp.bonito.conf b/nfc/libnfc-nxp.bonito.conf
index c11e4c30..876b7001 100644
--- a/nfc/libnfc-nxp.bonito.conf
+++ b/nfc/libnfc-nxp.bonito.conf
@@ -72,7 +72,7 @@ NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01,
###############################################################################
#config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
#monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
-NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, BA, 1E, 15, 00, D0, 0C}
+NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, BA, 1E, 10, 00, D0, 0C}
###############################################################################
# NXP RF configuration ALM/PLM settings
@@ -123,14 +123,23 @@ DC, 05, 00
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
NXP_RF_CONF_BLK_5={
-20, 02, 0C, 01, A0, 18, 08, AC, 00, 28, 01, B2, FE, 9C, 00
+20, 02, A4, 01, A0, A9, A0, 00, C1, 00, 0A, 01, 80, 41, 0A, 02, 81, 83, 0A,
+03, C0, 42, 06, 04, 80, 46, 06, 05, C3, 01, 03, 06, C2, 05, 03, 07, C2, 4A,
+03, 07, 81, 01, 01, 08, C3, 8B, 03, 08, C3, 05, 01, 09, C3, 92, 03, 09, C6,
+84, 01, 0A, C4, CC, 03, 0A, C6, 89, 01, 0B, C5, D4, 03, 0B, C7, 92, 01, 0C,
+44, 00, 03, 0C, C7, C6, 01, 0D, 42, 04, 03, 0D, C9, CE, 01, 0E, 42, 48, 03,
+0E, 03, 00, 01, 0F, 43, 50, 03, 0F, 43, 04, 01, 10, 43, 91, 03, 10, 45, 0A,
+01, 11, 44, 95, 03, 11, 46, 11, 01, 12, 46, 8E, 01, 13, 47, C5, 01, 14, 48,
+CC, 01, 15, 4B, D4, 01, 16, 4E, D7, 01, 17, 45, A2, 01, 18, 46, A6, 01, 19,
+46, AE, 01, 1A, 47, B4, 01, 1B, 48, EA, 01, 1C, 49, F0, 01
}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
-#NXP_RF_CONF_BLK_6={
-#}
+NXP_RF_CONF_BLK_6={
+20, 02, 0C, 01, A0, 18, 08, AC, 00, 28, 01, B2, FE, 9C, 00
+}
###############################################################################
# Core configuration extensions
diff --git a/nfc/libnfc-nxp.sargo.conf b/nfc/libnfc-nxp.sargo.conf
index a25794ec..60d15aba 100644
--- a/nfc/libnfc-nxp.sargo.conf
+++ b/nfc/libnfc-nxp.sargo.conf
@@ -67,7 +67,7 @@ NXP_EXT_TVDD_CFG=0x02
###############################################################################
#config1:SLALM, 3.3V for both RM and CM
-NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, BA, 1E, 15, 00, D0, 0C}
+NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, BA, 1E, 10, 00, D0, 0C}
###############################################################################
#config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
@@ -123,14 +123,23 @@ DC, 05, 00
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
NXP_RF_CONF_BLK_5={
-20, 02, 0C, 01, A0, 18, 08, 8F, 00, 83, 01, 5D, FE, BC, 00
+20, 02, A4, 01, A0, A9, A0, 00, C1, 00, 0A, 01, 80, 41, 0A, 02, 81, 83, 0A,
+03, C0, 42, 06, 04, 80, 46, 06, 05, C3, 01, 03, 06, C2, 05, 03, 07, C2, 4A,
+03, 07, 81, 01, 01, 08, C3, 8B, 03, 08, C3, 05, 01, 09, C3, 92, 03, 09, C6,
+84, 01, 0A, C4, CC, 03, 0A, C6, 89, 01, 0B, C5, D4, 03, 0B, C7, 92, 01, 0C,
+44, 00, 03, 0C, C7, C6, 01, 0D, 42, 04, 03, 0D, C9, CE, 01, 0E, 42, 48, 03,
+0E, 03, 00, 01, 0F, 43, 50, 03, 0F, 43, 04, 01, 10, 43, 91, 03, 10, 45, 0A,
+01, 11, 44, 95, 03, 11, 46, 11, 01, 12, 46, 8E, 01, 13, 47, C5, 01, 14, 48,
+CC, 01, 15, 4B, D4, 01, 16, 4E, D7, 01, 17, 45, A2, 01, 18, 46, A6, 01, 19,
+46, AE, 01, 1A, 47, B4, 01, 1B, 48, EA, 01, 1C, 49, F0, 01
}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
-#NXP_RF_CONF_BLK_6={
-#}
+NXP_RF_CONF_BLK_6={
+20, 02, 0C, 01, A0, 18, 08, 8F, 00, 83, 01, 5D, FE, BC, 00
+}
###############################################################################
# Core configuration extensions