Update RF Related configuration.

Test: boots, HCE, Tag reading
Bug: 69876039
Bug: 78678732
Change-Id: I987c13ae9455d0242b18e4a14a439f93d98f23bd

2 files changed, 365 insertions, 17 deletions

diff --git a/nfc/libnfc-nxp.conf b/nfc/libnfc-nxp.blueline.conf
index 4a70b81..19cd15f 100644
--- a/nfc/libnfc-nxp.conf
+++ b/nfc/libnfc-nxp.blueline.conf
@@ -28,7 +28,7 @@ MIFARE_READER_ENABLE=0x01
 # Firmware file type
 #.so file   0x01
 #.bin file  0x02
-NXP_FW_TYPE=0x01
+NXP_FW_TYPE=0x02
 
 ###############################################################################
 # System clock source selection configuration
@@ -72,37 +72,65 @@ NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01,
 ###############################################################################
 #config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
 #monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
-NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, B2, 00, B2, 1E, 1F, 00, D0, 0C}
+NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, B2, 1E, 14, 00, D0, 0C}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
-#NXP_RF_CONF_BLK_1={
-#}
+NXP_RF_CONF_BLK_1={
+20, 02, 19, 03,
+A0, 0D, 03, 24, 03, 7F,
+A0, 0D, 06, 08, 37, 08, 76, 00, 00,
+A0, 0D, 06, 08, 42, 00, 02, F8, F8
+}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
-#NXP_RF_CONF_BLK_2={
-#}
+NXP_RF_CONF_BLK_2={
+20, 02, 10, 01, A0, AF, 0C, 83, E3, DF, 80, 00, 83, C1, DF, 80, 00, 77, 08
+}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
-#NXP_RF_CONF_BLK_3={
-#}
+NXP_RF_CONF_BLK_3={
+20, 02, 98, 01, A0, 34, 94, 23, 04, 18, 35, 00, 00, 4B, 00, 00, 71, 00, 00,
+71, 00, 00, 96, 00, 00, BC, 00, 00, BC, 00, 00, E1, 00, 00, 07, 01, 00, 07,
+01, 00, 2C, 01, 00, 2C, 01, 00, 52, 01, 00, 52, 01, 00, 77, 01, 00, 77, 01,
+00, C2, 01, 00, C2, 01, 00, 0D, 02, 00, 0D, 02, 00, 58, 02, 00, 58, 02, 00,
+EE, 02, 00, EE, 02, 00, 18, 35, 00, 00, 4B, 00, 00, 71, 00, 00, 96, 00, 00,
+96, 00, 00, 96, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00, E1,
+00, 00, E1, 00, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01,
+00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00,
+DC, 05, 00
+}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
-#NXP_RF_CONF_BLK_4={
-#}
+NXP_RF_CONF_BLK_4={
+20, 02, A4, 01, A0, A9, A0, 00, C1, 00, 0A, 01, 80, 41, 0A, 02, 81, 83, 0A,
+03, C0, 42, 06, 04, 80, 46, 06, 05, C3, 01, 03, 06, C2, 05, 03, 07, C2, 4A,
+03, 07, 81, 01, 01, 08, C3, 8B, 03, 08, C3, 05, 01, 09, C3, 92, 03, 09, C6,
+84, 01, 0A, C4, CC, 03, 0A, C6, 89, 01, 0B, C5, D4, 03, 0B, C7, 92, 01, 0C,
+44, 00, 03, 0C, C7, C6, 01, 0D, 42, 04, 03, 0D, C9, CE, 01, 0E, 42, 48, 03,
+0E, 03, 00, 01, 0F, 43, 50, 03, 0F, 43, 04, 01, 10, 43, 91, 03, 10, 45, 0A,
+01, 11, 44, 95, 03, 11, 46, 11, 01, 12, 46, 8E, 01, 13, 47, C5, 01, 14, 48,
+CC, 01, 15, 4B, D4, 01, 16, 4E, D7, 01, 17, 5E, A2, 01, 18, 5F, A6, 01, 19,
+5F, AE, 01, 1A, 60, B4, 01, 1B, 61, EA, 01, 1C, 62, F0, 01
+}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
-#NXP_RF_CONF_BLK_5={
-#}
+NXP_RF_CONF_BLK_5={
+20, 02, 5B, 01, A0, 0B, 57, ED, 0D, 90, 3F, 0F, 4E, 00, 53, 95, 00, 00, 53,
+9F, 00, 00, 6B, 9F, 00, 00, 78, 9F, 00, 00, 7A, 9F, 00, 00, 86, 9F, 00, 00,
+89, 9F, 00, 00, 95, 9F, 00, 00, 9A, 9F, 00, 00, A4, 9F, 00, 00, A6, 9F, 00,
+00, B3, 9F, 00, 00, B5, 9F, 00, 00, C1, 9F, 00, 00, C4, 1F, 00, 00, D0, 1F,
+00, 00, DA, 1F, 00, 00, E1, 1F, 00, 00, EE, 1F, 00, 00, FA, 1F, 00, 00
+}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
@@ -127,7 +155,7 @@ NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, B2, 00, B2, 1E, 1F,
 # SWP1A interface A0D4
 # DWP intf behavior config, SVDD Load activated by default if set to 0x31 A037
 # SPI CL Sync enable  A098
-NXP_CORE_CONF_EXTN={20, 02, 2D, 0B,
+NXP_CORE_CONF_EXTN={20, 02, 46, 0E,
     A0, EC, 01, 01,
     A0, ED, 01, 01,
     A0, 5E, 01, 01,
@@ -138,7 +166,10 @@ NXP_CORE_CONF_EXTN={20, 02, 2D, 0B,
     A0, 37, 01, 35,
     A0, D8, 01, 02,
     A0, D5, 01, 0A,
-    A0, 98, 01, 01
+    A0, 98, 01, 01,
+    A0, AA, 04, FD, 03, 2C, 01,
+    A0, 38, 04, 14, 0B, 0B, 00,
+    A0, 3A, 08, B4, 00, B4, 00, B4, 00, B4, 00
 }
 
 ###############################################################################
@@ -215,7 +246,7 @@ RF_STATUS_UPDATE_ENABLE=0x01
 # SE that is detected by the stack.  This value might be used when the phone
 # supports multiple SE (e.g. 0xF3 and 0xF4) but you want to force it to use
 # one of them (e.g. 0xF4).
-DEFAULT_OFFHOST_ROUTE=0xC0
+DEFAULT_OFFHOST_ROUTE=0x80
 
 ###############################################################################
 # Configure the single default SE to use.  The default is to use the first
@@ -227,7 +258,7 @@ DEFAULT_NFCF_ROUTE=0xC0
 ###############################################################################
 # Configure the default NfcA/IsoDep techology and protocol route. Can be
 # either a secure element (e.g. 0xF4) or the host (0x00)
-DEFAULT_ROUTE=0xC0
+DEFAULT_ROUTE=0x00
 
 ###############################################################################
 # Vendor Specific Proprietary Protocol & Discovery Configuration
@@ -251,7 +282,7 @@ NFA_POLL_BAIL_OUT_MODE=0x01
 ###############################################################################
 # White list of Hosts
 # This values will be the Hosts(NFCEEs) in the HCI Network.
-DEVICE_HOST_WHITE_LIST={ C0, 02}
+DEVICE_HOST_WHITE_LIST={C0, 80}
 
 ###############################################################################
 # Extended APDU length for ISO_DEP
diff --git a/nfc/libnfc-nxp.crosshatch.conf b/nfc/libnfc-nxp.crosshatch.conf
new file mode 100644
index 0000000..10ec45a
--- /dev/null
+++ b/nfc/libnfc-nxp.crosshatch.conf
@@ -0,0 +1,317 @@
+## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn547)
+## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn547)
+###############################################################################
+# Application options
+# Logging Levels
+# NXPLOG_DEFAULT_LOGLEVEL    0x01
+# ANDROID_LOG_DEBUG          0x03
+# ANDROID_LOG_WARN           0x02
+# ANDROID_LOG_ERROR          0x01
+# ANDROID_LOG_SILENT         0x00
+NXPLOG_EXTNS_LOGLEVEL=0x01
+NXPLOG_NCIHAL_LOGLEVEL=0x01
+NXPLOG_NCIX_LOGLEVEL=0x01
+NXPLOG_NCIR_LOGLEVEL=0x01
+NXPLOG_FWDNLD_LOGLEVEL=0x01
+NXPLOG_TML_LOGLEVEL=0x01
+NFC_DEBUG_ENABLED=0x00
+
+###############################################################################
+# Nfc Device Node name
+NXP_NFC_DEV_NODE="/dev/nq-nci"
+
+###############################################################################
+# Extension for Mifare reader enable
+MIFARE_READER_ENABLE=0x01
+
+###############################################################################
+# Firmware file type
+#.so file   0x01
+#.bin file  0x02
+NXP_FW_TYPE=0x02
+
+###############################################################################
+# System clock source selection configuration
+#define CLK_SRC_XTAL       1
+#define CLK_SRC_PLL        2
+NXP_SYS_CLK_SRC_SEL=0x01
+
+###############################################################################
+# System clock frequency selection configuration
+#define CLK_FREQ_13MHZ         1
+#define CLK_FREQ_19_2MHZ       2
+#define CLK_FREQ_24MHZ         3
+#define CLK_FREQ_26MHZ         4
+#define CLK_FREQ_38_4MHZ       5
+#define CLK_FREQ_52MHZ         6
+NXP_SYS_CLK_FREQ_SEL=0x00
+
+###############################################################################
+# The timeout value to be used for clock request acknowledgment
+# min value = 0x01 to max = 0x06
+NXP_SYS_CLOCK_TO_CFG=0x01
+
+###############################################################################
+# NXP proprietary settings
+NXP_ACT_PROP_EXTN={2F, 02, 00}
+
+###############################################################################
+# NFC forum profile settings
+NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00}
+
+###############################################################################
+# NXP TVDD configurations settings
+# Allow NFCC to configure External TVDD, two configurations (1 and 2) supported,
+# out of them only one can be configured at a time.
+NXP_EXT_TVDD_CFG=0x02
+
+###############################################################################
+#config1:SLALM, 3.3V for both RM and CM
+NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01, 00, D0, 0C}
+
+###############################################################################
+#config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
+#monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
+NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, B2, 1E, 14, 00, D0, 0C}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+NXP_RF_CONF_BLK_1={
+20, 02, 19, 03,
+A0, 0D, 03, 24, 03, 80,
+A0, 0D, 06, 08, 37, 08, 76, 00, 00,
+A0, 0D, 06, 08, 42, 00, 02, F8, F8
+}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+NXP_RF_CONF_BLK_2={
+20, 02, 10, 01, A0, AF, 0C, 83, E3, B9, 80, 00, 83, C2, B9, 80, 00, 77, 08
+}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+NXP_RF_CONF_BLK_3={
+20, 02, 98, 01, A0, 34, 94, 23, 04, 18, 35, 00, 00, 4B, 00, 00, 71, 00, 00,
+71, 00, 00, 96, 00, 00, BC, 00, 00, BC, 00, 00, E1, 00, 00, 07, 01, 00, 07,
+01, 00, 2C, 01, 00, 2C, 01, 00, 52, 01, 00, 52, 01, 00, 77, 01, 00, 77, 01,
+00, C2, 01, 00, C2, 01, 00, 0D, 02, 00, 0D, 02, 00, 58, 02, 00, 58, 02, 00,
+EE, 02, 00, EE, 02, 00, 18, 35, 00, 00, 4B, 00, 00, 71, 00, 00, 96, 00, 00,
+96, 00, 00, 96, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00, E1,
+00, 00, E1, 00, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01,
+00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00,
+DC, 05, 00
+}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+NXP_RF_CONF_BLK_4={
+20, 02, A4, 01, A0, A9, A0, 00, C1, 00, 0A, 01, 80, 41, 0A, 02, 81, 83, 0A,
+03, C0, 42, 06, 04, 80, 46, 06, 05, C3, 01, 03, 06, C2, 05, 03, 07, C2, 4A,
+03, 07, 81, 01, 01, 08, C3, 8B, 03, 08, C3, 05, 01, 09, C3, 92, 03, 09, C6,
+84, 01, 0A, C4, CC, 03, 0A, C6, 89, 01, 0B, C5, D4, 03, 0B, C7, 92, 01, 0C,
+44, 00, 03, 0C, C7, C6, 01, 0D, 42, 04, 03, 0D, C9, CE, 01, 0E, 42, 48, 03,
+0E, 03, 00, 01, 0F, 43, 50, 03, 0F, 43, 04, 01, 10, 43, 91, 03, 10, 45, 0A,
+01, 11, 44, 95, 03, 11, 46, 11, 01, 12, 46, 8E, 01, 13, 47, C5, 01, 14, 48,
+CC, 01, 15, 4B, D4, 01, 16, 4E, D7, 01, 17, 5E, A2, 01, 18, 5F, A6, 01, 19,
+5F, AE, 01, 1A, 60, B4, 01, 1B, 61, EA, 01, 1C, 62, F0, 01
+}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+NXP_RF_CONF_BLK_5={
+20, 02, 5B, 01, A0, 0B, 57, ED, 0D, 90, 7F, 0F, 4E, 00, 3B, 95, 00, 00, 3B,
+9F, 00, 00, 4D, 9F, 00, 00, 56, 9F, 00, 00, 58, 9F, 00, 00, 60, 9F, 00, 00,
+62, 9F, 00, 00, 6B, 9F, 00, 00, 6F, 9F, 00, 00, 76, 9F, 00, 00, 77, 9F, 00,
+00, 80, 9F, 00, 00, 82, 9F, 00, 00, 8B, 9F, 00, 00, 8C, 1F, 00, 00, 95, 1F,
+00, 00, 9C, 1F, 00, 00, A2, 1F, 00, 00, AA, 1F, 00, 00, B3, 1F, 00, 00
+}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_6={
+#}
+
+###############################################################################
+# Core configuration extensions
+# It includes
+# Wired mode settings A0ED, A0EE
+# Tag Detector A040, A041, A043
+# Low Power mode A007
+# Clock settings A002, A003
+# PbF settings A008
+# Clock timeout settings A004
+# eSE (SVDD) PWR REQ settings A0F2
+# Window size A0D8
+# DWP Speed   A0D5
+# How eSE connected to PN553 A012
+# UICC2 bit rate A0D1
+# SWP1A interface A0D4
+# DWP intf behavior config, SVDD Load activated by default if set to 0x31 A037
+# SPI CL Sync enable  A098
+NXP_CORE_CONF_EXTN={20, 02, 46, 0E,
+    A0, EC, 01, 01,
+    A0, ED, 01, 01,
+    A0, 5E, 01, 01,
+    A0, 12, 01, 02,
+    A0, 40, 01, 01,
+    A0, D1, 01, 02,
+    A0, D4, 01, 00,
+    A0, 37, 01, 35,
+    A0, D8, 01, 02,
+    A0, D5, 01, 0A,
+    A0, 98, 01, 01,
+    A0, AA, 04, FD, 03, F4, 01,
+    A0, 38, 04, 14, 0B, 0B, 00,
+    A0, 3A, 08, C8, 00, C8, 00, C8, 00, C8, 00
+}
+
+###############################################################################
+# Core configuration rf field filter settings to enable set to 01 to disable set
+# to 00 last bit
+NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 00 }
+
+###############################################################################
+# To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set
+# to 0x00
+NXP_I2C_FRAGMENTATION_ENABLED=0x00
+
+###############################################################################
+# Core configuration settings
+NXP_CORE_CONF={ 20, 02, 31, 0F,
+        85, 01, 01,
+        28, 01, 00,
+        21, 01, 00,
+        30, 01, 08,
+        31, 01, 03,
+        32, 01, 60,
+        38, 01, 01,
+        33, 04, 01, 02, 03, 04,
+        54, 01, 06,
+        50, 01, 02,
+        5B, 01, 00,
+        80, 01, 01,
+        81, 01, 01,
+        82, 01, 0E,
+        18, 01, 01
+}
+
+###############################################################################
+#Enable SWP full power mode when phone is power off
+NXP_SWP_FULL_PWR_ON=0x00
+
+###############################################################################
+#Set the default Felica T3T System Code OffHost route Location :
+#This settings will be used when application does not set this parameter
+# host  0x00
+# eSE   0x01
+# UICC  0x02
+# UICC2 0x03
+DEFAULT_SYS_CODE_ROUTE=0xC0
+
+###############################################################################
+# AID Matching platform options
+# AID_MATCHING_L 0x01
+# AID_MATCHING_K 0x02
+AID_MATCHING_PLATFORM=0x01
+
+###############################################################################
+#CHINA_TIANJIN_RF_SETTING
+#Enable  0x01
+#Disable  0x00
+NXP_CHINA_TIANJIN_RF_ENABLED=0x01
+
+###############################################################################
+#SWP_SWITCH_TIMEOUT_SETTING
+# Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60].
+# Timeout in milliseconds, for example
+# No Timeout  0x00
+# 10 millisecond timeout 0x0A
+NXP_SWP_SWITCH_TIMEOUT=0x0A
+
+###############################################################################
+# Enable or Disable RF_STATUS_UPDATE to EseHal module
+# Disable           0x00
+# Enable            0x01
+RF_STATUS_UPDATE_ENABLE=0x01
+
+###############################################################################
+# Configure the single default SE to use.  The default is to use the first
+# SE that is detected by the stack.  This value might be used when the phone
+# supports multiple SE (e.g. 0xF3 and 0xF4) but you want to force it to use
+# one of them (e.g. 0xF4).
+DEFAULT_OFFHOST_ROUTE=0x80
+
+###############################################################################
+# Configure the single default SE to use.  The default is to use the first
+# SE that is detected by the stack.  This value might be used when the phone
+# supports multiple SE (e.g. 0xF3 and 0xF4) but you want to force it to use
+# one of them (e.g. 0xF4).
+DEFAULT_NFCF_ROUTE=0xC0
+
+###############################################################################
+# Configure the default NfcA/IsoDep techology and protocol route. Can be
+# either a secure element (e.g. 0xF4) or the host (0x00)
+DEFAULT_ROUTE=0x00
+
+###############################################################################
+# Vendor Specific Proprietary Protocol & Discovery Configuration
+# Set to 0xFF if unsupported
+#  byte[0] NCI_PROTOCOL_18092_ACTIVE
+#  byte[1] NCI_PROTOCOL_B_PRIME
+#  byte[2] NCI_PROTOCOL_DUAL
+#  byte[3] NCI_PROTOCOL_15693
+#  byte[4] NCI_PROTOCOL_KOVIO
+#  byte[5] NCI_PROTOCOL_MIFARE
+#  byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO
+#  byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME
+#  byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME
+NFA_PROPRIETARY_CFG={05, FF, FF, 06, 81, 80, 70, FF, FF}
+
+###############################################################################
+# Bail out mode
+#  If set to 1, NFCC is using bail out mode for either Type A or Type B poll.
+NFA_POLL_BAIL_OUT_MODE=0x01
+
+###############################################################################
+# White list of Hosts
+# This values will be the Hosts(NFCEEs) in the HCI Network.
+DEVICE_HOST_WHITE_LIST={C0, 80}
+
+###############################################################################
+# Extended APDU length for ISO_DEP
+ISO_DEP_MAX_TRANSCEIVE=0xFEFF
+
+###############################################################################
+# Choose the presence-check algorithm for type-4 tag.  If not defined, the default value is 1.
+# 0  NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm
+# 1  NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block
+# 2 NFA_RW_PRES_CHK_ISO_DEP_NAK; Type - 4 tag protocol iso-dep nak presence check
+#    command is sent waiting for rsp and ntf.
+PRESENCE_CHECK_ALGORITHM=2
+###############################################################################
+# Configure the NFC Extras to open and use a static pipe.  If the value is
+# not set or set to 0, then the default is use a dynamic pipe based on a
+# destination gate (see NFA_HCI_DEFAULT_DEST_GATE).  Note there is a value
+# for each UICC (where F3="UICC0" and F4="UICC1")
+OFF_HOST_ESE_PIPE_ID=0x16
+OFF_HOST_SIM_PIPE_ID=0x70
+
+###############################################################################
+#Set the Felica T3T System Code Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Screen On lock
+# bit pos 4 = Screen off unlock
+# bit pos 5 = Screen Off lock
+DEFAULT_SYS_CODE_PWR_STATE=0x39
+
+###############################################################################