Update RF configurations

Test: Enable/Disable, HCE, Tag reading
Bug: 79387533
Change-Id: I20830bec0075382ff7963cd5815ff2d51ee2254c

2 files changed, 42 insertions, 32 deletions

diff --git a/nfc/libnfc-nxp.blueline.conf b/nfc/libnfc-nxp.blueline.conf
index 171c709..d4fbcc3 100644
--- a/nfc/libnfc-nxp.blueline.conf
+++ b/nfc/libnfc-nxp.blueline.conf
@@ -72,23 +72,24 @@ NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01,
 ###############################################################################
 #config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
 #monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
-NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, B2, 1E, 14, 00, D0, 0C}
+NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, BA, 1E, 14, 00, D0, 0C}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
 NXP_RF_CONF_BLK_1={
-20, 02, 19, 03,
-A0, 0D, 03, 24, 03, 7F,
+20, 02, 1F, 04,
+A0, 0D, 03, 24, 03, 80,
+A0, 0D, 03, 08, 41, 10,
 A0, 0D, 06, 08, 37, 08, 76, 00, 00,
-A0, 0D, 06, 08, 42, 00, 02, F8, F8
+A0, 0D, 06, 08, 42, 00, 02, F9, F9
 }
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
 NXP_RF_CONF_BLK_2={
-20, 02, 10, 01, A0, AF, 0C, 83, E3, DF, 80, 00, 83, C1, DF, 80, 00, 77, 08
+20, 02, 10, 01, A0, AF, 0C, 83, 42, B2, 80, 00, 83, 08, B2, 80, 00, 77, 08
 }
 
 ###############################################################################
@@ -99,9 +100,9 @@ NXP_RF_CONF_BLK_3={
 71, 00, 00, 96, 00, 00, BC, 00, 00, BC, 00, 00, E1, 00, 00, 07, 01, 00, 07,
 01, 00, 2C, 01, 00, 2C, 01, 00, 52, 01, 00, 52, 01, 00, 77, 01, 00, 77, 01,
 00, C2, 01, 00, C2, 01, 00, 0D, 02, 00, 0D, 02, 00, 58, 02, 00, 58, 02, 00,
-EE, 02, 00, EE, 02, 00, 18, 35, 00, 00, 4B, 00, 00, 71, 00, 00, 96, 00, 00,
-96, 00, 00, 96, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00, E1,
-00, 00, E1, 00, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01,
+EE, 02, 00, EE, 02, 00, 18, BC, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00,
+E1, 00, 00, E1, 00, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C,
+01, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05,
 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00,
 DC, 05, 00
 }
@@ -117,8 +118,8 @@ NXP_RF_CONF_BLK_4={
 44, 00, 03, 0C, C7, C6, 01, 0D, 42, 04, 03, 0D, C9, CE, 01, 0E, 42, 48, 03,
 0E, 03, 00, 01, 0F, 43, 50, 03, 0F, 43, 04, 01, 10, 43, 91, 03, 10, 45, 0A,
 01, 11, 44, 95, 03, 11, 46, 11, 01, 12, 46, 8E, 01, 13, 47, C5, 01, 14, 48,
-CC, 01, 15, 4B, D4, 01, 16, 4E, D7, 01, 17, 5E, A2, 01, 18, 5F, A6, 01, 19,
-5F, AE, 01, 1A, 60, B4, 01, 1B, 61, EA, 01, 1C, 62, F0, 01
+CC, 01, 15, 4B, D4, 01, 16, 4E, D7, 01, 17, 45, A2, 01, 18, 46, A6, 01, 19,
+46, AE, 01, 1A, 47, B4, 01, 1B, 48, EA, 01, 1C, 49, F0, 01
 }
 
 ###############################################################################
@@ -135,8 +136,10 @@ NXP_RF_CONF_BLK_5={
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
-#NXP_RF_CONF_BLK_6={
-#}
+NXP_RF_CONF_BLK_6={
+20, 02, 0C, 01, A0, 18, 08, 0C, 00, 54, 00, F4, FF, F9, FF
+}
+
 
 ###############################################################################
 # Core configuration extensions
@@ -155,21 +158,24 @@ NXP_RF_CONF_BLK_5={
 # SWP1A interface A0D4
 # DWP intf behavior config, SVDD Load activated by default if set to 0x31 A037
 # SPI CL Sync enable  A098
-NXP_CORE_CONF_EXTN={20, 02, 4A, 0F,
+NXP_CORE_CONF_EXTN={20, 02, 57, 12,
     A0, EC, 01, 01,
     A0, ED, 01, 01,
     A0, 5E, 01, 01,
     A0, 12, 01, 02,
     A0, 40, 01, 01,
+    A0, 41, 01, 02,
+    A0, 43, 01, 50,
     A0, D1, 01, 02,
     A0, D4, 01, 00,
     A0, 37, 01, 35,
     A0, D8, 01, 02,
     A0, D5, 01, 0A,
     A0, 98, 01, 03,
-    A0, AA, 04, FD, 03, 2C, 01,
+    A0, 9C, 02, 42, 00,
+    A0, AA, 04, F1, 03, 2D, 01,
     A0, 38, 04, 14, 0B, 0B, 00,
-    A0, 3A, 08, B4, 00, B4, 00, B4, 00, B4, 00,
+    A0, 3A, 08, 19, 00, 19, 00, 19, 00, 19, 00,
     A0, B2, 01, 19
 }
 
diff --git a/nfc/libnfc-nxp.crosshatch.conf b/nfc/libnfc-nxp.crosshatch.conf
index ba24631..9a3d896 100644
--- a/nfc/libnfc-nxp.crosshatch.conf
+++ b/nfc/libnfc-nxp.crosshatch.conf
@@ -72,7 +72,7 @@ NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01,
 ###############################################################################
 #config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
 #monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
-NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, B2, 1E, 14, 00, D0, 0C}
+NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, BA, 1E, 14, 00, D0, 0C}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
@@ -81,14 +81,14 @@ NXP_RF_CONF_BLK_1={
 20, 02, 19, 03,
 A0, 0D, 03, 24, 03, 80,
 A0, 0D, 06, 08, 37, 08, 76, 00, 00,
-A0, 0D, 06, 08, 42, 00, 02, F8, F8
+A0, 0D, 06, 08, 42, 00, 02, F9, F9
 }
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
 NXP_RF_CONF_BLK_2={
-20, 02, 10, 01, A0, AF, 0C, 83, E3, B9, 80, 00, 83, C2, B9, 80, 00, 77, 08
+20, 02, 10, 01, A0, AF, 0C, 83, 41, 74, 80, 00, 83, 09, 74, 80, 00, 77, 08
 }
 
 ###############################################################################
@@ -99,9 +99,9 @@ NXP_RF_CONF_BLK_3={
 71, 00, 00, 96, 00, 00, BC, 00, 00, BC, 00, 00, E1, 00, 00, 07, 01, 00, 07,
 01, 00, 2C, 01, 00, 2C, 01, 00, 52, 01, 00, 52, 01, 00, 77, 01, 00, 77, 01,
 00, C2, 01, 00, C2, 01, 00, 0D, 02, 00, 0D, 02, 00, 58, 02, 00, 58, 02, 00,
-EE, 02, 00, EE, 02, 00, 18, 35, 00, 00, 4B, 00, 00, 71, 00, 00, 96, 00, 00,
-96, 00, 00, 96, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00, E1,
-00, 00, E1, 00, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01,
+EE, 02, 00, EE, 02, 00, 18, BC, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00,
+E1, 00, 00, E1, 00, 00, 19, 01, 00, 19, 01, 00, 19, 01, 00, DC, 05, 00, DC,
+05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05,
 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00,
 DC, 05, 00
 }
@@ -117,26 +117,27 @@ NXP_RF_CONF_BLK_4={
 44, 00, 03, 0C, C7, C6, 01, 0D, 42, 04, 03, 0D, C9, CE, 01, 0E, 42, 48, 03,
 0E, 03, 00, 01, 0F, 43, 50, 03, 0F, 43, 04, 01, 10, 43, 91, 03, 10, 45, 0A,
 01, 11, 44, 95, 03, 11, 46, 11, 01, 12, 46, 8E, 01, 13, 47, C5, 01, 14, 48,
-CC, 01, 15, 4B, D4, 01, 16, 4E, D7, 01, 17, 5E, A2, 01, 18, 5F, A6, 01, 19,
-5F, AE, 01, 1A, 60, B4, 01, 1B, 61, EA, 01, 1C, 62, F0, 01
+CC, 01, 15, 4B, D4, 01, 16, 4E, D7, 01, 17, 45, A2, 01, 18, 46, A6, 01, 19,
+46, AE, 01, 1A, 47, B4, 01, 1B, 48, EA, 01, 1C, 49, F0, 01
 }
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
 NXP_RF_CONF_BLK_5={
-20, 02, 5B, 01, A0, 0B, 57, ED, 0D, 90, 7F, 0F, 4E, 00, 3B, 95, 00, 00, 3B,
-9F, 00, 00, 4D, 9F, 00, 00, 56, 9F, 00, 00, 58, 9F, 00, 00, 60, 9F, 00, 00,
-62, 9F, 00, 00, 6B, 9F, 00, 00, 6F, 9F, 00, 00, 76, 9F, 00, 00, 77, 9F, 00,
-00, 80, 9F, 00, 00, 82, 9F, 00, 00, 8B, 9F, 00, 00, 8C, 1F, 00, 00, 95, 1F,
-00, 00, 9C, 1F, 00, 00, A2, 1F, 00, 00, AA, 1F, 00, 00, B3, 1F, 00, 00
+20, 02, 5B, 01, A0, 0B, 57, ED, 0D, 90, 3F, 0F, 4E, 00, 53, 95, 00, 00, 53,
+9F, 00, 00, 6B, 9F, 00, 00, 78, 9F, 00, 00, 7A, 9F, 00, 00, 86, 9F, 00, 00,
+89, 9F, 00, 00, 95, 9F, 00, 00, 9A, 9F, 00, 00, A4, 9F, 00, 00, A6, 9F, 00,
+00, B3, 9F, 00, 00, B5, 9F, 00, 00, C1, 9F, 00, 00, C4, 1F, 00, 00, D0, 1F,
+00, 00, DA, 1F, 00, 00, E1, 1F, 00, 00, EE, 1F, 00, 00, FA, 1F, 00, 00
 }
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
-#NXP_RF_CONF_BLK_6={
-#}
+NXP_RF_CONF_BLK_6={
+20, 02, 0C, 01, A0, 18, 08, 34, 00, A1, 00, 81, FF, 30,00
+}
 
 ###############################################################################
 # Core configuration extensions
@@ -155,21 +156,24 @@ NXP_RF_CONF_BLK_5={
 # SWP1A interface A0D4
 # DWP intf behavior config, SVDD Load activated by default if set to 0x31 A037
 # SPI CL Sync enable  A098
-NXP_CORE_CONF_EXTN={20, 02, 4A, 0F,
+NXP_CORE_CONF_EXTN={20, 02, 57, 12,
     A0, EC, 01, 01,
     A0, ED, 01, 01,
     A0, 5E, 01, 01,
     A0, 12, 01, 02,
     A0, 40, 01, 01,
+    A0, 41, 01, 02,
+    A0, 43, 01, 50,
     A0, D1, 01, 02,
     A0, D4, 01, 00,
     A0, 37, 01, 35,
     A0, D8, 01, 02,
     A0, D5, 01, 0A,
     A0, 98, 01, 03,
+    A0, 9C, 02, 42, 00,
     A0, AA, 04, FD, 03, F4, 01,
     A0, 38, 04, 14, 0B, 0B, 00,
-    A0, 3A, 08, C8, 00, C8, 00, C8, 00, C8, 00,
+    A0, 3A, 08, 96, 00, 96, 00, 96, 00, 96, 00,
     A0, B2, 01, 19
 }