diff options
| author | TreeHugger Robot <treehugger-gerrit@google.com> | 2017-08-09 03:51:30 +0000 |
|---|---|---|
| committer | Android (Google) Code Review <android-gerrit@google.com> | 2017-08-09 03:51:30 +0000 |
| commit | 77c576190b066c89c0a3bba32b3b87b481279529 (patch) | |
| tree | 42bfc432f4df5628fc312f61b024483a6430739c | |
| parent | 8208b41d9ed50c130ddb8824aa97caa684763c52 (diff) | |
| parent | 845e1f7e9413e84c32530293c6e11040a891f39d (diff) | |
Merge "RF config paramters for libnfc-nxp.muskie.conf" into oc-dr1-dev
| -rw-r--r-- | nfc/libnfc-nxp.muskie.conf | 29 |
1 files changed, 20 insertions, 9 deletions
diff --git a/nfc/libnfc-nxp.muskie.conf b/nfc/libnfc-nxp.muskie.conf index 393050d..9e13ceb 100644 --- a/nfc/libnfc-nxp.muskie.conf +++ b/nfc/libnfc-nxp.muskie.conf @@ -84,25 +84,32 @@ NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01, ############################################################################### #config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM, #monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms -NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, B2, 00, B2, 1E, 1F, 00, D0, 0C} +NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, B2, 00, BA, 1E, 18, 00, D0, 0C} ############################################################################### # NXP RF configuration ALM/PLM settings # This section needs to be updated with the correct values based on the platform -#NXP_RF_CONF_BLK_1={ -#} +NXP_RF_CONF_BLK_1={ +20, 02, 22, 04, + A0, 0D, 03, 24, 03, 7E, + A0, 0D, 06, 34, 44, 66, 0A, 00, 00, + A0, 0D, 06, 06, 42, 00, 02, F4, F4, + A0, 0D, 06, 06, 37, 28, 76, 00, 00 +} ############################################################################### # NXP RF configuration ALM/PLM settings # This section needs to be updated with the correct values based on the platform -#NXP_RF_CONF_BLK_2={ -#} +NXP_RF_CONF_BLK_2={ +20, 02, D6, 01, A0, 34, D2, 23, 04, 18, 47, 40, 00, 00, 40, 01, 10, 00, 00, 03, 1E, 00, 80, 02, 32, 00, B0, 00, 4B, 00, 30, 02, 67, 00, 38, 02, 99, 00, 38, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 00, 00, 00, 00, 00, 00, 47, 00, 00, 40, 01, 10, 00, 00, 03, 1E, 00, 80, 02, 32, 00, B0, 00, 4B, 00, 30, 02, 67, 00, 38, 02, 99, 00, 38, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 00, 00 +} ############################################################################### # NXP RF configuration ALM/PLM settings # This section needs to be updated with the correct values based on the platform -#NXP_RF_CONF_BLK_3={ -#} +NXP_RF_CONF_BLK_3={ +20, 02, 5B, 01, A0, 0B, 57, F2, 12, 90, 78, 0F, 4E, 00, 3D, 95, 00, 00, 3D, 9F, 00, 00, 50, 9F, 00, 00, 59, 9F, 00, 00, 5A, 9F, 00, 00, 64, 9F, 00, 00, 65, 9F, 00, 00, 6E, 9F, 00, 00, 72, 9F, 00, 00, 79, 9F, 00, 00, 7B, 9F, 00, 00, 84, 9F, 00, 00, 86, 9F, 00, 00, 8F, 9F, 00, 00, 91, 9F, 00, 00, 9A, 9F, 00, 00, A1, 9F, 00, 00, A7, 9F, 00, 00, B0, 9F, 00, 00, B9, 1F, 00, 00 +} ############################################################################### # NXP RF configuration ALM/PLM settings @@ -144,7 +151,7 @@ NXP_SET_CONFIG_ALWAYS=0x00 # UICC2 bit rate A0D1 # SWP1A interface A0D4 # DWP intf behavior config, SVDD Load activated by default if set to 0x31 A037 -NXP_CORE_CONF_EXTN={20, 02, 29, 0A, +NXP_CORE_CONF_EXTN={20, 02, 29, 0E, A0, EC, 01, 01, A0, ED, 01, 01, A0, 5E, 01, 01, @@ -154,7 +161,11 @@ NXP_CORE_CONF_EXTN={20, 02, 29, 0A, A0, D4, 01, 00, A0, 37, 01, 35, A0, D8, 01, 02, - A0, D5, 01, 0A + A0, D5, 01, 0A, + A0, 43, 01, 00, + A0, B1, 02, 8C, 0A, + A0, 38, 04, 0A, 06, 06, 00, + A0, 3A, 08, 0E, 01, 0E, 01, 0E, 01, 0E, 01 } ############################################################################### |