klteusc: Update PN547 NFC configs for lollipop

Change-Id: I99903c30db608c19f1715e41bbe456eeace9c3c0

2 files changed, 144 insertions, 383 deletions

diff --git a/configs/libnfc-brcm.conf b/configs/libnfc-brcm.conf
index 9d2d113..8e245ce 100644
--- a/configs/libnfc-brcm.conf
+++ b/configs/libnfc-brcm.conf
@@ -2,7 +2,7 @@
 
 ###############################################################################
 # Application options
-APPL_TRACE_LEVEL=0xFF
+APPL_TRACE_LEVEL=0x02
 PROTOCOL_TRACE_LEVEL=0xFFFFFFFF
 
 ###############################################################################
@@ -133,7 +133,13 @@ OBERTHUR_WARM_RESET_COMMAND=0x03
 # Force UICC to only listen to the following technology(s).
 # The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
 # Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B | NFA_TECHNOLOGY_MASK_F
-UICC_LISTEN_TECH_MASK=0x00
+UICC_LISTEN_TECH_MASK=0x07
+
+###############################################################################
+# Force HOST listen feature enable or disable.
+# 0: Disable
+# 1: Enable
+HOST_LISTEN_ENABLE=0x01
 
 ###############################################################################
 # Allow UICC to be powered off if there is no traffic.
@@ -295,7 +301,7 @@ MAX_RF_DATA_CREDITS=1
 # NFA_TECHNOLOGY_MASK_KOVIO	        0x20    /* Proprietary Technology       */
 # NFA_TECHNOLOGY_MASK_A_ACTIVE      0x40    /* NFC Technology A active mode */
 # NFA_TECHNOLOGY_MASK_F_ACTIVE      0x80    /* NFC Technology F active mode */
-POLLING_TECH_MASK=0x6F
+POLLING_TECH_MASK=0xEF
 
 ###############################################################################
 # Force P2P to only listen for the following technology(s).
@@ -308,13 +314,16 @@ POLLING_TECH_MASK=0x6F
 # NFA_TECHNOLOGY_MASK_F	            0x04    /* NFC Technology F             */
 # NFA_TECHNOLOGY_MASK_A_ACTIVE      0x40    /* NFC Technology A active mode */
 # NFA_TECHNOLOGY_MASK_F_ACTIVE      0x80    /* NFC Technology F active mode */
-P2P_LISTEN_TECH_MASK=0x45
+P2P_LISTEN_TECH_MASK=0xC5        
 
 PRESERVE_STORAGE=0x01
 
 ###############################################################################
 # Maximum EE supported number
-# NXP PN547C2   0x02
-# NXP PN65T     0x03
-NFA_MAX_EE_SUPPORTED=0x01
+# NXP PN547C2 0x02
+# NXP PN65T 0x03
+NFA_MAX_EE_SUPPORTED=0x03
 
+###############################################################################
+# NCI Hal Module name
+NCI_HAL_MODULE="nfc_nci.pn54x"
diff --git a/configs/libnfc-nxp.conf b/configs/libnfc-nxp.conf
index cc8f6af..f8ac47c 100644
--- a/configs/libnfc-nxp.conf
+++ b/configs/libnfc-nxp.conf
@@ -2,25 +2,23 @@
 ## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn547)
 
 ###############################################################################
-# Application options
+# Application options 
 # Logging Levels
-# NXPLOG_DEFAULT_LOGLEVEL    0x01
-# ANDROID_LOG_DEBUG          0x03
-# ANDROID_LOG_WARN           0x02
-# ANDROID_LOG_ERROR          0x01
+# NXPLOG_DEFAULT_LOGLEVEL    0x01  
+# ANDROID_LOG_DEBUG          0x03 
+# ANDROID_LOG_WARN           0x02 
+# ANDROID_LOG_ERROR          0x01 
 # ANDROID_LOG_SILENT         0x00
 #
-NXPLOG_EXTNS_LOGLEVEL=0x03
-NXPLOG_NCIHAL_LOGLEVEL=0x03
-NXPLOG_NCIX_LOGLEVEL=0x03
-NXPLOG_NCIR_LOGLEVEL=0x03
-NXPLOG_FWDNLD_LOGLEVEL=0x03
-NXPLOG_TML_LOGLEVEL=0x03
+NXPLOG_EXTNS_LOGLEVEL=0x02
+NXPLOG_NCIHAL_LOGLEVEL=0x02
+NXPLOG_NCIX_LOGLEVEL=0x02
+NXPLOG_NCIR_LOGLEVEL=0x02
+NXPLOG_FWDNLD_LOGLEVEL=0x02
+NXPLOG_TML_LOGLEVEL=0x02
 
 ###############################################################################
 # Extension for Mifare reader enable
-#    0x00 - Disabled
-#    0x01 - Enabled
 MIFARE_READER_ENABLE=0x01
 
 ###############################################################################
@@ -29,24 +27,27 @@ MIFARE_READER_ENABLE=0x01
 
 ###############################################################################
 # System clock source selection configuration
-#    CLK_SRC_XTAL     - 0x01
-#    CLK_SRC_PLL      - 0x02
-NXP_SYS_CLK_SRC_SEL=0x02
+#define CLK_SRC_XTAL       1
+#define CLK_SRC_PLL        2
+
+NXP_SYS_CLK_SRC_SEL=0x01
 
 ###############################################################################
-# System clock frequency selection configuration for PLL
-#    CLK_FREQ_13MHZ   - 0x01
-#    CLK_FREQ_19_2MHZ - 0x02
-#    CLK_FREQ_24MHZ   - 0x03
-#    CLK_FREQ_26MHZ   - 0x04
-#    CLK_FREQ_38_4MHZ - 0x05
-#    CLK_FREQ_52MHZ   - 0x06
-NXP_SYS_CLK_FREQ_SEL=0x02
+# System clock frequency selection configuration
+#define CLK_FREQ_13MHZ         1
+#define CLK_FREQ_19_2MHZ       2
+#define CLK_FREQ_24MHZ         3
+#define CLK_FREQ_26MHZ         4
+#define CLK_FREQ_38_4MHZ       5
+#define CLK_FREQ_52MHZ         6
+
+NXP_SYS_CLK_FREQ_SEL=0x00
 
 ###############################################################################
 # The timeout value to be used for clock request acknowledgment
-# min value = 0x01 to max = 0x0A
-NXP_SYS_CLOCK_TO_CFG=0x0A
+# min value = 0x01 to max = 0x19
+
+NXP_SYS_CLOCK_TO_CFG=0x01
 
 ###############################################################################
 # NXP proprietary settings
@@ -57,376 +58,97 @@ NXP_ACT_PROP_EXTN={2F, 02, 00}
 NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00}
 
 ###############################################################################
-# Standby enable settings
-#    0x00 - Disabled
-#    0x01 - Enabled
-NXP_CORE_STANDBY={2F, 00, 01, 01}
+# Standby enable settings 
+#NXP_CORE_STANDBY={2F, 00, 01, 01}
 
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+# NXP_RF_CONF_BLK_1={
+#}
 
 ###############################################################################
-# NXP RF ALM (NO BOOSTER) configuration settings for FW VERSION = 08.01.15
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_2={
+#}
+
 ###############################################################################
-#    A0, 0D, 03, 00, 40, 02                RF_CLIF_BOOT                CLIF_ANA_NFCLD_REG
-#    A0, 0D, 03, 04, 43, 20                RF_CLIF_CFG_INITIATOR       CLIF_ANA_PBF_CONTROL_REG
-#    A0, 0D, 03, 04, FF, 05                RF_CLIF_CFG_INITIATOR       SMU_PMU_REG (0x40024010)
-#    A0, 0D, 06, 06, 44, A3, 90, 03, 00    RF_CLIF_CFG_TARGET          CLIF_ANA_RX_REG
-#    A0, 0D, 06, 06, 30, CF, 00, 08, 00    RF_CLIF_CFG_TARGET          CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
-#    A0, 0D, 06, 06, 2F, 8F, 05, 80, 0C    RF_CLIF_CFG_TARGET          CLIF_SIGPRO_ADCBCM_CONFIG_REG
-#    A0, 0D, 04, 06, 03, 00, 6E            RF_CLIF_CFG_TARGET          CLIF_TRANSCEIVE_CONTROL_REG
-#    A0, 0D, 03, 06, 48, 1F                RF_CLIF_CFG_TARGET          CLIF_ANA_CLK_MAN_REG
-#    A0, 0D, 03, 06, 43, A0                RF_CLIF_CFG_TARGET          CLIF_ANA_PBF_CONTROL_REG
-#    A0, 0D, 06, 06, 42, 00, 00, FF, FF    RF_CLIF_CFG_TARGET          CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 06, 06, 41, 80, 00, 00, 00    RF_CLIF_CFG_TARGET          CLIF_ANA_TX_CLK_CONTROL_REG
-#    A0, 0D, 03, 06, 37, 18                RF_CLIF_CFG_TARGET          CLIF_TX_CONTROL_REG
-#    A0, 0D, 03, 06, 16, 00                RF_CLIF_CFG_TARGET          CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 06, 15, 00                RF_CLIF_CFG_TARGET          CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 06, FF, 05, 00, 00, 00    RF_CLIF_CFG_TARGET          SMU_PMU_REG (0x40024010)
-#    A0, 0D, 06, 08, 44, 00, 00, 00, 00    RF_CLIF_CFG_I_PASSIVE       CLIF_ANA_RX_REG
-#    A0, 0D, 06, 20, 4A, 00, 00, 00, 00    RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 06, 20, 42, 88, 10, FF, FF    RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 03, 20, 16, 00                RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 20, 15, 00                RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 22, 44, 22, 00, 02, 00    RF_CLIF_CFG_TECHNO_I_RX15693CLIF_ANA_RX_REG
-#    A0, 0D, 06, 22, 2D, 50, 44, 0C, 00    RF_CLIF_CFG_TECHNO_I_RX15693CLIF_SIGPRO_RM_CONFIG1_REG
-#    A0, 0D, 04, 32, 03, 40, 3D            RF_CLIF_CFG_BR_106_I_TXA    CLIF_TRANSCEIVE_CONTROL_REG
-#    A0, 0D, 06, 32, 42, F8, 10, FF, FF    RF_CLIF_CFG_BR_106_I_TXA    CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 03, 32, 16, 00                RF_CLIF_CFG_BR_106_I_TXA    CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 32, 15, 01                RF_CLIF_CFG_BR_106_I_TXA    CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 32, 0D, 22                RF_CLIF_CFG_BR_106_I_TXA    CLIF_TX_DATA_MOD_REG
-#    A0, 0D, 03, 32, 14, 22                RF_CLIF_CFG_BR_106_I_TXA    CLIF_TX_SYMBOL23_MOD_REG
-#    A0, 0D, 06, 32, 4A, 30, 0F, 01, 1F    RF_CLIF_CFG_BR_106_I_TXA    CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 06, 34, 2D, 24, 77, 0C, 00    RF_CLIF_CFG_BR_106_I_RXA_P  CLIF_SIGPRO_RM_CONFIG1_REG
-#    A0, 0D, 06, 34, 44, 21, 00, 02, 00    RF_CLIF_CFG_BR_106_I_RXA_P  CLIF_ANA_RX_REG
-#    A0, 0D, 06, 35, 44, 21, 00, 02, 00    RF_CLIF_CFG_BR_106_I_RXA_P  CLIF_ANA_RX_REG
-#    A0, 0D, 06, 38, 4A, 53, 07, 01, 1B    RF_CLIF_CFG_BR_212_I_TXA    CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 06, 38, 42, 68, 10, FF, FF    RF_CLIF_CFG_BR_212_I_TXA    CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 03, 38, 16, 00                RF_CLIF_CFG_BR_212_I_TXA    CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 38, 15, 00                RF_CLIF_CFG_BR_212_I_TXA    CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00    RF_CLIF_CFG_BR_212_I_RXA    CLIF_SIGPRO_RM_CONFIG1_REG
-#    A0, 0D, 06, 3C, 4A, 52, 07, 01, 1B    RF_CLIF_CFG_BR_424_I_TXA    CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 06, 3C, 42, 68, 10, FF, FF    RF_CLIF_CFG_BR_424_I_TXA    CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 03, 3C, 16, 00                RF_CLIF_CFG_BR_424_I_TXA    CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 3C, 15, 00                RF_CLIF_CFG_BR_424_I_TXA    CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00    RF_CLIF_CFG_BR_424_I_RXA    CLIF_SIGPRO_RM_CONFIG1_REG
-#    A0, 0D, 06, 40, 42, F0, 10, FF, FF    RF_CLIF_CFG_BR_848_I_TXA    CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 03, 40, 0D, 02                RF_CLIF_CFG_BR_848_I_TXA    CLIF_TX_DATA_MOD_REG
-#    A0, 0D, 03, 40, 14, 02                RF_CLIF_CFG_BR_848_I_TXA    CLIF_TX_SYMBOL23_MOD_REG
-#    A0, 0D, 06, 40, 4A, 12, 07, 00, 00    RF_CLIF_CFG_BR_848_I_TXA    CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 03, 40, 16, 00                RF_CLIF_CFG_BR_848_I_TXA    CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 40, 15, 00                RF_CLIF_CFG_BR_848_I_TXA    CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 42, 2D, 15, 47, 0D, 00    RF_CLIF_CFG_BR_848_I_RXA    CLIF_SIGPRO_RM_CONFIG1_REG
-#    A0, 0D, 06, 46, 44, 21, 00, 02, 00    RF_CLIF_CFG_BR_106_I_RXB    CLIF_ANA_RX_REG
-#    A0, 0D, 06, 46, 2D, 05, 47, 0E, 00    RF_CLIF_CFG_BR_106_I_RXB    CLIF_SIGPRO_RM_CONFIG1_REG
-#    A0, 0D, 06, 44, 4A, 33, 07, 01, 07    RF_CLIF_CFG_BR_106_I_TXB    CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 06, 44, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_106_I_TXB    CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 03, 44, 16, 00                RF_CLIF_CFG_BR_106_I_TXB    CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 44, 15, 00                RF_CLIF_CFG_BR_106_I_TXB    CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 4A, 44, 22, 00, 02, 00    RF_CLIF_CFG_BR_212_I_RXB    CLIF_ANA_RX_REG
-#    A0, 0D, 06, 4A, 2D, 05, 37, 0C, 00    RF_CLIF_CFG_BR_212_I_RXB    CLIF_SIGPRO_RM_CONFIG1_REG
-#    A0, 0D, 06, 48, 4A, 33, 07, 01, 07    RF_CLIF_CFG_BR_212_I_TXB    CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 06, 48, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_212_I_TXB    CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 03, 48, 16, 00                RF_CLIF_CFG_BR_212_I_TXB    CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 48, 15, 00                RF_CLIF_CFG_BR_212_I_TXB    CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 4E, 44, 22, 00, 02, 00    RF_CLIF_CFG_BR_424_I_RXB    CLIF_ANA_RX_REG
-#    A0, 0D, 06, 4E, 2D, 05, 37, 0C, 00    RF_CLIF_CFG_BR_424_I_RXB    CLIF_SIGPRO_RM_CONFIG1_REG
-#    A0, 0D, 06, 4C, 4A, 33, 07, 01, 07    RF_CLIF_CFG_BR_424_I_TXB    CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 06, 4C, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_424_I_TXB    CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 03, 4C, 16, 00                RF_CLIF_CFG_BR_424_I_TXB    CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 4C, 15, 00                RF_CLIF_CFG_BR_424_I_TXB    CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 52, 44, 22, 00, 02, 00    RF_CLIF_CFG_BR_848_I_RXB    CLIF_ANA_RX_REG
-#    A0, 0D, 06, 52, 2D, 05, 25, 0C, 00    RF_CLIF_CFG_BR_848_I_RXB    CLIF_SIGPRO_RM_CONFIG1_REG
-#    A0, 0D, 06, 50, 42, 90, 10, FF, FF    RF_CLIF_CFG_BR_848_I_TXB    CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 06, 50, 4A, 11, 0F, 01, 07    RF_CLIF_CFG_BR_848_I_TXB    CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 03, 50, 16, 00                RF_CLIF_CFG_BR_848_I_TXB    CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 50, 15, 00                RF_CLIF_CFG_BR_848_I_TXB    CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00    RF_CLIF_CFG_BR_212_I_RXF_P  CLIF_SIGPRO_RM_CONFIG1_REG
-#    A0, 0D, 06, 56, 44, 22, 00, 02, 00    RF_CLIF_CFG_BR_212_I_RXF_P  CLIF_ANA_RX_REG
-#    A0, 0D, 06, 5C, 2D, 05, 69, 0C, 00    RF_CLIF_CFG_BR_424_I_RXF_P  CLIF_SIGPRO_RM_CONFIG1_REG
-#    A0, 0D, 06, 5C, 44, 21, 00, 02, 00    RF_CLIF_CFG_BR_424_I_RXF_P  CLIF_ANA_RX_REG
-#    A0, 0D, 06, 54, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_212_I_TXF    CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 06, 54, 4A, 33, 07, 01, 07    RF_CLIF_CFG_BR_212_I_TXF    CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 03, 54, 16, 00                RF_CLIF_CFG_BR_212_I_TXF    CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 54, 15, 00                RF_CLIF_CFG_BR_212_I_TXF    CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 5A, 42, 90, 10, FF, FF    RF_CLIF_CFG_BR_424_I_TXF    CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 06, 5A, 4A, 31, 07, 01, 07    RF_CLIF_CFG_BR_424_I_TXF    CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 03, 5A, 16, 00                RF_CLIF_CFG_BR_424_I_TXF    CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 5A, 15, 00                RF_CLIF_CFG_BR_424_I_TXF    CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 98, 2F, AF, 05, 80, 0F    RF_CLIF_GTM_B               CLIF_SIGPRO_ADCBCM_CONFIG_REG
-#    A0, 0D, 06, 9A, 42, 00, 00, FF, FF    RF_CLIF_GTM_FELICA          CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 06, 30, 44, A3, 90, 03, 00    RF_CLIF_CFG_TECHNO_T_RXF    CLIF_ANA_RX_REG
-#    A0, 0D, 06, 6C, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_106_T_RXA    CLIF_ANA_RX_REG
-#    A0, 0D, 06, 6C, 30, CF, 00, 08, 00    RF_CLIF_CFG_BR_106_T_RXA    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
-#    A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C    RF_CLIF_CFG_BR_106_T_RXA    CLIF_SIGPRO_ADCBCM_CONFIG_REG
-#    A0, 0D, 06, 70, 2F, 8F, 05, 80, 12    RF_CLIF_CFG_BR_212_T_RXA    CLIF_SIGPRO_ADCBCM_CONFIG_REG
-#    A0, 0D, 06, 70, 30, CF, 00, 08, 00    RF_CLIF_CFG_BR_212_T_RXA    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
-#    A0, 0D, 06, 74, 2F, 8F, 05, 80, 12    RF_CLIF_CFG_BR_424_T_RXA    CLIF_SIGPRO_ADCBCM_CONFIG_REG
-#    A0, 0D, 06, 74, 30, DF, 00, 07, 00    RF_CLIF_CFG_BR_424_T_RXA    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
-#    A0, 0D, 06, 78, 2F, 1F, 06, 80, 01    RF_CLIF_CFG_BR_848_T_RXA    CLIF_SIGPRO_ADCBCM_CONFIG_REG
-#    A0, 0D, 06, 78, 30, 3F, 00, 04, 00    RF_CLIF_CFG_BR_848_T_RXA    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
-#    A0, 0D, 06, 78, 44, A2, 90, 03, 00    RF_CLIF_CFG_BR_848_T_RXA    CLIF_ANA_RX_REG
-#    A0, 0D, 03, 78, 47, 00                RF_CLIF_CFG_BR_848_T_RXA    CLIF_ANA_AGC_REG
-#    A0, 0D, 06, 7C, 2F, AF, 05, 80, 0F    RF_CLIF_CFG_BR_106_T_RXB    CLIF_SIGPRO_ADCBCM_CONFIG_REG
-#    A0, 0D, 06, 7C, 30, CF, 00, 07, 00    RF_CLIF_CFG_BR_106_T_RXB    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
-#    A0, 0D, 06, 7C, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_106_T_RXB    CLIF_ANA_RX_REG
-#    A0, 0D, 06, 7D, 30, CF, 00, 08, 00    RF_CLIF_CFG_BR_106_T_RXB    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
-#    A0, 0D, 06, 80, 2F, AF, 05, 80, 90    RF_CLIF_CFG_BR_212_T_RXB    CLIF_SIGPRO_ADCBCM_CONFIG_REG
-#    A0, 0D, 06, 80, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_212_T_RXB    CLIF_ANA_RX_REG
-#    A0, 0D, 06, 84, 2F, AF, 05, 80, 92    RF_CLIF_CFG_BR_424_T_RXB    CLIF_SIGPRO_ADCBCM_CONFIG_REG
-#    A0, 0D, 06, 84, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_424_T_RXB    CLIF_ANA_RX_REG
-#    A0, 0D, 06, 88, 2F, 7F, 04, 80, 10    RF_CLIF_CFG_BR_848_T_RXB    CLIF_SIGPRO_ADCBCM_CONFIG_REG
-#    A0, 0D, 06, 88, 30, 5F, 00, 16, 00    RF_CLIF_CFG_BR_848_T_RXB    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
-#    A0, 0D, 03, 88, 47, 00                RF_CLIF_CFG_BR_848_T_RXB    CLIF_ANA_AGC_REG
-#    A0, 0D, 06, 88, 44, A1, 90, 03, 00    RF_CLIF_CFG_BR_848_T_RXB    CLIF_ANA_RX_REG
-#    A0, 0D, 03, 0C, 48, 1F                RF_CLIF_CFG_T_PASSIVE       CLIF_ANA_CLK_MAN_REG
-#    A0, 0D, 03, 10, 43, 20                RF_CLIF_CFG_T_ACTIVE        CLIF_ANA_PBF_CONTROL_REG
-#    A0, 0D, 06, 6A, 42, F8, 10, FF, FF    RF_CLIF_CFG_BR_106_T_TXA_A  CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 03, 6A, 16, 00                RF_CLIF_CFG_BR_106_T_TXA_A  CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 6A, 15, 01                RF_CLIF_CFG_BR_106_T_TXA_A  CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F    RF_CLIF_CFG_BR_106_T_TXA_A  CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 06, 8C, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_212_T_TXF_A  CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 06, 8C, 4A, 33, 07, 01, 07    RF_CLIF_CFG_BR_212_T_TXF_A  CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 03, 8C, 16, 00                RF_CLIF_CFG_BR_212_T_TXF_A  CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 8C, 15, 00                RF_CLIF_CFG_BR_212_T_TXF_A  CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 92, 42, 90, 10, FF, FF    RF_CLIF_CFG_BR_424_T_TXF_A  CLIF_ANA_TX_AMPLITUDE_REG
-#    A0, 0D, 06, 92, 4A, 31, 07, 01, 07    RF_CLIF_CFG_BR_424_T_TXF_A  CLIF_ANA_TX_SHAPE_CONTROL_REG
-#    A0, 0D, 03, 92, 16, 00                RF_CLIF_CFG_BR_424_T_TXF_A  CLIF_TX_UNDERSHOOT_CONFIG_REG
-#    A0, 0D, 03, 92, 15, 00                RF_CLIF_CFG_BR_424_T_TXF_A  CLIF_TX_OVERSHOOT_CONFIG_REG
-#    A0, 0D, 06, 0A, 30, CF, 00, 08, 00    RF_CLIF_CFG_I_ACTIVE        CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
-#    A0, 0D, 06, 0A, 2F, 8F, 05, 80, 0C    RF_CLIF_CFG_I_ACTIVE        CLIF_SIGPRO_ADCBCM_CONFIG_REG
-#    A0, 0D, 03, 0A, 48, 10                RF_CLIF_CFG_I_ACTIVE        CLIF_ANA_CLK_MAN_REG
-#    A0, 0D, 06, 0A, 44, A3, 90, 03, 00    RF_CLIF_CFG_I_ACTIVE        CLIF_ANA_RX_REG
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_3={
+#}
 
-# *** ALM(NO BOOSTER) FW VERSION = 08.01.15 ***
-NXP_RF_CONF_BLK_1={
-    20, 02, F3, 20,
-    A0, 0D, 03, 00, 40, 03,
-    A0, 0D, 03, 04, 43, 20,
-    A0, 0D, 03, 04, FF, 05,
-    A0, 0D, 06, 06, 44, A3, 90, 03, 00,
-    A0, 0D, 06, 06, 30, CF, 00, 08, 00,
-    A0, 0D, 06, 06, 2F, 8F, 05, 80, 0C,
-    A0, 0D, 04, 06, 03, 00, 71,
-    A0, 0D, 03, 06, 48, 1F,
-    A0, 0D, 03, 06, 43, A0,
-    A0, 0D, 06, 06, 42, 00, 00, F1, F6,
-    A0, 0D, 06, 06, 41, 80, 00, 00, 00,
-    A0, 0D, 03, 06, 37, 18,
-    A0, 0D, 03, 06, 16, 00,
-    A0, 0D, 03, 06, 15, 00,
-    A0, 0D, 06, 06, FF, 05, 00, 00, 00,
-    A0, 0D, 06, 08, 44, 00, 00, 00, 00,
-    A0, 0D, 06, 20, 4A, 00, 00, 00, 00,
-    A0, 0D, 06, 20, 42, 88, 10, FF, FF,
-    A0, 0D, 03, 20, 16, 00,
-    A0, 0D, 03, 20, 15, 00,
-    A0, 0D, 06, 22, 44, 22, 00, 02, 00,
-    A0, 0D, 06, 22, 2D, 50, 44, 0C, 00,
-    A0, 0D, 04, 32, 03, 40, 3D,
-    A0, 0D, 06, 32, 42, F8, 10, FF, FF,
-    A0, 0D, 03, 32, 16, 00,
-    A0, 0D, 03, 32, 15, 01,
-    A0, 0D, 03, 32, 0D, 22,
-    A0, 0D, 03, 32, 14, 22,
-    A0, 0D, 06, 32, 4A, 30, 0F, 01, 1F,
-    A0, 0D, 06, 34, 2D, 24, 77, 0C, 00,
-    A0, 0D, 06, 34, 44, 21, 00, 02, 00,
-    A0, 0D, 06, 35, 44, 21, 00, 02, 00
-}
-# *** ALM(NO BOOSTER) FW VERSION = 08.01.15 ***
-NXP_RF_CONF_BLK_2={
-    20, 02, F4, 1F,
-    A0, 0D, 06, 38, 4A, 53, 07, 01, 1B,
-    A0, 0D, 06, 38, 42, 68, 10, FF, FF,
-    A0, 0D, 03, 38, 16, 00,
-    A0, 0D, 03, 38, 15, 00,
-    A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00,
-    A0, 0D, 06, 3C, 4A, 52, 07, 01, 1B,
-    A0, 0D, 06, 3C, 42, 68, 10, FF, FF,
-    A0, 0D, 03, 3C, 16, 00,
-    A0, 0D, 03, 3C, 15, 00,
-    A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00,
-    A0, 0D, 06, 40, 42, F0, 10, FF, FF,
-    A0, 0D, 03, 40, 0D, 02,
-    A0, 0D, 03, 40, 14, 02,
-    A0, 0D, 06, 40, 4A, 12, 07, 00, 00,
-    A0, 0D, 03, 40, 16, 00,
-    A0, 0D, 03, 40, 15, 00,
-    A0, 0D, 06, 42, 2D, 15, 47, 0D, 00,
-    A0, 0D, 06, 46, 44, 21, 00, 02, 00,
-    A0, 0D, 06, 46, 2D, 05, 47, 0E, 00,
-    A0, 0D, 06, 44, 4A, 33, 07, 01, 07,
-    A0, 0D, 06, 44, 42, 88, 10, FF, FF,
-    A0, 0D, 03, 44, 16, 00,
-    A0, 0D, 03, 44, 15, 00,
-    A0, 0D, 06, 4A, 44, 22, 00, 02, 00,
-    A0, 0D, 06, 4A, 2D, 05, 37, 0C, 00,
-    A0, 0D, 06, 48, 4A, 33, 07, 01, 07,
-    A0, 0D, 06, 48, 42, 88, 10, FF, FF,
-    A0, 0D, 03, 48, 16, 00,
-    A0, 0D, 03, 48, 15, 00,
-    A0, 0D, 06, 4E, 44, 22, 00, 02, 00,
-    A0, 0D, 06, 4E, 2D, 05, 37, 0C, 00
-}
-# *** ALM(NO BOOSTER) FW VERSION = 08.01.15 ***
-NXP_RF_CONF_BLK_3={
-    20, 02, F7, 1E,
-    A0, 0D, 06, 4C, 4A, 33, 07, 01, 07,
-    A0, 0D, 06, 4C, 42, 88, 10, FF, FF,
-    A0, 0D, 03, 4C, 16, 00,
-    A0, 0D, 03, 4C, 15, 00,
-    A0, 0D, 06, 52, 44, 22, 00, 02, 00,
-    A0, 0D, 06, 52, 2D, 05, 25, 0C, 00,
-    A0, 0D, 06, 50, 42, 90, 10, FF, FF,
-    A0, 0D, 06, 50, 4A, 11, 0F, 01, 07,
-    A0, 0D, 03, 50, 16, 00,
-    A0, 0D, 03, 50, 15, 00,
-    A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00,
-    A0, 0D, 06, 56, 44, 22, 00, 02, 00,
-    A0, 0D, 06, 5C, 2D, 05, 69, 0C, 00,
-    A0, 0D, 06, 5C, 44, 21, 00, 02, 00,
-    A0, 0D, 06, 54, 42, 88, 10, FF, FF,
-    A0, 0D, 06, 54, 4A, 33, 07, 01, 07,
-    A0, 0D, 03, 54, 16, 00,
-    A0, 0D, 03, 54, 15, 00,
-    A0, 0D, 06, 5A, 42, 90, 10, FF, FF,
-    A0, 0D, 06, 5A, 4A, 31, 07, 01, 07,
-    A0, 0D, 03, 5A, 16, 00,
-    A0, 0D, 03, 5A, 15, 00,
-    A0, 0D, 06, 98, 2F, AF, 05, 80, 0F,
-    A0, 0D, 06, 9A, 42, 00, 00, F1, F6,
-    A0, 0D, 06, 30, 44, A3, 90, 03, 00,
-    A0, 0D, 06, 6C, 44, A3, 90, 03, 00,
-    A0, 0D, 06, 6C, 30, CF, 00, 08, 00,
-    A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C,
-    A0, 0D, 06, 70, 2F, 8F, 05, 80, 12,
-    A0, 0D, 06, 70, 30, CF, 00, 08, 00
-}
-# *** ALM(NO BOOSTER) FW VERSION = 08.01.15 ***
-NXP_RF_CONF_BLK_4={
-    20, 02, F7, 1E,
-    A0, 0D, 06, 74, 2F, 8F, 05, 80, 12,
-    A0, 0D, 06, 74, 30, DF, 00, 07, 00,
-    A0, 0D, 06, 78, 2F, 1F, 06, 80, 01,
-    A0, 0D, 06, 78, 30, 3F, 00, 04, 00,
-    A0, 0D, 06, 78, 44, A2, 90, 03, 00,
-    A0, 0D, 03, 78, 47, 00,
-    A0, 0D, 06, 7C, 2F, AF, 05, 80, 0F,
-    A0, 0D, 06, 7C, 30, CF, 00, 07, 00,
-    A0, 0D, 06, 7C, 44, A3, 90, 03, 00,
-    A0, 0D, 06, 7D, 30, CF, 00, 08, 00,
-    A0, 0D, 06, 80, 2F, AF, 05, 80, 90,
-    A0, 0D, 06, 80, 44, A3, 90, 03, 00,
-    A0, 0D, 06, 84, 2F, AF, 05, 80, 92,
-    A0, 0D, 06, 84, 44, A3, 90, 03, 00,
-    A0, 0D, 06, 88, 2F, 7F, 04, 80, 10,
-    A0, 0D, 06, 88, 30, 5F, 00, 16, 00,
-    A0, 0D, 03, 88, 47, 00,
-    A0, 0D, 06, 88, 44, A1, 90, 03, 00,
-    A0, 0D, 03, 0C, 48, 1F,
-    A0, 0D, 03, 10, 43, 20,
-    A0, 0D, 06, 6A, 42, F8, 10, FF, FF,
-    A0, 0D, 03, 6A, 16, 00,
-    A0, 0D, 03, 6A, 15, 01,
-    A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F,
-    A0, 0D, 06, 8C, 42, 88, 10, FF, FF,
-    A0, 0D, 06, 8C, 4A, 33, 07, 01, 07,
-    A0, 0D, 03, 8C, 16, 00,
-    A0, 0D, 03, 8C, 15, 00,
-    A0, 0D, 06, 92, 42, 90, 10, FF, FF,
-    A0, 0D, 06, 92, 4A, 31, 07, 01, 07
-}
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_4={
+#}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_5={
+#}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_6={
+#}
 
 ###############################################################################
 # Core configuration extensions
 # It includes
-# A002      - Clock Request
-#             0x00 - Disabled
-#             0x01 - Enabled
-# A003      - Clock Selection
-#             Please refer to User Manual
-# A004      - Clock Time Out
-#             Defined in ms
-# A00E      - Load Modulation Mode
-#             0x00 - PLM
-#             0x01 - ALM
-# A011      - Clock specific configuration
-#             Please refer to User Manual
-# A012      - NFCEE interface 2 configuration
-#             0x00 - SWP 2 interface is used
-#             0x02 - DWP interface is used
-# A013      - TVdd configuration
-#             0x00 - TVdd is set to 3.1V in Poll mode
-#             0x02 - TVdd is set to 2.7V in Poll mode
-# A040-A043 - Low Power Card Detector
-#             Please refer to Application Note of LPCD
-# A05E      - Jewel Reader
-#             0x00 - RID is not sent during activation
-#             0x01 - RID is sent during activation
-# A061      - Retry after LPCD
-#             0b0000XXXX - Number of retry if activation failed
-#             0bXXXX0000 - Duration to wait before retry (10ms per step)
-#             Please refer to User Manual
-# A0CD      - SWP interface 1: S1 line behavior
-#             Defined S1 High time-out during Activation sequence
-# A0EC      - SWP1 interface
-#             0x00 - Disabled
-#             0x01 - Enabled
-# A0ED      - SWP2 interface
-#             0x00 - Disabled
-#             0x01 - Enabled
-NXP_CORE_CONF_EXTN={20, 02, 40, 0F,
-        A0, 02, 01, 01,
-        A0, 04, 01, 0A,
-        A0, 0E, 01, 01,
-        A0, 11, 04, 01, 22, 67, CD,
-        A0, 12, 01, 00,
-        A0, 13, 01, 00,
-        A0, 40, 01, 01,
-        A0, 41, 01, 01, 
-        A0, 42, 01, 19,
-        A0, 43, 01, 00, 
-        A0, 5E, 01, 01,
-        A0, 61, 01, 00,
-        A0, CD, 01, 0F,
-        A0, EC, 01, 00,
-        A0, ED, 01, 00
+# Wired mode settings A0ED, A0EE
+# Tag Detector A040, A041, A043
+# Low Power mode A007
+# Clock settings A002, A003
+# PbF settings A008
+NXP_CORE_CONF_EXTN={20, 02, 16, 04,
+    A0, EC, 01, 01,  
+    A0, ED, 01, 01,
+    A0, 5E, 01, 01,
+    A0, 0D, 06, 3E, 2D, 15, 88, 15, 00
     }
+#       A0, 40, 01, 01, 
+#       A0, 41, 01, 02, 
+#       A0, 43, 01, 04,
+#       A0, 02, 01, 01, 
+#       A0, 03, 01, 11,
+#       A0, 07, 01, 03,
+#       A0, 08, 01, 01
+#       }
+
+###############################################################################
+# Core configuration rf field filter settings to enable set 01 ,to disable set to 00 last bit
+NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 01
+        }
+###############################################################################
+# To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set to 0x00
+NXP_I2C_FRAGMENTATION_ENABLED=0x00
 
 ###############################################################################
-# Core configuration settings
-# It includes
-# 18        - Poll Mode NFC-F:   PF_BIT_RATE
-# 21        - Poll Mode ISO-DEP: PI_BIT_RATE
-# 28        - Poll Mode NFC-DEP: PN_NFC_DEP_SPEED
-# 30        - Lis. Mode NFC-A:   LA_BIT_FRAME_SDD
-# 31        - Lis. Mode NFC-A:   LA_PLATFORM_CONFIG
-# 33        - Lis. Mode NFC-A:   LA_SEL_INFO
-# 50        - Lis. Mode NFC-F:   LF_PROTOCOL_TYPE
-# 54        - Lis. Mode NFC-F:   LF_CON_BITR_F
-# 5B        - Lis. Mode ISO-DEP: LI_BIT_RATE
-# 60        - Lis. Mode NFC-DEP: LN_WT
-# 80        - Other Param.:      RF_FIELD_INFO
-# 81        - Other Param.:      RF_NFCEE_ACTION
-# 82        - Other Param.:      NFCDEP_OP
+# Core configuration settings 
 NXP_CORE_CONF={ 20, 02, 2B, 0D,
-        18, 01, 01,
+        28, 01, 00,
         21, 01, 00,
-        28, 01, 01,
         30, 01, 08,
         31, 01, 03,
         33, 04, 01, 02, 03, 04,
-        50, 01, 02,
         54, 01, 06,
-        5B, 01, 02,
+        50, 01, 02,
+        5B, 01, 00,
         60, 01, 0E,
         80, 01, 01,
         81, 01, 01,
-        82, 01, 0E
+        82, 01, 0E,
+        18, 01, 01 
         }
-
+ 
 ###############################################################################
-# Mifare Classic Key settings
-#NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5,
+# Mifare Classic Key settings 
+#NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5, 
 #                                     A0, 52, 06, D3, F7, D3, F7, D3, F7,
 #                                     A0, 53, 06, FF, FF, FF, FF, FF, FF,
 #                                     A0, 54, 06, 00, 00, 00, 00, 00, 00}
@@ -436,18 +158,48 @@ NXP_CORE_CONF={ 20, 02, 2B, 0D,
 # No secure element 0x00
 # eSE               0x01
 # UICC              0x02
-# MULTI_SE          0x03 
+ 
 NXP_DEFAULT_SE=0x02
 
-###############################################################################
 NXP_DEFAULT_NFCEE_TIMEOUT=0x06
 
 ###############################################################################
 #Enable SWP full power mode when phone is power off
-NXP_SWP_FULL_PWR_ON=0x00
+NXP_SWP_FULL_PWR_ON=0x01
+
+###############################################################################
+#Set the default AID route Location : 
+#This settings will be used when application does not set this parameter
+# host 0x00
+# eSE  0x01
+# UICC 0x02
+DEFAULT_AID_ROUTE=0x00
+
+###############################################################################
+#Set the Mifare Desfire route Location : 
+#This settings will be used when application does not set this parameter
+# host 0x00
+# eSE  0x01
+# UICC 0x02
+DEFAULT_DESFIRE_ROUTE=0x02
+
+###############################################################################
+#Set the Mifare CLT route Location : 
+#This settings will be used when application does not set this parameter
+# host 0x00
+# eSE  0x01
+# UICC 0x02
+DEFAULT_MIFARE_CLT_ROUTE=0x02
 
 ###############################################################################
 #Chip type
 #PN547C2            0x01
 #PN65T              0x02
+
 NXP_NFC_CHIP=0x01
+
+#Timeout in secs
+NXP_SWP_RD_START_TIMEOUT=0x0A
+
+#Timeout in secs
+NXP_SWP_RD_TAG_OP_TIMEOUT=0x01