msm: pcie: formalize the logging output

The logging in PCIe bus driver did not distinguish different PCIe
instances in some places and missed some logging info as well. The
change here adds the needed logging info based on the feedback of
the testing.

Change-Id: Ib1c52f8cc2ffdfb2672161e4a79d299dba7861ed
CRs-fixed: 643320
Signed-off-by: Yan He <yanhe@codeaurora.org>

2 files changed, 171 insertions, 103 deletions

diff --git a/arch/arm/mach-msm/pcie.c b/arch/arm/mach-msm/pcie.c
index 586e3b16707..b43c6701109 100644
--- a/arch/arm/mach-msm/pcie.c
+++ b/arch/arm/mach-msm/pcie.c
@@ -264,7 +264,7 @@ static inline int msm_pcie_oper_conf(struct pci_bus *bus, u32 devfn, int oper,
 		rc_idx = dev->rc_idx;
 		break;
 	default:
-		pr_err("PCIe: unsupported bus number.\n");
+		pr_err("PCIe: unsupported bus number:%d.\n", bus->number);
 		*val = ~0;
 		rv = PCIBIOS_DEVICE_NOT_FOUND;
 		goto out;
@@ -299,7 +299,8 @@ static inline int msm_pcie_oper_conf(struct pci_bus *bus, u32 devfn, int oper,
 
 	/* check if the link is up for endpoint */
 	if (!rc && !msm_pcie_is_link_up(dev)) {
-			pr_err("RC%d %s fail, link down - bus %d devfn %d\n",
+			pr_err(
+				"PCIe: RC%d %s fail, link down - bus %d devfn %d\n",
 				rc_idx, (oper == RD) ? "rd" : "wr",
 				bus->number, devfn);
 			*val = ~0;
@@ -365,7 +366,7 @@ static int msm_pcie_gpio_init(struct msm_pcie_dev_t *dev)
 	int rc, i;
 	struct msm_pcie_gpio_info_t *info;
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 	for (i = 0; i < dev->gpio_n; i++) {
 		info = &dev->gpio[i];
@@ -375,7 +376,8 @@ static int msm_pcie_gpio_init(struct msm_pcie_dev_t *dev)
 
 		rc = gpio_request(info->num, info->name);
 		if (rc) {
-			pr_err("can't get gpio %s; %d\n", info->name, rc);
+			pr_err("PCIe: RC%d can't get gpio %s; %d\n",
+				dev->rc_idx, info->name, rc);
 			break;
 		}
 
@@ -384,8 +386,9 @@ static int msm_pcie_gpio_init(struct msm_pcie_dev_t *dev)
 		else
 			rc = gpio_direction_input(info->num);
 		if (rc) {
-			pr_err("can't set gpio direction %s; %d\n",
-			       info->name, rc);
+			pr_err(
+				"PCIe: RC%d can't set direction for GPIO %s:%d\n",
+				dev->rc_idx, info->name, rc);
 			gpio_free(info->num);
 			break;
 		}
@@ -402,6 +405,8 @@ static void msm_pcie_gpio_deinit(struct msm_pcie_dev_t *dev)
 {
 	int i;
 
+	PCIE_DBG("RC%d\n", dev->rc_idx);
+
 	for (i = 0; i < dev->gpio_n; i++)
 		gpio_free(dev->gpio[i].num);
 }
@@ -412,7 +417,7 @@ int msm_pcie_vreg_init(struct msm_pcie_dev_t *dev)
 	struct regulator *vreg;
 	struct msm_pcie_vreg_info_t *info;
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 	for (i = 0; i < MSM_PCIE_MAX_VREG; i++) {
 		info = &dev->vreg[i];
@@ -421,13 +426,15 @@ int msm_pcie_vreg_init(struct msm_pcie_dev_t *dev)
 		if (!vreg)
 			continue;
 
-		PCIE_DBG("Vreg %s is being enabled\n", info->name);
+		PCIE_DBG("RC%d Vreg %s is being enabled\n",
+			dev->rc_idx, info->name);
 		if (info->max_v) {
 			rc = regulator_set_voltage(vreg,
 						   info->min_v, info->max_v);
 			if (rc) {
-				pr_err("can't set voltage %s; %d\n",
-				       info->name, rc);
+				pr_err(
+					"PCIe: RC%d can't set voltage for %s: %d\n",
+					dev->rc_idx, info->name, rc);
 				break;
 			}
 		}
@@ -435,15 +442,16 @@ int msm_pcie_vreg_init(struct msm_pcie_dev_t *dev)
 		if (info->opt_mode) {
 			rc = regulator_set_optimum_mode(vreg, info->opt_mode);
 			if (rc < 0) {
-				pr_err("can't set mode %s; %d\n",
-				       info->name, rc);
+				pr_err("PCIe: RC%d can't set mode for %s: %d\n",
+					dev->rc_idx, info->name, rc);
 				break;
 			}
 		}
 
 		rc = regulator_enable(vreg);
 		if (rc) {
-			pr_err("can't enable %s, %d\n", info->name, rc);
+			pr_err("PCIe: RC%d can't enable regulator %s: %d\n",
+				dev->rc_idx, info->name, rc);
 			break;
 		}
 	}
@@ -462,6 +470,8 @@ static void msm_pcie_vreg_deinit(struct msm_pcie_dev_t *dev)
 {
 	int i;
 
+	PCIE_DBG("RC%d\n", dev->rc_idx);
+
 	for (i = MSM_PCIE_MAX_VREG - 1; i >= 0; i--) {
 		if (dev->vreg[i].hdl) {
 			PCIE_DBG("Vreg %s is being disabled\n",
@@ -476,11 +486,13 @@ static int msm_pcie_clk_init(struct msm_pcie_dev_t *dev)
 	int i, rc = 0;
 	struct msm_pcie_clk_info_t *info;
 
+	PCIE_DBG("RC%d\n", dev->rc_idx);
+
 	rc = regulator_enable(dev->gdsc);
 
 	if (rc) {
-		pr_err("PCIe: fail to enable GDSC for RC %s\n",
-			dev->pdev->name);
+		pr_err("PCIe: fail to enable GDSC for RC%d (%s)\n",
+			dev->rc_idx, dev->pdev->name);
 		return rc;
 	}
 
@@ -488,9 +500,13 @@ static int msm_pcie_clk_init(struct msm_pcie_dev_t *dev)
 		rc = msm_bus_scale_client_update_request(dev->bus_client, 1);
 		if (rc) {
 			pr_err(
-				"PCIe:%s:fail to set bus bandwidth for RC %d:%d\n",
+				"PCIe:%s:fail to set bus bandwidth for RC%d:%d.\n",
 				__func__, dev->rc_idx, rc);
 			return rc;
+		} else {
+			PCIE_DBG(
+				"PCIe:%s: set bus bandwidth for RC%d.\n",
+				__func__, dev->rc_idx);
 		}
 	}
 
@@ -503,22 +519,30 @@ static int msm_pcie_clk_init(struct msm_pcie_dev_t *dev)
 		if (info->freq) {
 			rc = clk_set_rate(info->hdl, info->freq);
 			if (rc) {
-				pr_err("PCIe: can't set rate for clk %s: %d\n",
-					info->name, rc);
+				pr_err(
+					"PCIe: RC%d can't set rate for clk %s: %d.\n",
+					dev->rc_idx, info->name, rc);
 				break;
+			} else {
+				PCIE_DBG(
+					"PCIe: RC%d set rate for clk %s.\n",
+					dev->rc_idx, info->name);
 			}
 		}
 
 		rc = clk_prepare_enable(info->hdl);
 
 		if (rc)
-			pr_err("failed to enable clk %s\n", info->name);
+			pr_err("PCIe: RC%d failed to enable clk %s\n",
+				dev->rc_idx, info->name);
 		else
-			PCIE_DBG("enable clk %s\n", info->name);
+			PCIE_DBG("enable clk %s for RC%d.\n",
+				info->name, dev->rc_idx);
 	}
 
 	if (rc) {
-		PCIE_DBG("disable clocks for error handling\n");
+		PCIE_DBG("RC%d disable clocks for error handling.\n",
+			dev->rc_idx);
 		while (i--) {
 			struct clk *hdl = dev->clk[i].hdl;
 			if (hdl)
@@ -536,6 +560,8 @@ static void msm_pcie_clk_deinit(struct msm_pcie_dev_t *dev)
 	int i;
 	int rc;
 
+	PCIE_DBG("RC%d\n", dev->rc_idx);
+
 	for (i = 0; i < MSM_PCIE_MAX_CLK; i++)
 		if (dev->clk[i].hdl)
 			clk_disable_unprepare(dev->clk[i].hdl);
@@ -544,8 +570,12 @@ static void msm_pcie_clk_deinit(struct msm_pcie_dev_t *dev)
 		rc = msm_bus_scale_client_update_request(dev->bus_client, 0);
 		if (rc)
 			pr_err(
-				"PCIe:%s:fail to set bus bandwidth for RC %d:%d\n",
+				"PCIe:%s:fail to relinquish bus bandwidth for RC%d:%d.\n",
 				__func__, dev->rc_idx, rc);
+		else
+			PCIE_DBG(
+				"PCIe:%s:relinquish bus bandwidth for RC%d.\n",
+				__func__, dev->rc_idx);
 	}
 
 	regulator_disable(dev->gdsc);
@@ -556,6 +586,8 @@ static int msm_pcie_pipe_clk_init(struct msm_pcie_dev_t *dev)
 	int i, rc = 0;
 	struct msm_pcie_clk_info_t *info;
 
+	PCIE_DBG("RC%d\n", dev->rc_idx);
+
 	for (i = 0; i < MSM_PCIE_MAX_PIPE_CLK; i++) {
 		info = &dev->pipeclk[i];
 
@@ -567,22 +599,30 @@ static int msm_pcie_pipe_clk_init(struct msm_pcie_dev_t *dev)
 		if (info->freq) {
 			rc = clk_set_rate(info->hdl, info->freq);
 			if (rc) {
-				pr_err("PCIe: can't set rate for clk %s: %d\n",
-					info->name, rc);
+				pr_err(
+					"PCIe: RC%d can't set rate for clk %s: %d.\n",
+					dev->rc_idx, info->name, rc);
 				break;
+			} else {
+				PCIE_DBG(
+					"PCIe: RC%d set rate for clk %s: %d.\n",
+					dev->rc_idx, info->name, rc);
 			}
 		}
 
 		rc = clk_prepare_enable(info->hdl);
 
 		if (rc)
-			pr_err("failed to enable clk %s\n", info->name);
+			pr_err("PCIe: RC%d failed to enable clk %s.\n",
+				dev->rc_idx, info->name);
 		else
-			PCIE_DBG("enabled pipe clk %s\n", info->name);
+			PCIE_DBG("RC%d enabled pipe clk %s.\n",
+				dev->rc_idx, info->name);
 	}
 
 	if (rc) {
-		PCIE_DBG("disable pipe clocks for error handling\n");
+		PCIE_DBG("RC%d disable pipe clocks for error handling.\n",
+			dev->rc_idx);
 		while (i--)
 			if (dev->pipeclk[i].hdl)
 				clk_disable_unprepare(dev->pipeclk[i].hdl);
@@ -595,6 +635,8 @@ static void msm_pcie_pipe_clk_deinit(struct msm_pcie_dev_t *dev)
 {
 	int i;
 
+	PCIE_DBG("RC%d\n", dev->rc_idx);
+
 	for (i = 0; i < MSM_PCIE_MAX_PIPE_CLK; i++)
 		if (dev->pipeclk[i].hdl)
 			clk_disable_unprepare(
@@ -607,7 +649,7 @@ static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev)
 	struct resource *axi_conf = dev->res[MSM_PCIE_RES_CONF].resource;
 	u32 dev_conf, upper, lower, limit;
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 	if (IS_ENABLED(CONFIG_ARM_LPAE)) {
 		lower = PCIE_LOWER_ADDR(axi_conf->start);
@@ -728,8 +770,8 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev,
 		clkfreq = kzalloc(cnt * sizeof(*clkfreq),
 					GFP_KERNEL);
 		if (!clkfreq) {
-			pr_err("%s: memory alloc failed\n",
-					__func__);
+			pr_err("%s: memory alloc failed for RC%d\n",
+					__func__, dev->rc_idx);
 			return -ENOMEM;
 		}
 		ret = of_property_read_u32_array(
@@ -737,13 +779,13 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev,
 			"max-clock-frequency-hz", clkfreq, cnt);
 		if (ret) {
 			pr_err(
-				"%s: invalid max-clock-frequency-hz property, %d\n",
-				__func__, ret);
+				"%s: invalid max-clock-frequency-hz property for RC%d:%d\n",
+				__func__, dev->rc_idx, ret);
 			goto out;
 		}
 	}
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 	for (i = 0; i < MSM_PCIE_MAX_VREG; i++) {
 		vreg_info = &dev->vreg[i];
@@ -790,8 +832,8 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev,
 	dev->gdsc = devm_regulator_get(&pdev->dev, "gdsc-vdd");
 
 	if (IS_ERR(dev->gdsc)) {
-		pr_err("PCIe: Failed to get %s GDSC:%ld\n",
-			dev->pdev->name, PTR_ERR(dev->gdsc));
+		pr_err("PCIe: RC%d Failed to get %s GDSC:%ld\n",
+			dev->rc_idx, dev->pdev->name, PTR_ERR(dev->gdsc));
 		if (PTR_ERR(dev->gdsc) == -EPROBE_DEFER)
 			PCIE_DBG("PCIe: EPROBE_DEFER for %s GDSC\n",
 					dev->pdev->name);
@@ -867,7 +909,7 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev,
 
 	dev->bus_scale_table = msm_bus_cl_get_pdata(pdev);
 	if (!dev->bus_scale_table) {
-		PCIE_DBG("PCIe: No bus scale table for RC %d (%s)\n",
+		PCIE_DBG("PCIe: No bus scale table for RC%d (%s)\n",
 			dev->rc_idx, dev->pdev->name);
 		dev->bus_client = 0;
 	} else {
@@ -875,7 +917,7 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev,
 			msm_bus_scale_register_client(dev->bus_scale_table);
 		if (!dev->bus_client) {
 			pr_err(
-				"PCIe: Failed to register bus client for RC %d (%s)\n",
+				"PCIe: Failed to register bus client for RC%d (%s)\n",
 				dev->rc_idx, dev->pdev->name);
 			msm_bus_cl_clear_pdata(dev->bus_scale_table);
 			ret = -ENODEV;
@@ -890,7 +932,8 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev,
 							   res_info->name);
 
 		if (!res) {
-			pr_err("pcie:can't get %s resource.\n", res_info->name);
+			pr_err("PCIe: RC%d can't get %s resource.\n",
+				dev->rc_idx, res_info->name);
 			ret = -ENOMEM;
 			goto out;
 		} else
@@ -900,7 +943,8 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev,
 		res_info->base = devm_ioremap(&pdev->dev,
 						res->start, resource_size(res));
 		if (!res_info->base) {
-			pr_err("pcie: can't remap %s.\n", res_info->name);
+			pr_err("PCIe: RC%d can't remap %s.\n",
+				dev->rc_idx, res_info->name);
 			ret = -ENOMEM;
 			goto out;
 		}
@@ -919,8 +963,8 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev,
 				iounmap(dev->res[j].base);
 				dev->res[j].base = NULL;
 			}
-			pr_err("pcie: can't find IRQ # for %s.\n",
-				irq_info->name);
+			pr_err("PCIe: RC%d can't find IRQ # for %s.\n",
+				dev->rc_idx, irq_info->name);
 			ret = -ENODEV;
 			goto out;
 		} else {
@@ -967,13 +1011,13 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
 	long int retries = 0;
 	int link_check_count = 0;
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 	mutex_lock(&setup_lock);
 
 	/* assert PCIe reset link to keep EP in reset */
 
-	pr_info("PCIe: Assert the reset of endpoint\n");
+	pr_info("PCIe: Assert the reset of endpoint of RC%d.\n", dev->rc_idx);
 	gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num,
 				dev->gpio[MSM_PCIE_GPIO_PERST].on);
 	usleep_range(PERST_PROPAGATION_DELAY_US_MIN,
@@ -1014,7 +1058,7 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
 			goto link_fail;
 	}
 
-	PCIE_DBG("waiting for phy ready...\n");
+	PCIE_DBG("RC%d: waiting for phy ready...\n", dev->rc_idx);
 
 	do {
 		if (pcie_phy_is_ready(dev))
@@ -1024,12 +1068,12 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
 					 REFCLK_STABILIZATION_DELAY_US_MAX);
 	} while (retries < PHY_READY_TIMEOUT_COUNT);
 
-	PCIE_DBG("number of PHY retries: %ld\n", retries);
+	PCIE_DBG("RC%d: number of PHY retries:%ld.\n", dev->rc_idx, retries);
 
 	if (pcie_phy_is_ready(dev))
-		pr_info("PCIe RC %d PHY is ready!\n", dev->rc_idx);
+		pr_info("PCIe RC%d PHY is ready!\n", dev->rc_idx);
 	else {
-		pr_err("PCIe PHY RC %d failed to come up!\n", dev->rc_idx);
+		pr_err("PCIe PHY RC%d failed to come up!\n", dev->rc_idx);
 		ret = -ENODEV;
 		goto link_fail;
 	}
@@ -1039,7 +1083,7 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
 
 	/* de-assert PCIe reset link to bring EP out of reset */
 
-	pr_info("PCIe: Release the reset of endpoint\n");
+	pr_info("PCIe: Release the reset of endpoint of RC%d.\n", dev->rc_idx);
 	gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num,
 				1 - dev->gpio[MSM_PCIE_GPIO_PERST].on);
 	usleep_range(PERST_PROPAGATION_DELAY_US_MIN,
@@ -1065,7 +1109,8 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
 	retries = 0;
 
 	while (!(val & XMLH_LINK_UP) && (retries < MAX_LINK_RETRIES)) {
-		PCIE_DBG("LTSSM_STATE:0x%x\n", (val >> 0xC) & 0x1f);
+		pr_err("RC%d:No. %ld:LTSSM_STATE:0x%x\n", dev->rc_idx,
+			retries + 1, (val >> 0xC) & 0x1f);
 		gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num,
 				dev->gpio[MSM_PCIE_GPIO_PERST].on);
 		usleep_range(PERST_PROPAGATION_DELAY_US_MIN,
@@ -1081,12 +1126,13 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
 	PCIE_DBG("number of link training retries: %ld\n", retries);
 
 	if (val & XMLH_LINK_UP) {
-		pr_info("PCIe RC %d link initialized\n", dev->rc_idx);
+		pr_info("PCIe RC%d link initialized\n", dev->rc_idx);
 	} else {
-		pr_info("PCIe: Assert the reset of endpoint\n");
+		pr_info("PCIe: Assert the reset of endpoint of RC%d.\n",
+			dev->rc_idx);
 		gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num,
 			dev->gpio[MSM_PCIE_GPIO_PERST].on);
-		pr_err("PCIe RC %d link initialization failed\n", dev->rc_idx);
+		pr_err("PCIe RC%d link initialization failed\n", dev->rc_idx);
 		ret = -1;
 		goto link_fail;
 	}
@@ -1116,9 +1162,9 @@ out:
 
 void msm_pcie_disable(struct msm_pcie_dev_t *dev, u32 options)
 {
-	PCIE_DBG("RC %d\n", dev->rc_idx);
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
-	pr_info("PCIe: Assert the reset of endpoint\n");
+	pr_info("PCIe: Assert the reset of endpoint of RC%d.\n", dev->rc_idx);
 	gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num,
 				dev->gpio[MSM_PCIE_GPIO_PERST].on);
 
@@ -1189,7 +1235,8 @@ static int msm_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 		ret = pcie_dev->irq[MSM_PCIE_INT_D].num;
 		break;
 	default:
-		pr_err("PCIe: unsupported pin number.\n");
+		pr_err("PCIe: RC%d: unsupported pin number.\n",
+			pcie_dev->rc_idx);
 	}
 
 	return ret;
@@ -1220,7 +1267,7 @@ int msm_pcie_enumerate(u32 rc_idx)
 	int ret = 0;
 	struct msm_pcie_dev_t *dev = &msm_pcie_dev[rc_idx];
 
-	PCIE_DBG("Enumerate RC %d\n", rc_idx);
+	PCIE_DBG("Enumerate RC%d\n", rc_idx);
 
 	if (!dev->enumerated) {
 		ret = msm_pcie_enable(dev, PM_ALL);
@@ -1250,23 +1297,23 @@ int msm_pcie_enumerate(u32 rc_idx)
 					msm_pcie_dev[rc_idx].dev = pcidev;
 					found = true;
 					PCIE_DBG(
-						"PCI device is found for RC %d\n",
+						"PCI device is found for RC%d\n",
 						rc_idx);
 				}
 			} while (!found && pcidev);
 
 			if (!pcidev) {
 				pr_err(
-					"PCIe: %s: Did not find PCI device for RC %d.\n",
+					"PCIe: %s: Did not find PCI device for RC%d.\n",
 					__func__, dev->rc_idx);
 				return -ENODEV;
 			}
 		} else {
-			pr_err("PCIe: %s: failed to enable RC %d.\n",
+			pr_err("PCIe: %s: failed to enable RC%d.\n",
 				__func__, dev->rc_idx);
 		}
 	} else {
-		pr_err("PCIe: %s: RC %d has already been enumerated.\n",
+		pr_err("PCIe: %s: RC%d has already been enumerated.\n",
 			__func__, dev->rc_idx);
 	}
 
@@ -1276,7 +1323,7 @@ int msm_pcie_enumerate(u32 rc_idx)
 static int msm_pcie_probe(struct platform_device *pdev)
 {
 	int ret = 0;
-	int rc_idx;
+	int rc_idx = -1;
 
 	PCIE_DBG("\n");
 
@@ -1368,7 +1415,8 @@ static int msm_pcie_probe(struct platform_device *pdev)
 				&msm_pcie_dev[rc_idx].msi_gicm_base);
 
 		if (ret) {
-			pr_err("msi-gicm-base does not exist.\n");
+			pr_err("PCIe: RC%d: msi-gicm-base does not exist.\n",
+				rc_idx);
 			goto decrease_rc_num;
 		} else {
 			PCIE_DBG("msi-gicm-base: 0x%x.\n",
@@ -1422,10 +1470,10 @@ static int msm_pcie_probe(struct platform_device *pdev)
 
 	if (ret)
 		pr_err(
-			"PCIe:failed to enable RC %d in bootup; it will be enumerated upon WAKE signal.\n",
+			"PCIe: RC%d is not enabled during bootup; it will be enumerated upon WAKE signal.\n",
 			rc_idx);
 	else
-		PCIE_DBG("RC %d is enabled in bootup\n", rc_idx);
+		PCIE_DBG("RC%d is enabled in bootup\n", rc_idx);
 
 	PCIE_DBG("PCIE probed %s\n", dev_name(&(pdev->dev)));
 	mutex_unlock(&pcie_drv.drv_lock);
@@ -1434,7 +1482,7 @@ static int msm_pcie_probe(struct platform_device *pdev)
 decrease_rc_num:
 	pcie_drv.rc_num--;
 out:
-	pr_err("Driver Failed ret=%d\n", ret);
+	pr_err("PCIe: Driver probe failed for RC%d:%d\n", rc_idx, ret);
 	mutex_unlock(&pcie_drv.drv_lock);
 
 	return ret;
@@ -1445,6 +1493,8 @@ static int __exit msm_pcie_remove(struct platform_device *pdev)
 	int ret = 0;
 	int rc_idx;
 
+	PCIE_DBG("PCIe:%s.\n", __func__);
+
 	mutex_lock(&pcie_drv.drv_lock);
 
 	ret = of_property_read_u32((&pdev->dev)->of_node,
@@ -1536,15 +1586,16 @@ static int msm_pcie_pm_suspend(struct pci_dev *dev,
 	int ret_l23;
 	struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev);
 
-	PCIE_DBG("RC %d\n", pcie_dev->rc_idx);
+	PCIE_DBG("RC%d\n", pcie_dev->rc_idx);
 
 	if (dev) {
+		PCIE_DBG("Save config space of RC%d.\n", pcie_dev->rc_idx);
 		ret = pci_save_state(dev);
 		pcie_dev->saved_state =	pci_store_saved_state(dev);
 	}
 	if (ret) {
-		pr_err("PCIe: fail to save state of RC 0x%p:%d.\n",
-				dev, ret);
+		pr_err("PCIe: fail to save state of RC%d:%d.\n",
+			pcie_dev->rc_idx, ret);
 		return ret;
 	}
 
@@ -1557,16 +1608,17 @@ static int msm_pcie_pm_suspend(struct pci_dev *dev,
 	msm_pcie_write_mask(pcie_dev->elbi + PCIE20_ELBI_SYS_CTRL, 0,
 				BIT(4));
 
-	PCIE_DBG("PME_TURNOFF_MSG is sent out\n");
+	PCIE_DBG("RC%d: PME_TURNOFF_MSG is sent out\n", pcie_dev->rc_idx);
 
 	ret_l23 = readl_poll_timeout((pcie_dev->parf
 		+ PCIE20_PARF_PM_STTS), val, (val & BIT(6)), 10000, 100000);
 
 	/* check L23_Ready */
 	if (!ret_l23)
-		PCIE_DBG("PM_Enter_L23 is received\n");
+		PCIE_DBG("RC%d: PM_Enter_L23 is received\n", pcie_dev->rc_idx);
 	else
-		PCIE_DBG("PM_Enter_L23 is NOT received\n");
+		PCIE_DBG("RC%d: PM_Enter_L23 is NOT received\n",
+			pcie_dev->rc_idx);
 
 	msm_pcie_disable(pcie_dev, PM_PIPE_CLK | PM_CLK | PM_VREG);
 
@@ -1578,14 +1630,15 @@ static void msm_pcie_fixup_suspend(struct pci_dev *dev)
 	int ret;
 	struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev);
 
-	PCIE_DBG("RC %d\n", pcie_dev->rc_idx);
+	PCIE_DBG("RC%d\n", pcie_dev->rc_idx);
 
 	if (pcie_dev->link_status != MSM_PCIE_LINK_ENABLED)
 		return;
 
 	ret = msm_pcie_pm_suspend(dev, NULL, NULL, 0);
 	if (ret)
-		pr_err("PCIe: got failure in suspend:%d.\n", ret);
+		pr_err("PCIe: RC%d got failure in suspend:%d.\n",
+			pcie_dev->rc_idx, ret);
 }
 DECLARE_PCI_FIXUP_SUSPEND(PCIE_VENDOR_ID_RCP, PCIE_DEVICE_ID_RCP,
 			  msm_pcie_fixup_suspend);
@@ -1597,7 +1650,7 @@ static int msm_pcie_pm_resume(struct pci_dev *dev,
 	int ret;
 	struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev);
 
-	PCIE_DBG("RC %d\n", pcie_dev->rc_idx);
+	PCIE_DBG("RC%d\n", pcie_dev->rc_idx);
 
 	spin_lock_irqsave(&pcie_dev->cfg_lock,
 				pcie_dev->irqsave_flags);
@@ -1607,7 +1660,8 @@ static int msm_pcie_pm_resume(struct pci_dev *dev,
 
 	ret = msm_pcie_enable(pcie_dev, PM_PIPE_CLK | PM_CLK | PM_VREG);
 	if (ret) {
-		pr_err("PCIe:fail to enable PCIe link in resume\n");
+		pr_err("PCIe: RC%d fail to enable PCIe link in resume.\n",
+			pcie_dev->rc_idx);
 		return ret;
 	} else {
 		PCIE_DBG("dev->bus->number = %d dev->bus->primary = %d\n",
@@ -1626,7 +1680,7 @@ void msm_pcie_fixup_resume(struct pci_dev *dev)
 	int ret;
 	struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev);
 
-	PCIE_DBG("RC %d\n", pcie_dev->rc_idx);
+	PCIE_DBG("RC%d\n", pcie_dev->rc_idx);
 
 	if ((pcie_dev->link_status != MSM_PCIE_LINK_DISABLED) ||
 		pcie_dev->user_suspend)
@@ -1634,7 +1688,8 @@ void msm_pcie_fixup_resume(struct pci_dev *dev)
 
 	ret = msm_pcie_pm_resume(dev, NULL, NULL, 0);
 	if (ret)
-		pr_err("PCIe: got failure in fixup resume:%d.\n", ret);
+		pr_err("PCIe: RC%d got failure in fixup resume:%d.\n",
+			pcie_dev->rc_idx, ret);
 }
 DECLARE_PCI_FIXUP_RESUME(PCIE_VENDOR_ID_RCP, PCIE_DEVICE_ID_RCP,
 				 msm_pcie_fixup_resume);
@@ -1644,7 +1699,7 @@ void msm_pcie_fixup_resume_early(struct pci_dev *dev)
 	int ret;
 	struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev);
 
-	PCIE_DBG("RC %d\n", pcie_dev->rc_idx);
+	PCIE_DBG("RC%d\n", pcie_dev->rc_idx);
 
 	if ((pcie_dev->link_status != MSM_PCIE_LINK_DISABLED) ||
 		pcie_dev->user_suspend)
@@ -1652,7 +1707,8 @@ void msm_pcie_fixup_resume_early(struct pci_dev *dev)
 
 	ret = msm_pcie_pm_resume(dev, NULL, NULL, 0);
 	if (ret)
-		pr_err("PCIe: got failure in resume:%d.\n", ret);
+		pr_err("PCIe: RC%d got failure in resume:%d.\n",
+			pcie_dev->rc_idx, ret);
 }
 DECLARE_PCI_FIXUP_RESUME_EARLY(PCIE_VENDOR_ID_RCP, PCIE_DEVICE_ID_RCP,
 				 msm_pcie_fixup_resume_early);
@@ -1660,7 +1716,7 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCIE_VENDOR_ID_RCP, PCIE_DEVICE_ID_RCP,
 static void msm_pcie_fixup_final(struct pci_dev *dev)
 {
 	struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev);
-	PCIE_DBG("RC %d\n", pcie_dev->rc_idx);
+	PCIE_DBG("RC%d\n", pcie_dev->rc_idx);
 	pcie_drv.current_rc++;
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, msm_pcie_fixup_final);
@@ -1682,7 +1738,7 @@ int msm_pcie_pm_control(enum msm_pcie_pm_opt pm_opt, u32 busnr, void *user,
 
 			if (pcie_dev) {
 				rc_idx = pcie_dev->rc_idx;
-				PCIE_DBG("RC %d\n", pcie_dev->rc_idx);
+				PCIE_DBG("RC%d\n", pcie_dev->rc_idx);
 			} else {
 				pr_err(
 					"PCIe: did not find RC for pci endpoint device 0x%x.\n",
@@ -1702,35 +1758,41 @@ int msm_pcie_pm_control(enum msm_pcie_pm_opt pm_opt, u32 busnr, void *user,
 
 	switch (pm_opt) {
 	case MSM_PCIE_SUSPEND:
+		PCIE_DBG("User of RC%d requests to suspend the link\n",	rc_idx);
 		if (msm_pcie_dev[rc_idx].link_status != MSM_PCIE_LINK_ENABLED) {
 			pr_err(
-				"PCIe: requested to suspend when link is not enabled:%d.\n",
-				msm_pcie_dev[rc_idx].link_status);
+				"PCIe: RC%d: requested to suspend when link is not enabled:%d.\n",
+				rc_idx, msm_pcie_dev[rc_idx].link_status);
 			break;
 		}
 		msm_pcie_dev[rc_idx].user_suspend = true;
 		ret = msm_pcie_pm_suspend(dev, user, data, options);
 		if (ret) {
-			pr_err("PCIe: user failed to suspend the link.\n");
+			pr_err(
+				"PCIe: RC%d: user failed to suspend the link.\n",
+				rc_idx);
 			msm_pcie_dev[rc_idx].user_suspend = false;
 		}
 		break;
 	case MSM_PCIE_RESUME:
+		PCIE_DBG("User of RC%d requests to resume the link\n", rc_idx);
 		if (msm_pcie_dev[rc_idx].link_status !=
 					MSM_PCIE_LINK_DISABLED) {
 			pr_err(
-				"PCIe: requested to resume when link is not disabled:%d.\n",
-				msm_pcie_dev[rc_idx].link_status);
+				"PCIe: RC%d: requested to resume when link is not disabled:%d.\n",
+				rc_idx, msm_pcie_dev[rc_idx].link_status);
 			break;
 		}
 		ret = msm_pcie_pm_resume(dev, user, data, options);
 		if (ret)
-			pr_err("PCIe: user failed to resume the link.\n");
+			pr_err("PCIe: RC%d: user failed to resume the link.\n",
+				rc_idx);
 		else
 			msm_pcie_dev[rc_idx].user_suspend = false;
 		break;
 	default:
-		pr_err("PCIe: unsupported pm operation:%d.\n", pm_opt);
+		pr_err("PCIe: RC%d: unsupported pm operation:%d.\n",
+			rc_idx, pm_opt);
 		ret = -ENODEV;
 		goto out;
 	}
diff --git a/arch/arm/mach-msm/pcie_irq.c b/arch/arm/mach-msm/pcie_irq.c
index 48a07054cc8..a81b7675d2d 100644
--- a/arch/arm/mach-msm/pcie_irq.c
+++ b/arch/arm/mach-msm/pcie_irq.c
@@ -111,7 +111,7 @@ void msm_pcie_config_msi_controller(struct msm_pcie_dev_t *dev)
 {
 	int i;
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 	/* program MSI controller and enable all interrupts */
 	writel_relaxed(MSM_PCIE_MSI_PHY, dev->dm_core + PCIE20_MSI_CTRL_ADDR);
@@ -143,7 +143,7 @@ void msm_pcie_destroy_irq(unsigned int irq, struct msm_pcie_dev_t *pcie_dev)
 		pos = irq - irq_find_mapping(dev->irq_domain, 0);
 	}
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 	if (!dev->msi_gicm_addr)
 		dynamic_irq_cleanup(irq);
@@ -199,7 +199,7 @@ static int msm_pcie_create_irq(struct msm_pcie_dev_t *dev)
 {
 	int irq, pos;
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 again:
 	pos = find_first_zero_bit(dev->msi_irq_in_use, PCIE_MSI_NR_IRQS);
@@ -228,7 +228,7 @@ static int arch_setup_msi_irq_default(struct pci_dev *pdev,
 	struct msi_msg msg;
 	struct msm_pcie_dev_t *dev = PCIE_BUS_PRIV_DATA(pdev);
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 	irq = msm_pcie_create_irq(dev);
 
@@ -254,7 +254,7 @@ static int msm_pcie_create_irq_qgic(struct msm_pcie_dev_t *dev)
 {
 	int irq, pos;
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 again:
 	pos = find_first_zero_bit(dev->msi_irq_in_use, PCIE_MSI_NR_IRQS);
@@ -271,7 +271,8 @@ again:
 
 	irq = dev->msi_gicm_base + pos;
 	if (!irq) {
-		pr_err("PCIe: failed to create QGIC MSI IRQ.\n");
+		pr_err("PCIe: RC%d failed to create QGIC MSI IRQ.\n",
+			dev->rc_idx);
 		return -EINVAL;
 	}
 
@@ -285,7 +286,7 @@ static int arch_setup_msi_irq_qgic(struct pci_dev *pdev,
 	struct msi_msg msg;
 	struct msm_pcie_dev_t *dev = PCIE_BUS_PRIV_DATA(pdev);
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 	for (index = 0; index < nvec; index++) {
 		irq = msm_pcie_create_irq_qgic(dev);
@@ -314,7 +315,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
 {
 	struct msm_pcie_dev_t *dev = PCIE_BUS_PRIV_DATA(pdev);
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 	if (dev->msi_gicm_addr)
 		return arch_setup_msi_irq_qgic(pdev, desc, 1);
@@ -344,7 +345,7 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
 	int ret;
 	struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev);
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", pcie_dev->rc_idx);
 
 	if (type != PCI_CAP_ID_MSI || nvec > 32)
 		return -ENOSPC;
@@ -374,6 +375,7 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
 static int msm_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
 	   irq_hw_number_t hwirq)
 {
+	PCIE_DBG("\n");
 	irq_set_chip_and_handler (irq, &pcie_msi_chip, handle_simple_irq);
 	irq_set_chip_data(irq, domain->host_data);
 	set_irq_flags(irq, IRQF_VALID);
@@ -390,7 +392,7 @@ int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev)
 	int msi_start =  0;
 	struct device *pdev = &dev->pdev->dev;
 
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 	wakeup_source_init(&dev->ws, "pcie_wakeup_source");
 
@@ -399,7 +401,8 @@ int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev)
 		dev->irq[MSM_PCIE_INT_MSI].num, handle_msi_irq,
 		IRQF_TRIGGER_RISING, dev->irq[MSM_PCIE_INT_MSI].name, dev);
 	if (rc) {
-		pr_err("PCIe: Unable to request MSI interrupt\n");
+		pr_err("PCIe: RC%d: Unable to request MSI interrupt\n",
+			dev->rc_idx);
 		return rc;
 	}
 
@@ -408,7 +411,8 @@ int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev)
 			dev->wake_n, handle_wake_irq, IRQF_TRIGGER_FALLING,
 			 "msm_pcie_wake", dev);
 	if (rc) {
-		pr_err("PCIe: Unable to request wake interrupt\n");
+		pr_err("PCIe: RC%d: Unable to request wake interrupt\n",
+			dev->rc_idx);
 		return rc;
 	}
 
@@ -416,7 +420,8 @@ int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev)
 
 	rc = enable_irq_wake(dev->wake_n);
 	if (rc) {
-		pr_err("PCIe: Unable to enable wake interrupt\n");
+		pr_err("PCIe: RC%d: Unable to enable wake interrupt\n",
+			dev->rc_idx);
 		return rc;
 	}
 
@@ -426,7 +431,8 @@ int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev)
 			PCIE_MSI_NR_IRQS, &msm_pcie_msi_ops, dev);
 
 		if (!dev->irq_domain) {
-			pr_err("PCIe: Unable to initialize irq domain\n");
+			pr_err("PCIe: RC%d: Unable to initialize irq domain\n",
+				dev->rc_idx);
 			disable_irq(dev->wake_n);
 			return PTR_ERR(dev->irq_domain);
 		}
@@ -439,7 +445,7 @@ int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev)
 
 void msm_pcie_irq_deinit(struct msm_pcie_dev_t *dev)
 {
-	PCIE_DBG("\n");
+	PCIE_DBG("RC%d\n", dev->rc_idx);
 
 	wakeup_source_trash(&dev->ws);
 	disable_irq(dev->wake_n);