diff options
| author | Vivek Veenam <vveenam@codeaurora.org> | 2014-04-07 19:12:12 +0530 |
|---|---|---|
| committer | Vivek Veenam <vveenam@codeaurora.org> | 2014-04-10 07:41:16 +0530 |
| commit | 1a3e51df2a2c9fec30bfa9f41387611b04d61142 (patch) | |
| tree | f590f20fd5e65e4ba027ab7460facbb85dd2d17e /scripts/build-all.py | |
| parent | 93980fdb49b713418433a2d9233ebe1bb521f99f (diff) | |
Arm: dts: msm: camera: Enable csiphy_clk in CSIPHY init
csiphy_clk is enabled and disabled as part of csid
init and release. In release sequence csid release
is called before csiphy release and csiphy_clk is
disabled in csid release. This causes unclock register
access in csiphy release.
Enable and disable csiphy_clk in csiphy init and release.
CRs-Fixed: 640406
Change-Id: I04505e71e82e6766da09c2a98cfa4be7e8afea5a
Signed-off-by: Vivek Veenam <vveenam@codeaurora.org>
Diffstat (limited to 'scripts/build-all.py')
0 files changed, 0 insertions, 0 deletions