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| author | Archana Sathyakumar <asathyak@codeaurora.org> | 2013-09-30 13:12:39 -0600 |
|---|---|---|
| committer | Archana Sathyakumar <asathyak@codeaurora.org> | 2013-09-30 17:03:18 -0600 |
| commit | 2a5e932c99446b559cf50b28b2f29f758db20e6d (patch) | |
| tree | eb5b1408daa715154c0f677dca1e9097e8d08e9f /scripts/build-all.py | |
| parent | c99f9b850aa753a04271342b2c28320eee6a94fc (diff) | |
msm: spm: Update the vctl, phase and pfm port values for cpu devices
Currently only L2 device updates these values. Update this information
for cpu devices as well to support individual rail configuration.
Update device tree documentation for these nodes.
Change-Id: Ib147ab1eaf8ac961c566cfc48f54ed904efaca1d
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
Diffstat (limited to 'scripts/build-all.py')
0 files changed, 0 insertions, 0 deletions