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| author | Junjie Wu <junjiew@codeaurora.org> | 2014-02-21 16:19:24 -0800 |
|---|---|---|
| committer | Junjie Wu <junjiew@codeaurora.org> | 2014-03-06 01:51:54 -0800 |
| commit | 99b16ba9ba57a04b3fcce24c78edc85d12a40cf8 (patch) | |
| tree | 0c6aca59db44d11ba2dcd706c915194e9b1a0c11 /scripts/build-all.py | |
| parent | aeccbbdcc632ea9d0b03d5c88ee9d8e495faefcb (diff) | |
clock-plutonium: Model GPLL0 gating from GCC to MMSS
MMSS needs to vote enable one bit in GCC before GPLL0 signal is propagated
to MMSS clock controller. Model this bit as a gate clock.
Change-Id: Iff8a228655cb778e4cc880ce9693ac756d41dda0
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
Diffstat (limited to 'scripts/build-all.py')
0 files changed, 0 insertions, 0 deletions