path: root/drivers/misc/mnh/mnh-hwio-ddr-ctl.h

/* auto generated: Friday, August 26th, 2016 11:42:15am */
/*
 * Copyright (c) 2016, Intel Corporation. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * Redistributions of source code must retain the above copyright notice, this
 * list of conditions and the following disclaimer.
 *
 * Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * Neither the name of Intel nor the names of its contributors may be used
 * to endorse or promote products derived from this software without specific
 * prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
#ifndef __MNH_HWIO_DDR_CTL_
#define __MNH_HWIO_DDR_CTL_

#define HWIO_DDR_CTL_00_REGOFF 0x0
#define HWIO_DDR_CTL_00_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_00_REGOFF)
#define HWIO_DDR_CTL_00_START_FLDMASK (0x1)
#define HWIO_DDR_CTL_00_START_FLDSHFT (0)
#define HWIO_DDR_CTL_00_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_00_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_00_DRAM_CLASS_FLDMASK (0xf00)
#define HWIO_DDR_CTL_00_DRAM_CLASS_FLDSHFT (8)
#define HWIO_DDR_CTL_00_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_00_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_00_VERSION_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_00_VERSION_FLDSHFT (16)

#define HWIO_DDR_CTL_01_REGOFF 0x4
#define HWIO_DDR_CTL_01_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_01_REGOFF)
#define HWIO_DDR_CTL_01_MAX_ROW_REG_FLDMASK (0xf)
#define HWIO_DDR_CTL_01_MAX_ROW_REG_FLDSHFT (0)
#define HWIO_DDR_CTL_01_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_01_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_01_MAX_COL_REG_FLDMASK (0xf00)
#define HWIO_DDR_CTL_01_MAX_COL_REG_FLDSHFT (8)
#define HWIO_DDR_CTL_01_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_01_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_01_MAX_CS_REG_FLDMASK (0x10000)
#define HWIO_DDR_CTL_01_MAX_CS_REG_FLDSHFT (16)
#define HWIO_DDR_CTL_01_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_01_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_01_READ_DATA_FIFO_DEPTH_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_01_READ_DATA_FIFO_DEPTH_FLDSHFT (24)

#define HWIO_DDR_CTL_02_REGOFF 0x8
#define HWIO_DDR_CTL_02_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_02_REGOFF)
#define HWIO_DDR_CTL_02_READ_DATA_FIFO_PTR_WIDTH_FLDMASK (0xff)
#define HWIO_DDR_CTL_02_READ_DATA_FIFO_PTR_WIDTH_FLDSHFT (0)
#define HWIO_DDR_CTL_02_WRITE_DATA_FIFO_DEPTH_FLDMASK (0xff00)
#define HWIO_DDR_CTL_02_WRITE_DATA_FIFO_DEPTH_FLDSHFT (8)
#define HWIO_DDR_CTL_02_WRITE_DATA_FIFO_PTR_WIDTH_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_02_WRITE_DATA_FIFO_PTR_WIDTH_FLDSHFT (16)
#define HWIO_DDR_CTL_02_MEMCD_RMODW_FIFO_DEPTH_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_02_MEMCD_RMODW_FIFO_DEPTH_FLDSHFT (24)

#define HWIO_DDR_CTL_03_REGOFF 0xc
#define HWIO_DDR_CTL_03_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_03_REGOFF)
#define HWIO_DDR_CTL_03_MEMCD_RMODW_FIFO_PTR_WIDTH_FLDMASK (0xff)
#define HWIO_DDR_CTL_03_MEMCD_RMODW_FIFO_PTR_WIDTH_FLDSHFT (0)
#define HWIO_DDR_CTL_03_ASYNC_CDC_STAGES_FLDMASK (0xff00)
#define HWIO_DDR_CTL_03_ASYNC_CDC_STAGES_FLDSHFT (8)
#define HWIO_DDR_CTL_03_AXI0_CMDFIFO_LOG2_DEPTH_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_03_AXI0_CMDFIFO_LOG2_DEPTH_FLDSHFT (16)
#define HWIO_DDR_CTL_03_AXI0_RDFIFO_LOG2_DEPTH_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_03_AXI0_RDFIFO_LOG2_DEPTH_FLDSHFT (24)

#define HWIO_DDR_CTL_04_REGOFF 0x10
#define HWIO_DDR_CTL_04_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_04_REGOFF)
#define HWIO_DDR_CTL_04_OBSOLETE0_FLDMASK (0xff)
#define HWIO_DDR_CTL_04_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_04_AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_FLDMASK (0xff00)
#define HWIO_DDR_CTL_04_AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_FLDSHFT (8)
#define HWIO_DDR_CTL_04_AXI1_CMDFIFO_LOG2_DEPTH_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_04_AXI1_CMDFIFO_LOG2_DEPTH_FLDSHFT (16)
#define HWIO_DDR_CTL_04_AXI1_RDFIFO_LOG2_DEPTH_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_04_AXI1_RDFIFO_LOG2_DEPTH_FLDSHFT (24)

#define HWIO_DDR_CTL_05_REGOFF 0x14
#define HWIO_DDR_CTL_05_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_05_REGOFF)
#define HWIO_DDR_CTL_05_OBSOLETE0_FLDMASK (0xff)
#define HWIO_DDR_CTL_05_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_05_AXI1_WRCMD_PROC_FIFO_LOG2_DEPTH_FLDMASK (0xff00)
#define HWIO_DDR_CTL_05_AXI1_WRCMD_PROC_FIFO_LOG2_DEPTH_FLDSHFT (8)
#define HWIO_DDR_CTL_05_DFS_CLOSE_BANKS_FLDMASK (0x10000)
#define HWIO_DDR_CTL_05_DFS_CLOSE_BANKS_FLDSHFT (16)
#define HWIO_DDR_CTL_05_RESERVED_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_05_RESERVED_FLDSHFT (17)
#define HWIO_DDR_CTL_05_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_05_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_CTL_06_REGOFF 0x18
#define HWIO_DDR_CTL_06_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_06_REGOFF)
#define HWIO_DDR_CTL_06_TINIT_F0_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_06_TINIT_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_06_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_06_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_07_REGOFF 0x1c
#define HWIO_DDR_CTL_07_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_07_REGOFF)
#define HWIO_DDR_CTL_07_TINIT3_F0_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_07_TINIT3_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_07_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_07_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_08_REGOFF 0x20
#define HWIO_DDR_CTL_08_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_08_REGOFF)
#define HWIO_DDR_CTL_08_TINIT4_F0_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_08_TINIT4_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_08_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_08_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_09_REGOFF 0x24
#define HWIO_DDR_CTL_09_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_09_REGOFF)
#define HWIO_DDR_CTL_09_TINIT5_F0_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_09_TINIT5_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_09_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_09_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_10_REGOFF 0x28
#define HWIO_DDR_CTL_10_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_10_REGOFF)
#define HWIO_DDR_CTL_10_TINIT_F1_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_10_TINIT_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_10_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_10_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_11_REGOFF 0x2c
#define HWIO_DDR_CTL_11_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_11_REGOFF)
#define HWIO_DDR_CTL_11_TINIT3_F1_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_11_TINIT3_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_11_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_11_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_12_REGOFF 0x30
#define HWIO_DDR_CTL_12_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_12_REGOFF)
#define HWIO_DDR_CTL_12_TINIT4_F1_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_12_TINIT4_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_12_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_12_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_13_REGOFF 0x34
#define HWIO_DDR_CTL_13_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_13_REGOFF)
#define HWIO_DDR_CTL_13_TINIT5_F1_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_13_TINIT5_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_13_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_13_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_14_REGOFF 0x38
#define HWIO_DDR_CTL_14_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_14_REGOFF)
#define HWIO_DDR_CTL_14_TINIT_F2_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_14_TINIT_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_14_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_14_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_15_REGOFF 0x3c
#define HWIO_DDR_CTL_15_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_15_REGOFF)
#define HWIO_DDR_CTL_15_TINIT3_F2_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_15_TINIT3_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_15_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_15_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_16_REGOFF 0x40
#define HWIO_DDR_CTL_16_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_16_REGOFF)
#define HWIO_DDR_CTL_16_TINIT4_F2_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_16_TINIT4_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_16_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_16_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_17_REGOFF 0x44
#define HWIO_DDR_CTL_17_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_17_REGOFF)
#define HWIO_DDR_CTL_17_TINIT5_F2_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_17_TINIT5_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_17_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_17_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_18_REGOFF 0x48
#define HWIO_DDR_CTL_18_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_18_REGOFF)
#define HWIO_DDR_CTL_18_TINIT_F3_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_18_TINIT_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_18_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_18_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_19_REGOFF 0x4c
#define HWIO_DDR_CTL_19_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_19_REGOFF)
#define HWIO_DDR_CTL_19_TINIT3_F3_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_19_TINIT3_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_19_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_19_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_20_REGOFF 0x50
#define HWIO_DDR_CTL_20_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_20_REGOFF)
#define HWIO_DDR_CTL_20_TINIT4_F3_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_20_TINIT4_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_20_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_20_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_21_REGOFF 0x54
#define HWIO_DDR_CTL_21_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_21_REGOFF)
#define HWIO_DDR_CTL_21_TINIT5_F3_FLDMASK (0xffffff)
#define HWIO_DDR_CTL_21_TINIT5_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_21_NO_AUTO_MRR_INIT_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_21_NO_AUTO_MRR_INIT_FLDSHFT (24)
#define HWIO_DDR_CTL_21_RESERVED_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_21_RESERVED_FLDSHFT (25)

#define HWIO_DDR_CTL_22_REGOFF 0x58
#define HWIO_DDR_CTL_22_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_22_REGOFF)
#define HWIO_DDR_CTL_22_MRR_ERROR_STATUS_FLDMASK (0x3)
#define HWIO_DDR_CTL_22_MRR_ERROR_STATUS_FLDSHFT (0)
#define HWIO_DDR_CTL_22_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_CTL_22_RESERVED_FLDSHFT (2)
#define HWIO_DDR_CTL_22_DFI_INV_DATA_CS_FLDMASK (0x100)
#define HWIO_DDR_CTL_22_DFI_INV_DATA_CS_FLDSHFT (8)
#define HWIO_DDR_CTL_22_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_22_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_22_NO_MRW_BT_INIT_FLDMASK (0x10000)
#define HWIO_DDR_CTL_22_NO_MRW_BT_INIT_FLDSHFT (16)
#define HWIO_DDR_CTL_22_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_22_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_22_NO_MRW_INIT_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_22_NO_MRW_INIT_FLDSHFT (24)
#define HWIO_DDR_CTL_22_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_22_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_23_REGOFF 0x5c
#define HWIO_DDR_CTL_23_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_23_REGOFF)
#define HWIO_DDR_CTL_23_CDNS_INTRL0_FLDMASK (0x1)
#define HWIO_DDR_CTL_23_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_23_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_23_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_23_PHY_INDEP_TRAIN_MODE_FLDMASK (0x100)
#define HWIO_DDR_CTL_23_PHY_INDEP_TRAIN_MODE_FLDSHFT (8)
#define HWIO_DDR_CTL_23_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_23_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_23_DFIBUS_FREQ_INIT_FLDMASK (0x30000)
#define HWIO_DDR_CTL_23_DFIBUS_FREQ_INIT_FLDSHFT (16)
#define HWIO_DDR_CTL_23_CDNS_INTRL2_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_23_CDNS_INTRL2_FLDSHFT (18)
#define HWIO_DDR_CTL_23_DFIBUS_BOOT_FREQ_FLDMASK (0x3000000)
#define HWIO_DDR_CTL_23_DFIBUS_BOOT_FREQ_FLDSHFT (24)
#define HWIO_DDR_CTL_23_CDNS_INTRL3_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_23_CDNS_INTRL3_FLDSHFT (26)

#define HWIO_DDR_CTL_24_REGOFF 0x60
#define HWIO_DDR_CTL_24_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_24_REGOFF)
#define HWIO_DDR_CTL_24_DFIBUS_FREQ_F0_FLDMASK (0x1f)
#define HWIO_DDR_CTL_24_DFIBUS_FREQ_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_24_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_CTL_24_RESERVED_FLDSHFT (5)
#define HWIO_DDR_CTL_24_DFIBUS_FREQ_F1_FLDMASK (0x1f00)
#define HWIO_DDR_CTL_24_DFIBUS_FREQ_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_24_CDNS_INTRL1_FLDMASK (0xe000)
#define HWIO_DDR_CTL_24_CDNS_INTRL1_FLDSHFT (13)
#define HWIO_DDR_CTL_24_DFIBUS_FREQ_F2_FLDMASK (0x1f0000)
#define HWIO_DDR_CTL_24_DFIBUS_FREQ_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_24_CDNS_INTRL2_FLDMASK (0xe00000)
#define HWIO_DDR_CTL_24_CDNS_INTRL2_FLDSHFT (21)
#define HWIO_DDR_CTL_24_DFIBUS_FREQ_F3_FLDMASK (0x1f000000)
#define HWIO_DDR_CTL_24_DFIBUS_FREQ_F3_FLDSHFT (24)
#define HWIO_DDR_CTL_24_CDNS_INTRL3_FLDMASK (0xe0000000)
#define HWIO_DDR_CTL_24_CDNS_INTRL3_FLDSHFT (29)

#define HWIO_DDR_CTL_25_REGOFF 0x64
#define HWIO_DDR_CTL_25_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_25_REGOFF)
#define HWIO_DDR_CTL_25_TRST_PWRON_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_25_TRST_PWRON_FLDSHFT (0)

#define HWIO_DDR_CTL_26_REGOFF 0x68
#define HWIO_DDR_CTL_26_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_26_REGOFF)
#define HWIO_DDR_CTL_26_CKE_INACTIVE_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_26_CKE_INACTIVE_FLDSHFT (0)

#define HWIO_DDR_CTL_27_REGOFF 0x6c
#define HWIO_DDR_CTL_27_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_27_REGOFF)
#define HWIO_DDR_CTL_27_CASLAT_LIN_F0_FLDMASK (0x7f)
#define HWIO_DDR_CTL_27_CASLAT_LIN_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_27_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_CTL_27_RESERVED_FLDSHFT (7)
#define HWIO_DDR_CTL_27_WRLAT_F0_FLDMASK (0x7f00)
#define HWIO_DDR_CTL_27_WRLAT_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_27_CDNS_INTRL1_FLDMASK (0x8000)
#define HWIO_DDR_CTL_27_CDNS_INTRL1_FLDSHFT (15)
#define HWIO_DDR_CTL_27_CASLAT_LIN_F1_FLDMASK (0x7f0000)
#define HWIO_DDR_CTL_27_CASLAT_LIN_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_27_CDNS_INTRL2_FLDMASK (0x800000)
#define HWIO_DDR_CTL_27_CDNS_INTRL2_FLDSHFT (23)
#define HWIO_DDR_CTL_27_WRLAT_F1_FLDMASK (0x7f000000)
#define HWIO_DDR_CTL_27_WRLAT_F1_FLDSHFT (24)
#define HWIO_DDR_CTL_27_CDNS_INTRL3_FLDMASK (0x80000000)
#define HWIO_DDR_CTL_27_CDNS_INTRL3_FLDSHFT (31)

#define HWIO_DDR_CTL_28_REGOFF 0x70
#define HWIO_DDR_CTL_28_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_28_REGOFF)
#define HWIO_DDR_CTL_28_CASLAT_LIN_F2_FLDMASK (0x7f)
#define HWIO_DDR_CTL_28_CASLAT_LIN_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_28_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_CTL_28_RESERVED_FLDSHFT (7)
#define HWIO_DDR_CTL_28_WRLAT_F2_FLDMASK (0x7f00)
#define HWIO_DDR_CTL_28_WRLAT_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_28_CDNS_INTRL1_FLDMASK (0x8000)
#define HWIO_DDR_CTL_28_CDNS_INTRL1_FLDSHFT (15)
#define HWIO_DDR_CTL_28_CASLAT_LIN_F3_FLDMASK (0x7f0000)
#define HWIO_DDR_CTL_28_CASLAT_LIN_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_28_CDNS_INTRL2_FLDMASK (0x800000)
#define HWIO_DDR_CTL_28_CDNS_INTRL2_FLDSHFT (23)
#define HWIO_DDR_CTL_28_WRLAT_F3_FLDMASK (0x7f000000)
#define HWIO_DDR_CTL_28_WRLAT_F3_FLDSHFT (24)
#define HWIO_DDR_CTL_28_CDNS_INTRL3_FLDMASK (0x80000000)
#define HWIO_DDR_CTL_28_CDNS_INTRL3_FLDSHFT (31)

#define HWIO_DDR_CTL_29_REGOFF 0x74
#define HWIO_DDR_CTL_29_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_29_REGOFF)
#define HWIO_DDR_CTL_29_TBST_INT_INTERVAL_FLDMASK (0x7)
#define HWIO_DDR_CTL_29_TBST_INT_INTERVAL_FLDSHFT (0)
#define HWIO_DDR_CTL_29_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_CTL_29_RESERVED_FLDSHFT (3)
#define HWIO_DDR_CTL_29_TCCD_FLDMASK (0x1f00)
#define HWIO_DDR_CTL_29_TCCD_FLDSHFT (8)
#define HWIO_DDR_CTL_29_CDNS_INTRL1_FLDMASK (0xe000)
#define HWIO_DDR_CTL_29_CDNS_INTRL1_FLDSHFT (13)
#define HWIO_DDR_CTL_29_TRRD_F0_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_29_TRRD_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_29_TRC_F0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_29_TRC_F0_FLDSHFT (24)

#define HWIO_DDR_CTL_30_REGOFF 0x78
#define HWIO_DDR_CTL_30_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_30_REGOFF)
#define HWIO_DDR_CTL_30_TRAS_MIN_F0_FLDMASK (0xff)
#define HWIO_DDR_CTL_30_TRAS_MIN_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_30_TWTR_F0_FLDMASK (0x3f00)
#define HWIO_DDR_CTL_30_TWTR_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_30_RESERVED_FLDMASK (0xc000)
#define HWIO_DDR_CTL_30_RESERVED_FLDSHFT (14)
#define HWIO_DDR_CTL_30_TRP_F0_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_30_TRP_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_30_TFAW_F0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_30_TFAW_F0_FLDSHFT (24)

#define HWIO_DDR_CTL_31_REGOFF 0x7c
#define HWIO_DDR_CTL_31_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_31_REGOFF)
#define HWIO_DDR_CTL_31_TRRD_F1_FLDMASK (0xff)
#define HWIO_DDR_CTL_31_TRRD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_31_TRC_F1_FLDMASK (0xff00)
#define HWIO_DDR_CTL_31_TRC_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_31_TRAS_MIN_F1_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_31_TRAS_MIN_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_31_TWTR_F1_FLDMASK (0x3f000000)
#define HWIO_DDR_CTL_31_TWTR_F1_FLDSHFT (24)
#define HWIO_DDR_CTL_31_RESERVED_FLDMASK (0xc0000000)
#define HWIO_DDR_CTL_31_RESERVED_FLDSHFT (30)

#define HWIO_DDR_CTL_32_REGOFF 0x80
#define HWIO_DDR_CTL_32_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_32_REGOFF)
#define HWIO_DDR_CTL_32_TRP_F1_FLDMASK (0xff)
#define HWIO_DDR_CTL_32_TRP_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_32_TFAW_F1_FLDMASK (0xff00)
#define HWIO_DDR_CTL_32_TFAW_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_32_TRRD_F2_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_32_TRRD_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_32_TRC_F2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_32_TRC_F2_FLDSHFT (24)

#define HWIO_DDR_CTL_33_REGOFF 0x84
#define HWIO_DDR_CTL_33_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_33_REGOFF)
#define HWIO_DDR_CTL_33_TRAS_MIN_F2_FLDMASK (0xff)
#define HWIO_DDR_CTL_33_TRAS_MIN_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_33_TWTR_F2_FLDMASK (0x3f00)
#define HWIO_DDR_CTL_33_TWTR_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_33_RESERVED_FLDMASK (0xc000)
#define HWIO_DDR_CTL_33_RESERVED_FLDSHFT (14)
#define HWIO_DDR_CTL_33_TRP_F2_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_33_TRP_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_33_TFAW_F2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_33_TFAW_F2_FLDSHFT (24)

#define HWIO_DDR_CTL_34_REGOFF 0x88
#define HWIO_DDR_CTL_34_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_34_REGOFF)
#define HWIO_DDR_CTL_34_TRRD_F3_FLDMASK (0xff)
#define HWIO_DDR_CTL_34_TRRD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_34_TRC_F3_FLDMASK (0xff00)
#define HWIO_DDR_CTL_34_TRC_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_34_TRAS_MIN_F3_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_34_TRAS_MIN_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_34_TWTR_F3_FLDMASK (0x3f000000)
#define HWIO_DDR_CTL_34_TWTR_F3_FLDSHFT (24)
#define HWIO_DDR_CTL_34_RESERVED_FLDMASK (0xc0000000)
#define HWIO_DDR_CTL_34_RESERVED_FLDSHFT (30)

#define HWIO_DDR_CTL_35_REGOFF 0x8c
#define HWIO_DDR_CTL_35_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_35_REGOFF)
#define HWIO_DDR_CTL_35_TRP_F3_FLDMASK (0xff)
#define HWIO_DDR_CTL_35_TRP_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_35_TFAW_F3_FLDMASK (0xff00)
#define HWIO_DDR_CTL_35_TFAW_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_35_TCCDMW_FLDMASK (0x3f0000)
#define HWIO_DDR_CTL_35_TCCDMW_FLDSHFT (16)
#define HWIO_DDR_CTL_35_RESERVED_FLDMASK (0xc00000)
#define HWIO_DDR_CTL_35_RESERVED_FLDSHFT (22)
#define HWIO_DDR_CTL_35_TRTP_F0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_35_TRTP_F0_FLDSHFT (24)

#define HWIO_DDR_CTL_36_REGOFF 0x90
#define HWIO_DDR_CTL_36_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_36_REGOFF)
#define HWIO_DDR_CTL_36_TMRD_F0_FLDMASK (0xff)
#define HWIO_DDR_CTL_36_TMRD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_36_TMOD_F0_FLDMASK (0xff00)
#define HWIO_DDR_CTL_36_TMOD_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_36_OBSOLETE2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_36_OBSOLETE2_FLDSHFT (16)

#define HWIO_DDR_CTL_37_REGOFF 0x94
#define HWIO_DDR_CTL_37_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_37_REGOFF)
#define HWIO_DDR_CTL_37_TRAS_MAX_F0_FLDMASK (0x1ffff)
#define HWIO_DDR_CTL_37_TRAS_MAX_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_37_RESERVED_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_37_RESERVED_FLDSHFT (17)
#define HWIO_DDR_CTL_37_TCKE_F0_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_37_TCKE_F0_FLDSHFT (24)
#define HWIO_DDR_CTL_37_CDNS_INTRL1_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_37_CDNS_INTRL1_FLDSHFT (28)

#define HWIO_DDR_CTL_38_REGOFF 0x98
#define HWIO_DDR_CTL_38_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_38_REGOFF)
#define HWIO_DDR_CTL_38_TCKESR_F0_FLDMASK (0xff)
#define HWIO_DDR_CTL_38_TCKESR_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_38_TRTP_F1_FLDMASK (0xff00)
#define HWIO_DDR_CTL_38_TRTP_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_38_TMRD_F1_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_38_TMRD_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_38_TMOD_F1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_38_TMOD_F1_FLDSHFT (24)

#define HWIO_DDR_CTL_39_REGOFF 0x9c
#define HWIO_DDR_CTL_39_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_39_REGOFF)
#define HWIO_DDR_CTL_39_TRAS_MAX_F1_FLDMASK (0x1ffff)
#define HWIO_DDR_CTL_39_TRAS_MAX_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_39_RESERVED_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_39_RESERVED_FLDSHFT (17)
#define HWIO_DDR_CTL_39_TCKE_F1_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_39_TCKE_F1_FLDSHFT (24)
#define HWIO_DDR_CTL_39_CDNS_INTRL1_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_39_CDNS_INTRL1_FLDSHFT (28)

#define HWIO_DDR_CTL_40_REGOFF 0xa0
#define HWIO_DDR_CTL_40_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_40_REGOFF)
#define HWIO_DDR_CTL_40_TCKESR_F1_FLDMASK (0xff)
#define HWIO_DDR_CTL_40_TCKESR_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_40_TRTP_F2_FLDMASK (0xff00)
#define HWIO_DDR_CTL_40_TRTP_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_40_TMRD_F2_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_40_TMRD_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_40_TMOD_F2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_40_TMOD_F2_FLDSHFT (24)

#define HWIO_DDR_CTL_41_REGOFF 0xa4
#define HWIO_DDR_CTL_41_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_41_REGOFF)
#define HWIO_DDR_CTL_41_TRAS_MAX_F2_FLDMASK (0x1ffff)
#define HWIO_DDR_CTL_41_TRAS_MAX_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_41_RESERVED_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_41_RESERVED_FLDSHFT (17)
#define HWIO_DDR_CTL_41_TCKE_F2_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_41_TCKE_F2_FLDSHFT (24)
#define HWIO_DDR_CTL_41_CDNS_INTRL1_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_41_CDNS_INTRL1_FLDSHFT (28)

#define HWIO_DDR_CTL_42_REGOFF 0xa8
#define HWIO_DDR_CTL_42_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_42_REGOFF)
#define HWIO_DDR_CTL_42_TCKESR_F2_FLDMASK (0xff)
#define HWIO_DDR_CTL_42_TCKESR_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_42_TRTP_F3_FLDMASK (0xff00)
#define HWIO_DDR_CTL_42_TRTP_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_42_TMRD_F3_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_42_TMRD_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_42_TMOD_F3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_42_TMOD_F3_FLDSHFT (24)

#define HWIO_DDR_CTL_43_REGOFF 0xac
#define HWIO_DDR_CTL_43_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_43_REGOFF)
#define HWIO_DDR_CTL_43_TRAS_MAX_F3_FLDMASK (0x1ffff)
#define HWIO_DDR_CTL_43_TRAS_MAX_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_43_RESERVED_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_43_RESERVED_FLDSHFT (17)
#define HWIO_DDR_CTL_43_TCKE_F3_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_43_TCKE_F3_FLDSHFT (24)
#define HWIO_DDR_CTL_43_CDNS_INTRL1_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_43_CDNS_INTRL1_FLDSHFT (28)

#define HWIO_DDR_CTL_44_REGOFF 0xb0
#define HWIO_DDR_CTL_44_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_44_REGOFF)
#define HWIO_DDR_CTL_44_TCKESR_F3_FLDMASK (0xff)
#define HWIO_DDR_CTL_44_TCKESR_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_44_TPPD_FLDMASK (0x700)
#define HWIO_DDR_CTL_44_TPPD_FLDSHFT (8)
#define HWIO_DDR_CTL_44_RESERVED_FLDMASK (0xf800)
#define HWIO_DDR_CTL_44_RESERVED_FLDSHFT (11)
#define HWIO_DDR_CTL_44_CDNS_INTRL2_FLDMASK (0x70000)
#define HWIO_DDR_CTL_44_CDNS_INTRL2_FLDSHFT (16)
#define HWIO_DDR_CTL_44_CDNS_INTRL1_FLDMASK (0xf80000)
#define HWIO_DDR_CTL_44_CDNS_INTRL1_FLDSHFT (19)
#define HWIO_DDR_CTL_44_CDNS_INTRL3_FLDMASK (0x7000000)
#define HWIO_DDR_CTL_44_CDNS_INTRL3_FLDSHFT (24)
#define HWIO_DDR_CTL_44_RESERVED4_FLDMASK (0xf8000000)
#define HWIO_DDR_CTL_44_RESERVED4_FLDSHFT (27)

#define HWIO_DDR_CTL_45_REGOFF 0xb4
#define HWIO_DDR_CTL_45_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_45_REGOFF)
#define HWIO_DDR_CTL_45_WRITEINTERP_FLDMASK (0x1)
#define HWIO_DDR_CTL_45_WRITEINTERP_FLDSHFT (0)
#define HWIO_DDR_CTL_45_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_45_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_45_TRCD_F0_FLDMASK (0xff00)
#define HWIO_DDR_CTL_45_TRCD_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_45_TWR_F0_FLDMASK (0x3f0000)
#define HWIO_DDR_CTL_45_TWR_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_45_CDNS_INTRL1_FLDMASK (0xc00000)
#define HWIO_DDR_CTL_45_CDNS_INTRL1_FLDSHFT (22)
#define HWIO_DDR_CTL_45_TRCD_F1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_45_TRCD_F1_FLDSHFT (24)

#define HWIO_DDR_CTL_46_REGOFF 0xb8
#define HWIO_DDR_CTL_46_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_46_REGOFF)
#define HWIO_DDR_CTL_46_TWR_F1_FLDMASK (0x3f)
#define HWIO_DDR_CTL_46_TWR_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_46_RESERVED_FLDMASK (0xc0)
#define HWIO_DDR_CTL_46_RESERVED_FLDSHFT (6)
#define HWIO_DDR_CTL_46_TRCD_F2_FLDMASK (0xff00)
#define HWIO_DDR_CTL_46_TRCD_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_46_TWR_F2_FLDMASK (0x3f0000)
#define HWIO_DDR_CTL_46_TWR_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_46_CDNS_INTRL1_FLDMASK (0xc00000)
#define HWIO_DDR_CTL_46_CDNS_INTRL1_FLDSHFT (22)
#define HWIO_DDR_CTL_46_TRCD_F3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_46_TRCD_F3_FLDSHFT (24)

#define HWIO_DDR_CTL_47_REGOFF 0xbc
#define HWIO_DDR_CTL_47_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_47_REGOFF)
#define HWIO_DDR_CTL_47_TWR_F3_FLDMASK (0x3f)
#define HWIO_DDR_CTL_47_TWR_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_47_RESERVED_FLDMASK (0xc0)
#define HWIO_DDR_CTL_47_RESERVED_FLDSHFT (6)
#define HWIO_DDR_CTL_47_TMRR_FLDMASK (0xf00)
#define HWIO_DDR_CTL_47_TMRR_FLDSHFT (8)
#define HWIO_DDR_CTL_47_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_47_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_47_TCACKEL_FLDMASK (0x1f0000)
#define HWIO_DDR_CTL_47_TCACKEL_FLDSHFT (16)
#define HWIO_DDR_CTL_47_CDNS_INTRL2_FLDMASK (0xe00000)
#define HWIO_DDR_CTL_47_CDNS_INTRL2_FLDSHFT (21)
#define HWIO_DDR_CTL_47_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_47_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_CTL_48_REGOFF 0xc0
#define HWIO_DDR_CTL_48_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_48_REGOFF)
#define HWIO_DDR_CTL_48_TCAENT_FLDMASK (0x3ff)
#define HWIO_DDR_CTL_48_TCAENT_FLDSHFT (0)
#define HWIO_DDR_CTL_48_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_48_RESERVED_FLDSHFT (10)
#define HWIO_DDR_CTL_48_TCAMRD_FLDMASK (0x3f0000)
#define HWIO_DDR_CTL_48_TCAMRD_FLDSHFT (16)
#define HWIO_DDR_CTL_48_CDNS_INTRL1_FLDMASK (0xc00000)
#define HWIO_DDR_CTL_48_CDNS_INTRL1_FLDSHFT (22)
#define HWIO_DDR_CTL_48_TCAEXT_FLDMASK (0x1f000000)
#define HWIO_DDR_CTL_48_TCAEXT_FLDSHFT (24)
#define HWIO_DDR_CTL_48_CDNS_INTRL2_FLDMASK (0xe0000000)
#define HWIO_DDR_CTL_48_CDNS_INTRL2_FLDSHFT (29)

#define HWIO_DDR_CTL_49_REGOFF 0xc4
#define HWIO_DDR_CTL_49_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_49_REGOFF)
#define HWIO_DDR_CTL_49_TCACKEH_FLDMASK (0x1f)
#define HWIO_DDR_CTL_49_TCACKEH_FLDSHFT (0)
#define HWIO_DDR_CTL_49_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_CTL_49_RESERVED_FLDSHFT (5)
#define HWIO_DDR_CTL_49_TMRZ_F0_FLDMASK (0x1f00)
#define HWIO_DDR_CTL_49_TMRZ_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_49_CDNS_INTRL1_FLDMASK (0xe000)
#define HWIO_DDR_CTL_49_CDNS_INTRL1_FLDSHFT (13)
#define HWIO_DDR_CTL_49_TMRZ_F1_FLDMASK (0x1f0000)
#define HWIO_DDR_CTL_49_TMRZ_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_49_CDNS_INTRL2_FLDMASK (0xe00000)
#define HWIO_DDR_CTL_49_CDNS_INTRL2_FLDSHFT (21)
#define HWIO_DDR_CTL_49_TMRZ_F2_FLDMASK (0x1f000000)
#define HWIO_DDR_CTL_49_TMRZ_F2_FLDSHFT (24)
#define HWIO_DDR_CTL_49_CDNS_INTRL3_FLDMASK (0xe0000000)
#define HWIO_DDR_CTL_49_CDNS_INTRL3_FLDSHFT (29)

#define HWIO_DDR_CTL_50_REGOFF 0xc8
#define HWIO_DDR_CTL_50_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_50_REGOFF)
#define HWIO_DDR_CTL_50_TMRZ_F3_FLDMASK (0x1f)
#define HWIO_DDR_CTL_50_TMRZ_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_50_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_CTL_50_RESERVED_FLDSHFT (5)
#define HWIO_DDR_CTL_50_AP_FLDMASK (0x100)
#define HWIO_DDR_CTL_50_AP_FLDSHFT (8)
#define HWIO_DDR_CTL_50_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_50_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_50_CONCURRENTAP_FLDMASK (0x10000)
#define HWIO_DDR_CTL_50_CONCURRENTAP_FLDSHFT (16)
#define HWIO_DDR_CTL_50_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_50_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_50_TRAS_LOCKOUT_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_50_TRAS_LOCKOUT_FLDSHFT (24)
#define HWIO_DDR_CTL_50_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_50_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_51_REGOFF 0xcc
#define HWIO_DDR_CTL_51_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_51_REGOFF)
#define HWIO_DDR_CTL_51_TDAL_F0_FLDMASK (0xff)
#define HWIO_DDR_CTL_51_TDAL_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_51_TDAL_F1_FLDMASK (0xff00)
#define HWIO_DDR_CTL_51_TDAL_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_51_TDAL_F2_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_51_TDAL_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_51_TDAL_F3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_51_TDAL_F3_FLDSHFT (24)

#define HWIO_DDR_CTL_52_REGOFF 0xd0
#define HWIO_DDR_CTL_52_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_52_REGOFF)
#define HWIO_DDR_CTL_52_BSTLEN_FLDMASK (0x1f)
#define HWIO_DDR_CTL_52_BSTLEN_FLDSHFT (0)
#define HWIO_DDR_CTL_52_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_CTL_52_RESERVED_FLDSHFT (5)
#define HWIO_DDR_CTL_52_TRP_AB_F0_FLDMASK (0xff00)
#define HWIO_DDR_CTL_52_TRP_AB_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_52_TRP_AB_F1_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_52_TRP_AB_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_52_TRP_AB_F2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_52_TRP_AB_F2_FLDSHFT (24)

#define HWIO_DDR_CTL_53_REGOFF 0xd4
#define HWIO_DDR_CTL_53_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_53_REGOFF)
#define HWIO_DDR_CTL_53_TRP_AB_F3_FLDMASK (0xff)
#define HWIO_DDR_CTL_53_TRP_AB_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_53_REG_DIMM_ENABLE_FLDMASK (0x100)
#define HWIO_DDR_CTL_53_REG_DIMM_ENABLE_FLDSHFT (8)
#define HWIO_DDR_CTL_53_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_53_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_53_OPTIMAL_RMODW_EN_FLDMASK (0x10000)
#define HWIO_DDR_CTL_53_OPTIMAL_RMODW_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_53_CDNS_INTRL1_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_53_CDNS_INTRL1_FLDSHFT (17)
#define HWIO_DDR_CTL_53_CDNS_INTRL3_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_53_CDNS_INTRL3_FLDSHFT (24)
#define HWIO_DDR_CTL_53_CDNS_INTRL2_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_53_CDNS_INTRL2_FLDSHFT (25)

#define HWIO_DDR_CTL_54_REGOFF 0xd8
#define HWIO_DDR_CTL_54_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_54_REGOFF)
#define HWIO_DDR_CTL_54_NO_MEMORY_DM_FLDMASK (0x1)
#define HWIO_DDR_CTL_54_NO_MEMORY_DM_FLDSHFT (0)
#define HWIO_DDR_CTL_54_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_54_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_54_AREFRESH_FLDMASK (0x100)
#define HWIO_DDR_CTL_54_AREFRESH_FLDSHFT (8)
#define HWIO_DDR_CTL_54_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_54_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_54_CDNS_INTRL2_FLDMASK (0x10000)
#define HWIO_DDR_CTL_54_CDNS_INTRL2_FLDSHFT (16)
#define HWIO_DDR_CTL_54_CDNS_INTRL3_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_54_CDNS_INTRL3_FLDSHFT (17)
#define HWIO_DDR_CTL_54_TREF_ENABLE_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_54_TREF_ENABLE_FLDSHFT (24)
#define HWIO_DDR_CTL_54_RESERVED4_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_54_RESERVED4_FLDSHFT (25)

#define HWIO_DDR_CTL_55_REGOFF 0xdc
#define HWIO_DDR_CTL_55_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_55_REGOFF)
#define HWIO_DDR_CTL_55_CDNS_INTRL0_FLDMASK (0x7)
#define HWIO_DDR_CTL_55_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_55_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_CTL_55_RESERVED_FLDSHFT (3)
#define HWIO_DDR_CTL_55_TRFC_F0_FLDMASK (0x3ff00)
#define HWIO_DDR_CTL_55_TRFC_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_55_CDNS_INTRL1_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_55_CDNS_INTRL1_FLDSHFT (18)
#define HWIO_DDR_CTL_55_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_55_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_56_REGOFF 0xe0
#define HWIO_DDR_CTL_56_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_56_REGOFF)
#define HWIO_DDR_CTL_56_TREF_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_56_TREF_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_56_TRFC_F1_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_56_TRFC_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_56_RESERVED_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_56_RESERVED_FLDSHFT (26)

#define HWIO_DDR_CTL_57_REGOFF 0xe4
#define HWIO_DDR_CTL_57_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_57_REGOFF)
#define HWIO_DDR_CTL_57_TREF_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_57_TREF_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_57_TRFC_F2_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_57_TRFC_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_57_RESERVED_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_57_RESERVED_FLDSHFT (26)

#define HWIO_DDR_CTL_58_REGOFF 0xe8
#define HWIO_DDR_CTL_58_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_58_REGOFF)
#define HWIO_DDR_CTL_58_TREF_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_58_TREF_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_58_TRFC_F3_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_58_TRFC_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_58_RESERVED_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_58_RESERVED_FLDSHFT (26)

#define HWIO_DDR_CTL_59_REGOFF 0xec
#define HWIO_DDR_CTL_59_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_59_REGOFF)
#define HWIO_DDR_CTL_59_TREF_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_59_TREF_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_59_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_59_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_CTL_60_REGOFF 0xf0
#define HWIO_DDR_CTL_60_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_60_REGOFF)
#define HWIO_DDR_CTL_60_TPDEX_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_60_TPDEX_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_60_TPDEX_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_60_TPDEX_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_61_REGOFF 0xf4
#define HWIO_DDR_CTL_61_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_61_REGOFF)
#define HWIO_DDR_CTL_61_TPDEX_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_61_TPDEX_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_61_TPDEX_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_61_TPDEX_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_62_REGOFF 0xf8
#define HWIO_DDR_CTL_62_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_62_REGOFF)
#define HWIO_DDR_CTL_62_TMRRI_F0_FLDMASK (0xff)
#define HWIO_DDR_CTL_62_TMRRI_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_62_TMRRI_F1_FLDMASK (0xff00)
#define HWIO_DDR_CTL_62_TMRRI_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_62_TMRRI_F2_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_62_TMRRI_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_62_TMRRI_F3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_62_TMRRI_F3_FLDSHFT (24)

#define HWIO_DDR_CTL_63_REGOFF 0xfc
#define HWIO_DDR_CTL_63_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_63_REGOFF)
#define HWIO_DDR_CTL_63_TCSCKE_F0_FLDMASK (0xf)
#define HWIO_DDR_CTL_63_TCSCKE_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_63_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_63_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_63_TCKELCS_F0_FLDMASK (0xf00)
#define HWIO_DDR_CTL_63_TCKELCS_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_63_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_63_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_63_TCKEHCS_F0_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_63_TCKEHCS_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_63_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_63_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_63_TMRWCKEL_F0_FLDMASK (0x1f000000)
#define HWIO_DDR_CTL_63_TMRWCKEL_F0_FLDSHFT (24)
#define HWIO_DDR_CTL_63_CDNS_INTRL3_FLDMASK (0xe0000000)
#define HWIO_DDR_CTL_63_CDNS_INTRL3_FLDSHFT (29)

#define HWIO_DDR_CTL_64_REGOFF 0x100
#define HWIO_DDR_CTL_64_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_64_REGOFF)
#define HWIO_DDR_CTL_64_TZQCKE_F0_FLDMASK (0xf)
#define HWIO_DDR_CTL_64_TZQCKE_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_64_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_64_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_64_CA_DEFAULT_VAL_F0_FLDMASK (0x100)
#define HWIO_DDR_CTL_64_CA_DEFAULT_VAL_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_64_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_64_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_64_TCSCKE_F1_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_64_TCSCKE_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_64_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_64_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_64_TCKELCS_F1_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_64_TCKELCS_F1_FLDSHFT (24)
#define HWIO_DDR_CTL_64_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_64_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_65_REGOFF 0x104
#define HWIO_DDR_CTL_65_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_65_REGOFF)
#define HWIO_DDR_CTL_65_TCKEHCS_F1_FLDMASK (0xf)
#define HWIO_DDR_CTL_65_TCKEHCS_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_65_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_65_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_65_TMRWCKEL_F1_FLDMASK (0x1f00)
#define HWIO_DDR_CTL_65_TMRWCKEL_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_65_CDNS_INTRL1_FLDMASK (0xe000)
#define HWIO_DDR_CTL_65_CDNS_INTRL1_FLDSHFT (13)
#define HWIO_DDR_CTL_65_TZQCKE_F1_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_65_TZQCKE_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_65_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_65_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_65_CA_DEFAULT_VAL_F1_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_65_CA_DEFAULT_VAL_F1_FLDSHFT (24)
#define HWIO_DDR_CTL_65_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_65_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_66_REGOFF 0x108
#define HWIO_DDR_CTL_66_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_66_REGOFF)
#define HWIO_DDR_CTL_66_TCSCKE_F2_FLDMASK (0xf)
#define HWIO_DDR_CTL_66_TCSCKE_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_66_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_66_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_66_TCKELCS_F2_FLDMASK (0xf00)
#define HWIO_DDR_CTL_66_TCKELCS_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_66_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_66_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_66_TCKEHCS_F2_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_66_TCKEHCS_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_66_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_66_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_66_TMRWCKEL_F2_FLDMASK (0x1f000000)
#define HWIO_DDR_CTL_66_TMRWCKEL_F2_FLDSHFT (24)
#define HWIO_DDR_CTL_66_CDNS_INTRL3_FLDMASK (0xe0000000)
#define HWIO_DDR_CTL_66_CDNS_INTRL3_FLDSHFT (29)

#define HWIO_DDR_CTL_67_REGOFF 0x10c
#define HWIO_DDR_CTL_67_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_67_REGOFF)
#define HWIO_DDR_CTL_67_TZQCKE_F2_FLDMASK (0xf)
#define HWIO_DDR_CTL_67_TZQCKE_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_67_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_67_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_67_CA_DEFAULT_VAL_F2_FLDMASK (0x100)
#define HWIO_DDR_CTL_67_CA_DEFAULT_VAL_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_67_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_67_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_67_TCSCKE_F3_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_67_TCSCKE_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_67_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_67_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_67_TCKELCS_F3_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_67_TCKELCS_F3_FLDSHFT (24)
#define HWIO_DDR_CTL_67_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_67_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_68_REGOFF 0x110
#define HWIO_DDR_CTL_68_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_68_REGOFF)
#define HWIO_DDR_CTL_68_TCKEHCS_F3_FLDMASK (0xf)
#define HWIO_DDR_CTL_68_TCKEHCS_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_68_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_68_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_68_TMRWCKEL_F3_FLDMASK (0x1f00)
#define HWIO_DDR_CTL_68_TMRWCKEL_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_68_CDNS_INTRL1_FLDMASK (0xe000)
#define HWIO_DDR_CTL_68_CDNS_INTRL1_FLDSHFT (13)
#define HWIO_DDR_CTL_68_TZQCKE_F3_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_68_TZQCKE_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_68_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_68_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_68_CA_DEFAULT_VAL_F3_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_68_CA_DEFAULT_VAL_F3_FLDSHFT (24)
#define HWIO_DDR_CTL_68_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_68_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_69_REGOFF 0x114
#define HWIO_DDR_CTL_69_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_69_REGOFF)
#define HWIO_DDR_CTL_69_TXSR_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_69_TXSR_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_69_TXSNR_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_69_TXSNR_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_70_REGOFF 0x118
#define HWIO_DDR_CTL_70_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_70_REGOFF)
#define HWIO_DDR_CTL_70_TXSR_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_70_TXSR_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_70_TXSNR_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_70_TXSNR_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_71_REGOFF 0x11c
#define HWIO_DDR_CTL_71_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_71_REGOFF)
#define HWIO_DDR_CTL_71_TXSR_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_71_TXSR_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_71_TXSNR_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_71_TXSNR_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_72_REGOFF 0x120
#define HWIO_DDR_CTL_72_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_72_REGOFF)
#define HWIO_DDR_CTL_72_TXSR_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_72_TXSR_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_72_TXSNR_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_72_TXSNR_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_73_REGOFF 0x124
#define HWIO_DDR_CTL_73_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_73_REGOFF)
#define HWIO_DDR_CTL_73_TCKELCMD_F0_FLDMASK (0xf)
#define HWIO_DDR_CTL_73_TCKELCMD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_73_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_73_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_73_TCKEHCMD_F0_FLDMASK (0xf00)
#define HWIO_DDR_CTL_73_TCKEHCMD_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_73_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_73_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_73_TCKCKEL_F0_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_73_TCKCKEL_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_73_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_73_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_73_TSR_F0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_73_TSR_F0_FLDSHFT (24)

#define HWIO_DDR_CTL_74_REGOFF 0x128
#define HWIO_DDR_CTL_74_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_74_REGOFF)
#define HWIO_DDR_CTL_74_TESCKE_F0_FLDMASK (0x7)
#define HWIO_DDR_CTL_74_TESCKE_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_74_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_CTL_74_RESERVED_FLDSHFT (3)
#define HWIO_DDR_CTL_74_TCKELPD_F0_FLDMASK (0xf00)
#define HWIO_DDR_CTL_74_TCKELPD_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_74_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_74_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_74_TCSCKEH_F0_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_74_TCSCKEH_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_74_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_74_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_74_TCMDCKE_F0_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_74_TCMDCKE_F0_FLDSHFT (24)
#define HWIO_DDR_CTL_74_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_74_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_75_REGOFF 0x12c
#define HWIO_DDR_CTL_75_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_75_REGOFF)
#define HWIO_DDR_CTL_75_TCKELCMD_F1_FLDMASK (0xf)
#define HWIO_DDR_CTL_75_TCKELCMD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_75_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_75_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_75_TCKEHCMD_F1_FLDMASK (0xf00)
#define HWIO_DDR_CTL_75_TCKEHCMD_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_75_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_75_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_75_TCKCKEL_F1_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_75_TCKCKEL_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_75_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_75_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_75_TSR_F1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_75_TSR_F1_FLDSHFT (24)

#define HWIO_DDR_CTL_76_REGOFF 0x130
#define HWIO_DDR_CTL_76_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_76_REGOFF)
#define HWIO_DDR_CTL_76_TESCKE_F1_FLDMASK (0x7)
#define HWIO_DDR_CTL_76_TESCKE_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_76_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_CTL_76_RESERVED_FLDSHFT (3)
#define HWIO_DDR_CTL_76_TCKELPD_F1_FLDMASK (0xf00)
#define HWIO_DDR_CTL_76_TCKELPD_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_76_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_76_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_76_TCSCKEH_F1_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_76_TCSCKEH_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_76_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_76_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_76_TCMDCKE_F1_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_76_TCMDCKE_F1_FLDSHFT (24)
#define HWIO_DDR_CTL_76_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_76_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_77_REGOFF 0x134
#define HWIO_DDR_CTL_77_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_77_REGOFF)
#define HWIO_DDR_CTL_77_TCKELCMD_F2_FLDMASK (0xf)
#define HWIO_DDR_CTL_77_TCKELCMD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_77_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_77_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_77_TCKEHCMD_F2_FLDMASK (0xf00)
#define HWIO_DDR_CTL_77_TCKEHCMD_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_77_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_77_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_77_TCKCKEL_F2_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_77_TCKCKEL_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_77_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_77_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_77_TSR_F2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_77_TSR_F2_FLDSHFT (24)

#define HWIO_DDR_CTL_78_REGOFF 0x138
#define HWIO_DDR_CTL_78_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_78_REGOFF)
#define HWIO_DDR_CTL_78_TESCKE_F2_FLDMASK (0x7)
#define HWIO_DDR_CTL_78_TESCKE_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_78_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_CTL_78_RESERVED_FLDSHFT (3)
#define HWIO_DDR_CTL_78_TCKELPD_F2_FLDMASK (0xf00)
#define HWIO_DDR_CTL_78_TCKELPD_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_78_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_78_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_78_TCSCKEH_F2_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_78_TCSCKEH_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_78_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_78_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_78_TCMDCKE_F2_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_78_TCMDCKE_F2_FLDSHFT (24)
#define HWIO_DDR_CTL_78_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_78_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_79_REGOFF 0x13c
#define HWIO_DDR_CTL_79_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_79_REGOFF)
#define HWIO_DDR_CTL_79_TCKELCMD_F3_FLDMASK (0xf)
#define HWIO_DDR_CTL_79_TCKELCMD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_79_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_79_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_79_TCKEHCMD_F3_FLDMASK (0xf00)
#define HWIO_DDR_CTL_79_TCKEHCMD_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_79_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_79_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_79_TCKCKEL_F3_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_79_TCKCKEL_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_79_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_79_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_79_TSR_F3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_79_TSR_F3_FLDSHFT (24)

#define HWIO_DDR_CTL_80_REGOFF 0x140
#define HWIO_DDR_CTL_80_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_80_REGOFF)
#define HWIO_DDR_CTL_80_TESCKE_F3_FLDMASK (0x7)
#define HWIO_DDR_CTL_80_TESCKE_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_80_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_CTL_80_RESERVED_FLDSHFT (3)
#define HWIO_DDR_CTL_80_TCKELPD_F3_FLDMASK (0xf00)
#define HWIO_DDR_CTL_80_TCKELPD_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_80_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_80_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_80_TCSCKEH_F3_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_80_TCSCKEH_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_80_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_80_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_80_TCMDCKE_F3_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_80_TCMDCKE_F3_FLDSHFT (24)
#define HWIO_DDR_CTL_80_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_80_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_81_REGOFF 0x144
#define HWIO_DDR_CTL_81_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_81_REGOFF)
#define HWIO_DDR_CTL_81_PWRUP_SREFRESH_EXIT_FLDMASK (0x1)
#define HWIO_DDR_CTL_81_PWRUP_SREFRESH_EXIT_FLDSHFT (0)
#define HWIO_DDR_CTL_81_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_81_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_81_CDNS_INTRL1_FLDMASK (0x100)
#define HWIO_DDR_CTL_81_CDNS_INTRL1_FLDSHFT (8)
#define HWIO_DDR_CTL_81_CDNS_INTRL2_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_81_CDNS_INTRL2_FLDSHFT (9)
#define HWIO_DDR_CTL_81_ENABLE_QUICK_SREFRESH_FLDMASK (0x10000)
#define HWIO_DDR_CTL_81_ENABLE_QUICK_SREFRESH_FLDSHFT (16)
#define HWIO_DDR_CTL_81_CDNS_INTRL3_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_81_CDNS_INTRL3_FLDSHFT (17)
#define HWIO_DDR_CTL_81_CKE_DELAY_FLDMASK (0x7000000)
#define HWIO_DDR_CTL_81_CKE_DELAY_FLDSHFT (24)
#define HWIO_DDR_CTL_81_RESERVED4_FLDMASK (0xf8000000)
#define HWIO_DDR_CTL_81_RESERVED4_FLDSHFT (27)

#define HWIO_DDR_CTL_82_REGOFF 0x148
#define HWIO_DDR_CTL_82_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_82_REGOFF)
#define HWIO_DDR_CTL_82_CDNS_INTRL0_FLDMASK (0x1f)
#define HWIO_DDR_CTL_82_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_82_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_CTL_82_RESERVED_FLDSHFT (5)
#define HWIO_DDR_CTL_82_DFS_STATUS_FLDMASK (0x300)
#define HWIO_DDR_CTL_82_DFS_STATUS_FLDSHFT (8)
#define HWIO_DDR_CTL_82_CDNS_INTRL1_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_82_CDNS_INTRL1_FLDSHFT (10)
#define HWIO_DDR_CTL_82_DFS_ZQ_EN_FLDMASK (0x10000)
#define HWIO_DDR_CTL_82_DFS_ZQ_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_82_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_82_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_82_DFS_CALVL_EN_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_82_DFS_CALVL_EN_FLDSHFT (24)
#define HWIO_DDR_CTL_82_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_82_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_83_REGOFF 0x14c
#define HWIO_DDR_CTL_83_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_83_REGOFF)
#define HWIO_DDR_CTL_83_DFS_WRLVL_EN_FLDMASK (0x1)
#define HWIO_DDR_CTL_83_DFS_WRLVL_EN_FLDSHFT (0)
#define HWIO_DDR_CTL_83_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_83_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_83_DFS_RDLVL_EN_FLDMASK (0x100)
#define HWIO_DDR_CTL_83_DFS_RDLVL_EN_FLDSHFT (8)
#define HWIO_DDR_CTL_83_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_83_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_83_DFS_RDLVL_GATE_EN_FLDMASK (0x10000)
#define HWIO_DDR_CTL_83_DFS_RDLVL_GATE_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_83_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_83_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_83_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_83_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_CTL_84_REGOFF 0x150
#define HWIO_DDR_CTL_84_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_84_REGOFF)
#define HWIO_DDR_CTL_84_DFS_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_84_DFS_PROMOTE_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_84_DFS_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_84_DFS_PROMOTE_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_85_REGOFF 0x154
#define HWIO_DDR_CTL_85_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_85_REGOFF)
#define HWIO_DDR_CTL_85_DFS_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_85_DFS_PROMOTE_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_85_DFS_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_85_DFS_PROMOTE_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_86_REGOFF 0x158
#define HWIO_DDR_CTL_86_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_86_REGOFF)
#define HWIO_DDR_CTL_86_ZQ_CALSTART_STATUS_FLDMASK (0x3)
#define HWIO_DDR_CTL_86_ZQ_CALSTART_STATUS_FLDSHFT (0)
#define HWIO_DDR_CTL_86_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_CTL_86_RESERVED_FLDSHFT (2)
#define HWIO_DDR_CTL_86_ZQ_CALLATCH_STATUS_FLDMASK (0x300)
#define HWIO_DDR_CTL_86_ZQ_CALLATCH_STATUS_FLDSHFT (8)
#define HWIO_DDR_CTL_86_CDNS_INTRL1_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_86_CDNS_INTRL1_FLDSHFT (10)
#define HWIO_DDR_CTL_86_ZQ_CALINIT_CS_CL_STATUS_FLDMASK (0x30000)
#define HWIO_DDR_CTL_86_ZQ_CALINIT_CS_CL_STATUS_FLDSHFT (16)
#define HWIO_DDR_CTL_86_CDNS_INTRL2_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_86_CDNS_INTRL2_FLDSHFT (18)
#define HWIO_DDR_CTL_86_CDNS_INTRL3_FLDMASK (0x7000000)
#define HWIO_DDR_CTL_86_CDNS_INTRL3_FLDSHFT (24)
#define HWIO_DDR_CTL_86_RESERVED4_FLDMASK (0xf8000000)
#define HWIO_DDR_CTL_86_RESERVED4_FLDSHFT (27)

#define HWIO_DDR_CTL_87_REGOFF 0x15c
#define HWIO_DDR_CTL_87_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_87_REGOFF)
#define HWIO_DDR_CTL_87_CDNS_INTRL0_FLDMASK (0x7)
#define HWIO_DDR_CTL_87_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_87_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_CTL_87_RESERVED_FLDSHFT (3)
#define HWIO_DDR_CTL_87_CDNS_INTRL1_FLDMASK (0xff00)
#define HWIO_DDR_CTL_87_CDNS_INTRL1_FLDSHFT (8)
#define HWIO_DDR_CTL_87_CDNS_INTRL2_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_87_CDNS_INTRL2_FLDSHFT (16)
#define HWIO_DDR_CTL_87_CDNS_INTRL3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_87_CDNS_INTRL3_FLDSHFT (24)

#define HWIO_DDR_CTL_88_REGOFF 0x160
#define HWIO_DDR_CTL_88_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_88_REGOFF)
#define HWIO_DDR_CTL_88_UPD_CTRLUPD_NORM_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_88_UPD_CTRLUPD_NORM_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_88_UPD_CTRLUPD_HIGH_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_88_UPD_CTRLUPD_HIGH_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_89_REGOFF 0x164
#define HWIO_DDR_CTL_89_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_89_REGOFF)
#define HWIO_DDR_CTL_89_UPD_CTRLUPD_TIMEOUT_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_89_UPD_CTRLUPD_TIMEOUT_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_89_UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_89_UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_90_REGOFF 0x168
#define HWIO_DDR_CTL_90_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_90_REGOFF)
#define HWIO_DDR_CTL_90_UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_90_UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_90_UPD_CTRLUPD_NORM_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_90_UPD_CTRLUPD_NORM_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_91_REGOFF 0x16c
#define HWIO_DDR_CTL_91_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_91_REGOFF)
#define HWIO_DDR_CTL_91_UPD_CTRLUPD_HIGH_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_91_UPD_CTRLUPD_HIGH_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_91_UPD_CTRLUPD_TIMEOUT_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_91_UPD_CTRLUPD_TIMEOUT_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_92_REGOFF 0x170
#define HWIO_DDR_CTL_92_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_92_REGOFF)
#define HWIO_DDR_CTL_92_UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_92_UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_92_UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_92_UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_93_REGOFF 0x174
#define HWIO_DDR_CTL_93_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_93_REGOFF)
#define HWIO_DDR_CTL_93_UPD_CTRLUPD_NORM_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_93_UPD_CTRLUPD_NORM_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_93_UPD_CTRLUPD_HIGH_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_93_UPD_CTRLUPD_HIGH_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_94_REGOFF 0x178
#define HWIO_DDR_CTL_94_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_94_REGOFF)
#define HWIO_DDR_CTL_94_UPD_CTRLUPD_TIMEOUT_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_94_UPD_CTRLUPD_TIMEOUT_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_94_UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_94_UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_95_REGOFF 0x17c
#define HWIO_DDR_CTL_95_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_95_REGOFF)
#define HWIO_DDR_CTL_95_UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_95_UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_95_UPD_CTRLUPD_NORM_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_95_UPD_CTRLUPD_NORM_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_96_REGOFF 0x180
#define HWIO_DDR_CTL_96_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_96_REGOFF)
#define HWIO_DDR_CTL_96_UPD_CTRLUPD_HIGH_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_96_UPD_CTRLUPD_HIGH_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_96_UPD_CTRLUPD_TIMEOUT_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_96_UPD_CTRLUPD_TIMEOUT_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_97_REGOFF 0x184
#define HWIO_DDR_CTL_97_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_97_REGOFF)
#define HWIO_DDR_CTL_97_UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_97_UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_97_UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_97_UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_98_REGOFF 0x188
#define HWIO_DDR_CTL_98_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_98_REGOFF)
#define HWIO_DDR_CTL_98_TDFI_PHYMSTR_MAX_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_98_TDFI_PHYMSTR_MAX_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_98_TDFI_PHYMSTR_RESP_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_98_TDFI_PHYMSTR_RESP_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_99_REGOFF 0x18c
#define HWIO_DDR_CTL_99_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_99_REGOFF)
#define HWIO_DDR_CTL_99_PHYMSTR_DFI_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_99_PHYMSTR_DFI_PROMOTE_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_99_TDFI_PHYMSTR_MAX_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_99_TDFI_PHYMSTR_MAX_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_100_REGOFF 0x190
#define HWIO_DDR_CTL_100_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_100_REGOFF)
#define HWIO_DDR_CTL_100_TDFI_PHYMSTR_RESP_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_100_TDFI_PHYMSTR_RESP_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_100_PHYMSTR_DFI_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_100_PHYMSTR_DFI_PROMOTE_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_101_REGOFF 0x194
#define HWIO_DDR_CTL_101_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_101_REGOFF)
#define HWIO_DDR_CTL_101_TDFI_PHYMSTR_MAX_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_101_TDFI_PHYMSTR_MAX_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_101_TDFI_PHYMSTR_RESP_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_101_TDFI_PHYMSTR_RESP_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_102_REGOFF 0x198
#define HWIO_DDR_CTL_102_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_102_REGOFF)
#define HWIO_DDR_CTL_102_PHYMSTR_DFI_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_102_PHYMSTR_DFI_PROMOTE_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_102_TDFI_PHYMSTR_MAX_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_102_TDFI_PHYMSTR_MAX_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_103_REGOFF 0x19c
#define HWIO_DDR_CTL_103_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_103_REGOFF)
#define HWIO_DDR_CTL_103_TDFI_PHYMSTR_RESP_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_103_TDFI_PHYMSTR_RESP_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_103_PHYMSTR_DFI_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_103_PHYMSTR_DFI_PROMOTE_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_104_REGOFF 0x1a0
#define HWIO_DDR_CTL_104_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_104_REGOFF)
#define HWIO_DDR_CTL_104_PHYMSTR_NO_AREF_FLDMASK (0x1)
#define HWIO_DDR_CTL_104_PHYMSTR_NO_AREF_FLDSHFT (0)
#define HWIO_DDR_CTL_104_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_104_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_104_PHYMSTR_ERROR_STATUS_FLDMASK (0x300)
#define HWIO_DDR_CTL_104_PHYMSTR_ERROR_STATUS_FLDSHFT (8)
#define HWIO_DDR_CTL_104_CDNS_INTRL1_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_104_CDNS_INTRL1_FLDSHFT (10)
#define HWIO_DDR_CTL_104_MRR_TEMPCHK_NORM_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_104_MRR_TEMPCHK_NORM_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_105_REGOFF 0x1a4
#define HWIO_DDR_CTL_105_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_105_REGOFF)
#define HWIO_DDR_CTL_105_MRR_TEMPCHK_HIGH_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_105_MRR_TEMPCHK_HIGH_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_105_MRR_TEMPCHK_TIMEOUT_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_105_MRR_TEMPCHK_TIMEOUT_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_106_REGOFF 0x1a8
#define HWIO_DDR_CTL_106_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_106_REGOFF)
#define HWIO_DDR_CTL_106_MRR_TEMPCHK_NORM_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_106_MRR_TEMPCHK_NORM_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_106_MRR_TEMPCHK_HIGH_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_106_MRR_TEMPCHK_HIGH_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_107_REGOFF 0x1ac
#define HWIO_DDR_CTL_107_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_107_REGOFF)
#define HWIO_DDR_CTL_107_MRR_TEMPCHK_TIMEOUT_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_107_MRR_TEMPCHK_TIMEOUT_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_107_MRR_TEMPCHK_NORM_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_107_MRR_TEMPCHK_NORM_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_108_REGOFF 0x1b0
#define HWIO_DDR_CTL_108_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_108_REGOFF)
#define HWIO_DDR_CTL_108_MRR_TEMPCHK_HIGH_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_108_MRR_TEMPCHK_HIGH_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_108_MRR_TEMPCHK_TIMEOUT_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_108_MRR_TEMPCHK_TIMEOUT_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_109_REGOFF 0x1b4
#define HWIO_DDR_CTL_109_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_109_REGOFF)
#define HWIO_DDR_CTL_109_MRR_TEMPCHK_NORM_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_109_MRR_TEMPCHK_NORM_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_109_MRR_TEMPCHK_HIGH_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_109_MRR_TEMPCHK_HIGH_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_110_REGOFF 0x1b8
#define HWIO_DDR_CTL_110_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_110_REGOFF)
#define HWIO_DDR_CTL_110_MRR_TEMPCHK_TIMEOUT_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_110_MRR_TEMPCHK_TIMEOUT_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_110_LOWPOWER_REFRESH_ENABLE_FLDMASK (0x10000)
#define HWIO_DDR_CTL_110_LOWPOWER_REFRESH_ENABLE_FLDSHFT (16)
#define HWIO_DDR_CTL_110_RESERVED_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_110_RESERVED_FLDSHFT (17)
#define HWIO_DDR_CTL_110_CKSRE_F0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_110_CKSRE_F0_FLDSHFT (24)

#define HWIO_DDR_CTL_111_REGOFF 0x1bc
#define HWIO_DDR_CTL_111_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_111_REGOFF)
#define HWIO_DDR_CTL_111_CKSRX_F0_FLDMASK (0xff)
#define HWIO_DDR_CTL_111_CKSRX_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_111_CKSRE_F1_FLDMASK (0xff00)
#define HWIO_DDR_CTL_111_CKSRE_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_111_CKSRX_F1_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_111_CKSRX_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_111_CKSRE_F2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_111_CKSRE_F2_FLDSHFT (24)

#define HWIO_DDR_CTL_112_REGOFF 0x1c0
#define HWIO_DDR_CTL_112_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_112_REGOFF)
#define HWIO_DDR_CTL_112_CKSRX_F2_FLDMASK (0xff)
#define HWIO_DDR_CTL_112_CKSRX_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_112_CKSRE_F3_FLDMASK (0xff00)
#define HWIO_DDR_CTL_112_CKSRE_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_112_CKSRX_F3_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_112_CKSRX_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_112_LP_CMD_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_112_LP_CMD_FLDSHFT (24)

#define HWIO_DDR_CTL_113_REGOFF 0x1c4
#define HWIO_DDR_CTL_113_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_113_REGOFF)
#define HWIO_DDR_CTL_113_LPI_PD_WAKEUP_F0_FLDMASK (0xf)
#define HWIO_DDR_CTL_113_LPI_PD_WAKEUP_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_113_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_113_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_113_LPI_SR_WAKEUP_F0_FLDMASK (0xf00)
#define HWIO_DDR_CTL_113_LPI_SR_WAKEUP_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_113_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_113_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_113_LPI_SR_MCCLK_GATE_WAKEUP_F0_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_113_LPI_SR_MCCLK_GATE_WAKEUP_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_113_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_113_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_113_LPI_SRPD_LITE_WAKEUP_F0_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_113_LPI_SRPD_LITE_WAKEUP_F0_FLDSHFT (24)
#define HWIO_DDR_CTL_113_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_113_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_114_REGOFF 0x1c8
#define HWIO_DDR_CTL_114_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_114_REGOFF)
#define HWIO_DDR_CTL_114_LPI_SRPD_DEEP_WAKEUP_F0_FLDMASK (0xf)
#define HWIO_DDR_CTL_114_LPI_SRPD_DEEP_WAKEUP_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_114_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_114_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_114_LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F0_FLDMASK (0xf00)
#define HWIO_DDR_CTL_114_LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_114_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_114_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_114_LPI_TIMER_WAKEUP_F0_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_114_LPI_TIMER_WAKEUP_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_114_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_114_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_114_LPI_PD_WAKEUP_F1_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_114_LPI_PD_WAKEUP_F1_FLDSHFT (24)
#define HWIO_DDR_CTL_114_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_114_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_115_REGOFF 0x1cc
#define HWIO_DDR_CTL_115_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_115_REGOFF)
#define HWIO_DDR_CTL_115_LPI_SR_WAKEUP_F1_FLDMASK (0xf)
#define HWIO_DDR_CTL_115_LPI_SR_WAKEUP_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_115_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_115_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_115_LPI_SR_MCCLK_GATE_WAKEUP_F1_FLDMASK (0xf00)
#define HWIO_DDR_CTL_115_LPI_SR_MCCLK_GATE_WAKEUP_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_115_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_115_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_115_LPI_SRPD_LITE_WAKEUP_F1_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_115_LPI_SRPD_LITE_WAKEUP_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_115_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_115_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_115_LPI_SRPD_DEEP_WAKEUP_F1_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_115_LPI_SRPD_DEEP_WAKEUP_F1_FLDSHFT (24)
#define HWIO_DDR_CTL_115_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_115_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_116_REGOFF 0x1d0
#define HWIO_DDR_CTL_116_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_116_REGOFF)
#define HWIO_DDR_CTL_116_LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F1_FLDMASK (0xf)
#define HWIO_DDR_CTL_116_LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_116_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_116_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_116_LPI_TIMER_WAKEUP_F1_FLDMASK (0xf00)
#define HWIO_DDR_CTL_116_LPI_TIMER_WAKEUP_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_116_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_116_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_116_LPI_PD_WAKEUP_F2_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_116_LPI_PD_WAKEUP_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_116_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_116_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_116_LPI_SR_WAKEUP_F2_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_116_LPI_SR_WAKEUP_F2_FLDSHFT (24)
#define HWIO_DDR_CTL_116_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_116_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_117_REGOFF 0x1d4
#define HWIO_DDR_CTL_117_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_117_REGOFF)
#define HWIO_DDR_CTL_117_LPI_SR_MCCLK_GATE_WAKEUP_F2_FLDMASK (0xf)
#define HWIO_DDR_CTL_117_LPI_SR_MCCLK_GATE_WAKEUP_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_117_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_117_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_117_LPI_SRPD_LITE_WAKEUP_F2_FLDMASK (0xf00)
#define HWIO_DDR_CTL_117_LPI_SRPD_LITE_WAKEUP_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_117_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_117_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_117_LPI_SRPD_DEEP_WAKEUP_F2_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_117_LPI_SRPD_DEEP_WAKEUP_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_117_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_117_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_117_LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F2_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_117_LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F2_FLDSHFT (24)
#define HWIO_DDR_CTL_117_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_117_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_118_REGOFF 0x1d8
#define HWIO_DDR_CTL_118_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_118_REGOFF)
#define HWIO_DDR_CTL_118_LPI_TIMER_WAKEUP_F2_FLDMASK (0xf)
#define HWIO_DDR_CTL_118_LPI_TIMER_WAKEUP_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_118_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_118_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_118_LPI_PD_WAKEUP_F3_FLDMASK (0xf00)
#define HWIO_DDR_CTL_118_LPI_PD_WAKEUP_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_118_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_118_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_118_LPI_SR_WAKEUP_F3_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_118_LPI_SR_WAKEUP_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_118_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_118_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_118_LPI_SR_MCCLK_GATE_WAKEUP_F3_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_118_LPI_SR_MCCLK_GATE_WAKEUP_F3_FLDSHFT (24)
#define HWIO_DDR_CTL_118_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_118_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_119_REGOFF 0x1dc
#define HWIO_DDR_CTL_119_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_119_REGOFF)
#define HWIO_DDR_CTL_119_LPI_SRPD_LITE_WAKEUP_F3_FLDMASK (0xf)
#define HWIO_DDR_CTL_119_LPI_SRPD_LITE_WAKEUP_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_119_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_119_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_119_LPI_SRPD_DEEP_WAKEUP_F3_FLDMASK (0xf00)
#define HWIO_DDR_CTL_119_LPI_SRPD_DEEP_WAKEUP_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_119_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_119_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_119_LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F3_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_119_LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_119_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_119_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_119_LPI_TIMER_WAKEUP_F3_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_119_LPI_TIMER_WAKEUP_F3_FLDSHFT (24)
#define HWIO_DDR_CTL_119_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_119_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_120_REGOFF 0x1e0
#define HWIO_DDR_CTL_120_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_120_REGOFF)
#define HWIO_DDR_CTL_120_LPI_WAKEUP_EN_FLDMASK (0x1f)
#define HWIO_DDR_CTL_120_LPI_WAKEUP_EN_FLDSHFT (0)
#define HWIO_DDR_CTL_120_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_CTL_120_RESERVED_FLDSHFT (5)
#define HWIO_DDR_CTL_120_LPI_TIMER_COUNT_FLDMASK (0xfff00)
#define HWIO_DDR_CTL_120_LPI_TIMER_COUNT_FLDSHFT (8)
#define HWIO_DDR_CTL_120_CDNS_INTRL1_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_120_CDNS_INTRL1_FLDSHFT (20)
#define HWIO_DDR_CTL_120_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_120_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_121_REGOFF 0x1e4
#define HWIO_DDR_CTL_121_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_121_REGOFF)
#define HWIO_DDR_CTL_121_LPI_WAKEUP_TIMEOUT_FLDMASK (0xfff)
#define HWIO_DDR_CTL_121_LPI_WAKEUP_TIMEOUT_FLDSHFT (0)
#define HWIO_DDR_CTL_121_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_CTL_121_RESERVED_FLDSHFT (12)
#define HWIO_DDR_CTL_121_TDFI_LP_RESP_FLDMASK (0x70000)
#define HWIO_DDR_CTL_121_TDFI_LP_RESP_FLDSHFT (16)
#define HWIO_DDR_CTL_121_CDNS_INTRL1_FLDMASK (0xf80000)
#define HWIO_DDR_CTL_121_CDNS_INTRL1_FLDSHFT (19)
#define HWIO_DDR_CTL_121_LP_STATE_FLDMASK (0x7f000000)
#define HWIO_DDR_CTL_121_LP_STATE_FLDSHFT (24)
#define HWIO_DDR_CTL_121_CDNS_INTRL2_FLDMASK (0x80000000)
#define HWIO_DDR_CTL_121_CDNS_INTRL2_FLDSHFT (31)

#define HWIO_DDR_CTL_122_REGOFF 0x1e8
#define HWIO_DDR_CTL_122_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_122_REGOFF)
#define HWIO_DDR_CTL_122_LP_AUTO_ENTRY_EN_FLDMASK (0xf)
#define HWIO_DDR_CTL_122_LP_AUTO_ENTRY_EN_FLDSHFT (0)
#define HWIO_DDR_CTL_122_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_122_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_122_LP_AUTO_EXIT_EN_FLDMASK (0xf00)
#define HWIO_DDR_CTL_122_LP_AUTO_EXIT_EN_FLDSHFT (8)
#define HWIO_DDR_CTL_122_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_122_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_122_LP_AUTO_MEM_GATE_EN_FLDMASK (0x70000)
#define HWIO_DDR_CTL_122_LP_AUTO_MEM_GATE_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_122_CDNS_INTRL2_FLDMASK (0xf80000)
#define HWIO_DDR_CTL_122_CDNS_INTRL2_FLDSHFT (19)
#define HWIO_DDR_CTL_122_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_122_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_CTL_123_REGOFF 0x1ec
#define HWIO_DDR_CTL_123_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_123_REGOFF)
#define HWIO_DDR_CTL_123_LP_AUTO_PD_IDLE_FLDMASK (0xfff)
#define HWIO_DDR_CTL_123_LP_AUTO_PD_IDLE_FLDSHFT (0)
#define HWIO_DDR_CTL_123_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_CTL_123_RESERVED_FLDSHFT (12)
#define HWIO_DDR_CTL_123_LP_AUTO_SRPD_LITE_IDLE_FLDMASK (0xfff0000)
#define HWIO_DDR_CTL_123_LP_AUTO_SRPD_LITE_IDLE_FLDSHFT (16)
#define HWIO_DDR_CTL_123_CDNS_INTRL1_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_123_CDNS_INTRL1_FLDSHFT (28)

#define HWIO_DDR_CTL_124_REGOFF 0x1f0
#define HWIO_DDR_CTL_124_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_124_REGOFF)
#define HWIO_DDR_CTL_124_LP_AUTO_SR_IDLE_FLDMASK (0xff)
#define HWIO_DDR_CTL_124_LP_AUTO_SR_IDLE_FLDSHFT (0)
#define HWIO_DDR_CTL_124_LP_AUTO_SR_MC_GATE_IDLE_FLDMASK (0xff00)
#define HWIO_DDR_CTL_124_LP_AUTO_SR_MC_GATE_IDLE_FLDSHFT (8)
#define HWIO_DDR_CTL_124_HW_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_124_HW_PROMOTE_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_125_REGOFF 0x1f4
#define HWIO_DDR_CTL_125_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_125_REGOFF)
#define HWIO_DDR_CTL_125_HW_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_125_HW_PROMOTE_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_125_HW_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_125_HW_PROMOTE_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_126_REGOFF 0x1f8
#define HWIO_DDR_CTL_126_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_126_REGOFF)
#define HWIO_DDR_CTL_126_HW_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_126_HW_PROMOTE_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_126_LPC_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_126_LPC_PROMOTE_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_127_REGOFF 0x1fc
#define HWIO_DDR_CTL_127_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_127_REGOFF)
#define HWIO_DDR_CTL_127_LPC_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_127_LPC_PROMOTE_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_127_LPC_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_127_LPC_PROMOTE_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_128_REGOFF 0x200
#define HWIO_DDR_CTL_128_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_128_REGOFF)
#define HWIO_DDR_CTL_128_LPC_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_128_LPC_PROMOTE_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_128_LPC_SR_CTRLUPD_EN_FLDMASK (0x10000)
#define HWIO_DDR_CTL_128_LPC_SR_CTRLUPD_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_128_RESERVED_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_128_RESERVED_FLDSHFT (17)
#define HWIO_DDR_CTL_128_LPC_SR_PHYUPD_EN_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_128_LPC_SR_PHYUPD_EN_FLDSHFT (24)
#define HWIO_DDR_CTL_128_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_128_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_129_REGOFF 0x204
#define HWIO_DDR_CTL_129_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_129_REGOFF)
#define HWIO_DDR_CTL_129_LPC_SR_PHYMSTR_EN_FLDMASK (0x1)
#define HWIO_DDR_CTL_129_LPC_SR_PHYMSTR_EN_FLDSHFT (0)
#define HWIO_DDR_CTL_129_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_129_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_129_CDNS_INTRL1_FLDMASK (0x100)
#define HWIO_DDR_CTL_129_CDNS_INTRL1_FLDSHFT (8)
#define HWIO_DDR_CTL_129_CDNS_INTRL2_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_129_CDNS_INTRL2_FLDSHFT (9)
#define HWIO_DDR_CTL_129_LPC_SR_ZQ_EN_FLDMASK (0x10000)
#define HWIO_DDR_CTL_129_LPC_SR_ZQ_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_129_RESERVED4_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_129_RESERVED4_FLDSHFT (17)
#define HWIO_DDR_CTL_129_CDNS_INTRL3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_129_CDNS_INTRL3_FLDSHFT (24)

#define HWIO_DDR_CTL_130_REGOFF 0x208
#define HWIO_DDR_CTL_130_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_130_REGOFF)
#define HWIO_DDR_CTL_130_DFS_ENABLE_FLDMASK (0x1)
#define HWIO_DDR_CTL_130_DFS_ENABLE_FLDSHFT (0)
#define HWIO_DDR_CTL_130_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_130_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_130_TDFI_INIT_START_F0_FLDMASK (0xff00)
#define HWIO_DDR_CTL_130_TDFI_INIT_START_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_130_TDFI_INIT_COMPLETE_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_130_TDFI_INIT_COMPLETE_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_131_REGOFF 0x20c
#define HWIO_DDR_CTL_131_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_131_REGOFF)
#define HWIO_DDR_CTL_131_TDFI_INIT_START_F1_FLDMASK (0xff)
#define HWIO_DDR_CTL_131_TDFI_INIT_START_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_131_TDFI_INIT_COMPLETE_F1_FLDMASK (0xffff00)
#define HWIO_DDR_CTL_131_TDFI_INIT_COMPLETE_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_131_TDFI_INIT_START_F2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_131_TDFI_INIT_START_F2_FLDSHFT (24)

#define HWIO_DDR_CTL_132_REGOFF 0x210
#define HWIO_DDR_CTL_132_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_132_REGOFF)
#define HWIO_DDR_CTL_132_TDFI_INIT_COMPLETE_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_132_TDFI_INIT_COMPLETE_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_132_TDFI_INIT_START_F3_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_132_TDFI_INIT_START_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_132_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_132_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_133_REGOFF 0x214
#define HWIO_DDR_CTL_133_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_133_REGOFF)
#define HWIO_DDR_CTL_133_TDFI_INIT_COMPLETE_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_133_TDFI_INIT_COMPLETE_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_133_CURRENT_REG_COPY_FLDMASK (0x30000)
#define HWIO_DDR_CTL_133_CURRENT_REG_COPY_FLDSHFT (16)
#define HWIO_DDR_CTL_133_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_133_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_133_DFS_PHY_REG_WRITE_EN_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_133_DFS_PHY_REG_WRITE_EN_FLDSHFT (24)
#define HWIO_DDR_CTL_133_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_133_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_134_REGOFF 0x218
#define HWIO_DDR_CTL_134_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_134_REGOFF)
#define HWIO_DDR_CTL_134_DFS_PHY_REG_WRITE_ADDR_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_134_DFS_PHY_REG_WRITE_ADDR_FLDSHFT (0)

#define HWIO_DDR_CTL_135_REGOFF 0x21c
#define HWIO_DDR_CTL_135_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_135_REGOFF)
#define HWIO_DDR_CTL_135_DFS_PHY_REG_WRITE_DATA_F0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_135_DFS_PHY_REG_WRITE_DATA_F0_FLDSHFT (0)

#define HWIO_DDR_CTL_136_REGOFF 0x220
#define HWIO_DDR_CTL_136_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_136_REGOFF)
#define HWIO_DDR_CTL_136_DFS_PHY_REG_WRITE_DATA_F1_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_136_DFS_PHY_REG_WRITE_DATA_F1_FLDSHFT (0)

#define HWIO_DDR_CTL_137_REGOFF 0x224
#define HWIO_DDR_CTL_137_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_137_REGOFF)
#define HWIO_DDR_CTL_137_DFS_PHY_REG_WRITE_DATA_F2_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_137_DFS_PHY_REG_WRITE_DATA_F2_FLDSHFT (0)

#define HWIO_DDR_CTL_138_REGOFF 0x228
#define HWIO_DDR_CTL_138_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_138_REGOFF)
#define HWIO_DDR_CTL_138_DFS_PHY_REG_WRITE_DATA_F3_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_138_DFS_PHY_REG_WRITE_DATA_F3_FLDSHFT (0)

#define HWIO_DDR_CTL_139_REGOFF 0x22c
#define HWIO_DDR_CTL_139_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_139_REGOFF)
#define HWIO_DDR_CTL_139_DFS_PHY_REG_WRITE_MASK_FLDMASK (0xf)
#define HWIO_DDR_CTL_139_DFS_PHY_REG_WRITE_MASK_FLDSHFT (0)
#define HWIO_DDR_CTL_139_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_139_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_139_DFS_PHY_REG_WRITE_WAIT_FLDMASK (0xffff00)
#define HWIO_DDR_CTL_139_DFS_PHY_REG_WRITE_WAIT_FLDSHFT (8)
#define HWIO_DDR_CTL_139_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_139_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_140_REGOFF 0x230
#define HWIO_DDR_CTL_140_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_140_REGOFF)
#define HWIO_DDR_CTL_140_WRITE_MODEREG_FLDMASK (0x7ffffff)
#define HWIO_DDR_CTL_140_WRITE_MODEREG_FLDSHFT (0)
#define HWIO_DDR_CTL_140_RESERVED_FLDMASK (0xf8000000)
#define HWIO_DDR_CTL_140_RESERVED_FLDSHFT (27)

#define HWIO_DDR_CTL_141_REGOFF 0x234
#define HWIO_DDR_CTL_141_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_141_REGOFF)
#define HWIO_DDR_CTL_141_MRW_STATUS_FLDMASK (0xff)
#define HWIO_DDR_CTL_141_MRW_STATUS_FLDSHFT (0)
#define HWIO_DDR_CTL_141_READ_MODEREG_FLDMASK (0x1ffff00)
#define HWIO_DDR_CTL_141_READ_MODEREG_FLDSHFT (8)
#define HWIO_DDR_CTL_141_RESERVED_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_141_RESERVED_FLDSHFT (25)

#define HWIO_DDR_CTL_142_REGOFF 0x238
#define HWIO_DDR_CTL_142_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_142_REGOFF)
#define HWIO_DDR_CTL_142_PERIPHERAL_MRR_DATA_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_142_PERIPHERAL_MRR_DATA_FLDSHFT (0)

#define HWIO_DDR_CTL_143_REGOFF 0x23c
#define HWIO_DDR_CTL_143_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_143_REGOFF)
#define HWIO_DDR_CTL_143_PERIPHERAL_MRR_DATA_FLDMASK (0xff)
#define HWIO_DDR_CTL_143_PERIPHERAL_MRR_DATA_FLDSHFT (0)
#define HWIO_DDR_CTL_143_AUTO_TEMPCHK_VAL_0_FLDMASK (0xffff00)
#define HWIO_DDR_CTL_143_AUTO_TEMPCHK_VAL_0_FLDSHFT (8)
#define HWIO_DDR_CTL_143_DISABLE_UPDATE_TVRCG_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_143_DISABLE_UPDATE_TVRCG_FLDSHFT (24)
#define HWIO_DDR_CTL_143_RESERVED_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_143_RESERVED_FLDSHFT (25)

#define HWIO_DDR_CTL_144_REGOFF 0x240
#define HWIO_DDR_CTL_144_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_144_REGOFF)
#define HWIO_DDR_CTL_144_MRW_DFS_UPDATE_FRC_FLDMASK (0x3)
#define HWIO_DDR_CTL_144_MRW_DFS_UPDATE_FRC_FLDSHFT (0)
#define HWIO_DDR_CTL_144_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_CTL_144_RESERVED_FLDSHFT (2)
#define HWIO_DDR_CTL_144_OBSOLETE1_FLDMASK (0xff00)
#define HWIO_DDR_CTL_144_OBSOLETE1_FLDSHFT (8)
#define HWIO_DDR_CTL_144_TVRCG_ENABLE_F0_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_144_TVRCG_ENABLE_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_144_CDNS_INTRL1_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_144_CDNS_INTRL1_FLDSHFT (26)

#define HWIO_DDR_CTL_145_REGOFF 0x244
#define HWIO_DDR_CTL_145_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_145_REGOFF)
#define HWIO_DDR_CTL_145_TVRCG_DISABLE_F0_FLDMASK (0x3ff)
#define HWIO_DDR_CTL_145_TVRCG_DISABLE_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_145_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_145_RESERVED_FLDSHFT (10)
#define HWIO_DDR_CTL_145_TFC_F0_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_145_TFC_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_145_CDNS_INTRL1_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_145_CDNS_INTRL1_FLDSHFT (26)

#define HWIO_DDR_CTL_146_REGOFF 0x248
#define HWIO_DDR_CTL_146_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_146_REGOFF)
#define HWIO_DDR_CTL_146_TCKFSPE_F0_FLDMASK (0x1f)
#define HWIO_DDR_CTL_146_TCKFSPE_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_146_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_CTL_146_RESERVED_FLDSHFT (5)
#define HWIO_DDR_CTL_146_TCKFSPX_F0_FLDMASK (0x1f00)
#define HWIO_DDR_CTL_146_TCKFSPX_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_146_CDNS_INTRL1_FLDMASK (0xe000)
#define HWIO_DDR_CTL_146_CDNS_INTRL1_FLDSHFT (13)
#define HWIO_DDR_CTL_146_TVREF_LONG_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_146_TVREF_LONG_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_147_REGOFF 0x24c
#define HWIO_DDR_CTL_147_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_147_REGOFF)
#define HWIO_DDR_CTL_147_TVRCG_ENABLE_F1_FLDMASK (0x3ff)
#define HWIO_DDR_CTL_147_TVRCG_ENABLE_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_147_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_147_RESERVED_FLDSHFT (10)
#define HWIO_DDR_CTL_147_TVRCG_DISABLE_F1_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_147_TVRCG_DISABLE_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_147_CDNS_INTRL1_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_147_CDNS_INTRL1_FLDSHFT (26)

#define HWIO_DDR_CTL_148_REGOFF 0x250
#define HWIO_DDR_CTL_148_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_148_REGOFF)
#define HWIO_DDR_CTL_148_TFC_F1_FLDMASK (0x3ff)
#define HWIO_DDR_CTL_148_TFC_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_148_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_148_RESERVED_FLDSHFT (10)
#define HWIO_DDR_CTL_148_TCKFSPE_F1_FLDMASK (0x1f0000)
#define HWIO_DDR_CTL_148_TCKFSPE_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_148_CDNS_INTRL1_FLDMASK (0xe00000)
#define HWIO_DDR_CTL_148_CDNS_INTRL1_FLDSHFT (21)
#define HWIO_DDR_CTL_148_TCKFSPX_F1_FLDMASK (0x1f000000)
#define HWIO_DDR_CTL_148_TCKFSPX_F1_FLDSHFT (24)
#define HWIO_DDR_CTL_148_CDNS_INTRL2_FLDMASK (0xe0000000)
#define HWIO_DDR_CTL_148_CDNS_INTRL2_FLDSHFT (29)

#define HWIO_DDR_CTL_149_REGOFF 0x254
#define HWIO_DDR_CTL_149_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_149_REGOFF)
#define HWIO_DDR_CTL_149_TVREF_LONG_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_149_TVREF_LONG_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_149_TVRCG_ENABLE_F2_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_149_TVRCG_ENABLE_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_149_RESERVED_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_149_RESERVED_FLDSHFT (26)

#define HWIO_DDR_CTL_150_REGOFF 0x258
#define HWIO_DDR_CTL_150_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_150_REGOFF)
#define HWIO_DDR_CTL_150_TVRCG_DISABLE_F2_FLDMASK (0x3ff)
#define HWIO_DDR_CTL_150_TVRCG_DISABLE_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_150_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_150_RESERVED_FLDSHFT (10)
#define HWIO_DDR_CTL_150_TFC_F2_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_150_TFC_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_150_CDNS_INTRL1_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_150_CDNS_INTRL1_FLDSHFT (26)

#define HWIO_DDR_CTL_151_REGOFF 0x25c
#define HWIO_DDR_CTL_151_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_151_REGOFF)
#define HWIO_DDR_CTL_151_TCKFSPE_F2_FLDMASK (0x1f)
#define HWIO_DDR_CTL_151_TCKFSPE_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_151_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_CTL_151_RESERVED_FLDSHFT (5)
#define HWIO_DDR_CTL_151_TCKFSPX_F2_FLDMASK (0x1f00)
#define HWIO_DDR_CTL_151_TCKFSPX_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_151_CDNS_INTRL1_FLDMASK (0xe000)
#define HWIO_DDR_CTL_151_CDNS_INTRL1_FLDSHFT (13)
#define HWIO_DDR_CTL_151_TVREF_LONG_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_151_TVREF_LONG_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_152_REGOFF 0x260
#define HWIO_DDR_CTL_152_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_152_REGOFF)
#define HWIO_DDR_CTL_152_TVRCG_ENABLE_F3_FLDMASK (0x3ff)
#define HWIO_DDR_CTL_152_TVRCG_ENABLE_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_152_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_152_RESERVED_FLDSHFT (10)
#define HWIO_DDR_CTL_152_TVRCG_DISABLE_F3_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_152_TVRCG_DISABLE_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_152_CDNS_INTRL1_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_152_CDNS_INTRL1_FLDSHFT (26)

#define HWIO_DDR_CTL_153_REGOFF 0x264
#define HWIO_DDR_CTL_153_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_153_REGOFF)
#define HWIO_DDR_CTL_153_TFC_F3_FLDMASK (0x3ff)
#define HWIO_DDR_CTL_153_TFC_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_153_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_153_RESERVED_FLDSHFT (10)
#define HWIO_DDR_CTL_153_TCKFSPE_F3_FLDMASK (0x1f0000)
#define HWIO_DDR_CTL_153_TCKFSPE_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_153_CDNS_INTRL1_FLDMASK (0xe00000)
#define HWIO_DDR_CTL_153_CDNS_INTRL1_FLDSHFT (21)
#define HWIO_DDR_CTL_153_TCKFSPX_F3_FLDMASK (0x1f000000)
#define HWIO_DDR_CTL_153_TCKFSPX_F3_FLDSHFT (24)
#define HWIO_DDR_CTL_153_CDNS_INTRL2_FLDMASK (0xe0000000)
#define HWIO_DDR_CTL_153_CDNS_INTRL2_FLDSHFT (29)

#define HWIO_DDR_CTL_154_REGOFF 0x268
#define HWIO_DDR_CTL_154_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_154_REGOFF)
#define HWIO_DDR_CTL_154_TVREF_LONG_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_154_TVREF_LONG_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_154_MRR_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_154_MRR_PROMOTE_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_155_REGOFF 0x26c
#define HWIO_DDR_CTL_155_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_155_REGOFF)
#define HWIO_DDR_CTL_155_MRR_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_155_MRR_PROMOTE_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_155_MRR_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_155_MRR_PROMOTE_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_156_REGOFF 0x270
#define HWIO_DDR_CTL_156_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_156_REGOFF)
#define HWIO_DDR_CTL_156_MRR_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_156_MRR_PROMOTE_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_156_MRW_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_156_MRW_PROMOTE_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_157_REGOFF 0x274
#define HWIO_DDR_CTL_157_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_157_REGOFF)
#define HWIO_DDR_CTL_157_MRW_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_157_MRW_PROMOTE_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_157_MRW_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_157_MRW_PROMOTE_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_158_REGOFF 0x278
#define HWIO_DDR_CTL_158_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_158_REGOFF)
#define HWIO_DDR_CTL_158_MRW_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_158_MRW_PROMOTE_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_158_MR1_DATA_F0_0_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_158_MR1_DATA_F0_0_FLDSHFT (16)
#define HWIO_DDR_CTL_158_MR2_DATA_F0_0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_158_MR2_DATA_F0_0_FLDSHFT (24)

#define HWIO_DDR_CTL_159_REGOFF 0x27c
#define HWIO_DDR_CTL_159_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_159_REGOFF)
#define HWIO_DDR_CTL_159_MR1_DATA_F1_0_FLDMASK (0xff)
#define HWIO_DDR_CTL_159_MR1_DATA_F1_0_FLDSHFT (0)
#define HWIO_DDR_CTL_159_MR2_DATA_F1_0_FLDMASK (0xff00)
#define HWIO_DDR_CTL_159_MR2_DATA_F1_0_FLDSHFT (8)
#define HWIO_DDR_CTL_159_MR1_DATA_F2_0_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_159_MR1_DATA_F2_0_FLDSHFT (16)
#define HWIO_DDR_CTL_159_MR2_DATA_F2_0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_159_MR2_DATA_F2_0_FLDSHFT (24)

#define HWIO_DDR_CTL_160_REGOFF 0x280
#define HWIO_DDR_CTL_160_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_160_REGOFF)
#define HWIO_DDR_CTL_160_MR1_DATA_F3_0_FLDMASK (0xff)
#define HWIO_DDR_CTL_160_MR1_DATA_F3_0_FLDSHFT (0)
#define HWIO_DDR_CTL_160_MR2_DATA_F3_0_FLDMASK (0xff00)
#define HWIO_DDR_CTL_160_MR2_DATA_F3_0_FLDSHFT (8)
#define HWIO_DDR_CTL_160_MRSINGLE_DATA_0_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_160_MRSINGLE_DATA_0_FLDSHFT (16)
#define HWIO_DDR_CTL_160_MR3_DATA_F0_0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_160_MR3_DATA_F0_0_FLDSHFT (24)

#define HWIO_DDR_CTL_161_REGOFF 0x284
#define HWIO_DDR_CTL_161_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_161_REGOFF)
#define HWIO_DDR_CTL_161_MR3_DATA_F1_0_FLDMASK (0xff)
#define HWIO_DDR_CTL_161_MR3_DATA_F1_0_FLDSHFT (0)
#define HWIO_DDR_CTL_161_MR3_DATA_F2_0_FLDMASK (0xff00)
#define HWIO_DDR_CTL_161_MR3_DATA_F2_0_FLDSHFT (8)
#define HWIO_DDR_CTL_161_MR3_DATA_F3_0_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_161_MR3_DATA_F3_0_FLDSHFT (16)
#define HWIO_DDR_CTL_161_MR8_DATA_0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_161_MR8_DATA_0_FLDSHFT (24)

#define HWIO_DDR_CTL_162_REGOFF 0x288
#define HWIO_DDR_CTL_162_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_162_REGOFF)
#define HWIO_DDR_CTL_162_MR11_DATA_F0_0_FLDMASK (0xff)
#define HWIO_DDR_CTL_162_MR11_DATA_F0_0_FLDSHFT (0)
#define HWIO_DDR_CTL_162_MR11_DATA_F1_0_FLDMASK (0xff00)
#define HWIO_DDR_CTL_162_MR11_DATA_F1_0_FLDSHFT (8)
#define HWIO_DDR_CTL_162_MR11_DATA_F2_0_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_162_MR11_DATA_F2_0_FLDSHFT (16)
#define HWIO_DDR_CTL_162_MR11_DATA_F3_0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_162_MR11_DATA_F3_0_FLDSHFT (24)

#define HWIO_DDR_CTL_163_REGOFF 0x28c
#define HWIO_DDR_CTL_163_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_163_REGOFF)
#define HWIO_DDR_CTL_163_MR12_DATA_F0_0_FLDMASK (0xff)
#define HWIO_DDR_CTL_163_MR12_DATA_F0_0_FLDSHFT (0)
#define HWIO_DDR_CTL_163_MR12_DATA_F1_0_FLDMASK (0xff00)
#define HWIO_DDR_CTL_163_MR12_DATA_F1_0_FLDSHFT (8)
#define HWIO_DDR_CTL_163_MR12_DATA_F2_0_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_163_MR12_DATA_F2_0_FLDSHFT (16)
#define HWIO_DDR_CTL_163_MR12_DATA_F3_0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_163_MR12_DATA_F3_0_FLDSHFT (24)

#define HWIO_DDR_CTL_164_REGOFF 0x290
#define HWIO_DDR_CTL_164_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_164_REGOFF)
#define HWIO_DDR_CTL_164_MR13_DATA_0_FLDMASK (0xff)
#define HWIO_DDR_CTL_164_MR13_DATA_0_FLDSHFT (0)
#define HWIO_DDR_CTL_164_MR14_DATA_F0_0_FLDMASK (0xff00)
#define HWIO_DDR_CTL_164_MR14_DATA_F0_0_FLDSHFT (8)
#define HWIO_DDR_CTL_164_MR14_DATA_F1_0_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_164_MR14_DATA_F1_0_FLDSHFT (16)
#define HWIO_DDR_CTL_164_MR14_DATA_F2_0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_164_MR14_DATA_F2_0_FLDSHFT (24)

#define HWIO_DDR_CTL_165_REGOFF 0x294
#define HWIO_DDR_CTL_165_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_165_REGOFF)
#define HWIO_DDR_CTL_165_MR14_DATA_F3_0_FLDMASK (0xff)
#define HWIO_DDR_CTL_165_MR14_DATA_F3_0_FLDSHFT (0)
#define HWIO_DDR_CTL_165_MR_FSP_DATA_VALID_F0_0_FLDMASK (0x100)
#define HWIO_DDR_CTL_165_MR_FSP_DATA_VALID_F0_0_FLDSHFT (8)
#define HWIO_DDR_CTL_165_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_165_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_165_MR_FSP_DATA_VALID_F1_0_FLDMASK (0x10000)
#define HWIO_DDR_CTL_165_MR_FSP_DATA_VALID_F1_0_FLDSHFT (16)
#define HWIO_DDR_CTL_165_CDNS_INTRL1_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_165_CDNS_INTRL1_FLDSHFT (17)
#define HWIO_DDR_CTL_165_MR_FSP_DATA_VALID_F2_0_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_165_MR_FSP_DATA_VALID_F2_0_FLDSHFT (24)
#define HWIO_DDR_CTL_165_CDNS_INTRL2_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_165_CDNS_INTRL2_FLDSHFT (25)

#define HWIO_DDR_CTL_166_REGOFF 0x298
#define HWIO_DDR_CTL_166_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_166_REGOFF)
#define HWIO_DDR_CTL_166_MR_FSP_DATA_VALID_F3_0_FLDMASK (0x1)
#define HWIO_DDR_CTL_166_MR_FSP_DATA_VALID_F3_0_FLDSHFT (0)
#define HWIO_DDR_CTL_166_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_166_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_166_MR16_DATA_0_FLDMASK (0xff00)
#define HWIO_DDR_CTL_166_MR16_DATA_0_FLDSHFT (8)
#define HWIO_DDR_CTL_166_MR17_DATA_0_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_166_MR17_DATA_0_FLDSHFT (16)
#define HWIO_DDR_CTL_166_MR20_DATA_0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_166_MR20_DATA_0_FLDSHFT (24)

#define HWIO_DDR_CTL_167_REGOFF 0x29c
#define HWIO_DDR_CTL_167_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_167_REGOFF)
#define HWIO_DDR_CTL_167_MR22_DATA_F0_0_FLDMASK (0xff)
#define HWIO_DDR_CTL_167_MR22_DATA_F0_0_FLDSHFT (0)
#define HWIO_DDR_CTL_167_MR22_DATA_F1_0_FLDMASK (0xff00)
#define HWIO_DDR_CTL_167_MR22_DATA_F1_0_FLDSHFT (8)
#define HWIO_DDR_CTL_167_MR22_DATA_F2_0_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_167_MR22_DATA_F2_0_FLDSHFT (16)
#define HWIO_DDR_CTL_167_MR22_DATA_F3_0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_167_MR22_DATA_F3_0_FLDSHFT (24)

#define HWIO_DDR_CTL_168_REGOFF 0x2a0
#define HWIO_DDR_CTL_168_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_168_REGOFF)
#define HWIO_DDR_CTL_168_RL3_SUPPORT_EN_FLDMASK (0x1)
#define HWIO_DDR_CTL_168_RL3_SUPPORT_EN_FLDSHFT (0)
#define HWIO_DDR_CTL_168_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_168_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_168_CDNS_INTRL1_FLDMASK (0x100)
#define HWIO_DDR_CTL_168_CDNS_INTRL1_FLDSHFT (8)
#define HWIO_DDR_CTL_168_CDNS_INTRL3_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_168_CDNS_INTRL3_FLDSHFT (9)
#define HWIO_DDR_CTL_168_CDNS_INTRL2_FLDMASK (0x10000)
#define HWIO_DDR_CTL_168_CDNS_INTRL2_FLDSHFT (16)
#define HWIO_DDR_CTL_168_RESERVED4_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_168_RESERVED4_FLDSHFT (17)
#define HWIO_DDR_CTL_168_FSP_PHY_UPDATE_MRW_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_168_FSP_PHY_UPDATE_MRW_FLDSHFT (24)
#define HWIO_DDR_CTL_168_RESERVED5_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_168_RESERVED5_FLDSHFT (25)

#define HWIO_DDR_CTL_169_REGOFF 0x2a4
#define HWIO_DDR_CTL_169_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_169_REGOFF)
#define HWIO_DDR_CTL_169_DFS_ALWAYS_WRITE_FSP_FLDMASK (0x1)
#define HWIO_DDR_CTL_169_DFS_ALWAYS_WRITE_FSP_FLDSHFT (0)
#define HWIO_DDR_CTL_169_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_169_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_169_FSP_STATUS_FLDMASK (0x100)
#define HWIO_DDR_CTL_169_FSP_STATUS_FLDSHFT (8)
#define HWIO_DDR_CTL_169_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_169_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_169_FSP_OP_CURRENT_FLDMASK (0x10000)
#define HWIO_DDR_CTL_169_FSP_OP_CURRENT_FLDSHFT (16)
#define HWIO_DDR_CTL_169_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_169_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_169_FSP_WR_CURRENT_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_169_FSP_WR_CURRENT_FLDSHFT (24)
#define HWIO_DDR_CTL_169_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_169_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_170_REGOFF 0x2a8
#define HWIO_DDR_CTL_170_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_170_REGOFF)
#define HWIO_DDR_CTL_170_FSP0_FRC_VALID_FLDMASK (0x1)
#define HWIO_DDR_CTL_170_FSP0_FRC_VALID_FLDSHFT (0)
#define HWIO_DDR_CTL_170_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_170_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_170_FSP1_FRC_VALID_FLDMASK (0x100)
#define HWIO_DDR_CTL_170_FSP1_FRC_VALID_FLDSHFT (8)
#define HWIO_DDR_CTL_170_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_170_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_170_FSP0_FRC_FLDMASK (0x30000)
#define HWIO_DDR_CTL_170_FSP0_FRC_FLDSHFT (16)
#define HWIO_DDR_CTL_170_CDNS_INTRL2_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_170_CDNS_INTRL2_FLDSHFT (18)
#define HWIO_DDR_CTL_170_FSP1_FRC_FLDMASK (0x3000000)
#define HWIO_DDR_CTL_170_FSP1_FRC_FLDSHFT (24)
#define HWIO_DDR_CTL_170_CDNS_INTRL3_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_170_CDNS_INTRL3_FLDSHFT (26)

#define HWIO_DDR_CTL_171_REGOFF 0x2ac
#define HWIO_DDR_CTL_171_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_171_REGOFF)
#define HWIO_DDR_CTL_171_BIST_GO_FLDMASK (0x1)
#define HWIO_DDR_CTL_171_BIST_GO_FLDSHFT (0)
#define HWIO_DDR_CTL_171_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_171_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_171_BIST_RESULT_FLDMASK (0x300)
#define HWIO_DDR_CTL_171_BIST_RESULT_FLDSHFT (8)
#define HWIO_DDR_CTL_171_CDNS_INTRL1_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_171_CDNS_INTRL1_FLDSHFT (10)
#define HWIO_DDR_CTL_171_ADDR_SPACE_FLDMASK (0x3f0000)
#define HWIO_DDR_CTL_171_ADDR_SPACE_FLDSHFT (16)
#define HWIO_DDR_CTL_171_CDNS_INTRL2_FLDMASK (0xc00000)
#define HWIO_DDR_CTL_171_CDNS_INTRL2_FLDSHFT (22)
#define HWIO_DDR_CTL_171_BIST_DATA_CHECK_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_171_BIST_DATA_CHECK_FLDSHFT (24)
#define HWIO_DDR_CTL_171_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_171_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_172_REGOFF 0x2b0
#define HWIO_DDR_CTL_172_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_172_REGOFF)
#define HWIO_DDR_CTL_172_BIST_ADDR_CHECK_FLDMASK (0x1)
#define HWIO_DDR_CTL_172_BIST_ADDR_CHECK_FLDSHFT (0)
#define HWIO_DDR_CTL_172_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_172_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_172_OBSOLETE1_FLDMASK (0xffffff00)
#define HWIO_DDR_CTL_172_OBSOLETE1_FLDSHFT (8)

#define HWIO_DDR_CTL_173_REGOFF 0x2b4
#define HWIO_DDR_CTL_173_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_173_REGOFF)
#define HWIO_DDR_CTL_173_BIST_START_ADDRESS_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_173_BIST_START_ADDRESS_FLDSHFT (0)

#define HWIO_DDR_CTL_174_REGOFF 0x2b8
#define HWIO_DDR_CTL_174_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_174_REGOFF)
#define HWIO_DDR_CTL_174_OBSOLETE0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_174_OBSOLETE0_FLDSHFT (0)

#define HWIO_DDR_CTL_175_REGOFF 0x2bc
#define HWIO_DDR_CTL_175_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_175_REGOFF)
#define HWIO_DDR_CTL_175_BIST_DATA_MASK_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_175_BIST_DATA_MASK_FLDSHFT (0)

#define HWIO_DDR_CTL_176_REGOFF 0x2c0
#define HWIO_DDR_CTL_176_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_176_REGOFF)
#define HWIO_DDR_CTL_176_BIST_DATA_MASK_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_176_BIST_DATA_MASK_FLDSHFT (0)

#define HWIO_DDR_CTL_177_REGOFF 0x2c4
#define HWIO_DDR_CTL_177_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_177_REGOFF)
#define HWIO_DDR_CTL_177_BIST_TEST_MODE_FLDMASK (0x7)
#define HWIO_DDR_CTL_177_BIST_TEST_MODE_FLDSHFT (0)
#define HWIO_DDR_CTL_177_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_CTL_177_RESERVED_FLDSHFT (3)
#define HWIO_DDR_CTL_177_OBSOLETE1_FLDMASK (0xffffff00)
#define HWIO_DDR_CTL_177_OBSOLETE1_FLDSHFT (8)

#define HWIO_DDR_CTL_178_REGOFF 0x2c8
#define HWIO_DDR_CTL_178_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_178_REGOFF)
#define HWIO_DDR_CTL_178_BIST_DATA_PATTERN_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_178_BIST_DATA_PATTERN_FLDSHFT (0)

#define HWIO_DDR_CTL_179_REGOFF 0x2cc
#define HWIO_DDR_CTL_179_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_179_REGOFF)
#define HWIO_DDR_CTL_179_BIST_DATA_PATTERN_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_179_BIST_DATA_PATTERN_FLDSHFT (0)

#define HWIO_DDR_CTL_180_REGOFF 0x2d0
#define HWIO_DDR_CTL_180_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_180_REGOFF)
#define HWIO_DDR_CTL_180_BIST_DATA_PATTERN_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_180_BIST_DATA_PATTERN_FLDSHFT (0)

#define HWIO_DDR_CTL_181_REGOFF 0x2d4
#define HWIO_DDR_CTL_181_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_181_REGOFF)
#define HWIO_DDR_CTL_181_BIST_DATA_PATTERN_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_181_BIST_DATA_PATTERN_FLDSHFT (0)

#define HWIO_DDR_CTL_182_REGOFF 0x2d8
#define HWIO_DDR_CTL_182_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_182_REGOFF)
#define HWIO_DDR_CTL_182_BIST_RET_STATE_EXIT_FLDMASK (0x1)
#define HWIO_DDR_CTL_182_BIST_RET_STATE_EXIT_FLDSHFT (0)
#define HWIO_DDR_CTL_182_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_182_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_182_BIST_RET_STATE_FLDMASK (0x100)
#define HWIO_DDR_CTL_182_BIST_RET_STATE_FLDSHFT (8)
#define HWIO_DDR_CTL_182_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_182_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_182_BIST_ERR_STOP_FLDMASK (0xfff0000)
#define HWIO_DDR_CTL_182_BIST_ERR_STOP_FLDSHFT (16)
#define HWIO_DDR_CTL_182_CDNS_INTRL2_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_182_CDNS_INTRL2_FLDSHFT (28)

#define HWIO_DDR_CTL_183_REGOFF 0x2dc
#define HWIO_DDR_CTL_183_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_183_REGOFF)
#define HWIO_DDR_CTL_183_BIST_ERR_COUNT_FLDMASK (0xfff)
#define HWIO_DDR_CTL_183_BIST_ERR_COUNT_FLDSHFT (0)
#define HWIO_DDR_CTL_183_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_CTL_183_RESERVED_FLDSHFT (12)
#define HWIO_DDR_CTL_183_LONG_COUNT_MASK_FLDMASK (0x1f0000)
#define HWIO_DDR_CTL_183_LONG_COUNT_MASK_FLDSHFT (16)
#define HWIO_DDR_CTL_183_CDNS_INTRL1_FLDMASK (0xe00000)
#define HWIO_DDR_CTL_183_CDNS_INTRL1_FLDSHFT (21)
#define HWIO_DDR_CTL_183_AREF_NORM_THRESHOLD_FLDMASK (0x1f000000)
#define HWIO_DDR_CTL_183_AREF_NORM_THRESHOLD_FLDSHFT (24)
#define HWIO_DDR_CTL_183_CDNS_INTRL2_FLDMASK (0xe0000000)
#define HWIO_DDR_CTL_183_CDNS_INTRL2_FLDSHFT (29)

#define HWIO_DDR_CTL_184_REGOFF 0x2e0
#define HWIO_DDR_CTL_184_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_184_REGOFF)
#define HWIO_DDR_CTL_184_AREF_HIGH_THRESHOLD_FLDMASK (0x1f)
#define HWIO_DDR_CTL_184_AREF_HIGH_THRESHOLD_FLDSHFT (0)
#define HWIO_DDR_CTL_184_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_CTL_184_RESERVED_FLDSHFT (5)
#define HWIO_DDR_CTL_184_AREF_MAX_DEFICIT_FLDMASK (0x1f00)
#define HWIO_DDR_CTL_184_AREF_MAX_DEFICIT_FLDSHFT (8)
#define HWIO_DDR_CTL_184_CDNS_INTRL1_FLDMASK (0xe000)
#define HWIO_DDR_CTL_184_CDNS_INTRL1_FLDSHFT (13)
#define HWIO_DDR_CTL_184_AREF_MAX_CREDIT_FLDMASK (0x1f0000)
#define HWIO_DDR_CTL_184_AREF_MAX_CREDIT_FLDSHFT (16)
#define HWIO_DDR_CTL_184_CDNS_INTRL2_FLDMASK (0xe00000)
#define HWIO_DDR_CTL_184_CDNS_INTRL2_FLDSHFT (21)
#define HWIO_DDR_CTL_184_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_184_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_CTL_185_REGOFF 0x2e4
#define HWIO_DDR_CTL_185_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_185_REGOFF)
#define HWIO_DDR_CTL_185_ZQ_CALSTART_NORM_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_185_ZQ_CALSTART_NORM_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_185_ZQ_CALSTART_HIGH_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_185_ZQ_CALSTART_HIGH_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_186_REGOFF 0x2e8
#define HWIO_DDR_CTL_186_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_186_REGOFF)
#define HWIO_DDR_CTL_186_ZQ_CALLATCH_HIGH_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_186_ZQ_CALLATCH_HIGH_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_186_ZQ_CS_NORM_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_186_ZQ_CS_NORM_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_187_REGOFF 0x2ec
#define HWIO_DDR_CTL_187_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_187_REGOFF)
#define HWIO_DDR_CTL_187_ZQ_CS_HIGH_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_187_ZQ_CS_HIGH_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_187_ZQ_CALSTART_TIMEOUT_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_187_ZQ_CALSTART_TIMEOUT_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_188_REGOFF 0x2f0
#define HWIO_DDR_CTL_188_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_188_REGOFF)
#define HWIO_DDR_CTL_188_ZQ_CALLATCH_TIMEOUT_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_188_ZQ_CALLATCH_TIMEOUT_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_188_ZQ_CS_TIMEOUT_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_188_ZQ_CS_TIMEOUT_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_189_REGOFF 0x2f4
#define HWIO_DDR_CTL_189_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_189_REGOFF)
#define HWIO_DDR_CTL_189_ZQ_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_189_ZQ_PROMOTE_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_189_ZQ_CALSTART_NORM_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_189_ZQ_CALSTART_NORM_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_190_REGOFF 0x2f8
#define HWIO_DDR_CTL_190_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_190_REGOFF)
#define HWIO_DDR_CTL_190_ZQ_CALSTART_HIGH_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_190_ZQ_CALSTART_HIGH_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_190_ZQ_CALLATCH_HIGH_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_190_ZQ_CALLATCH_HIGH_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_191_REGOFF 0x2fc
#define HWIO_DDR_CTL_191_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_191_REGOFF)
#define HWIO_DDR_CTL_191_ZQ_CS_NORM_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_191_ZQ_CS_NORM_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_191_ZQ_CS_HIGH_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_191_ZQ_CS_HIGH_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_192_REGOFF 0x300
#define HWIO_DDR_CTL_192_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_192_REGOFF)
#define HWIO_DDR_CTL_192_ZQ_CALSTART_TIMEOUT_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_192_ZQ_CALSTART_TIMEOUT_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_192_ZQ_CALLATCH_TIMEOUT_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_192_ZQ_CALLATCH_TIMEOUT_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_193_REGOFF 0x304
#define HWIO_DDR_CTL_193_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_193_REGOFF)
#define HWIO_DDR_CTL_193_ZQ_CS_TIMEOUT_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_193_ZQ_CS_TIMEOUT_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_193_ZQ_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_193_ZQ_PROMOTE_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_194_REGOFF 0x308
#define HWIO_DDR_CTL_194_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_194_REGOFF)
#define HWIO_DDR_CTL_194_ZQ_CALSTART_NORM_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_194_ZQ_CALSTART_NORM_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_194_ZQ_CALSTART_HIGH_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_194_ZQ_CALSTART_HIGH_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_195_REGOFF 0x30c
#define HWIO_DDR_CTL_195_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_195_REGOFF)
#define HWIO_DDR_CTL_195_ZQ_CALLATCH_HIGH_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_195_ZQ_CALLATCH_HIGH_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_195_ZQ_CS_NORM_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_195_ZQ_CS_NORM_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_196_REGOFF 0x310
#define HWIO_DDR_CTL_196_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_196_REGOFF)
#define HWIO_DDR_CTL_196_ZQ_CS_HIGH_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_196_ZQ_CS_HIGH_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_196_ZQ_CALSTART_TIMEOUT_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_196_ZQ_CALSTART_TIMEOUT_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_197_REGOFF 0x314
#define HWIO_DDR_CTL_197_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_197_REGOFF)
#define HWIO_DDR_CTL_197_ZQ_CALLATCH_TIMEOUT_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_197_ZQ_CALLATCH_TIMEOUT_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_197_ZQ_CS_TIMEOUT_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_197_ZQ_CS_TIMEOUT_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_198_REGOFF 0x318
#define HWIO_DDR_CTL_198_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_198_REGOFF)
#define HWIO_DDR_CTL_198_ZQ_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_198_ZQ_PROMOTE_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_198_ZQ_CALSTART_NORM_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_198_ZQ_CALSTART_NORM_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_199_REGOFF 0x31c
#define HWIO_DDR_CTL_199_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_199_REGOFF)
#define HWIO_DDR_CTL_199_ZQ_CALSTART_HIGH_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_199_ZQ_CALSTART_HIGH_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_199_ZQ_CALLATCH_HIGH_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_199_ZQ_CALLATCH_HIGH_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_200_REGOFF 0x320
#define HWIO_DDR_CTL_200_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_200_REGOFF)
#define HWIO_DDR_CTL_200_ZQ_CS_NORM_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_200_ZQ_CS_NORM_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_200_ZQ_CS_HIGH_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_200_ZQ_CS_HIGH_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_201_REGOFF 0x324
#define HWIO_DDR_CTL_201_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_201_REGOFF)
#define HWIO_DDR_CTL_201_ZQ_CALSTART_TIMEOUT_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_201_ZQ_CALSTART_TIMEOUT_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_201_ZQ_CALLATCH_TIMEOUT_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_201_ZQ_CALLATCH_TIMEOUT_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_202_REGOFF 0x328
#define HWIO_DDR_CTL_202_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_202_REGOFF)
#define HWIO_DDR_CTL_202_ZQ_CS_TIMEOUT_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_202_ZQ_CS_TIMEOUT_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_202_ZQ_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_202_ZQ_PROMOTE_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_203_REGOFF 0x32c
#define HWIO_DDR_CTL_203_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_203_REGOFF)
#define HWIO_DDR_CTL_203_CDNS_INTRL0_FLDMASK (0x7)
#define HWIO_DDR_CTL_203_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_203_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_CTL_203_RESERVED_FLDSHFT (3)
#define HWIO_DDR_CTL_203_ZQINIT_F0_FLDMASK (0xfff00)
#define HWIO_DDR_CTL_203_ZQINIT_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_203_CDNS_INTRL1_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_203_CDNS_INTRL1_FLDSHFT (20)
#define HWIO_DDR_CTL_203_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_203_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_204_REGOFF 0x330
#define HWIO_DDR_CTL_204_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_204_REGOFF)
#define HWIO_DDR_CTL_204_ZQCL_F0_FLDMASK (0xfff)
#define HWIO_DDR_CTL_204_ZQCL_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_204_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_CTL_204_RESERVED_FLDSHFT (12)
#define HWIO_DDR_CTL_204_ZQCS_F0_FLDMASK (0xfff0000)
#define HWIO_DDR_CTL_204_ZQCS_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_204_CDNS_INTRL1_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_204_CDNS_INTRL1_FLDSHFT (28)

#define HWIO_DDR_CTL_205_REGOFF 0x334
#define HWIO_DDR_CTL_205_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_205_REGOFF)
#define HWIO_DDR_CTL_205_TZQCAL_F0_FLDMASK (0xfff)
#define HWIO_DDR_CTL_205_TZQCAL_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_205_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_CTL_205_RESERVED_FLDSHFT (12)
#define HWIO_DDR_CTL_205_TZQLAT_F0_FLDMASK (0x3f0000)
#define HWIO_DDR_CTL_205_TZQLAT_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_205_CDNS_INTRL1_FLDMASK (0xc00000)
#define HWIO_DDR_CTL_205_CDNS_INTRL1_FLDSHFT (22)
#define HWIO_DDR_CTL_205_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_205_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_206_REGOFF 0x338
#define HWIO_DDR_CTL_206_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_206_REGOFF)
#define HWIO_DDR_CTL_206_ZQINIT_F1_FLDMASK (0xfff)
#define HWIO_DDR_CTL_206_ZQINIT_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_206_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_CTL_206_RESERVED_FLDSHFT (12)
#define HWIO_DDR_CTL_206_ZQCL_F1_FLDMASK (0xfff0000)
#define HWIO_DDR_CTL_206_ZQCL_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_206_CDNS_INTRL1_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_206_CDNS_INTRL1_FLDSHFT (28)

#define HWIO_DDR_CTL_207_REGOFF 0x33c
#define HWIO_DDR_CTL_207_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_207_REGOFF)
#define HWIO_DDR_CTL_207_ZQCS_F1_FLDMASK (0xfff)
#define HWIO_DDR_CTL_207_ZQCS_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_207_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_CTL_207_RESERVED_FLDSHFT (12)
#define HWIO_DDR_CTL_207_TZQCAL_F1_FLDMASK (0xfff0000)
#define HWIO_DDR_CTL_207_TZQCAL_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_207_CDNS_INTRL1_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_207_CDNS_INTRL1_FLDSHFT (28)

#define HWIO_DDR_CTL_208_REGOFF 0x340
#define HWIO_DDR_CTL_208_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_208_REGOFF)
#define HWIO_DDR_CTL_208_TZQLAT_F1_FLDMASK (0x3f)
#define HWIO_DDR_CTL_208_TZQLAT_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_208_RESERVED_FLDMASK (0xc0)
#define HWIO_DDR_CTL_208_RESERVED_FLDSHFT (6)
#define HWIO_DDR_CTL_208_ZQINIT_F2_FLDMASK (0xfff00)
#define HWIO_DDR_CTL_208_ZQINIT_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_208_CDNS_INTRL1_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_208_CDNS_INTRL1_FLDSHFT (20)
#define HWIO_DDR_CTL_208_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_208_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_209_REGOFF 0x344
#define HWIO_DDR_CTL_209_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_209_REGOFF)
#define HWIO_DDR_CTL_209_ZQCL_F2_FLDMASK (0xfff)
#define HWIO_DDR_CTL_209_ZQCL_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_209_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_CTL_209_RESERVED_FLDSHFT (12)
#define HWIO_DDR_CTL_209_ZQCS_F2_FLDMASK (0xfff0000)
#define HWIO_DDR_CTL_209_ZQCS_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_209_CDNS_INTRL1_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_209_CDNS_INTRL1_FLDSHFT (28)

#define HWIO_DDR_CTL_210_REGOFF 0x348
#define HWIO_DDR_CTL_210_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_210_REGOFF)
#define HWIO_DDR_CTL_210_TZQCAL_F2_FLDMASK (0xfff)
#define HWIO_DDR_CTL_210_TZQCAL_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_210_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_CTL_210_RESERVED_FLDSHFT (12)
#define HWIO_DDR_CTL_210_TZQLAT_F2_FLDMASK (0x3f0000)
#define HWIO_DDR_CTL_210_TZQLAT_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_210_CDNS_INTRL1_FLDMASK (0xc00000)
#define HWIO_DDR_CTL_210_CDNS_INTRL1_FLDSHFT (22)
#define HWIO_DDR_CTL_210_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_210_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_211_REGOFF 0x34c
#define HWIO_DDR_CTL_211_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_211_REGOFF)
#define HWIO_DDR_CTL_211_ZQINIT_F3_FLDMASK (0xfff)
#define HWIO_DDR_CTL_211_ZQINIT_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_211_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_CTL_211_RESERVED_FLDSHFT (12)
#define HWIO_DDR_CTL_211_ZQCL_F3_FLDMASK (0xfff0000)
#define HWIO_DDR_CTL_211_ZQCL_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_211_CDNS_INTRL1_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_211_CDNS_INTRL1_FLDSHFT (28)

#define HWIO_DDR_CTL_212_REGOFF 0x350
#define HWIO_DDR_CTL_212_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_212_REGOFF)
#define HWIO_DDR_CTL_212_ZQCS_F3_FLDMASK (0xfff)
#define HWIO_DDR_CTL_212_ZQCS_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_212_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_CTL_212_RESERVED_FLDSHFT (12)
#define HWIO_DDR_CTL_212_TZQCAL_F3_FLDMASK (0xfff0000)
#define HWIO_DDR_CTL_212_TZQCAL_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_212_CDNS_INTRL1_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_212_CDNS_INTRL1_FLDSHFT (28)

#define HWIO_DDR_CTL_213_REGOFF 0x354
#define HWIO_DDR_CTL_213_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_213_REGOFF)
#define HWIO_DDR_CTL_213_TZQLAT_F3_FLDMASK (0x3f)
#define HWIO_DDR_CTL_213_TZQLAT_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_213_RESERVED_FLDMASK (0xc0)
#define HWIO_DDR_CTL_213_RESERVED_FLDSHFT (6)
#define HWIO_DDR_CTL_213_ZQ_REQ_FLDMASK (0xf00)
#define HWIO_DDR_CTL_213_ZQ_REQ_FLDSHFT (8)
#define HWIO_DDR_CTL_213_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_213_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_213_ZQ_REQ_PENDING_FLDMASK (0x10000)
#define HWIO_DDR_CTL_213_ZQ_REQ_PENDING_FLDSHFT (16)
#define HWIO_DDR_CTL_213_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_213_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_213_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_213_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_CTL_214_REGOFF 0x358
#define HWIO_DDR_CTL_214_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_214_REGOFF)
#define HWIO_DDR_CTL_214_ZQRESET_F0_FLDMASK (0xfff)
#define HWIO_DDR_CTL_214_ZQRESET_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_214_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_CTL_214_RESERVED_FLDSHFT (12)
#define HWIO_DDR_CTL_214_ZQRESET_F1_FLDMASK (0xfff0000)
#define HWIO_DDR_CTL_214_ZQRESET_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_214_CDNS_INTRL1_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_214_CDNS_INTRL1_FLDSHFT (28)

#define HWIO_DDR_CTL_215_REGOFF 0x35c
#define HWIO_DDR_CTL_215_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_215_REGOFF)
#define HWIO_DDR_CTL_215_ZQRESET_F2_FLDMASK (0xfff)
#define HWIO_DDR_CTL_215_ZQRESET_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_215_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_CTL_215_RESERVED_FLDSHFT (12)
#define HWIO_DDR_CTL_215_ZQRESET_F3_FLDMASK (0xfff0000)
#define HWIO_DDR_CTL_215_ZQRESET_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_215_CDNS_INTRL1_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_215_CDNS_INTRL1_FLDSHFT (28)

#define HWIO_DDR_CTL_216_REGOFF 0x360
#define HWIO_DDR_CTL_216_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_216_REGOFF)
#define HWIO_DDR_CTL_216_NO_ZQ_INIT_FLDMASK (0x1)
#define HWIO_DDR_CTL_216_NO_ZQ_INIT_FLDSHFT (0)
#define HWIO_DDR_CTL_216_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_216_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_216_BANK_DIFF_FLDMASK (0x300)
#define HWIO_DDR_CTL_216_BANK_DIFF_FLDSHFT (8)
#define HWIO_DDR_CTL_216_CDNS_INTRL1_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_216_CDNS_INTRL1_FLDSHFT (10)
#define HWIO_DDR_CTL_216_ROW_DIFF_FLDMASK (0x70000)
#define HWIO_DDR_CTL_216_ROW_DIFF_FLDSHFT (16)
#define HWIO_DDR_CTL_216_CDNS_INTRL2_FLDMASK (0xf80000)
#define HWIO_DDR_CTL_216_CDNS_INTRL2_FLDSHFT (19)
#define HWIO_DDR_CTL_216_COL_DIFF_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_216_COL_DIFF_FLDSHFT (24)
#define HWIO_DDR_CTL_216_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_216_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_217_REGOFF 0x364
#define HWIO_DDR_CTL_217_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_217_REGOFF)
#define HWIO_DDR_CTL_217_BANK_START_BIT_FLDMASK (0x1f)
#define HWIO_DDR_CTL_217_BANK_START_BIT_FLDSHFT (0)
#define HWIO_DDR_CTL_217_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_CTL_217_RESERVED_FLDSHFT (5)
#define HWIO_DDR_CTL_217_BANK_ADDR_INTLV_EN_FLDMASK (0x100)
#define HWIO_DDR_CTL_217_BANK_ADDR_INTLV_EN_FLDSHFT (8)
#define HWIO_DDR_CTL_217_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_217_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_217_APREBIT_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_217_APREBIT_FLDSHFT (16)
#define HWIO_DDR_CTL_217_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_217_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_217_AGE_COUNT_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_217_AGE_COUNT_FLDSHFT (24)

#define HWIO_DDR_CTL_218_REGOFF 0x368
#define HWIO_DDR_CTL_218_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_218_REGOFF)
#define HWIO_DDR_CTL_218_COMMAND_AGE_COUNT_FLDMASK (0xff)
#define HWIO_DDR_CTL_218_COMMAND_AGE_COUNT_FLDSHFT (0)
#define HWIO_DDR_CTL_218_ADDR_CMP_EN_FLDMASK (0x100)
#define HWIO_DDR_CTL_218_ADDR_CMP_EN_FLDSHFT (8)
#define HWIO_DDR_CTL_218_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_218_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_218_CDNS_INTRL2_FLDMASK (0x10000)
#define HWIO_DDR_CTL_218_CDNS_INTRL2_FLDSHFT (16)
#define HWIO_DDR_CTL_218_CDNS_INTRL1_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_218_CDNS_INTRL1_FLDSHFT (17)
#define HWIO_DDR_CTL_218_BANK_SPLIT_EN_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_218_BANK_SPLIT_EN_FLDSHFT (24)
#define HWIO_DDR_CTL_218_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_218_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_219_REGOFF 0x36c
#define HWIO_DDR_CTL_219_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_219_REGOFF)
#define HWIO_DDR_CTL_219_PLACEMENT_EN_FLDMASK (0x1)
#define HWIO_DDR_CTL_219_PLACEMENT_EN_FLDSHFT (0)
#define HWIO_DDR_CTL_219_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_219_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_219_PRIORITY_EN_FLDMASK (0x100)
#define HWIO_DDR_CTL_219_PRIORITY_EN_FLDSHFT (8)
#define HWIO_DDR_CTL_219_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_219_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_219_RW_SAME_EN_FLDMASK (0x10000)
#define HWIO_DDR_CTL_219_RW_SAME_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_219_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_219_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_219_RW_SAME_PAGE_EN_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_219_RW_SAME_PAGE_EN_FLDSHFT (24)
#define HWIO_DDR_CTL_219_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_219_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_220_REGOFF 0x370
#define HWIO_DDR_CTL_220_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_220_REGOFF)
#define HWIO_DDR_CTL_220_DISABLE_RW_GROUP_W_BNK_CONFLICT_FLDMASK (0x3)
#define HWIO_DDR_CTL_220_DISABLE_RW_GROUP_W_BNK_CONFLICT_FLDSHFT (0)
#define HWIO_DDR_CTL_220_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_CTL_220_RESERVED_FLDSHFT (2)
#define HWIO_DDR_CTL_220_NUM_Q_ENTRIES_ACT_DISABLE_FLDMASK (0xf00)
#define HWIO_DDR_CTL_220_NUM_Q_ENTRIES_ACT_DISABLE_FLDSHFT (8)
#define HWIO_DDR_CTL_220_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_220_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_220_SWAP_EN_FLDMASK (0x10000)
#define HWIO_DDR_CTL_220_SWAP_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_220_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_220_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_220_DISABLE_RD_INTERLEAVE_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_220_DISABLE_RD_INTERLEAVE_FLDSHFT (24)
#define HWIO_DDR_CTL_220_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_220_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_221_REGOFF 0x374
#define HWIO_DDR_CTL_221_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_221_REGOFF)
#define HWIO_DDR_CTL_221_INHIBIT_DRAM_CMD_FLDMASK (0x3)
#define HWIO_DDR_CTL_221_INHIBIT_DRAM_CMD_FLDSHFT (0)
#define HWIO_DDR_CTL_221_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_CTL_221_RESERVED_FLDSHFT (2)
#define HWIO_DDR_CTL_221_REDUC_FLDMASK (0x100)
#define HWIO_DDR_CTL_221_REDUC_FLDSHFT (8)
#define HWIO_DDR_CTL_221_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_221_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_221_MEMDATA_RATIO_0_FLDMASK (0x70000)
#define HWIO_DDR_CTL_221_MEMDATA_RATIO_0_FLDSHFT (16)
#define HWIO_DDR_CTL_221_CDNS_INTRL2_FLDMASK (0xf80000)
#define HWIO_DDR_CTL_221_CDNS_INTRL2_FLDSHFT (19)
#define HWIO_DDR_CTL_221_CDNS_INTRL3_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_221_CDNS_INTRL3_FLDSHFT (24)
#define HWIO_DDR_CTL_221_RESERVED4_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_221_RESERVED4_FLDSHFT (28)

#define HWIO_DDR_CTL_222_REGOFF 0x378
#define HWIO_DDR_CTL_222_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_222_REGOFF)
#define HWIO_DDR_CTL_222_CDNS_INTRL0_FLDMASK (0xf)
#define HWIO_DDR_CTL_222_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_222_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_222_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_222_CDNS_INTRL1_FLDMASK (0xf00)
#define HWIO_DDR_CTL_222_CDNS_INTRL1_FLDSHFT (8)
#define HWIO_DDR_CTL_222_CDNS_INTRL3_FLDMASK (0xf000)
#define HWIO_DDR_CTL_222_CDNS_INTRL3_FLDSHFT (12)
#define HWIO_DDR_CTL_222_CDNS_INTRL2_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_222_CDNS_INTRL2_FLDSHFT (16)
#define HWIO_DDR_CTL_222_RESERVED4_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_222_RESERVED4_FLDSHFT (20)
#define HWIO_DDR_CTL_222_Q_FULLNESS_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_222_Q_FULLNESS_FLDSHFT (24)
#define HWIO_DDR_CTL_222_RESERVED5_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_222_RESERVED5_FLDSHFT (28)

#define HWIO_DDR_CTL_223_REGOFF 0x37c
#define HWIO_DDR_CTL_223_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_223_REGOFF)
#define HWIO_DDR_CTL_223_IN_ORDER_ACCEPT_FLDMASK (0x1)
#define HWIO_DDR_CTL_223_IN_ORDER_ACCEPT_FLDSHFT (0)
#define HWIO_DDR_CTL_223_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_223_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_223_CONTROLLER_BUSY_FLDMASK (0x100)
#define HWIO_DDR_CTL_223_CONTROLLER_BUSY_FLDSHFT (8)
#define HWIO_DDR_CTL_223_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_223_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_223_CTRLUPD_REQ_FLDMASK (0x10000)
#define HWIO_DDR_CTL_223_CTRLUPD_REQ_FLDSHFT (16)
#define HWIO_DDR_CTL_223_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_223_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_223_CTRLUPD_REQ_PER_AREF_EN_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_223_CTRLUPD_REQ_PER_AREF_EN_FLDSHFT (24)
#define HWIO_DDR_CTL_223_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_223_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_224_REGOFF 0x380
#define HWIO_DDR_CTL_224_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_224_REGOFF)
#define HWIO_DDR_CTL_224_PREAMBLE_SUPPORT_F0_FLDMASK (0x3)
#define HWIO_DDR_CTL_224_PREAMBLE_SUPPORT_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_224_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_CTL_224_RESERVED_FLDSHFT (2)
#define HWIO_DDR_CTL_224_PREAMBLE_SUPPORT_F1_FLDMASK (0x300)
#define HWIO_DDR_CTL_224_PREAMBLE_SUPPORT_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_224_CDNS_INTRL1_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_224_CDNS_INTRL1_FLDSHFT (10)
#define HWIO_DDR_CTL_224_PREAMBLE_SUPPORT_F2_FLDMASK (0x30000)
#define HWIO_DDR_CTL_224_PREAMBLE_SUPPORT_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_224_CDNS_INTRL2_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_224_CDNS_INTRL2_FLDSHFT (18)
#define HWIO_DDR_CTL_224_PREAMBLE_SUPPORT_F3_FLDMASK (0x3000000)
#define HWIO_DDR_CTL_224_PREAMBLE_SUPPORT_F3_FLDSHFT (24)
#define HWIO_DDR_CTL_224_CDNS_INTRL3_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_224_CDNS_INTRL3_FLDSHFT (26)

#define HWIO_DDR_CTL_225_REGOFF 0x384
#define HWIO_DDR_CTL_225_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_225_REGOFF)
#define HWIO_DDR_CTL_225_RD_PREAMBLE_TRAINING_EN_FLDMASK (0x1)
#define HWIO_DDR_CTL_225_RD_PREAMBLE_TRAINING_EN_FLDSHFT (0)
#define HWIO_DDR_CTL_225_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_225_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_225_WR_DBI_EN_FLDMASK (0x100)
#define HWIO_DDR_CTL_225_WR_DBI_EN_FLDSHFT (8)
#define HWIO_DDR_CTL_225_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_225_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_225_RD_DBI_EN_FLDMASK (0x10000)
#define HWIO_DDR_CTL_225_RD_DBI_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_225_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_225_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_225_DFI_ERROR_FLDMASK (0x1f000000)
#define HWIO_DDR_CTL_225_DFI_ERROR_FLDSHFT (24)
#define HWIO_DDR_CTL_225_CDNS_INTRL3_FLDMASK (0xe0000000)
#define HWIO_DDR_CTL_225_CDNS_INTRL3_FLDSHFT (29)

#define HWIO_DDR_CTL_226_REGOFF 0x388
#define HWIO_DDR_CTL_226_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_226_REGOFF)
#define HWIO_DDR_CTL_226_DFI_ERROR_INFO_FLDMASK (0xfffff)
#define HWIO_DDR_CTL_226_DFI_ERROR_INFO_FLDSHFT (0)
#define HWIO_DDR_CTL_226_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_226_RESERVED_FLDSHFT (20)
#define HWIO_DDR_CTL_226_CDNS_INTRL1_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_226_CDNS_INTRL1_FLDSHFT (24)
#define HWIO_DDR_CTL_226_CDNS_INTRL2_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_226_CDNS_INTRL2_FLDSHFT (25)

#define HWIO_DDR_CTL_227_REGOFF 0x38c
#define HWIO_DDR_CTL_227_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_227_REGOFF)
#define HWIO_DDR_CTL_227_INT_STATUS_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_227_INT_STATUS_FLDSHFT (0)

#define HWIO_DDR_CTL_228_REGOFF 0x390
#define HWIO_DDR_CTL_228_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_228_REGOFF)
#define HWIO_DDR_CTL_228_INT_STATUS_FLDMASK (0xf)
#define HWIO_DDR_CTL_228_INT_STATUS_FLDSHFT (0)
#define HWIO_DDR_CTL_228_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_228_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_228_OBSOLETE1_FLDMASK (0xffffff00)
#define HWIO_DDR_CTL_228_OBSOLETE1_FLDSHFT (8)

#define HWIO_DDR_CTL_229_REGOFF 0x394
#define HWIO_DDR_CTL_229_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_229_REGOFF)
#define HWIO_DDR_CTL_229_INT_ACK_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_229_INT_ACK_FLDSHFT (0)

#define HWIO_DDR_CTL_230_REGOFF 0x398
#define HWIO_DDR_CTL_230_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_230_REGOFF)
#define HWIO_DDR_CTL_230_INT_ACK_FLDMASK (0x7)
#define HWIO_DDR_CTL_230_INT_ACK_FLDSHFT (0)
#define HWIO_DDR_CTL_230_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_CTL_230_RESERVED_FLDSHFT (3)
#define HWIO_DDR_CTL_230_OBSOLETE1_FLDMASK (0xffffff00)
#define HWIO_DDR_CTL_230_OBSOLETE1_FLDSHFT (8)

#define HWIO_DDR_CTL_231_REGOFF 0x39c
#define HWIO_DDR_CTL_231_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_231_REGOFF)
#define HWIO_DDR_CTL_231_INT_MASK_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_231_INT_MASK_FLDSHFT (0)

#define HWIO_DDR_CTL_232_REGOFF 0x3a0
#define HWIO_DDR_CTL_232_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_232_REGOFF)
#define HWIO_DDR_CTL_232_INT_MASK_FLDMASK (0xf)
#define HWIO_DDR_CTL_232_INT_MASK_FLDSHFT (0)
#define HWIO_DDR_CTL_232_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_232_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_232_OBSOLETE1_FLDMASK (0xffffff00)
#define HWIO_DDR_CTL_232_OBSOLETE1_FLDSHFT (8)

#define HWIO_DDR_CTL_233_REGOFF 0x3a4
#define HWIO_DDR_CTL_233_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_233_REGOFF)
#define HWIO_DDR_CTL_233_OUT_OF_RANGE_ADDR_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_233_OUT_OF_RANGE_ADDR_FLDSHFT (0)

#define HWIO_DDR_CTL_234_REGOFF 0x3a8
#define HWIO_DDR_CTL_234_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_234_REGOFF)
#define HWIO_DDR_CTL_234_OBSOLETE0_FLDMASK (0xff)
#define HWIO_DDR_CTL_234_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_234_OUT_OF_RANGE_LENGTH_FLDMASK (0xfff00)
#define HWIO_DDR_CTL_234_OUT_OF_RANGE_LENGTH_FLDSHFT (8)
#define HWIO_DDR_CTL_234_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_234_RESERVED_FLDSHFT (20)
#define HWIO_DDR_CTL_234_OUT_OF_RANGE_TYPE_FLDMASK (0x7f000000)
#define HWIO_DDR_CTL_234_OUT_OF_RANGE_TYPE_FLDSHFT (24)
#define HWIO_DDR_CTL_234_CDNS_INTRL1_FLDMASK (0x80000000)
#define HWIO_DDR_CTL_234_CDNS_INTRL1_FLDSHFT (31)

#define HWIO_DDR_CTL_235_REGOFF 0x3ac
#define HWIO_DDR_CTL_235_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_235_REGOFF)
#define HWIO_DDR_CTL_235_OBSOLETE0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_235_OBSOLETE0_FLDSHFT (0)

#define HWIO_DDR_CTL_236_REGOFF 0x3b0
#define HWIO_DDR_CTL_236_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_236_REGOFF)
#define HWIO_DDR_CTL_236_BIST_EXP_DATA_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_236_BIST_EXP_DATA_FLDSHFT (0)

#define HWIO_DDR_CTL_237_REGOFF 0x3b4
#define HWIO_DDR_CTL_237_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_237_REGOFF)
#define HWIO_DDR_CTL_237_BIST_EXP_DATA_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_237_BIST_EXP_DATA_FLDSHFT (0)

#define HWIO_DDR_CTL_238_REGOFF 0x3b8
#define HWIO_DDR_CTL_238_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_238_REGOFF)
#define HWIO_DDR_CTL_238_BIST_EXP_DATA_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_238_BIST_EXP_DATA_FLDSHFT (0)

#define HWIO_DDR_CTL_239_REGOFF 0x3bc
#define HWIO_DDR_CTL_239_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_239_REGOFF)
#define HWIO_DDR_CTL_239_BIST_EXP_DATA_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_239_BIST_EXP_DATA_FLDSHFT (0)

#define HWIO_DDR_CTL_240_REGOFF 0x3c0
#define HWIO_DDR_CTL_240_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_240_REGOFF)
#define HWIO_DDR_CTL_240_BIST_FAIL_DATA_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_240_BIST_FAIL_DATA_FLDSHFT (0)

#define HWIO_DDR_CTL_241_REGOFF 0x3c4
#define HWIO_DDR_CTL_241_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_241_REGOFF)
#define HWIO_DDR_CTL_241_BIST_FAIL_DATA_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_241_BIST_FAIL_DATA_FLDSHFT (0)

#define HWIO_DDR_CTL_242_REGOFF 0x3c8
#define HWIO_DDR_CTL_242_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_242_REGOFF)
#define HWIO_DDR_CTL_242_BIST_FAIL_DATA_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_242_BIST_FAIL_DATA_FLDSHFT (0)

#define HWIO_DDR_CTL_243_REGOFF 0x3cc
#define HWIO_DDR_CTL_243_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_243_REGOFF)
#define HWIO_DDR_CTL_243_BIST_FAIL_DATA_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_243_BIST_FAIL_DATA_FLDSHFT (0)

#define HWIO_DDR_CTL_244_REGOFF 0x3d0
#define HWIO_DDR_CTL_244_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_244_REGOFF)
#define HWIO_DDR_CTL_244_BIST_FAIL_ADDR_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_244_BIST_FAIL_ADDR_FLDSHFT (0)

#define HWIO_DDR_CTL_245_REGOFF 0x3d4
#define HWIO_DDR_CTL_245_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_245_REGOFF)
#define HWIO_DDR_CTL_245_OBSOLETE0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_245_OBSOLETE0_FLDSHFT (0)

#define HWIO_DDR_CTL_246_REGOFF 0x3d8
#define HWIO_DDR_CTL_246_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_246_REGOFF)
#define HWIO_DDR_CTL_246_PORT_CMD_ERROR_ADDR_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_246_PORT_CMD_ERROR_ADDR_FLDSHFT (0)

#define HWIO_DDR_CTL_247_REGOFF 0x3dc
#define HWIO_DDR_CTL_247_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_247_REGOFF)
#define HWIO_DDR_CTL_247_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_247_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_247_PORT_CMD_ERROR_TYPE_FLDMASK (0x70000)
#define HWIO_DDR_CTL_247_PORT_CMD_ERROR_TYPE_FLDSHFT (16)
#define HWIO_DDR_CTL_247_RESERVED_FLDMASK (0xf80000)
#define HWIO_DDR_CTL_247_RESERVED_FLDSHFT (19)
#define HWIO_DDR_CTL_247_TODTL_2CMD_F0_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_247_TODTL_2CMD_F0_FLDSHFT (24)

#define HWIO_DDR_CTL_248_REGOFF 0x3e0
#define HWIO_DDR_CTL_248_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_248_REGOFF)
#define HWIO_DDR_CTL_248_TODTH_WR_F0_FLDMASK (0xf)
#define HWIO_DDR_CTL_248_TODTH_WR_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_248_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_248_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_248_TODTL_2CMD_F1_FLDMASK (0xff00)
#define HWIO_DDR_CTL_248_TODTL_2CMD_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_248_TODTH_WR_F1_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_248_TODTH_WR_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_248_CDNS_INTRL1_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_248_CDNS_INTRL1_FLDSHFT (20)
#define HWIO_DDR_CTL_248_TODTL_2CMD_F2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_248_TODTL_2CMD_F2_FLDSHFT (24)

#define HWIO_DDR_CTL_249_REGOFF 0x3e4
#define HWIO_DDR_CTL_249_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_249_REGOFF)
#define HWIO_DDR_CTL_249_TODTH_WR_F2_FLDMASK (0xf)
#define HWIO_DDR_CTL_249_TODTH_WR_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_249_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_249_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_249_TODTL_2CMD_F3_FLDMASK (0xff00)
#define HWIO_DDR_CTL_249_TODTL_2CMD_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_249_TODTH_WR_F3_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_249_TODTH_WR_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_249_CDNS_INTRL1_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_249_CDNS_INTRL1_FLDSHFT (20)
#define HWIO_DDR_CTL_249_ODT_EN_F0_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_249_ODT_EN_F0_FLDSHFT (24)
#define HWIO_DDR_CTL_249_CDNS_INTRL2_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_249_CDNS_INTRL2_FLDSHFT (25)

#define HWIO_DDR_CTL_250_REGOFF 0x3e8
#define HWIO_DDR_CTL_250_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_250_REGOFF)
#define HWIO_DDR_CTL_250_ODT_EN_F1_FLDMASK (0x1)
#define HWIO_DDR_CTL_250_ODT_EN_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_250_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_250_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_250_ODT_EN_F2_FLDMASK (0x100)
#define HWIO_DDR_CTL_250_ODT_EN_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_250_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_250_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_250_ODT_EN_F3_FLDMASK (0x10000)
#define HWIO_DDR_CTL_250_ODT_EN_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_250_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_250_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_250_EN_ODT_ASSERT_EXCEPT_RD_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_250_EN_ODT_ASSERT_EXCEPT_RD_FLDSHFT (24)
#define HWIO_DDR_CTL_250_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_250_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_251_REGOFF 0x3ec
#define HWIO_DDR_CTL_251_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_251_REGOFF)
#define HWIO_DDR_CTL_251_CTLR_DISABLE_ODT_ON_ZQ_FLDMASK (0x1)
#define HWIO_DDR_CTL_251_CTLR_DISABLE_ODT_ON_ZQ_FLDSHFT (0)
#define HWIO_DDR_CTL_251_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_251_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_251_CDNS_INTRL1_FLDMASK (0x3f00)
#define HWIO_DDR_CTL_251_CDNS_INTRL1_FLDSHFT (8)
#define HWIO_DDR_CTL_251_CDNS_INTRL2_FLDMASK (0xc000)
#define HWIO_DDR_CTL_251_CDNS_INTRL2_FLDSHFT (14)
#define HWIO_DDR_CTL_251_RW2MRW_DLY_F0_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_251_RW2MRW_DLY_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_251_CDNS_INTRL3_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_251_CDNS_INTRL3_FLDSHFT (20)
#define HWIO_DDR_CTL_251_RW2MRW_DLY_F1_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_251_RW2MRW_DLY_F1_FLDSHFT (24)
#define HWIO_DDR_CTL_251_RESERVED4_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_251_RESERVED4_FLDSHFT (28)

#define HWIO_DDR_CTL_252_REGOFF 0x3f0
#define HWIO_DDR_CTL_252_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_252_REGOFF)
#define HWIO_DDR_CTL_252_RW2MRW_DLY_F2_FLDMASK (0xf)
#define HWIO_DDR_CTL_252_RW2MRW_DLY_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_252_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_252_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_252_RW2MRW_DLY_F3_FLDMASK (0xf00)
#define HWIO_DDR_CTL_252_RW2MRW_DLY_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_252_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_252_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_252_R2R_SAMECS_DLY_FLDMASK (0x1f0000)
#define HWIO_DDR_CTL_252_R2R_SAMECS_DLY_FLDSHFT (16)
#define HWIO_DDR_CTL_252_CDNS_INTRL2_FLDMASK (0xe00000)
#define HWIO_DDR_CTL_252_CDNS_INTRL2_FLDSHFT (21)
#define HWIO_DDR_CTL_252_R2W_SAMECS_DLY_F0_FLDMASK (0x1f000000)
#define HWIO_DDR_CTL_252_R2W_SAMECS_DLY_F0_FLDSHFT (24)
#define HWIO_DDR_CTL_252_CDNS_INTRL3_FLDMASK (0xe0000000)
#define HWIO_DDR_CTL_252_CDNS_INTRL3_FLDSHFT (29)

#define HWIO_DDR_CTL_253_REGOFF 0x3f4
#define HWIO_DDR_CTL_253_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_253_REGOFF)
#define HWIO_DDR_CTL_253_R2W_SAMECS_DLY_F1_FLDMASK (0x1f)
#define HWIO_DDR_CTL_253_R2W_SAMECS_DLY_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_253_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_CTL_253_RESERVED_FLDSHFT (5)
#define HWIO_DDR_CTL_253_R2W_SAMECS_DLY_F2_FLDMASK (0x1f00)
#define HWIO_DDR_CTL_253_R2W_SAMECS_DLY_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_253_CDNS_INTRL1_FLDMASK (0xe000)
#define HWIO_DDR_CTL_253_CDNS_INTRL1_FLDSHFT (13)
#define HWIO_DDR_CTL_253_R2W_SAMECS_DLY_F3_FLDMASK (0x1f0000)
#define HWIO_DDR_CTL_253_R2W_SAMECS_DLY_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_253_CDNS_INTRL2_FLDMASK (0xe00000)
#define HWIO_DDR_CTL_253_CDNS_INTRL2_FLDSHFT (21)
#define HWIO_DDR_CTL_253_W2R_SAMECS_DLY_FLDMASK (0x1f000000)
#define HWIO_DDR_CTL_253_W2R_SAMECS_DLY_FLDSHFT (24)
#define HWIO_DDR_CTL_253_CDNS_INTRL3_FLDMASK (0xe0000000)
#define HWIO_DDR_CTL_253_CDNS_INTRL3_FLDSHFT (29)

#define HWIO_DDR_CTL_254_REGOFF 0x3f8
#define HWIO_DDR_CTL_254_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_254_REGOFF)
#define HWIO_DDR_CTL_254_W2W_SAMECS_DLY_FLDMASK (0x1f)
#define HWIO_DDR_CTL_254_W2W_SAMECS_DLY_FLDSHFT (0)
#define HWIO_DDR_CTL_254_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_CTL_254_RESERVED_FLDSHFT (5)
#define HWIO_DDR_CTL_254_TDQSCK_MAX_F0_FLDMASK (0xf00)
#define HWIO_DDR_CTL_254_TDQSCK_MAX_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_254_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_254_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_254_TDQSCK_MAX_F1_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_254_TDQSCK_MAX_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_254_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_254_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_254_TDQSCK_MAX_F2_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_254_TDQSCK_MAX_F2_FLDSHFT (24)
#define HWIO_DDR_CTL_254_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_254_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_255_REGOFF 0x3fc
#define HWIO_DDR_CTL_255_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_255_REGOFF)
#define HWIO_DDR_CTL_255_TDQSCK_MAX_F3_FLDMASK (0xf)
#define HWIO_DDR_CTL_255_TDQSCK_MAX_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_255_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_255_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_255_SW_LEVELING_MODE_FLDMASK (0x700)
#define HWIO_DDR_CTL_255_SW_LEVELING_MODE_FLDSHFT (8)
#define HWIO_DDR_CTL_255_CDNS_INTRL1_FLDMASK (0xf800)
#define HWIO_DDR_CTL_255_CDNS_INTRL1_FLDSHFT (11)
#define HWIO_DDR_CTL_255_SWLVL_LOAD_FLDMASK (0x10000)
#define HWIO_DDR_CTL_255_SWLVL_LOAD_FLDSHFT (16)
#define HWIO_DDR_CTL_255_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_255_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_255_SWLVL_START_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_255_SWLVL_START_FLDSHFT (24)
#define HWIO_DDR_CTL_255_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_255_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_256_REGOFF 0x400
#define HWIO_DDR_CTL_256_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_256_REGOFF)
#define HWIO_DDR_CTL_256_SWLVL_EXIT_FLDMASK (0x1)
#define HWIO_DDR_CTL_256_SWLVL_EXIT_FLDSHFT (0)
#define HWIO_DDR_CTL_256_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_256_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_256_SWLVL_OP_DONE_FLDMASK (0x100)
#define HWIO_DDR_CTL_256_SWLVL_OP_DONE_FLDSHFT (8)
#define HWIO_DDR_CTL_256_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_256_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_256_SWLVL_RESP_0_FLDMASK (0x10000)
#define HWIO_DDR_CTL_256_SWLVL_RESP_0_FLDSHFT (16)
#define HWIO_DDR_CTL_256_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_256_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_256_SWLVL_RESP_1_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_256_SWLVL_RESP_1_FLDSHFT (24)
#define HWIO_DDR_CTL_256_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_256_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_257_REGOFF 0x404
#define HWIO_DDR_CTL_257_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_257_REGOFF)
#define HWIO_DDR_CTL_257_SWLVL_RESP_2_FLDMASK (0x1)
#define HWIO_DDR_CTL_257_SWLVL_RESP_2_FLDSHFT (0)
#define HWIO_DDR_CTL_257_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_257_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_257_SWLVL_RESP_3_FLDMASK (0x100)
#define HWIO_DDR_CTL_257_SWLVL_RESP_3_FLDSHFT (8)
#define HWIO_DDR_CTL_257_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_257_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_257_PHYUPD_APPEND_EN_FLDMASK (0x10000)
#define HWIO_DDR_CTL_257_PHYUPD_APPEND_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_257_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_257_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_257_WRLVL_REQ_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_257_WRLVL_REQ_FLDSHFT (24)
#define HWIO_DDR_CTL_257_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_257_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_258_REGOFF 0x408
#define HWIO_DDR_CTL_258_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_258_REGOFF)
#define HWIO_DDR_CTL_258_WRLVL_CS_FLDMASK (0x1)
#define HWIO_DDR_CTL_258_WRLVL_CS_FLDSHFT (0)
#define HWIO_DDR_CTL_258_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_258_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_258_WLDQSEN_FLDMASK (0x3f00)
#define HWIO_DDR_CTL_258_WLDQSEN_FLDSHFT (8)
#define HWIO_DDR_CTL_258_CDNS_INTRL1_FLDMASK (0xc000)
#define HWIO_DDR_CTL_258_CDNS_INTRL1_FLDSHFT (14)
#define HWIO_DDR_CTL_258_WLMRD_FLDMASK (0x3f0000)
#define HWIO_DDR_CTL_258_WLMRD_FLDSHFT (16)
#define HWIO_DDR_CTL_258_CDNS_INTRL2_FLDMASK (0xc00000)
#define HWIO_DDR_CTL_258_CDNS_INTRL2_FLDSHFT (22)
#define HWIO_DDR_CTL_258_WRLVL_EN_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_258_WRLVL_EN_FLDSHFT (24)
#define HWIO_DDR_CTL_258_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_258_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_259_REGOFF 0x40c
#define HWIO_DDR_CTL_259_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_259_REGOFF)
#define HWIO_DDR_CTL_259_DFI_PHY_WRLVL_MODE_FLDMASK (0x1)
#define HWIO_DDR_CTL_259_DFI_PHY_WRLVL_MODE_FLDSHFT (0)
#define HWIO_DDR_CTL_259_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_259_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_259_WRLVL_PERIODIC_FLDMASK (0x100)
#define HWIO_DDR_CTL_259_WRLVL_PERIODIC_FLDSHFT (8)
#define HWIO_DDR_CTL_259_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_259_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_259_WRLVL_ON_SREF_EXIT_FLDMASK (0x10000)
#define HWIO_DDR_CTL_259_WRLVL_ON_SREF_EXIT_FLDSHFT (16)
#define HWIO_DDR_CTL_259_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_259_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_259_WRLVL_RESP_MASK_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_259_WRLVL_RESP_MASK_FLDSHFT (24)
#define HWIO_DDR_CTL_259_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_259_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_260_REGOFF 0x410
#define HWIO_DDR_CTL_260_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_260_REGOFF)
#define HWIO_DDR_CTL_260_WRLVL_AREF_EN_FLDMASK (0x1)
#define HWIO_DDR_CTL_260_WRLVL_AREF_EN_FLDSHFT (0)
#define HWIO_DDR_CTL_260_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_260_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_260_WRLVL_ERROR_STATUS_FLDMASK (0x300)
#define HWIO_DDR_CTL_260_WRLVL_ERROR_STATUS_FLDSHFT (8)
#define HWIO_DDR_CTL_260_CDNS_INTRL1_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_260_CDNS_INTRL1_FLDSHFT (10)
#define HWIO_DDR_CTL_260_WRLVL_NORM_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_260_WRLVL_NORM_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_261_REGOFF 0x414
#define HWIO_DDR_CTL_261_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_261_REGOFF)
#define HWIO_DDR_CTL_261_WRLVL_HIGH_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_261_WRLVL_HIGH_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_261_WRLVL_TIMEOUT_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_261_WRLVL_TIMEOUT_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_262_REGOFF 0x418
#define HWIO_DDR_CTL_262_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_262_REGOFF)
#define HWIO_DDR_CTL_262_WRLVL_SW_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_262_WRLVL_SW_PROMOTE_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_262_WRLVL_DFI_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_262_WRLVL_DFI_PROMOTE_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_263_REGOFF 0x41c
#define HWIO_DDR_CTL_263_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_263_REGOFF)
#define HWIO_DDR_CTL_263_WRLVL_NORM_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_263_WRLVL_NORM_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_263_WRLVL_HIGH_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_263_WRLVL_HIGH_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_264_REGOFF 0x420
#define HWIO_DDR_CTL_264_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_264_REGOFF)
#define HWIO_DDR_CTL_264_WRLVL_TIMEOUT_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_264_WRLVL_TIMEOUT_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_264_WRLVL_SW_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_264_WRLVL_SW_PROMOTE_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_265_REGOFF 0x424
#define HWIO_DDR_CTL_265_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_265_REGOFF)
#define HWIO_DDR_CTL_265_WRLVL_DFI_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_265_WRLVL_DFI_PROMOTE_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_265_WRLVL_NORM_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_265_WRLVL_NORM_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_266_REGOFF 0x428
#define HWIO_DDR_CTL_266_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_266_REGOFF)
#define HWIO_DDR_CTL_266_WRLVL_HIGH_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_266_WRLVL_HIGH_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_266_WRLVL_TIMEOUT_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_266_WRLVL_TIMEOUT_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_267_REGOFF 0x42c
#define HWIO_DDR_CTL_267_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_267_REGOFF)
#define HWIO_DDR_CTL_267_WRLVL_SW_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_267_WRLVL_SW_PROMOTE_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_267_WRLVL_DFI_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_267_WRLVL_DFI_PROMOTE_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_268_REGOFF 0x430
#define HWIO_DDR_CTL_268_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_268_REGOFF)
#define HWIO_DDR_CTL_268_WRLVL_NORM_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_268_WRLVL_NORM_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_268_WRLVL_HIGH_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_268_WRLVL_HIGH_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_269_REGOFF 0x434
#define HWIO_DDR_CTL_269_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_269_REGOFF)
#define HWIO_DDR_CTL_269_WRLVL_TIMEOUT_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_269_WRLVL_TIMEOUT_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_269_WRLVL_SW_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_269_WRLVL_SW_PROMOTE_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_270_REGOFF 0x438
#define HWIO_DDR_CTL_270_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_270_REGOFF)
#define HWIO_DDR_CTL_270_WRLVL_DFI_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_270_WRLVL_DFI_PROMOTE_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_270_RDLVL_REQ_FLDMASK (0x10000)
#define HWIO_DDR_CTL_270_RDLVL_REQ_FLDSHFT (16)
#define HWIO_DDR_CTL_270_RESERVED_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_270_RESERVED_FLDSHFT (17)
#define HWIO_DDR_CTL_270_RDLVL_GATE_REQ_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_270_RDLVL_GATE_REQ_FLDSHFT (24)
#define HWIO_DDR_CTL_270_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_270_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_271_REGOFF 0x43c
#define HWIO_DDR_CTL_271_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_271_REGOFF)
#define HWIO_DDR_CTL_271_RDLVL_CS_FLDMASK (0x1)
#define HWIO_DDR_CTL_271_RDLVL_CS_FLDSHFT (0)
#define HWIO_DDR_CTL_271_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_271_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_271_RDLVL_SEQ_EN_FLDMASK (0xf00)
#define HWIO_DDR_CTL_271_RDLVL_SEQ_EN_FLDSHFT (8)
#define HWIO_DDR_CTL_271_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_271_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_271_RDLVL_GATE_SEQ_EN_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_271_RDLVL_GATE_SEQ_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_271_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_271_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_271_DFI_PHY_RDLVL_MODE_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_271_DFI_PHY_RDLVL_MODE_FLDSHFT (24)
#define HWIO_DDR_CTL_271_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_271_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_272_REGOFF 0x440
#define HWIO_DDR_CTL_272_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_272_REGOFF)
#define HWIO_DDR_CTL_272_DFI_PHY_RDLVL_GATE_MODE_FLDMASK (0x1)
#define HWIO_DDR_CTL_272_DFI_PHY_RDLVL_GATE_MODE_FLDSHFT (0)
#define HWIO_DDR_CTL_272_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_272_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_272_RDLVL_PERIODIC_FLDMASK (0x100)
#define HWIO_DDR_CTL_272_RDLVL_PERIODIC_FLDSHFT (8)
#define HWIO_DDR_CTL_272_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_272_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_272_RDLVL_ON_SREF_EXIT_FLDMASK (0x10000)
#define HWIO_DDR_CTL_272_RDLVL_ON_SREF_EXIT_FLDSHFT (16)
#define HWIO_DDR_CTL_272_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_272_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_272_RDLVL_GATE_PERIODIC_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_272_RDLVL_GATE_PERIODIC_FLDSHFT (24)
#define HWIO_DDR_CTL_272_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_272_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_273_REGOFF 0x444
#define HWIO_DDR_CTL_273_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_273_REGOFF)
#define HWIO_DDR_CTL_273_RDLVL_GATE_ON_SREF_EXIT_FLDMASK (0x1)
#define HWIO_DDR_CTL_273_RDLVL_GATE_ON_SREF_EXIT_FLDSHFT (0)
#define HWIO_DDR_CTL_273_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_273_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_273_RDLVL_AREF_EN_FLDMASK (0x100)
#define HWIO_DDR_CTL_273_RDLVL_AREF_EN_FLDSHFT (8)
#define HWIO_DDR_CTL_273_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_273_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_273_RDLVL_GATE_AREF_EN_FLDMASK (0x10000)
#define HWIO_DDR_CTL_273_RDLVL_GATE_AREF_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_273_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_273_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_273_CDNS_INTRL3_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_273_CDNS_INTRL3_FLDSHFT (24)
#define HWIO_DDR_CTL_273_RESERVED4_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_273_RESERVED4_FLDSHFT (25)

#define HWIO_DDR_CTL_274_REGOFF 0x448
#define HWIO_DDR_CTL_274_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_274_REGOFF)
#define HWIO_DDR_CTL_274_RDLVL_NORM_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_274_RDLVL_NORM_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_274_RDLVL_HIGH_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_274_RDLVL_HIGH_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_275_REGOFF 0x44c
#define HWIO_DDR_CTL_275_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_275_REGOFF)
#define HWIO_DDR_CTL_275_RDLVL_TIMEOUT_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_275_RDLVL_TIMEOUT_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_275_RDLVL_SW_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_275_RDLVL_SW_PROMOTE_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_276_REGOFF 0x450
#define HWIO_DDR_CTL_276_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_276_REGOFF)
#define HWIO_DDR_CTL_276_RDLVL_DFI_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_276_RDLVL_DFI_PROMOTE_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_276_RDLVL_GATE_NORM_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_276_RDLVL_GATE_NORM_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_277_REGOFF 0x454
#define HWIO_DDR_CTL_277_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_277_REGOFF)
#define HWIO_DDR_CTL_277_RDLVL_GATE_HIGH_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_277_RDLVL_GATE_HIGH_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_277_RDLVL_GATE_TIMEOUT_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_277_RDLVL_GATE_TIMEOUT_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_278_REGOFF 0x458
#define HWIO_DDR_CTL_278_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_278_REGOFF)
#define HWIO_DDR_CTL_278_RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_278_RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_278_RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_FLDMASK \
	(0xffff0000)
#define HWIO_DDR_CTL_278_RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_279_REGOFF 0x45c
#define HWIO_DDR_CTL_279_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_279_REGOFF)
#define HWIO_DDR_CTL_279_RDLVL_NORM_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_279_RDLVL_NORM_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_279_RDLVL_HIGH_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_279_RDLVL_HIGH_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_280_REGOFF 0x460
#define HWIO_DDR_CTL_280_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_280_REGOFF)
#define HWIO_DDR_CTL_280_RDLVL_TIMEOUT_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_280_RDLVL_TIMEOUT_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_280_RDLVL_SW_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_280_RDLVL_SW_PROMOTE_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_281_REGOFF 0x464
#define HWIO_DDR_CTL_281_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_281_REGOFF)
#define HWIO_DDR_CTL_281_RDLVL_DFI_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_281_RDLVL_DFI_PROMOTE_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_281_RDLVL_GATE_NORM_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_281_RDLVL_GATE_NORM_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_282_REGOFF 0x468
#define HWIO_DDR_CTL_282_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_282_REGOFF)
#define HWIO_DDR_CTL_282_RDLVL_GATE_HIGH_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_282_RDLVL_GATE_HIGH_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_282_RDLVL_GATE_TIMEOUT_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_282_RDLVL_GATE_TIMEOUT_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_283_REGOFF 0x46c
#define HWIO_DDR_CTL_283_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_283_REGOFF)
#define HWIO_DDR_CTL_283_RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_283_RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_283_RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_FLDMASK \
	(0xffff0000)
#define HWIO_DDR_CTL_283_RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_284_REGOFF 0x470
#define HWIO_DDR_CTL_284_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_284_REGOFF)
#define HWIO_DDR_CTL_284_RDLVL_NORM_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_284_RDLVL_NORM_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_284_RDLVL_HIGH_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_284_RDLVL_HIGH_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_285_REGOFF 0x474
#define HWIO_DDR_CTL_285_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_285_REGOFF)
#define HWIO_DDR_CTL_285_RDLVL_TIMEOUT_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_285_RDLVL_TIMEOUT_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_285_RDLVL_SW_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_285_RDLVL_SW_PROMOTE_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_286_REGOFF 0x478
#define HWIO_DDR_CTL_286_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_286_REGOFF)
#define HWIO_DDR_CTL_286_RDLVL_DFI_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_286_RDLVL_DFI_PROMOTE_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_286_RDLVL_GATE_NORM_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_286_RDLVL_GATE_NORM_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_287_REGOFF 0x47c
#define HWIO_DDR_CTL_287_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_287_REGOFF)
#define HWIO_DDR_CTL_287_RDLVL_GATE_HIGH_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_287_RDLVL_GATE_HIGH_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_287_RDLVL_GATE_TIMEOUT_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_287_RDLVL_GATE_TIMEOUT_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_288_REGOFF 0x480
#define HWIO_DDR_CTL_288_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_288_REGOFF)
#define HWIO_DDR_CTL_288_RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_288_RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_288_RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_FLDMASK \
	(0xffff0000)
#define HWIO_DDR_CTL_288_RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_289_REGOFF 0x484
#define HWIO_DDR_CTL_289_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_289_REGOFF)
#define HWIO_DDR_CTL_289_RDLVL_NORM_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_289_RDLVL_NORM_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_289_RDLVL_HIGH_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_289_RDLVL_HIGH_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_290_REGOFF 0x488
#define HWIO_DDR_CTL_290_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_290_REGOFF)
#define HWIO_DDR_CTL_290_RDLVL_TIMEOUT_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_290_RDLVL_TIMEOUT_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_290_RDLVL_SW_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_290_RDLVL_SW_PROMOTE_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_291_REGOFF 0x48c
#define HWIO_DDR_CTL_291_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_291_REGOFF)
#define HWIO_DDR_CTL_291_RDLVL_DFI_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_291_RDLVL_DFI_PROMOTE_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_291_RDLVL_GATE_NORM_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_291_RDLVL_GATE_NORM_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_292_REGOFF 0x490
#define HWIO_DDR_CTL_292_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_292_REGOFF)
#define HWIO_DDR_CTL_292_RDLVL_GATE_HIGH_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_292_RDLVL_GATE_HIGH_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_292_RDLVL_GATE_TIMEOUT_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_292_RDLVL_GATE_TIMEOUT_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_293_REGOFF 0x494
#define HWIO_DDR_CTL_293_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_293_REGOFF)
#define HWIO_DDR_CTL_293_RDLVL_GATE_SW_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_293_RDLVL_GATE_SW_PROMOTE_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_293_RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F3_FLDMASK \
	(0xffff0000)
#define HWIO_DDR_CTL_293_RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_294_REGOFF 0x498
#define HWIO_DDR_CTL_294_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_294_REGOFF)
#define HWIO_DDR_CTL_294_CALVL_REQ_FLDMASK (0x1)
#define HWIO_DDR_CTL_294_CALVL_REQ_FLDSHFT (0)
#define HWIO_DDR_CTL_294_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_294_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_294_CALVL_CS_FLDMASK (0x100)
#define HWIO_DDR_CTL_294_CALVL_CS_FLDSHFT (8)
#define HWIO_DDR_CTL_294_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_294_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_294_OBSOLETE2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_294_OBSOLETE2_FLDSHFT (16)

#define HWIO_DDR_CTL_295_REGOFF 0x49c
#define HWIO_DDR_CTL_295_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_295_REGOFF)
#define HWIO_DDR_CTL_295_CALVL_PAT_0_FLDMASK (0xfffff)
#define HWIO_DDR_CTL_295_CALVL_PAT_0_FLDSHFT (0)
#define HWIO_DDR_CTL_295_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_295_RESERVED_FLDSHFT (20)
#define HWIO_DDR_CTL_295_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_295_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_296_REGOFF 0x4a0
#define HWIO_DDR_CTL_296_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_296_REGOFF)
#define HWIO_DDR_CTL_296_CALVL_BG_PAT_0_FLDMASK (0xfffff)
#define HWIO_DDR_CTL_296_CALVL_BG_PAT_0_FLDSHFT (0)
#define HWIO_DDR_CTL_296_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_296_RESERVED_FLDSHFT (20)
#define HWIO_DDR_CTL_296_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_296_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_297_REGOFF 0x4a4
#define HWIO_DDR_CTL_297_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_297_REGOFF)
#define HWIO_DDR_CTL_297_CALVL_PAT_1_FLDMASK (0xfffff)
#define HWIO_DDR_CTL_297_CALVL_PAT_1_FLDSHFT (0)
#define HWIO_DDR_CTL_297_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_297_RESERVED_FLDSHFT (20)
#define HWIO_DDR_CTL_297_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_297_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_298_REGOFF 0x4a8
#define HWIO_DDR_CTL_298_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_298_REGOFF)
#define HWIO_DDR_CTL_298_CALVL_BG_PAT_1_FLDMASK (0xfffff)
#define HWIO_DDR_CTL_298_CALVL_BG_PAT_1_FLDSHFT (0)
#define HWIO_DDR_CTL_298_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_298_RESERVED_FLDSHFT (20)
#define HWIO_DDR_CTL_298_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_298_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_299_REGOFF 0x4ac
#define HWIO_DDR_CTL_299_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_299_REGOFF)
#define HWIO_DDR_CTL_299_CALVL_PAT_2_FLDMASK (0xfffff)
#define HWIO_DDR_CTL_299_CALVL_PAT_2_FLDSHFT (0)
#define HWIO_DDR_CTL_299_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_299_RESERVED_FLDSHFT (20)
#define HWIO_DDR_CTL_299_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_299_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_300_REGOFF 0x4b0
#define HWIO_DDR_CTL_300_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_300_REGOFF)
#define HWIO_DDR_CTL_300_CALVL_BG_PAT_2_FLDMASK (0xfffff)
#define HWIO_DDR_CTL_300_CALVL_BG_PAT_2_FLDSHFT (0)
#define HWIO_DDR_CTL_300_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_300_RESERVED_FLDSHFT (20)
#define HWIO_DDR_CTL_300_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_300_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_301_REGOFF 0x4b4
#define HWIO_DDR_CTL_301_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_301_REGOFF)
#define HWIO_DDR_CTL_301_CALVL_PAT_3_FLDMASK (0xfffff)
#define HWIO_DDR_CTL_301_CALVL_PAT_3_FLDSHFT (0)
#define HWIO_DDR_CTL_301_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_301_RESERVED_FLDSHFT (20)
#define HWIO_DDR_CTL_301_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_301_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_302_REGOFF 0x4b8
#define HWIO_DDR_CTL_302_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_302_REGOFF)
#define HWIO_DDR_CTL_302_CALVL_BG_PAT_3_FLDMASK (0xfffff)
#define HWIO_DDR_CTL_302_CALVL_BG_PAT_3_FLDSHFT (0)
#define HWIO_DDR_CTL_302_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_302_RESERVED_FLDSHFT (20)
#define HWIO_DDR_CTL_302_CDNS_INTRL1_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_302_CDNS_INTRL1_FLDSHFT (24)
#define HWIO_DDR_CTL_302_CDNS_INTRL2_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_302_CDNS_INTRL2_FLDSHFT (25)

#define HWIO_DDR_CTL_303_REGOFF 0x4bc
#define HWIO_DDR_CTL_303_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_303_REGOFF)
#define HWIO_DDR_CTL_303_CDNS_INTRL0_FLDMASK (0xf)
#define HWIO_DDR_CTL_303_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_303_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_303_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_303_CALVL_SEQ_EN_FLDMASK (0x300)
#define HWIO_DDR_CTL_303_CALVL_SEQ_EN_FLDSHFT (8)
#define HWIO_DDR_CTL_303_CDNS_INTRL1_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_303_CDNS_INTRL1_FLDSHFT (10)
#define HWIO_DDR_CTL_303_DFI_PHY_CALVL_MODE_FLDMASK (0x10000)
#define HWIO_DDR_CTL_303_DFI_PHY_CALVL_MODE_FLDSHFT (16)
#define HWIO_DDR_CTL_303_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_303_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_303_CALVL_PERIODIC_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_303_CALVL_PERIODIC_FLDSHFT (24)
#define HWIO_DDR_CTL_303_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_303_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_304_REGOFF 0x4c0
#define HWIO_DDR_CTL_304_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_304_REGOFF)
#define HWIO_DDR_CTL_304_CALVL_ON_SREF_EXIT_FLDMASK (0x1)
#define HWIO_DDR_CTL_304_CALVL_ON_SREF_EXIT_FLDSHFT (0)
#define HWIO_DDR_CTL_304_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_304_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_304_CALVL_AREF_EN_FLDMASK (0x100)
#define HWIO_DDR_CTL_304_CALVL_AREF_EN_FLDSHFT (8)
#define HWIO_DDR_CTL_304_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_304_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_304_CALVL_NORM_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_304_CALVL_NORM_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_305_REGOFF 0x4c4
#define HWIO_DDR_CTL_305_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_305_REGOFF)
#define HWIO_DDR_CTL_305_CALVL_HIGH_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_305_CALVL_HIGH_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_305_CALVL_TIMEOUT_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_305_CALVL_TIMEOUT_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_306_REGOFF 0x4c8
#define HWIO_DDR_CTL_306_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_306_REGOFF)
#define HWIO_DDR_CTL_306_CALVL_SW_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_306_CALVL_SW_PROMOTE_THRESHOLD_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_306_CALVL_DFI_PROMOTE_THRESHOLD_F0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_306_CALVL_DFI_PROMOTE_THRESHOLD_F0_FLDSHFT (16)

#define HWIO_DDR_CTL_307_REGOFF 0x4cc
#define HWIO_DDR_CTL_307_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_307_REGOFF)
#define HWIO_DDR_CTL_307_CALVL_NORM_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_307_CALVL_NORM_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_307_CALVL_HIGH_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_307_CALVL_HIGH_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_308_REGOFF 0x4d0
#define HWIO_DDR_CTL_308_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_308_REGOFF)
#define HWIO_DDR_CTL_308_CALVL_TIMEOUT_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_308_CALVL_TIMEOUT_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_308_CALVL_SW_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_308_CALVL_SW_PROMOTE_THRESHOLD_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_309_REGOFF 0x4d4
#define HWIO_DDR_CTL_309_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_309_REGOFF)
#define HWIO_DDR_CTL_309_CALVL_DFI_PROMOTE_THRESHOLD_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_309_CALVL_DFI_PROMOTE_THRESHOLD_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_309_CALVL_NORM_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_309_CALVL_NORM_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_310_REGOFF 0x4d8
#define HWIO_DDR_CTL_310_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_310_REGOFF)
#define HWIO_DDR_CTL_310_CALVL_HIGH_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_310_CALVL_HIGH_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_310_CALVL_TIMEOUT_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_310_CALVL_TIMEOUT_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_311_REGOFF 0x4dc
#define HWIO_DDR_CTL_311_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_311_REGOFF)
#define HWIO_DDR_CTL_311_CALVL_SW_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_311_CALVL_SW_PROMOTE_THRESHOLD_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_311_CALVL_DFI_PROMOTE_THRESHOLD_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_311_CALVL_DFI_PROMOTE_THRESHOLD_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_312_REGOFF 0x4e0
#define HWIO_DDR_CTL_312_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_312_REGOFF)
#define HWIO_DDR_CTL_312_CALVL_NORM_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_312_CALVL_NORM_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_312_CALVL_HIGH_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_312_CALVL_HIGH_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_313_REGOFF 0x4e4
#define HWIO_DDR_CTL_313_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_313_REGOFF)
#define HWIO_DDR_CTL_313_CALVL_TIMEOUT_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_313_CALVL_TIMEOUT_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_313_CALVL_SW_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_313_CALVL_SW_PROMOTE_THRESHOLD_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_314_REGOFF 0x4e8
#define HWIO_DDR_CTL_314_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_314_REGOFF)
#define HWIO_DDR_CTL_314_CALVL_DFI_PROMOTE_THRESHOLD_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_314_CALVL_DFI_PROMOTE_THRESHOLD_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_314_AXI0_ALL_STROBES_USED_ENABLE_FLDMASK (0x10000)
#define HWIO_DDR_CTL_314_AXI0_ALL_STROBES_USED_ENABLE_FLDSHFT (16)
#define HWIO_DDR_CTL_314_RESERVED_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_314_RESERVED_FLDSHFT (17)
#define HWIO_DDR_CTL_314_AXI0_FIXED_PORT_PRIORITY_ENABLE_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_314_AXI0_FIXED_PORT_PRIORITY_ENABLE_FLDSHFT (24)
#define HWIO_DDR_CTL_314_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_314_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_315_REGOFF 0x4ec
#define HWIO_DDR_CTL_315_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_315_REGOFF)
#define HWIO_DDR_CTL_315_AXI0_R_PRIORITY_FLDMASK (0x3)
#define HWIO_DDR_CTL_315_AXI0_R_PRIORITY_FLDSHFT (0)
#define HWIO_DDR_CTL_315_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_CTL_315_RESERVED_FLDSHFT (2)
#define HWIO_DDR_CTL_315_AXI0_W_PRIORITY_FLDMASK (0x300)
#define HWIO_DDR_CTL_315_AXI0_W_PRIORITY_FLDSHFT (8)
#define HWIO_DDR_CTL_315_CDNS_INTRL1_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_315_CDNS_INTRL1_FLDSHFT (10)
#define HWIO_DDR_CTL_315_AXI0_FIFO_TYPE_REG_FLDMASK (0x30000)
#define HWIO_DDR_CTL_315_AXI0_FIFO_TYPE_REG_FLDSHFT (16)
#define HWIO_DDR_CTL_315_CDNS_INTRL2_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_315_CDNS_INTRL2_FLDSHFT (18)
#define HWIO_DDR_CTL_315_AXI1_ALL_STROBES_USED_ENABLE_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_315_AXI1_ALL_STROBES_USED_ENABLE_FLDSHFT (24)
#define HWIO_DDR_CTL_315_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_315_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_316_REGOFF 0x4f0
#define HWIO_DDR_CTL_316_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_316_REGOFF)
#define HWIO_DDR_CTL_316_AXI1_FIXED_PORT_PRIORITY_ENABLE_FLDMASK (0x1)
#define HWIO_DDR_CTL_316_AXI1_FIXED_PORT_PRIORITY_ENABLE_FLDSHFT (0)
#define HWIO_DDR_CTL_316_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_316_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_316_AXI1_R_PRIORITY_FLDMASK (0x300)
#define HWIO_DDR_CTL_316_AXI1_R_PRIORITY_FLDSHFT (8)
#define HWIO_DDR_CTL_316_CDNS_INTRL1_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_316_CDNS_INTRL1_FLDSHFT (10)
#define HWIO_DDR_CTL_316_AXI1_W_PRIORITY_FLDMASK (0x30000)
#define HWIO_DDR_CTL_316_AXI1_W_PRIORITY_FLDSHFT (16)
#define HWIO_DDR_CTL_316_CDNS_INTRL2_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_316_CDNS_INTRL2_FLDSHFT (18)
#define HWIO_DDR_CTL_316_AXI1_FIFO_TYPE_REG_FLDMASK (0x3000000)
#define HWIO_DDR_CTL_316_AXI1_FIFO_TYPE_REG_FLDSHFT (24)
#define HWIO_DDR_CTL_316_CDNS_INTRL3_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_316_CDNS_INTRL3_FLDSHFT (26)

#define HWIO_DDR_CTL_317_REGOFF 0x4f4
#define HWIO_DDR_CTL_317_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_317_REGOFF)
#define HWIO_DDR_CTL_317_PORT_ADDR_PROTECTION_EN_FLDMASK (0x1)
#define HWIO_DDR_CTL_317_PORT_ADDR_PROTECTION_EN_FLDSHFT (0)
#define HWIO_DDR_CTL_317_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_317_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_317_AXI0_ADDRESS_RANGE_ENABLE_FLDMASK (0x100)
#define HWIO_DDR_CTL_317_AXI0_ADDRESS_RANGE_ENABLE_FLDSHFT (8)
#define HWIO_DDR_CTL_317_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_317_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_317_AXI1_ADDRESS_RANGE_ENABLE_FLDMASK (0x10000)
#define HWIO_DDR_CTL_317_AXI1_ADDRESS_RANGE_ENABLE_FLDSHFT (16)
#define HWIO_DDR_CTL_317_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_317_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_317_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_317_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_CTL_318_REGOFF 0x4f8
#define HWIO_DDR_CTL_318_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_318_REGOFF)
#define HWIO_DDR_CTL_318_AXI0_START_ADDR_0_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_318_AXI0_START_ADDR_0_FLDSHFT (0)
#define HWIO_DDR_CTL_318_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_318_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_318_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_318_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_319_REGOFF 0x4fc
#define HWIO_DDR_CTL_319_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_319_REGOFF)
#define HWIO_DDR_CTL_319_AXI0_END_ADDR_0_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_319_AXI0_END_ADDR_0_FLDSHFT (0)
#define HWIO_DDR_CTL_319_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_319_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_319_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_319_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_320_REGOFF 0x500
#define HWIO_DDR_CTL_320_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_320_REGOFF)
#define HWIO_DDR_CTL_320_AXI0_START_ADDR_1_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_320_AXI0_START_ADDR_1_FLDSHFT (0)
#define HWIO_DDR_CTL_320_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_320_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_320_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_320_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_321_REGOFF 0x504
#define HWIO_DDR_CTL_321_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_321_REGOFF)
#define HWIO_DDR_CTL_321_AXI0_END_ADDR_1_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_321_AXI0_END_ADDR_1_FLDSHFT (0)
#define HWIO_DDR_CTL_321_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_321_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_321_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_321_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_322_REGOFF 0x508
#define HWIO_DDR_CTL_322_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_322_REGOFF)
#define HWIO_DDR_CTL_322_AXI0_START_ADDR_2_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_322_AXI0_START_ADDR_2_FLDSHFT (0)
#define HWIO_DDR_CTL_322_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_322_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_322_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_322_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_323_REGOFF 0x50c
#define HWIO_DDR_CTL_323_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_323_REGOFF)
#define HWIO_DDR_CTL_323_AXI0_END_ADDR_2_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_323_AXI0_END_ADDR_2_FLDSHFT (0)
#define HWIO_DDR_CTL_323_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_323_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_323_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_323_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_324_REGOFF 0x510
#define HWIO_DDR_CTL_324_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_324_REGOFF)
#define HWIO_DDR_CTL_324_AXI0_START_ADDR_3_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_324_AXI0_START_ADDR_3_FLDSHFT (0)
#define HWIO_DDR_CTL_324_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_324_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_324_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_324_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_325_REGOFF 0x514
#define HWIO_DDR_CTL_325_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_325_REGOFF)
#define HWIO_DDR_CTL_325_AXI0_END_ADDR_3_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_325_AXI0_END_ADDR_3_FLDSHFT (0)
#define HWIO_DDR_CTL_325_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_325_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_325_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_325_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_326_REGOFF 0x518
#define HWIO_DDR_CTL_326_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_326_REGOFF)
#define HWIO_DDR_CTL_326_AXI0_START_ADDR_4_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_326_AXI0_START_ADDR_4_FLDSHFT (0)
#define HWIO_DDR_CTL_326_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_326_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_326_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_326_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_327_REGOFF 0x51c
#define HWIO_DDR_CTL_327_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_327_REGOFF)
#define HWIO_DDR_CTL_327_AXI0_END_ADDR_4_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_327_AXI0_END_ADDR_4_FLDSHFT (0)
#define HWIO_DDR_CTL_327_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_327_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_327_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_327_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_328_REGOFF 0x520
#define HWIO_DDR_CTL_328_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_328_REGOFF)
#define HWIO_DDR_CTL_328_AXI0_START_ADDR_5_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_328_AXI0_START_ADDR_5_FLDSHFT (0)
#define HWIO_DDR_CTL_328_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_328_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_328_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_328_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_329_REGOFF 0x524
#define HWIO_DDR_CTL_329_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_329_REGOFF)
#define HWIO_DDR_CTL_329_AXI0_END_ADDR_5_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_329_AXI0_END_ADDR_5_FLDSHFT (0)
#define HWIO_DDR_CTL_329_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_329_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_329_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_329_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_330_REGOFF 0x528
#define HWIO_DDR_CTL_330_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_330_REGOFF)
#define HWIO_DDR_CTL_330_AXI0_START_ADDR_6_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_330_AXI0_START_ADDR_6_FLDSHFT (0)
#define HWIO_DDR_CTL_330_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_330_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_330_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_330_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_331_REGOFF 0x52c
#define HWIO_DDR_CTL_331_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_331_REGOFF)
#define HWIO_DDR_CTL_331_AXI0_END_ADDR_6_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_331_AXI0_END_ADDR_6_FLDSHFT (0)
#define HWIO_DDR_CTL_331_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_331_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_331_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_331_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_332_REGOFF 0x530
#define HWIO_DDR_CTL_332_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_332_REGOFF)
#define HWIO_DDR_CTL_332_AXI0_START_ADDR_7_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_332_AXI0_START_ADDR_7_FLDSHFT (0)
#define HWIO_DDR_CTL_332_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_332_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_332_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_332_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_333_REGOFF 0x534
#define HWIO_DDR_CTL_333_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_333_REGOFF)
#define HWIO_DDR_CTL_333_AXI0_END_ADDR_7_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_333_AXI0_END_ADDR_7_FLDSHFT (0)
#define HWIO_DDR_CTL_333_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_333_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_333_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_333_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_334_REGOFF 0x538
#define HWIO_DDR_CTL_334_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_334_REGOFF)
#define HWIO_DDR_CTL_334_AXI0_START_ADDR_8_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_334_AXI0_START_ADDR_8_FLDSHFT (0)
#define HWIO_DDR_CTL_334_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_334_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_334_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_334_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_335_REGOFF 0x53c
#define HWIO_DDR_CTL_335_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_335_REGOFF)
#define HWIO_DDR_CTL_335_AXI0_END_ADDR_8_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_335_AXI0_END_ADDR_8_FLDSHFT (0)
#define HWIO_DDR_CTL_335_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_335_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_335_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_335_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_336_REGOFF 0x540
#define HWIO_DDR_CTL_336_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_336_REGOFF)
#define HWIO_DDR_CTL_336_AXI0_START_ADDR_9_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_336_AXI0_START_ADDR_9_FLDSHFT (0)
#define HWIO_DDR_CTL_336_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_336_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_336_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_336_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_337_REGOFF 0x544
#define HWIO_DDR_CTL_337_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_337_REGOFF)
#define HWIO_DDR_CTL_337_AXI0_END_ADDR_9_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_337_AXI0_END_ADDR_9_FLDSHFT (0)
#define HWIO_DDR_CTL_337_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_337_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_337_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_337_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_338_REGOFF 0x548
#define HWIO_DDR_CTL_338_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_338_REGOFF)
#define HWIO_DDR_CTL_338_AXI0_START_ADDR_10_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_338_AXI0_START_ADDR_10_FLDSHFT (0)
#define HWIO_DDR_CTL_338_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_338_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_338_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_338_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_339_REGOFF 0x54c
#define HWIO_DDR_CTL_339_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_339_REGOFF)
#define HWIO_DDR_CTL_339_AXI0_END_ADDR_10_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_339_AXI0_END_ADDR_10_FLDSHFT (0)
#define HWIO_DDR_CTL_339_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_339_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_339_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_339_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_340_REGOFF 0x550
#define HWIO_DDR_CTL_340_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_340_REGOFF)
#define HWIO_DDR_CTL_340_AXI0_START_ADDR_11_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_340_AXI0_START_ADDR_11_FLDSHFT (0)
#define HWIO_DDR_CTL_340_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_340_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_340_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_340_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_341_REGOFF 0x554
#define HWIO_DDR_CTL_341_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_341_REGOFF)
#define HWIO_DDR_CTL_341_AXI0_END_ADDR_11_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_341_AXI0_END_ADDR_11_FLDSHFT (0)
#define HWIO_DDR_CTL_341_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_341_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_341_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_341_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_342_REGOFF 0x558
#define HWIO_DDR_CTL_342_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_342_REGOFF)
#define HWIO_DDR_CTL_342_AXI0_START_ADDR_12_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_342_AXI0_START_ADDR_12_FLDSHFT (0)
#define HWIO_DDR_CTL_342_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_342_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_342_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_342_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_343_REGOFF 0x55c
#define HWIO_DDR_CTL_343_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_343_REGOFF)
#define HWIO_DDR_CTL_343_AXI0_END_ADDR_12_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_343_AXI0_END_ADDR_12_FLDSHFT (0)
#define HWIO_DDR_CTL_343_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_343_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_343_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_343_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_344_REGOFF 0x560
#define HWIO_DDR_CTL_344_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_344_REGOFF)
#define HWIO_DDR_CTL_344_AXI0_START_ADDR_13_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_344_AXI0_START_ADDR_13_FLDSHFT (0)
#define HWIO_DDR_CTL_344_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_344_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_344_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_344_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_345_REGOFF 0x564
#define HWIO_DDR_CTL_345_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_345_REGOFF)
#define HWIO_DDR_CTL_345_AXI0_END_ADDR_13_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_345_AXI0_END_ADDR_13_FLDSHFT (0)
#define HWIO_DDR_CTL_345_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_345_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_345_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_345_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_346_REGOFF 0x568
#define HWIO_DDR_CTL_346_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_346_REGOFF)
#define HWIO_DDR_CTL_346_AXI0_START_ADDR_14_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_346_AXI0_START_ADDR_14_FLDSHFT (0)
#define HWIO_DDR_CTL_346_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_346_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_346_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_346_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_347_REGOFF 0x56c
#define HWIO_DDR_CTL_347_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_347_REGOFF)
#define HWIO_DDR_CTL_347_AXI0_END_ADDR_14_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_347_AXI0_END_ADDR_14_FLDSHFT (0)
#define HWIO_DDR_CTL_347_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_347_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_347_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_347_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_348_REGOFF 0x570
#define HWIO_DDR_CTL_348_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_348_REGOFF)
#define HWIO_DDR_CTL_348_AXI0_START_ADDR_15_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_348_AXI0_START_ADDR_15_FLDSHFT (0)
#define HWIO_DDR_CTL_348_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_348_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_348_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_348_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_349_REGOFF 0x574
#define HWIO_DDR_CTL_349_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_349_REGOFF)
#define HWIO_DDR_CTL_349_AXI0_END_ADDR_15_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_349_AXI0_END_ADDR_15_FLDSHFT (0)
#define HWIO_DDR_CTL_349_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_349_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_349_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_349_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_350_REGOFF 0x578
#define HWIO_DDR_CTL_350_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_350_REGOFF)
#define HWIO_DDR_CTL_350_AXI1_START_ADDR_0_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_350_AXI1_START_ADDR_0_FLDSHFT (0)
#define HWIO_DDR_CTL_350_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_350_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_350_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_350_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_351_REGOFF 0x57c
#define HWIO_DDR_CTL_351_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_351_REGOFF)
#define HWIO_DDR_CTL_351_AXI1_END_ADDR_0_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_351_AXI1_END_ADDR_0_FLDSHFT (0)
#define HWIO_DDR_CTL_351_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_351_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_351_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_351_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_352_REGOFF 0x580
#define HWIO_DDR_CTL_352_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_352_REGOFF)
#define HWIO_DDR_CTL_352_AXI1_START_ADDR_1_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_352_AXI1_START_ADDR_1_FLDSHFT (0)
#define HWIO_DDR_CTL_352_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_352_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_352_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_352_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_353_REGOFF 0x584
#define HWIO_DDR_CTL_353_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_353_REGOFF)
#define HWIO_DDR_CTL_353_AXI1_END_ADDR_1_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_353_AXI1_END_ADDR_1_FLDSHFT (0)
#define HWIO_DDR_CTL_353_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_353_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_353_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_353_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_354_REGOFF 0x588
#define HWIO_DDR_CTL_354_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_354_REGOFF)
#define HWIO_DDR_CTL_354_AXI1_START_ADDR_2_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_354_AXI1_START_ADDR_2_FLDSHFT (0)
#define HWIO_DDR_CTL_354_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_354_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_354_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_354_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_355_REGOFF 0x58c
#define HWIO_DDR_CTL_355_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_355_REGOFF)
#define HWIO_DDR_CTL_355_AXI1_END_ADDR_2_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_355_AXI1_END_ADDR_2_FLDSHFT (0)
#define HWIO_DDR_CTL_355_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_355_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_355_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_355_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_356_REGOFF 0x590
#define HWIO_DDR_CTL_356_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_356_REGOFF)
#define HWIO_DDR_CTL_356_AXI1_START_ADDR_3_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_356_AXI1_START_ADDR_3_FLDSHFT (0)
#define HWIO_DDR_CTL_356_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_356_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_356_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_356_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_357_REGOFF 0x594
#define HWIO_DDR_CTL_357_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_357_REGOFF)
#define HWIO_DDR_CTL_357_AXI1_END_ADDR_3_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_357_AXI1_END_ADDR_3_FLDSHFT (0)
#define HWIO_DDR_CTL_357_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_357_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_357_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_357_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_358_REGOFF 0x598
#define HWIO_DDR_CTL_358_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_358_REGOFF)
#define HWIO_DDR_CTL_358_AXI1_START_ADDR_4_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_358_AXI1_START_ADDR_4_FLDSHFT (0)
#define HWIO_DDR_CTL_358_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_358_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_358_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_358_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_359_REGOFF 0x59c
#define HWIO_DDR_CTL_359_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_359_REGOFF)
#define HWIO_DDR_CTL_359_AXI1_END_ADDR_4_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_359_AXI1_END_ADDR_4_FLDSHFT (0)
#define HWIO_DDR_CTL_359_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_359_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_359_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_359_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_360_REGOFF 0x5a0
#define HWIO_DDR_CTL_360_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_360_REGOFF)
#define HWIO_DDR_CTL_360_AXI1_START_ADDR_5_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_360_AXI1_START_ADDR_5_FLDSHFT (0)
#define HWIO_DDR_CTL_360_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_360_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_360_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_360_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_361_REGOFF 0x5a4
#define HWIO_DDR_CTL_361_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_361_REGOFF)
#define HWIO_DDR_CTL_361_AXI1_END_ADDR_5_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_361_AXI1_END_ADDR_5_FLDSHFT (0)
#define HWIO_DDR_CTL_361_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_361_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_361_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_361_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_362_REGOFF 0x5a8
#define HWIO_DDR_CTL_362_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_362_REGOFF)
#define HWIO_DDR_CTL_362_AXI1_START_ADDR_6_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_362_AXI1_START_ADDR_6_FLDSHFT (0)
#define HWIO_DDR_CTL_362_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_362_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_362_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_362_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_363_REGOFF 0x5ac
#define HWIO_DDR_CTL_363_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_363_REGOFF)
#define HWIO_DDR_CTL_363_AXI1_END_ADDR_6_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_363_AXI1_END_ADDR_6_FLDSHFT (0)
#define HWIO_DDR_CTL_363_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_363_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_363_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_363_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_364_REGOFF 0x5b0
#define HWIO_DDR_CTL_364_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_364_REGOFF)
#define HWIO_DDR_CTL_364_AXI1_START_ADDR_7_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_364_AXI1_START_ADDR_7_FLDSHFT (0)
#define HWIO_DDR_CTL_364_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_364_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_364_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_364_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_365_REGOFF 0x5b4
#define HWIO_DDR_CTL_365_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_365_REGOFF)
#define HWIO_DDR_CTL_365_AXI1_END_ADDR_7_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_365_AXI1_END_ADDR_7_FLDSHFT (0)
#define HWIO_DDR_CTL_365_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_365_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_365_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_365_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_366_REGOFF 0x5b8
#define HWIO_DDR_CTL_366_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_366_REGOFF)
#define HWIO_DDR_CTL_366_AXI1_START_ADDR_8_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_366_AXI1_START_ADDR_8_FLDSHFT (0)
#define HWIO_DDR_CTL_366_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_366_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_366_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_366_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_367_REGOFF 0x5bc
#define HWIO_DDR_CTL_367_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_367_REGOFF)
#define HWIO_DDR_CTL_367_AXI1_END_ADDR_8_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_367_AXI1_END_ADDR_8_FLDSHFT (0)
#define HWIO_DDR_CTL_367_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_367_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_367_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_367_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_368_REGOFF 0x5c0
#define HWIO_DDR_CTL_368_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_368_REGOFF)
#define HWIO_DDR_CTL_368_AXI1_START_ADDR_9_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_368_AXI1_START_ADDR_9_FLDSHFT (0)
#define HWIO_DDR_CTL_368_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_368_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_368_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_368_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_369_REGOFF 0x5c4
#define HWIO_DDR_CTL_369_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_369_REGOFF)
#define HWIO_DDR_CTL_369_AXI1_END_ADDR_9_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_369_AXI1_END_ADDR_9_FLDSHFT (0)
#define HWIO_DDR_CTL_369_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_369_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_369_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_369_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_370_REGOFF 0x5c8
#define HWIO_DDR_CTL_370_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_370_REGOFF)
#define HWIO_DDR_CTL_370_AXI1_START_ADDR_10_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_370_AXI1_START_ADDR_10_FLDSHFT (0)
#define HWIO_DDR_CTL_370_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_370_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_370_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_370_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_371_REGOFF 0x5cc
#define HWIO_DDR_CTL_371_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_371_REGOFF)
#define HWIO_DDR_CTL_371_AXI1_END_ADDR_10_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_371_AXI1_END_ADDR_10_FLDSHFT (0)
#define HWIO_DDR_CTL_371_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_371_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_371_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_371_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_372_REGOFF 0x5d0
#define HWIO_DDR_CTL_372_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_372_REGOFF)
#define HWIO_DDR_CTL_372_AXI1_START_ADDR_11_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_372_AXI1_START_ADDR_11_FLDSHFT (0)
#define HWIO_DDR_CTL_372_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_372_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_372_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_372_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_373_REGOFF 0x5d4
#define HWIO_DDR_CTL_373_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_373_REGOFF)
#define HWIO_DDR_CTL_373_AXI1_END_ADDR_11_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_373_AXI1_END_ADDR_11_FLDSHFT (0)
#define HWIO_DDR_CTL_373_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_373_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_373_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_373_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_374_REGOFF 0x5d8
#define HWIO_DDR_CTL_374_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_374_REGOFF)
#define HWIO_DDR_CTL_374_AXI1_START_ADDR_12_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_374_AXI1_START_ADDR_12_FLDSHFT (0)
#define HWIO_DDR_CTL_374_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_374_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_374_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_374_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_375_REGOFF 0x5dc
#define HWIO_DDR_CTL_375_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_375_REGOFF)
#define HWIO_DDR_CTL_375_AXI1_END_ADDR_12_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_375_AXI1_END_ADDR_12_FLDSHFT (0)
#define HWIO_DDR_CTL_375_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_375_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_375_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_375_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_376_REGOFF 0x5e0
#define HWIO_DDR_CTL_376_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_376_REGOFF)
#define HWIO_DDR_CTL_376_AXI1_START_ADDR_13_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_376_AXI1_START_ADDR_13_FLDSHFT (0)
#define HWIO_DDR_CTL_376_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_376_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_376_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_376_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_377_REGOFF 0x5e4
#define HWIO_DDR_CTL_377_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_377_REGOFF)
#define HWIO_DDR_CTL_377_AXI1_END_ADDR_13_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_377_AXI1_END_ADDR_13_FLDSHFT (0)
#define HWIO_DDR_CTL_377_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_377_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_377_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_377_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_378_REGOFF 0x5e8
#define HWIO_DDR_CTL_378_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_378_REGOFF)
#define HWIO_DDR_CTL_378_AXI1_START_ADDR_14_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_378_AXI1_START_ADDR_14_FLDSHFT (0)
#define HWIO_DDR_CTL_378_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_378_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_378_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_378_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_379_REGOFF 0x5ec
#define HWIO_DDR_CTL_379_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_379_REGOFF)
#define HWIO_DDR_CTL_379_AXI1_END_ADDR_14_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_379_AXI1_END_ADDR_14_FLDSHFT (0)
#define HWIO_DDR_CTL_379_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_379_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_379_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_379_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_380_REGOFF 0x5f0
#define HWIO_DDR_CTL_380_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_380_REGOFF)
#define HWIO_DDR_CTL_380_AXI1_START_ADDR_15_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_380_AXI1_START_ADDR_15_FLDSHFT (0)
#define HWIO_DDR_CTL_380_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_380_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_380_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_380_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_CTL_381_REGOFF 0x5f4
#define HWIO_DDR_CTL_381_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_381_REGOFF)
#define HWIO_DDR_CTL_381_AXI1_END_ADDR_15_FLDMASK (0x3ffff)
#define HWIO_DDR_CTL_381_AXI1_END_ADDR_15_FLDSHFT (0)
#define HWIO_DDR_CTL_381_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_381_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_381_AXI0_RANGE_PROT_BITS_0_FLDMASK (0x3000000)
#define HWIO_DDR_CTL_381_AXI0_RANGE_PROT_BITS_0_FLDSHFT (24)
#define HWIO_DDR_CTL_381_CDNS_INTRL1_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_381_CDNS_INTRL1_FLDSHFT (26)

#define HWIO_DDR_CTL_382_REGOFF 0x5f8
#define HWIO_DDR_CTL_382_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_382_REGOFF)
#define HWIO_DDR_CTL_382_AXI0_RANGE_RID_CHECK_BITS_0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_382_AXI0_RANGE_RID_CHECK_BITS_0_FLDSHFT (0)
#define HWIO_DDR_CTL_382_AXI0_RANGE_WID_CHECK_BITS_0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_382_AXI0_RANGE_WID_CHECK_BITS_0_FLDSHFT (16)

#define HWIO_DDR_CTL_383_REGOFF 0x5fc
#define HWIO_DDR_CTL_383_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_383_REGOFF)
#define HWIO_DDR_CTL_383_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_383_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_383_AXI0_RANGE_PROT_BITS_1_FLDMASK (0x30000)
#define HWIO_DDR_CTL_383_AXI0_RANGE_PROT_BITS_1_FLDSHFT (16)
#define HWIO_DDR_CTL_383_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_383_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_383_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_383_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_384_REGOFF 0x600
#define HWIO_DDR_CTL_384_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_384_REGOFF)
#define HWIO_DDR_CTL_384_AXI0_RANGE_RID_CHECK_BITS_1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_384_AXI0_RANGE_RID_CHECK_BITS_1_FLDSHFT (0)
#define HWIO_DDR_CTL_384_AXI0_RANGE_WID_CHECK_BITS_1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_384_AXI0_RANGE_WID_CHECK_BITS_1_FLDSHFT (16)

#define HWIO_DDR_CTL_385_REGOFF 0x604
#define HWIO_DDR_CTL_385_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_385_REGOFF)
#define HWIO_DDR_CTL_385_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_385_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_385_AXI0_RANGE_PROT_BITS_2_FLDMASK (0x30000)
#define HWIO_DDR_CTL_385_AXI0_RANGE_PROT_BITS_2_FLDSHFT (16)
#define HWIO_DDR_CTL_385_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_385_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_385_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_385_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_386_REGOFF 0x608
#define HWIO_DDR_CTL_386_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_386_REGOFF)
#define HWIO_DDR_CTL_386_AXI0_RANGE_RID_CHECK_BITS_2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_386_AXI0_RANGE_RID_CHECK_BITS_2_FLDSHFT (0)
#define HWIO_DDR_CTL_386_AXI0_RANGE_WID_CHECK_BITS_2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_386_AXI0_RANGE_WID_CHECK_BITS_2_FLDSHFT (16)

#define HWIO_DDR_CTL_387_REGOFF 0x60c
#define HWIO_DDR_CTL_387_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_387_REGOFF)
#define HWIO_DDR_CTL_387_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_387_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_387_AXI0_RANGE_PROT_BITS_3_FLDMASK (0x30000)
#define HWIO_DDR_CTL_387_AXI0_RANGE_PROT_BITS_3_FLDSHFT (16)
#define HWIO_DDR_CTL_387_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_387_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_387_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_387_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_388_REGOFF 0x610
#define HWIO_DDR_CTL_388_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_388_REGOFF)
#define HWIO_DDR_CTL_388_AXI0_RANGE_RID_CHECK_BITS_3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_388_AXI0_RANGE_RID_CHECK_BITS_3_FLDSHFT (0)
#define HWIO_DDR_CTL_388_AXI0_RANGE_WID_CHECK_BITS_3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_388_AXI0_RANGE_WID_CHECK_BITS_3_FLDSHFT (16)

#define HWIO_DDR_CTL_389_REGOFF 0x614
#define HWIO_DDR_CTL_389_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_389_REGOFF)
#define HWIO_DDR_CTL_389_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_389_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_389_AXI0_RANGE_PROT_BITS_4_FLDMASK (0x30000)
#define HWIO_DDR_CTL_389_AXI0_RANGE_PROT_BITS_4_FLDSHFT (16)
#define HWIO_DDR_CTL_389_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_389_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_389_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_389_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_390_REGOFF 0x618
#define HWIO_DDR_CTL_390_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_390_REGOFF)
#define HWIO_DDR_CTL_390_AXI0_RANGE_RID_CHECK_BITS_4_FLDMASK (0xffff)
#define HWIO_DDR_CTL_390_AXI0_RANGE_RID_CHECK_BITS_4_FLDSHFT (0)
#define HWIO_DDR_CTL_390_AXI0_RANGE_WID_CHECK_BITS_4_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_390_AXI0_RANGE_WID_CHECK_BITS_4_FLDSHFT (16)

#define HWIO_DDR_CTL_391_REGOFF 0x61c
#define HWIO_DDR_CTL_391_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_391_REGOFF)
#define HWIO_DDR_CTL_391_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_391_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_391_AXI0_RANGE_PROT_BITS_5_FLDMASK (0x30000)
#define HWIO_DDR_CTL_391_AXI0_RANGE_PROT_BITS_5_FLDSHFT (16)
#define HWIO_DDR_CTL_391_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_391_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_391_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_391_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_392_REGOFF 0x620
#define HWIO_DDR_CTL_392_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_392_REGOFF)
#define HWIO_DDR_CTL_392_AXI0_RANGE_RID_CHECK_BITS_5_FLDMASK (0xffff)
#define HWIO_DDR_CTL_392_AXI0_RANGE_RID_CHECK_BITS_5_FLDSHFT (0)
#define HWIO_DDR_CTL_392_AXI0_RANGE_WID_CHECK_BITS_5_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_392_AXI0_RANGE_WID_CHECK_BITS_5_FLDSHFT (16)

#define HWIO_DDR_CTL_393_REGOFF 0x624
#define HWIO_DDR_CTL_393_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_393_REGOFF)
#define HWIO_DDR_CTL_393_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_393_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_393_AXI0_RANGE_PROT_BITS_6_FLDMASK (0x30000)
#define HWIO_DDR_CTL_393_AXI0_RANGE_PROT_BITS_6_FLDSHFT (16)
#define HWIO_DDR_CTL_393_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_393_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_393_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_393_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_394_REGOFF 0x628
#define HWIO_DDR_CTL_394_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_394_REGOFF)
#define HWIO_DDR_CTL_394_AXI0_RANGE_RID_CHECK_BITS_6_FLDMASK (0xffff)
#define HWIO_DDR_CTL_394_AXI0_RANGE_RID_CHECK_BITS_6_FLDSHFT (0)
#define HWIO_DDR_CTL_394_AXI0_RANGE_WID_CHECK_BITS_6_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_394_AXI0_RANGE_WID_CHECK_BITS_6_FLDSHFT (16)

#define HWIO_DDR_CTL_395_REGOFF 0x62c
#define HWIO_DDR_CTL_395_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_395_REGOFF)
#define HWIO_DDR_CTL_395_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_395_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_395_AXI0_RANGE_PROT_BITS_7_FLDMASK (0x30000)
#define HWIO_DDR_CTL_395_AXI0_RANGE_PROT_BITS_7_FLDSHFT (16)
#define HWIO_DDR_CTL_395_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_395_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_395_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_395_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_396_REGOFF 0x630
#define HWIO_DDR_CTL_396_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_396_REGOFF)
#define HWIO_DDR_CTL_396_AXI0_RANGE_RID_CHECK_BITS_7_FLDMASK (0xffff)
#define HWIO_DDR_CTL_396_AXI0_RANGE_RID_CHECK_BITS_7_FLDSHFT (0)
#define HWIO_DDR_CTL_396_AXI0_RANGE_WID_CHECK_BITS_7_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_396_AXI0_RANGE_WID_CHECK_BITS_7_FLDSHFT (16)

#define HWIO_DDR_CTL_397_REGOFF 0x634
#define HWIO_DDR_CTL_397_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_397_REGOFF)
#define HWIO_DDR_CTL_397_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_397_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_397_AXI0_RANGE_PROT_BITS_8_FLDMASK (0x30000)
#define HWIO_DDR_CTL_397_AXI0_RANGE_PROT_BITS_8_FLDSHFT (16)
#define HWIO_DDR_CTL_397_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_397_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_397_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_397_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_398_REGOFF 0x638
#define HWIO_DDR_CTL_398_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_398_REGOFF)
#define HWIO_DDR_CTL_398_AXI0_RANGE_RID_CHECK_BITS_8_FLDMASK (0xffff)
#define HWIO_DDR_CTL_398_AXI0_RANGE_RID_CHECK_BITS_8_FLDSHFT (0)
#define HWIO_DDR_CTL_398_AXI0_RANGE_WID_CHECK_BITS_8_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_398_AXI0_RANGE_WID_CHECK_BITS_8_FLDSHFT (16)

#define HWIO_DDR_CTL_399_REGOFF 0x63c
#define HWIO_DDR_CTL_399_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_399_REGOFF)
#define HWIO_DDR_CTL_399_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_399_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_399_AXI0_RANGE_PROT_BITS_9_FLDMASK (0x30000)
#define HWIO_DDR_CTL_399_AXI0_RANGE_PROT_BITS_9_FLDSHFT (16)
#define HWIO_DDR_CTL_399_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_399_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_399_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_399_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_400_REGOFF 0x640
#define HWIO_DDR_CTL_400_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_400_REGOFF)
#define HWIO_DDR_CTL_400_AXI0_RANGE_RID_CHECK_BITS_9_FLDMASK (0xffff)
#define HWIO_DDR_CTL_400_AXI0_RANGE_RID_CHECK_BITS_9_FLDSHFT (0)
#define HWIO_DDR_CTL_400_AXI0_RANGE_WID_CHECK_BITS_9_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_400_AXI0_RANGE_WID_CHECK_BITS_9_FLDSHFT (16)

#define HWIO_DDR_CTL_401_REGOFF 0x644
#define HWIO_DDR_CTL_401_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_401_REGOFF)
#define HWIO_DDR_CTL_401_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_401_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_401_AXI0_RANGE_PROT_BITS_10_FLDMASK (0x30000)
#define HWIO_DDR_CTL_401_AXI0_RANGE_PROT_BITS_10_FLDSHFT (16)
#define HWIO_DDR_CTL_401_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_401_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_401_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_401_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_402_REGOFF 0x648
#define HWIO_DDR_CTL_402_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_402_REGOFF)
#define HWIO_DDR_CTL_402_AXI0_RANGE_RID_CHECK_BITS_10_FLDMASK (0xffff)
#define HWIO_DDR_CTL_402_AXI0_RANGE_RID_CHECK_BITS_10_FLDSHFT (0)
#define HWIO_DDR_CTL_402_AXI0_RANGE_WID_CHECK_BITS_10_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_402_AXI0_RANGE_WID_CHECK_BITS_10_FLDSHFT (16)

#define HWIO_DDR_CTL_403_REGOFF 0x64c
#define HWIO_DDR_CTL_403_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_403_REGOFF)
#define HWIO_DDR_CTL_403_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_403_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_403_AXI0_RANGE_PROT_BITS_11_FLDMASK (0x30000)
#define HWIO_DDR_CTL_403_AXI0_RANGE_PROT_BITS_11_FLDSHFT (16)
#define HWIO_DDR_CTL_403_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_403_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_403_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_403_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_404_REGOFF 0x650
#define HWIO_DDR_CTL_404_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_404_REGOFF)
#define HWIO_DDR_CTL_404_AXI0_RANGE_RID_CHECK_BITS_11_FLDMASK (0xffff)
#define HWIO_DDR_CTL_404_AXI0_RANGE_RID_CHECK_BITS_11_FLDSHFT (0)
#define HWIO_DDR_CTL_404_AXI0_RANGE_WID_CHECK_BITS_11_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_404_AXI0_RANGE_WID_CHECK_BITS_11_FLDSHFT (16)

#define HWIO_DDR_CTL_405_REGOFF 0x654
#define HWIO_DDR_CTL_405_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_405_REGOFF)
#define HWIO_DDR_CTL_405_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_405_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_405_AXI0_RANGE_PROT_BITS_12_FLDMASK (0x30000)
#define HWIO_DDR_CTL_405_AXI0_RANGE_PROT_BITS_12_FLDSHFT (16)
#define HWIO_DDR_CTL_405_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_405_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_405_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_405_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_406_REGOFF 0x658
#define HWIO_DDR_CTL_406_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_406_REGOFF)
#define HWIO_DDR_CTL_406_AXI0_RANGE_RID_CHECK_BITS_12_FLDMASK (0xffff)
#define HWIO_DDR_CTL_406_AXI0_RANGE_RID_CHECK_BITS_12_FLDSHFT (0)
#define HWIO_DDR_CTL_406_AXI0_RANGE_WID_CHECK_BITS_12_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_406_AXI0_RANGE_WID_CHECK_BITS_12_FLDSHFT (16)

#define HWIO_DDR_CTL_407_REGOFF 0x65c
#define HWIO_DDR_CTL_407_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_407_REGOFF)
#define HWIO_DDR_CTL_407_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_407_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_407_AXI0_RANGE_PROT_BITS_13_FLDMASK (0x30000)
#define HWIO_DDR_CTL_407_AXI0_RANGE_PROT_BITS_13_FLDSHFT (16)
#define HWIO_DDR_CTL_407_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_407_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_407_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_407_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_408_REGOFF 0x660
#define HWIO_DDR_CTL_408_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_408_REGOFF)
#define HWIO_DDR_CTL_408_AXI0_RANGE_RID_CHECK_BITS_13_FLDMASK (0xffff)
#define HWIO_DDR_CTL_408_AXI0_RANGE_RID_CHECK_BITS_13_FLDSHFT (0)
#define HWIO_DDR_CTL_408_AXI0_RANGE_WID_CHECK_BITS_13_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_408_AXI0_RANGE_WID_CHECK_BITS_13_FLDSHFT (16)

#define HWIO_DDR_CTL_409_REGOFF 0x664
#define HWIO_DDR_CTL_409_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_409_REGOFF)
#define HWIO_DDR_CTL_409_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_409_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_409_AXI0_RANGE_PROT_BITS_14_FLDMASK (0x30000)
#define HWIO_DDR_CTL_409_AXI0_RANGE_PROT_BITS_14_FLDSHFT (16)
#define HWIO_DDR_CTL_409_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_409_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_409_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_409_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_410_REGOFF 0x668
#define HWIO_DDR_CTL_410_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_410_REGOFF)
#define HWIO_DDR_CTL_410_AXI0_RANGE_RID_CHECK_BITS_14_FLDMASK (0xffff)
#define HWIO_DDR_CTL_410_AXI0_RANGE_RID_CHECK_BITS_14_FLDSHFT (0)
#define HWIO_DDR_CTL_410_AXI0_RANGE_WID_CHECK_BITS_14_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_410_AXI0_RANGE_WID_CHECK_BITS_14_FLDSHFT (16)

#define HWIO_DDR_CTL_411_REGOFF 0x66c
#define HWIO_DDR_CTL_411_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_411_REGOFF)
#define HWIO_DDR_CTL_411_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_411_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_411_AXI0_RANGE_PROT_BITS_15_FLDMASK (0x30000)
#define HWIO_DDR_CTL_411_AXI0_RANGE_PROT_BITS_15_FLDSHFT (16)
#define HWIO_DDR_CTL_411_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_411_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_411_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_411_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_412_REGOFF 0x670
#define HWIO_DDR_CTL_412_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_412_REGOFF)
#define HWIO_DDR_CTL_412_AXI0_RANGE_RID_CHECK_BITS_15_FLDMASK (0xffff)
#define HWIO_DDR_CTL_412_AXI0_RANGE_RID_CHECK_BITS_15_FLDSHFT (0)
#define HWIO_DDR_CTL_412_AXI0_RANGE_WID_CHECK_BITS_15_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_412_AXI0_RANGE_WID_CHECK_BITS_15_FLDSHFT (16)

#define HWIO_DDR_CTL_413_REGOFF 0x674
#define HWIO_DDR_CTL_413_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_413_REGOFF)
#define HWIO_DDR_CTL_413_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_413_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_413_AXI1_RANGE_PROT_BITS_0_FLDMASK (0x30000)
#define HWIO_DDR_CTL_413_AXI1_RANGE_PROT_BITS_0_FLDSHFT (16)
#define HWIO_DDR_CTL_413_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_413_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_413_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_413_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_414_REGOFF 0x678
#define HWIO_DDR_CTL_414_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_414_REGOFF)
#define HWIO_DDR_CTL_414_AXI1_RANGE_RID_CHECK_BITS_0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_414_AXI1_RANGE_RID_CHECK_BITS_0_FLDSHFT (0)
#define HWIO_DDR_CTL_414_AXI1_RANGE_WID_CHECK_BITS_0_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_414_AXI1_RANGE_WID_CHECK_BITS_0_FLDSHFT (16)

#define HWIO_DDR_CTL_415_REGOFF 0x67c
#define HWIO_DDR_CTL_415_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_415_REGOFF)
#define HWIO_DDR_CTL_415_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_415_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_415_AXI1_RANGE_PROT_BITS_1_FLDMASK (0x30000)
#define HWIO_DDR_CTL_415_AXI1_RANGE_PROT_BITS_1_FLDSHFT (16)
#define HWIO_DDR_CTL_415_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_415_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_415_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_415_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_416_REGOFF 0x680
#define HWIO_DDR_CTL_416_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_416_REGOFF)
#define HWIO_DDR_CTL_416_AXI1_RANGE_RID_CHECK_BITS_1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_416_AXI1_RANGE_RID_CHECK_BITS_1_FLDSHFT (0)
#define HWIO_DDR_CTL_416_AXI1_RANGE_WID_CHECK_BITS_1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_416_AXI1_RANGE_WID_CHECK_BITS_1_FLDSHFT (16)

#define HWIO_DDR_CTL_417_REGOFF 0x684
#define HWIO_DDR_CTL_417_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_417_REGOFF)
#define HWIO_DDR_CTL_417_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_417_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_417_AXI1_RANGE_PROT_BITS_2_FLDMASK (0x30000)
#define HWIO_DDR_CTL_417_AXI1_RANGE_PROT_BITS_2_FLDSHFT (16)
#define HWIO_DDR_CTL_417_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_417_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_417_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_417_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_418_REGOFF 0x688
#define HWIO_DDR_CTL_418_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_418_REGOFF)
#define HWIO_DDR_CTL_418_AXI1_RANGE_RID_CHECK_BITS_2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_418_AXI1_RANGE_RID_CHECK_BITS_2_FLDSHFT (0)
#define HWIO_DDR_CTL_418_AXI1_RANGE_WID_CHECK_BITS_2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_418_AXI1_RANGE_WID_CHECK_BITS_2_FLDSHFT (16)

#define HWIO_DDR_CTL_419_REGOFF 0x68c
#define HWIO_DDR_CTL_419_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_419_REGOFF)
#define HWIO_DDR_CTL_419_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_419_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_419_AXI1_RANGE_PROT_BITS_3_FLDMASK (0x30000)
#define HWIO_DDR_CTL_419_AXI1_RANGE_PROT_BITS_3_FLDSHFT (16)
#define HWIO_DDR_CTL_419_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_419_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_419_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_419_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_420_REGOFF 0x690
#define HWIO_DDR_CTL_420_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_420_REGOFF)
#define HWIO_DDR_CTL_420_AXI1_RANGE_RID_CHECK_BITS_3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_420_AXI1_RANGE_RID_CHECK_BITS_3_FLDSHFT (0)
#define HWIO_DDR_CTL_420_AXI1_RANGE_WID_CHECK_BITS_3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_420_AXI1_RANGE_WID_CHECK_BITS_3_FLDSHFT (16)

#define HWIO_DDR_CTL_421_REGOFF 0x694
#define HWIO_DDR_CTL_421_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_421_REGOFF)
#define HWIO_DDR_CTL_421_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_421_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_421_AXI1_RANGE_PROT_BITS_4_FLDMASK (0x30000)
#define HWIO_DDR_CTL_421_AXI1_RANGE_PROT_BITS_4_FLDSHFT (16)
#define HWIO_DDR_CTL_421_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_421_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_421_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_421_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_422_REGOFF 0x698
#define HWIO_DDR_CTL_422_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_422_REGOFF)
#define HWIO_DDR_CTL_422_AXI1_RANGE_RID_CHECK_BITS_4_FLDMASK (0xffff)
#define HWIO_DDR_CTL_422_AXI1_RANGE_RID_CHECK_BITS_4_FLDSHFT (0)
#define HWIO_DDR_CTL_422_AXI1_RANGE_WID_CHECK_BITS_4_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_422_AXI1_RANGE_WID_CHECK_BITS_4_FLDSHFT (16)

#define HWIO_DDR_CTL_423_REGOFF 0x69c
#define HWIO_DDR_CTL_423_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_423_REGOFF)
#define HWIO_DDR_CTL_423_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_423_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_423_AXI1_RANGE_PROT_BITS_5_FLDMASK (0x30000)
#define HWIO_DDR_CTL_423_AXI1_RANGE_PROT_BITS_5_FLDSHFT (16)
#define HWIO_DDR_CTL_423_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_423_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_423_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_423_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_424_REGOFF 0x6a0
#define HWIO_DDR_CTL_424_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_424_REGOFF)
#define HWIO_DDR_CTL_424_AXI1_RANGE_RID_CHECK_BITS_5_FLDMASK (0xffff)
#define HWIO_DDR_CTL_424_AXI1_RANGE_RID_CHECK_BITS_5_FLDSHFT (0)
#define HWIO_DDR_CTL_424_AXI1_RANGE_WID_CHECK_BITS_5_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_424_AXI1_RANGE_WID_CHECK_BITS_5_FLDSHFT (16)

#define HWIO_DDR_CTL_425_REGOFF 0x6a4
#define HWIO_DDR_CTL_425_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_425_REGOFF)
#define HWIO_DDR_CTL_425_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_425_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_425_AXI1_RANGE_PROT_BITS_6_FLDMASK (0x30000)
#define HWIO_DDR_CTL_425_AXI1_RANGE_PROT_BITS_6_FLDSHFT (16)
#define HWIO_DDR_CTL_425_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_425_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_425_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_425_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_426_REGOFF 0x6a8
#define HWIO_DDR_CTL_426_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_426_REGOFF)
#define HWIO_DDR_CTL_426_AXI1_RANGE_RID_CHECK_BITS_6_FLDMASK (0xffff)
#define HWIO_DDR_CTL_426_AXI1_RANGE_RID_CHECK_BITS_6_FLDSHFT (0)
#define HWIO_DDR_CTL_426_AXI1_RANGE_WID_CHECK_BITS_6_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_426_AXI1_RANGE_WID_CHECK_BITS_6_FLDSHFT (16)

#define HWIO_DDR_CTL_427_REGOFF 0x6ac
#define HWIO_DDR_CTL_427_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_427_REGOFF)
#define HWIO_DDR_CTL_427_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_427_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_427_AXI1_RANGE_PROT_BITS_7_FLDMASK (0x30000)
#define HWIO_DDR_CTL_427_AXI1_RANGE_PROT_BITS_7_FLDSHFT (16)
#define HWIO_DDR_CTL_427_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_427_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_427_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_427_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_428_REGOFF 0x6b0
#define HWIO_DDR_CTL_428_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_428_REGOFF)
#define HWIO_DDR_CTL_428_AXI1_RANGE_RID_CHECK_BITS_7_FLDMASK (0xffff)
#define HWIO_DDR_CTL_428_AXI1_RANGE_RID_CHECK_BITS_7_FLDSHFT (0)
#define HWIO_DDR_CTL_428_AXI1_RANGE_WID_CHECK_BITS_7_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_428_AXI1_RANGE_WID_CHECK_BITS_7_FLDSHFT (16)

#define HWIO_DDR_CTL_429_REGOFF 0x6b4
#define HWIO_DDR_CTL_429_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_429_REGOFF)
#define HWIO_DDR_CTL_429_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_429_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_429_AXI1_RANGE_PROT_BITS_8_FLDMASK (0x30000)
#define HWIO_DDR_CTL_429_AXI1_RANGE_PROT_BITS_8_FLDSHFT (16)
#define HWIO_DDR_CTL_429_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_429_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_429_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_429_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_430_REGOFF 0x6b8
#define HWIO_DDR_CTL_430_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_430_REGOFF)
#define HWIO_DDR_CTL_430_AXI1_RANGE_RID_CHECK_BITS_8_FLDMASK (0xffff)
#define HWIO_DDR_CTL_430_AXI1_RANGE_RID_CHECK_BITS_8_FLDSHFT (0)
#define HWIO_DDR_CTL_430_AXI1_RANGE_WID_CHECK_BITS_8_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_430_AXI1_RANGE_WID_CHECK_BITS_8_FLDSHFT (16)

#define HWIO_DDR_CTL_431_REGOFF 0x6bc
#define HWIO_DDR_CTL_431_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_431_REGOFF)
#define HWIO_DDR_CTL_431_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_431_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_431_AXI1_RANGE_PROT_BITS_9_FLDMASK (0x30000)
#define HWIO_DDR_CTL_431_AXI1_RANGE_PROT_BITS_9_FLDSHFT (16)
#define HWIO_DDR_CTL_431_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_431_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_431_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_431_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_432_REGOFF 0x6c0
#define HWIO_DDR_CTL_432_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_432_REGOFF)
#define HWIO_DDR_CTL_432_AXI1_RANGE_RID_CHECK_BITS_9_FLDMASK (0xffff)
#define HWIO_DDR_CTL_432_AXI1_RANGE_RID_CHECK_BITS_9_FLDSHFT (0)
#define HWIO_DDR_CTL_432_AXI1_RANGE_WID_CHECK_BITS_9_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_432_AXI1_RANGE_WID_CHECK_BITS_9_FLDSHFT (16)

#define HWIO_DDR_CTL_433_REGOFF 0x6c4
#define HWIO_DDR_CTL_433_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_433_REGOFF)
#define HWIO_DDR_CTL_433_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_433_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_433_AXI1_RANGE_PROT_BITS_10_FLDMASK (0x30000)
#define HWIO_DDR_CTL_433_AXI1_RANGE_PROT_BITS_10_FLDSHFT (16)
#define HWIO_DDR_CTL_433_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_433_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_433_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_433_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_434_REGOFF 0x6c8
#define HWIO_DDR_CTL_434_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_434_REGOFF)
#define HWIO_DDR_CTL_434_AXI1_RANGE_RID_CHECK_BITS_10_FLDMASK (0xffff)
#define HWIO_DDR_CTL_434_AXI1_RANGE_RID_CHECK_BITS_10_FLDSHFT (0)
#define HWIO_DDR_CTL_434_AXI1_RANGE_WID_CHECK_BITS_10_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_434_AXI1_RANGE_WID_CHECK_BITS_10_FLDSHFT (16)

#define HWIO_DDR_CTL_435_REGOFF 0x6cc
#define HWIO_DDR_CTL_435_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_435_REGOFF)
#define HWIO_DDR_CTL_435_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_435_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_435_AXI1_RANGE_PROT_BITS_11_FLDMASK (0x30000)
#define HWIO_DDR_CTL_435_AXI1_RANGE_PROT_BITS_11_FLDSHFT (16)
#define HWIO_DDR_CTL_435_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_435_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_435_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_435_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_436_REGOFF 0x6d0
#define HWIO_DDR_CTL_436_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_436_REGOFF)
#define HWIO_DDR_CTL_436_AXI1_RANGE_RID_CHECK_BITS_11_FLDMASK (0xffff)
#define HWIO_DDR_CTL_436_AXI1_RANGE_RID_CHECK_BITS_11_FLDSHFT (0)
#define HWIO_DDR_CTL_436_AXI1_RANGE_WID_CHECK_BITS_11_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_436_AXI1_RANGE_WID_CHECK_BITS_11_FLDSHFT (16)

#define HWIO_DDR_CTL_437_REGOFF 0x6d4
#define HWIO_DDR_CTL_437_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_437_REGOFF)
#define HWIO_DDR_CTL_437_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_437_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_437_AXI1_RANGE_PROT_BITS_12_FLDMASK (0x30000)
#define HWIO_DDR_CTL_437_AXI1_RANGE_PROT_BITS_12_FLDSHFT (16)
#define HWIO_DDR_CTL_437_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_437_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_437_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_437_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_438_REGOFF 0x6d8
#define HWIO_DDR_CTL_438_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_438_REGOFF)
#define HWIO_DDR_CTL_438_AXI1_RANGE_RID_CHECK_BITS_12_FLDMASK (0xffff)
#define HWIO_DDR_CTL_438_AXI1_RANGE_RID_CHECK_BITS_12_FLDSHFT (0)
#define HWIO_DDR_CTL_438_AXI1_RANGE_WID_CHECK_BITS_12_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_438_AXI1_RANGE_WID_CHECK_BITS_12_FLDSHFT (16)

#define HWIO_DDR_CTL_439_REGOFF 0x6dc
#define HWIO_DDR_CTL_439_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_439_REGOFF)
#define HWIO_DDR_CTL_439_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_439_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_439_AXI1_RANGE_PROT_BITS_13_FLDMASK (0x30000)
#define HWIO_DDR_CTL_439_AXI1_RANGE_PROT_BITS_13_FLDSHFT (16)
#define HWIO_DDR_CTL_439_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_439_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_439_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_439_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_440_REGOFF 0x6e0
#define HWIO_DDR_CTL_440_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_440_REGOFF)
#define HWIO_DDR_CTL_440_AXI1_RANGE_RID_CHECK_BITS_13_FLDMASK (0xffff)
#define HWIO_DDR_CTL_440_AXI1_RANGE_RID_CHECK_BITS_13_FLDSHFT (0)
#define HWIO_DDR_CTL_440_AXI1_RANGE_WID_CHECK_BITS_13_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_440_AXI1_RANGE_WID_CHECK_BITS_13_FLDSHFT (16)

#define HWIO_DDR_CTL_441_REGOFF 0x6e4
#define HWIO_DDR_CTL_441_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_441_REGOFF)
#define HWIO_DDR_CTL_441_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_441_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_441_AXI1_RANGE_PROT_BITS_14_FLDMASK (0x30000)
#define HWIO_DDR_CTL_441_AXI1_RANGE_PROT_BITS_14_FLDSHFT (16)
#define HWIO_DDR_CTL_441_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_441_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_441_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_441_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_442_REGOFF 0x6e8
#define HWIO_DDR_CTL_442_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_442_REGOFF)
#define HWIO_DDR_CTL_442_AXI1_RANGE_RID_CHECK_BITS_14_FLDMASK (0xffff)
#define HWIO_DDR_CTL_442_AXI1_RANGE_RID_CHECK_BITS_14_FLDSHFT (0)
#define HWIO_DDR_CTL_442_AXI1_RANGE_WID_CHECK_BITS_14_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_442_AXI1_RANGE_WID_CHECK_BITS_14_FLDSHFT (16)

#define HWIO_DDR_CTL_443_REGOFF 0x6ec
#define HWIO_DDR_CTL_443_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_443_REGOFF)
#define HWIO_DDR_CTL_443_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_443_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_443_AXI1_RANGE_PROT_BITS_15_FLDMASK (0x30000)
#define HWIO_DDR_CTL_443_AXI1_RANGE_PROT_BITS_15_FLDSHFT (16)
#define HWIO_DDR_CTL_443_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_443_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_443_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_443_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_444_REGOFF 0x6f0
#define HWIO_DDR_CTL_444_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_444_REGOFF)
#define HWIO_DDR_CTL_444_AXI1_RANGE_RID_CHECK_BITS_15_FLDMASK (0xffff)
#define HWIO_DDR_CTL_444_AXI1_RANGE_RID_CHECK_BITS_15_FLDSHFT (0)
#define HWIO_DDR_CTL_444_AXI1_RANGE_WID_CHECK_BITS_15_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_444_AXI1_RANGE_WID_CHECK_BITS_15_FLDSHFT (16)

#define HWIO_DDR_CTL_445_REGOFF 0x6f4
#define HWIO_DDR_CTL_445_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_445_REGOFF)
#define HWIO_DDR_CTL_445_OBSOLETE0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_445_OBSOLETE0_FLDSHFT (0)
#define HWIO_DDR_CTL_445_WEIGHTED_ROUND_ROBIN_LATENCY_CONTROL_FLDMASK (0x10000)
#define HWIO_DDR_CTL_445_WEIGHTED_ROUND_ROBIN_LATENCY_CONTROL_FLDSHFT (16)
#define HWIO_DDR_CTL_445_RESERVED_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_445_RESERVED_FLDSHFT (17)
#define HWIO_DDR_CTL_445_WEIGHTED_ROUND_ROBIN_WEIGHT_SHARING_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_445_WEIGHTED_ROUND_ROBIN_WEIGHT_SHARING_FLDSHFT (24)
#define HWIO_DDR_CTL_445_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_445_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_446_REGOFF 0x6f8
#define HWIO_DDR_CTL_446_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_446_REGOFF)
#define HWIO_DDR_CTL_446_WRR_PARAM_VALUE_ERR_FLDMASK (0xf)
#define HWIO_DDR_CTL_446_WRR_PARAM_VALUE_ERR_FLDSHFT (0)
#define HWIO_DDR_CTL_446_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_446_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_446_AXI0_PRIORITY0_RELATIVE_PRIORITY_FLDMASK (0xf00)
#define HWIO_DDR_CTL_446_AXI0_PRIORITY0_RELATIVE_PRIORITY_FLDSHFT (8)
#define HWIO_DDR_CTL_446_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_446_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_446_AXI0_PRIORITY1_RELATIVE_PRIORITY_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_446_AXI0_PRIORITY1_RELATIVE_PRIORITY_FLDSHFT (16)
#define HWIO_DDR_CTL_446_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_446_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_446_AXI0_PRIORITY2_RELATIVE_PRIORITY_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_446_AXI0_PRIORITY2_RELATIVE_PRIORITY_FLDSHFT (24)
#define HWIO_DDR_CTL_446_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_446_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_447_REGOFF 0x6fc
#define HWIO_DDR_CTL_447_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_447_REGOFF)
#define HWIO_DDR_CTL_447_AXI0_PRIORITY3_RELATIVE_PRIORITY_FLDMASK (0xf)
#define HWIO_DDR_CTL_447_AXI0_PRIORITY3_RELATIVE_PRIORITY_FLDSHFT (0)
#define HWIO_DDR_CTL_447_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_447_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_447_AXI0_PORT_ORDERING_FLDMASK (0x100)
#define HWIO_DDR_CTL_447_AXI0_PORT_ORDERING_FLDSHFT (8)
#define HWIO_DDR_CTL_447_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_447_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_447_AXI0_PRIORITY_RELAX_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_447_AXI0_PRIORITY_RELAX_FLDSHFT (16)
#define HWIO_DDR_CTL_447_CDNS_INTRL2_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_447_CDNS_INTRL2_FLDSHFT (26)

#define HWIO_DDR_CTL_448_REGOFF 0x700
#define HWIO_DDR_CTL_448_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_448_REGOFF)
#define HWIO_DDR_CTL_448_AXI1_PRIORITY0_RELATIVE_PRIORITY_FLDMASK (0xf)
#define HWIO_DDR_CTL_448_AXI1_PRIORITY0_RELATIVE_PRIORITY_FLDSHFT (0)
#define HWIO_DDR_CTL_448_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_448_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_448_AXI1_PRIORITY1_RELATIVE_PRIORITY_FLDMASK (0xf00)
#define HWIO_DDR_CTL_448_AXI1_PRIORITY1_RELATIVE_PRIORITY_FLDSHFT (8)
#define HWIO_DDR_CTL_448_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_448_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_448_AXI1_PRIORITY2_RELATIVE_PRIORITY_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_448_AXI1_PRIORITY2_RELATIVE_PRIORITY_FLDSHFT (16)
#define HWIO_DDR_CTL_448_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_448_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_448_AXI1_PRIORITY3_RELATIVE_PRIORITY_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_448_AXI1_PRIORITY3_RELATIVE_PRIORITY_FLDSHFT (24)
#define HWIO_DDR_CTL_448_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_448_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_449_REGOFF 0x704
#define HWIO_DDR_CTL_449_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_449_REGOFF)
#define HWIO_DDR_CTL_449_AXI1_PORT_ORDERING_FLDMASK (0x1)
#define HWIO_DDR_CTL_449_AXI1_PORT_ORDERING_FLDSHFT (0)
#define HWIO_DDR_CTL_449_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_449_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_449_AXI1_PRIORITY_RELAX_FLDMASK (0x3ff00)
#define HWIO_DDR_CTL_449_AXI1_PRIORITY_RELAX_FLDSHFT (8)
#define HWIO_DDR_CTL_449_CDNS_INTRL1_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_449_CDNS_INTRL1_FLDSHFT (18)
#define HWIO_DDR_CTL_449_CKE_STATUS_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_449_CKE_STATUS_FLDSHFT (24)
#define HWIO_DDR_CTL_449_CDNS_INTRL2_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_449_CDNS_INTRL2_FLDSHFT (25)

#define HWIO_DDR_CTL_450_REGOFF 0x708
#define HWIO_DDR_CTL_450_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_450_REGOFF)
#define HWIO_DDR_CTL_450_MEM_RST_VALID_FLDMASK (0x1)
#define HWIO_DDR_CTL_450_MEM_RST_VALID_FLDSHFT (0)
#define HWIO_DDR_CTL_450_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_450_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_450_DLL_RST_DELAY_FLDMASK (0xffff00)
#define HWIO_DDR_CTL_450_DLL_RST_DELAY_FLDSHFT (8)
#define HWIO_DDR_CTL_450_DLL_RST_ADJ_DLY_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_450_DLL_RST_ADJ_DLY_FLDSHFT (24)

#define HWIO_DDR_CTL_451_REGOFF 0x70c
#define HWIO_DDR_CTL_451_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_451_REGOFF)
#define HWIO_DDR_CTL_451_TDFI_PHY_WRLAT_FLDMASK (0x7f)
#define HWIO_DDR_CTL_451_TDFI_PHY_WRLAT_FLDSHFT (0)
#define HWIO_DDR_CTL_451_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_CTL_451_RESERVED_FLDSHFT (7)
#define HWIO_DDR_CTL_451_UPDATE_ERROR_STATUS_FLDMASK (0x7f00)
#define HWIO_DDR_CTL_451_UPDATE_ERROR_STATUS_FLDSHFT (8)
#define HWIO_DDR_CTL_451_CDNS_INTRL1_FLDMASK (0x8000)
#define HWIO_DDR_CTL_451_CDNS_INTRL1_FLDSHFT (15)
#define HWIO_DDR_CTL_451_TDFI_PHY_RDLAT_F0_FLDMASK (0x7f0000)
#define HWIO_DDR_CTL_451_TDFI_PHY_RDLAT_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_451_CDNS_INTRL2_FLDMASK (0x800000)
#define HWIO_DDR_CTL_451_CDNS_INTRL2_FLDSHFT (23)
#define HWIO_DDR_CTL_451_TDFI_PHY_RDLAT_F1_FLDMASK (0x7f000000)
#define HWIO_DDR_CTL_451_TDFI_PHY_RDLAT_F1_FLDSHFT (24)
#define HWIO_DDR_CTL_451_CDNS_INTRL3_FLDMASK (0x80000000)
#define HWIO_DDR_CTL_451_CDNS_INTRL3_FLDSHFT (31)

#define HWIO_DDR_CTL_452_REGOFF 0x710
#define HWIO_DDR_CTL_452_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_452_REGOFF)
#define HWIO_DDR_CTL_452_TDFI_PHY_RDLAT_F2_FLDMASK (0x7f)
#define HWIO_DDR_CTL_452_TDFI_PHY_RDLAT_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_452_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_CTL_452_RESERVED_FLDSHFT (7)
#define HWIO_DDR_CTL_452_TDFI_PHY_RDLAT_F3_FLDMASK (0x7f00)
#define HWIO_DDR_CTL_452_TDFI_PHY_RDLAT_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_452_CDNS_INTRL1_FLDMASK (0x8000)
#define HWIO_DDR_CTL_452_CDNS_INTRL1_FLDSHFT (15)
#define HWIO_DDR_CTL_452_TDFI_RDDATA_EN_FLDMASK (0x7f0000)
#define HWIO_DDR_CTL_452_TDFI_RDDATA_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_452_CDNS_INTRL2_FLDMASK (0x800000)
#define HWIO_DDR_CTL_452_CDNS_INTRL2_FLDSHFT (23)
#define HWIO_DDR_CTL_452_DRAM_CLK_DISABLE_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_452_DRAM_CLK_DISABLE_FLDSHFT (24)
#define HWIO_DDR_CTL_452_CDNS_INTRL3_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_452_CDNS_INTRL3_FLDSHFT (25)

#define HWIO_DDR_CTL_453_REGOFF 0x714
#define HWIO_DDR_CTL_453_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_453_REGOFF)
#define HWIO_DDR_CTL_453_TDFI_CTRLUPD_MIN_FLDMASK (0xf)
#define HWIO_DDR_CTL_453_TDFI_CTRLUPD_MIN_FLDSHFT (0)
#define HWIO_DDR_CTL_453_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_453_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_453_TDFI_CTRLUPD_MAX_F0_FLDMASK (0xffff00)
#define HWIO_DDR_CTL_453_TDFI_CTRLUPD_MAX_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_453_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_453_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_454_REGOFF 0x718
#define HWIO_DDR_CTL_454_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_454_REGOFF)
#define HWIO_DDR_CTL_454_OBSOLETE0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_454_OBSOLETE0_FLDSHFT (0)

#define HWIO_DDR_CTL_455_REGOFF 0x71c
#define HWIO_DDR_CTL_455_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_455_REGOFF)
#define HWIO_DDR_CTL_455_OBSOLETE0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_455_OBSOLETE0_FLDSHFT (0)

#define HWIO_DDR_CTL_456_REGOFF 0x720
#define HWIO_DDR_CTL_456_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_456_REGOFF)
#define HWIO_DDR_CTL_456_TDFI_PHYUPD_RESP_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_456_TDFI_PHYUPD_RESP_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_456_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_456_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_CTL_457_REGOFF 0x724
#define HWIO_DDR_CTL_457_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_457_REGOFF)
#define HWIO_DDR_CTL_457_TDFI_CTRLUPD_INTERVAL_F0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_457_TDFI_CTRLUPD_INTERVAL_F0_FLDSHFT (0)

#define HWIO_DDR_CTL_458_REGOFF 0x728
#define HWIO_DDR_CTL_458_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_458_REGOFF)
#define HWIO_DDR_CTL_458_RDLAT_ADJ_F0_FLDMASK (0x7f)
#define HWIO_DDR_CTL_458_RDLAT_ADJ_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_458_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_CTL_458_RESERVED_FLDSHFT (7)
#define HWIO_DDR_CTL_458_WRLAT_ADJ_F0_FLDMASK (0x7f00)
#define HWIO_DDR_CTL_458_WRLAT_ADJ_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_458_CDNS_INTRL1_FLDMASK (0x8000)
#define HWIO_DDR_CTL_458_CDNS_INTRL1_FLDSHFT (15)
#define HWIO_DDR_CTL_458_TDFI_CTRLUPD_MAX_F1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_458_TDFI_CTRLUPD_MAX_F1_FLDSHFT (16)

#define HWIO_DDR_CTL_459_REGOFF 0x72c
#define HWIO_DDR_CTL_459_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_459_REGOFF)
#define HWIO_DDR_CTL_459_OBSOLETE0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_459_OBSOLETE0_FLDSHFT (0)

#define HWIO_DDR_CTL_460_REGOFF 0x730
#define HWIO_DDR_CTL_460_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_460_REGOFF)
#define HWIO_DDR_CTL_460_OBSOLETE0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_460_OBSOLETE0_FLDSHFT (0)

#define HWIO_DDR_CTL_461_REGOFF 0x734
#define HWIO_DDR_CTL_461_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_461_REGOFF)
#define HWIO_DDR_CTL_461_TDFI_PHYUPD_RESP_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_461_TDFI_PHYUPD_RESP_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_461_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_461_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_CTL_462_REGOFF 0x738
#define HWIO_DDR_CTL_462_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_462_REGOFF)
#define HWIO_DDR_CTL_462_TDFI_CTRLUPD_INTERVAL_F1_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_462_TDFI_CTRLUPD_INTERVAL_F1_FLDSHFT (0)

#define HWIO_DDR_CTL_463_REGOFF 0x73c
#define HWIO_DDR_CTL_463_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_463_REGOFF)
#define HWIO_DDR_CTL_463_RDLAT_ADJ_F1_FLDMASK (0x7f)
#define HWIO_DDR_CTL_463_RDLAT_ADJ_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_463_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_CTL_463_RESERVED_FLDSHFT (7)
#define HWIO_DDR_CTL_463_WRLAT_ADJ_F1_FLDMASK (0x7f00)
#define HWIO_DDR_CTL_463_WRLAT_ADJ_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_463_CDNS_INTRL1_FLDMASK (0x8000)
#define HWIO_DDR_CTL_463_CDNS_INTRL1_FLDSHFT (15)
#define HWIO_DDR_CTL_463_TDFI_CTRLUPD_MAX_F2_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_463_TDFI_CTRLUPD_MAX_F2_FLDSHFT (16)

#define HWIO_DDR_CTL_464_REGOFF 0x740
#define HWIO_DDR_CTL_464_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_464_REGOFF)
#define HWIO_DDR_CTL_464_OBSOLETE0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_464_OBSOLETE0_FLDSHFT (0)

#define HWIO_DDR_CTL_465_REGOFF 0x744
#define HWIO_DDR_CTL_465_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_465_REGOFF)
#define HWIO_DDR_CTL_465_OBSOLETE0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_465_OBSOLETE0_FLDSHFT (0)

#define HWIO_DDR_CTL_466_REGOFF 0x748
#define HWIO_DDR_CTL_466_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_466_REGOFF)
#define HWIO_DDR_CTL_466_TDFI_PHYUPD_RESP_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_466_TDFI_PHYUPD_RESP_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_466_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_466_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_CTL_467_REGOFF 0x74c
#define HWIO_DDR_CTL_467_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_467_REGOFF)
#define HWIO_DDR_CTL_467_TDFI_CTRLUPD_INTERVAL_F2_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_467_TDFI_CTRLUPD_INTERVAL_F2_FLDSHFT (0)

#define HWIO_DDR_CTL_468_REGOFF 0x750
#define HWIO_DDR_CTL_468_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_468_REGOFF)
#define HWIO_DDR_CTL_468_RDLAT_ADJ_F2_FLDMASK (0x7f)
#define HWIO_DDR_CTL_468_RDLAT_ADJ_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_468_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_CTL_468_RESERVED_FLDSHFT (7)
#define HWIO_DDR_CTL_468_WRLAT_ADJ_F2_FLDMASK (0x7f00)
#define HWIO_DDR_CTL_468_WRLAT_ADJ_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_468_CDNS_INTRL1_FLDMASK (0x8000)
#define HWIO_DDR_CTL_468_CDNS_INTRL1_FLDSHFT (15)
#define HWIO_DDR_CTL_468_TDFI_CTRLUPD_MAX_F3_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_468_TDFI_CTRLUPD_MAX_F3_FLDSHFT (16)

#define HWIO_DDR_CTL_469_REGOFF 0x754
#define HWIO_DDR_CTL_469_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_469_REGOFF)
#define HWIO_DDR_CTL_469_OBSOLETE0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_469_OBSOLETE0_FLDSHFT (0)

#define HWIO_DDR_CTL_470_REGOFF 0x758
#define HWIO_DDR_CTL_470_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_470_REGOFF)
#define HWIO_DDR_CTL_470_OBSOLETE0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_470_OBSOLETE0_FLDSHFT (0)

#define HWIO_DDR_CTL_471_REGOFF 0x75c
#define HWIO_DDR_CTL_471_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_471_REGOFF)
#define HWIO_DDR_CTL_471_TDFI_PHYUPD_RESP_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_471_TDFI_PHYUPD_RESP_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_471_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_471_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_CTL_472_REGOFF 0x760
#define HWIO_DDR_CTL_472_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_472_REGOFF)
#define HWIO_DDR_CTL_472_TDFI_CTRLUPD_INTERVAL_F3_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_472_TDFI_CTRLUPD_INTERVAL_F3_FLDSHFT (0)

#define HWIO_DDR_CTL_473_REGOFF 0x764
#define HWIO_DDR_CTL_473_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_473_REGOFF)
#define HWIO_DDR_CTL_473_RDLAT_ADJ_F3_FLDMASK (0x7f)
#define HWIO_DDR_CTL_473_RDLAT_ADJ_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_473_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_CTL_473_RESERVED_FLDSHFT (7)
#define HWIO_DDR_CTL_473_WRLAT_ADJ_F3_FLDMASK (0x7f00)
#define HWIO_DDR_CTL_473_WRLAT_ADJ_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_473_CDNS_INTRL1_FLDMASK (0x8000)
#define HWIO_DDR_CTL_473_CDNS_INTRL1_FLDSHFT (15)
#define HWIO_DDR_CTL_473_TDFI_CTRL_DELAY_F0_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_473_TDFI_CTRL_DELAY_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_473_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_473_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_473_TDFI_CTRL_DELAY_F1_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_473_TDFI_CTRL_DELAY_F1_FLDSHFT (24)
#define HWIO_DDR_CTL_473_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_473_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_474_REGOFF 0x768
#define HWIO_DDR_CTL_474_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_474_REGOFF)
#define HWIO_DDR_CTL_474_TDFI_CTRL_DELAY_F2_FLDMASK (0xf)
#define HWIO_DDR_CTL_474_TDFI_CTRL_DELAY_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_474_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_474_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_474_TDFI_CTRL_DELAY_F3_FLDMASK (0xf00)
#define HWIO_DDR_CTL_474_TDFI_CTRL_DELAY_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_474_CDNS_INTRL1_FLDMASK (0xf000)
#define HWIO_DDR_CTL_474_CDNS_INTRL1_FLDSHFT (12)
#define HWIO_DDR_CTL_474_TDFI_DRAM_CLK_DISABLE_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_474_TDFI_DRAM_CLK_DISABLE_FLDSHFT (16)
#define HWIO_DDR_CTL_474_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_474_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_474_TDFI_DRAM_CLK_ENABLE_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_474_TDFI_DRAM_CLK_ENABLE_FLDSHFT (24)
#define HWIO_DDR_CTL_474_CDNS_INTRL3_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_474_CDNS_INTRL3_FLDSHFT (28)

#define HWIO_DDR_CTL_475_REGOFF 0x76c
#define HWIO_DDR_CTL_475_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_475_REGOFF)
#define HWIO_DDR_CTL_475_TDFI_WRLVL_EN_FLDMASK (0xff)
#define HWIO_DDR_CTL_475_TDFI_WRLVL_EN_FLDSHFT (0)
#define HWIO_DDR_CTL_475_TDFI_WRLVL_WW_FLDMASK (0x3ff00)
#define HWIO_DDR_CTL_475_TDFI_WRLVL_WW_FLDSHFT (8)
#define HWIO_DDR_CTL_475_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_475_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_475_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_475_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_476_REGOFF 0x770
#define HWIO_DDR_CTL_476_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_476_REGOFF)
#define HWIO_DDR_CTL_476_TDFI_WRLVL_RESP_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_476_TDFI_WRLVL_RESP_FLDSHFT (0)

#define HWIO_DDR_CTL_477_REGOFF 0x774
#define HWIO_DDR_CTL_477_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_477_REGOFF)
#define HWIO_DDR_CTL_477_TDFI_WRLVL_MAX_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_477_TDFI_WRLVL_MAX_FLDSHFT (0)

#define HWIO_DDR_CTL_478_REGOFF 0x778
#define HWIO_DDR_CTL_478_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_478_REGOFF)
#define HWIO_DDR_CTL_478_TDFI_RDLVL_EN_FLDMASK (0xff)
#define HWIO_DDR_CTL_478_TDFI_RDLVL_EN_FLDSHFT (0)
#define HWIO_DDR_CTL_478_TDFI_RDLVL_RR_FLDMASK (0x3ff00)
#define HWIO_DDR_CTL_478_TDFI_RDLVL_RR_FLDSHFT (8)
#define HWIO_DDR_CTL_478_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_478_RESERVED_FLDSHFT (18)
#define HWIO_DDR_CTL_478_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_478_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_479_REGOFF 0x77c
#define HWIO_DDR_CTL_479_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_479_REGOFF)
#define HWIO_DDR_CTL_479_TDFI_RDLVL_RESP_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_479_TDFI_RDLVL_RESP_FLDSHFT (0)

#define HWIO_DDR_CTL_480_REGOFF 0x780
#define HWIO_DDR_CTL_480_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_480_REGOFF)
#define HWIO_DDR_CTL_480_RDLVL_RESP_MASK_FLDMASK (0xff)
#define HWIO_DDR_CTL_480_RDLVL_RESP_MASK_FLDSHFT (0)
#define HWIO_DDR_CTL_480_RDLVL_EN_FLDMASK (0x100)
#define HWIO_DDR_CTL_480_RDLVL_EN_FLDSHFT (8)
#define HWIO_DDR_CTL_480_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_480_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_480_RDLVL_GATE_EN_FLDMASK (0x10000)
#define HWIO_DDR_CTL_480_RDLVL_GATE_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_480_CDNS_INTRL1_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_480_CDNS_INTRL1_FLDSHFT (17)
#define HWIO_DDR_CTL_480_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_480_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_CTL_481_REGOFF 0x784
#define HWIO_DDR_CTL_481_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_481_REGOFF)
#define HWIO_DDR_CTL_481_TDFI_RDLVL_MAX_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_481_TDFI_RDLVL_MAX_FLDSHFT (0)

#define HWIO_DDR_CTL_482_REGOFF 0x788
#define HWIO_DDR_CTL_482_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_482_REGOFF)
#define HWIO_DDR_CTL_482_RDLVL_ERROR_STATUS_FLDMASK (0x3)
#define HWIO_DDR_CTL_482_RDLVL_ERROR_STATUS_FLDSHFT (0)
#define HWIO_DDR_CTL_482_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_CTL_482_RESERVED_FLDSHFT (2)
#define HWIO_DDR_CTL_482_RDLVL_GATE_ERROR_STATUS_FLDMASK (0x300)
#define HWIO_DDR_CTL_482_RDLVL_GATE_ERROR_STATUS_FLDSHFT (8)
#define HWIO_DDR_CTL_482_CDNS_INTRL1_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_482_CDNS_INTRL1_FLDSHFT (10)
#define HWIO_DDR_CTL_482_TDFI_CALVL_EN_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_482_TDFI_CALVL_EN_FLDSHFT (16)
#define HWIO_DDR_CTL_482_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_482_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_CTL_483_REGOFF 0x78c
#define HWIO_DDR_CTL_483_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_483_REGOFF)
#define HWIO_DDR_CTL_483_TDFI_CALVL_CC_F0_FLDMASK (0x3ff)
#define HWIO_DDR_CTL_483_TDFI_CALVL_CC_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_483_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_483_RESERVED_FLDSHFT (10)
#define HWIO_DDR_CTL_483_TDFI_CALVL_CAPTURE_F0_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_483_TDFI_CALVL_CAPTURE_F0_FLDSHFT (16)
#define HWIO_DDR_CTL_483_CDNS_INTRL1_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_483_CDNS_INTRL1_FLDSHFT (26)

#define HWIO_DDR_CTL_484_REGOFF 0x790
#define HWIO_DDR_CTL_484_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_484_REGOFF)
#define HWIO_DDR_CTL_484_TDFI_CALVL_CC_F1_FLDMASK (0x3ff)
#define HWIO_DDR_CTL_484_TDFI_CALVL_CC_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_484_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_484_RESERVED_FLDSHFT (10)
#define HWIO_DDR_CTL_484_TDFI_CALVL_CAPTURE_F1_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_484_TDFI_CALVL_CAPTURE_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_484_CDNS_INTRL1_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_484_CDNS_INTRL1_FLDSHFT (26)

#define HWIO_DDR_CTL_485_REGOFF 0x794
#define HWIO_DDR_CTL_485_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_485_REGOFF)
#define HWIO_DDR_CTL_485_TDFI_CALVL_CC_F2_FLDMASK (0x3ff)
#define HWIO_DDR_CTL_485_TDFI_CALVL_CC_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_485_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_485_RESERVED_FLDSHFT (10)
#define HWIO_DDR_CTL_485_TDFI_CALVL_CAPTURE_F2_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_485_TDFI_CALVL_CAPTURE_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_485_CDNS_INTRL1_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_485_CDNS_INTRL1_FLDSHFT (26)

#define HWIO_DDR_CTL_486_REGOFF 0x798
#define HWIO_DDR_CTL_486_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_486_REGOFF)
#define HWIO_DDR_CTL_486_TDFI_CALVL_CC_F3_FLDMASK (0x3ff)
#define HWIO_DDR_CTL_486_TDFI_CALVL_CC_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_486_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_486_RESERVED_FLDSHFT (10)
#define HWIO_DDR_CTL_486_TDFI_CALVL_CAPTURE_F3_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_486_TDFI_CALVL_CAPTURE_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_486_CDNS_INTRL1_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_486_CDNS_INTRL1_FLDSHFT (26)

#define HWIO_DDR_CTL_487_REGOFF 0x79c
#define HWIO_DDR_CTL_487_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_487_REGOFF)
#define HWIO_DDR_CTL_487_TDFI_CALVL_RESP_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_487_TDFI_CALVL_RESP_FLDSHFT (0)

#define HWIO_DDR_CTL_488_REGOFF 0x7a0
#define HWIO_DDR_CTL_488_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_488_REGOFF)
#define HWIO_DDR_CTL_488_TDFI_CALVL_MAX_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_488_TDFI_CALVL_MAX_FLDSHFT (0)

#define HWIO_DDR_CTL_489_REGOFF 0x7a4
#define HWIO_DDR_CTL_489_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_489_REGOFF)
#define HWIO_DDR_CTL_489_CALVL_RESP_MASK_FLDMASK (0x1)
#define HWIO_DDR_CTL_489_CALVL_RESP_MASK_FLDSHFT (0)
#define HWIO_DDR_CTL_489_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_489_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_489_CALVL_EN_FLDMASK (0x100)
#define HWIO_DDR_CTL_489_CALVL_EN_FLDSHFT (8)
#define HWIO_DDR_CTL_489_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_489_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_489_CALVL_ERROR_STATUS_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_489_CALVL_ERROR_STATUS_FLDSHFT (16)
#define HWIO_DDR_CTL_489_CDNS_INTRL2_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_489_CDNS_INTRL2_FLDSHFT (20)
#define HWIO_DDR_CTL_489_TDFI_PHY_WRDATA_F0_FLDMASK (0x7000000)
#define HWIO_DDR_CTL_489_TDFI_PHY_WRDATA_F0_FLDSHFT (24)
#define HWIO_DDR_CTL_489_CDNS_INTRL3_FLDMASK (0xf8000000)
#define HWIO_DDR_CTL_489_CDNS_INTRL3_FLDSHFT (27)

#define HWIO_DDR_CTL_490_REGOFF 0x7a8
#define HWIO_DDR_CTL_490_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_490_REGOFF)
#define HWIO_DDR_CTL_490_TDFI_PHY_WRDATA_F1_FLDMASK (0x7)
#define HWIO_DDR_CTL_490_TDFI_PHY_WRDATA_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_490_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_CTL_490_RESERVED_FLDSHFT (3)
#define HWIO_DDR_CTL_490_TDFI_PHY_WRDATA_F2_FLDMASK (0x700)
#define HWIO_DDR_CTL_490_TDFI_PHY_WRDATA_F2_FLDSHFT (8)
#define HWIO_DDR_CTL_490_CDNS_INTRL1_FLDMASK (0xf800)
#define HWIO_DDR_CTL_490_CDNS_INTRL1_FLDSHFT (11)
#define HWIO_DDR_CTL_490_TDFI_PHY_WRDATA_F3_FLDMASK (0x70000)
#define HWIO_DDR_CTL_490_TDFI_PHY_WRDATA_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_490_CDNS_INTRL2_FLDMASK (0xf80000)
#define HWIO_DDR_CTL_490_CDNS_INTRL2_FLDSHFT (19)
#define HWIO_DDR_CTL_490_TDFI_RDCSLAT_F0_FLDMASK (0x7f000000)
#define HWIO_DDR_CTL_490_TDFI_RDCSLAT_F0_FLDSHFT (24)
#define HWIO_DDR_CTL_490_CDNS_INTRL3_FLDMASK (0x80000000)
#define HWIO_DDR_CTL_490_CDNS_INTRL3_FLDSHFT (31)

#define HWIO_DDR_CTL_491_REGOFF 0x7ac
#define HWIO_DDR_CTL_491_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_491_REGOFF)
#define HWIO_DDR_CTL_491_TDFI_WRCSLAT_F0_FLDMASK (0x7f)
#define HWIO_DDR_CTL_491_TDFI_WRCSLAT_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_491_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_CTL_491_RESERVED_FLDSHFT (7)
#define HWIO_DDR_CTL_491_TDFI_RDCSLAT_F1_FLDMASK (0x7f00)
#define HWIO_DDR_CTL_491_TDFI_RDCSLAT_F1_FLDSHFT (8)
#define HWIO_DDR_CTL_491_CDNS_INTRL1_FLDMASK (0x8000)
#define HWIO_DDR_CTL_491_CDNS_INTRL1_FLDSHFT (15)
#define HWIO_DDR_CTL_491_TDFI_WRCSLAT_F1_FLDMASK (0x7f0000)
#define HWIO_DDR_CTL_491_TDFI_WRCSLAT_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_491_CDNS_INTRL2_FLDMASK (0x800000)
#define HWIO_DDR_CTL_491_CDNS_INTRL2_FLDSHFT (23)
#define HWIO_DDR_CTL_491_TDFI_RDCSLAT_F2_FLDMASK (0x7f000000)
#define HWIO_DDR_CTL_491_TDFI_RDCSLAT_F2_FLDSHFT (24)
#define HWIO_DDR_CTL_491_CDNS_INTRL3_FLDMASK (0x80000000)
#define HWIO_DDR_CTL_491_CDNS_INTRL3_FLDSHFT (31)

#define HWIO_DDR_CTL_492_REGOFF 0x7b0
#define HWIO_DDR_CTL_492_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_492_REGOFF)
#define HWIO_DDR_CTL_492_TDFI_WRCSLAT_F2_FLDMASK (0x7f)
#define HWIO_DDR_CTL_492_TDFI_WRCSLAT_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_492_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_CTL_492_RESERVED_FLDSHFT (7)
#define HWIO_DDR_CTL_492_TDFI_RDCSLAT_F3_FLDMASK (0x7f00)
#define HWIO_DDR_CTL_492_TDFI_RDCSLAT_F3_FLDSHFT (8)
#define HWIO_DDR_CTL_492_CDNS_INTRL1_FLDMASK (0x8000)
#define HWIO_DDR_CTL_492_CDNS_INTRL1_FLDSHFT (15)
#define HWIO_DDR_CTL_492_TDFI_WRCSLAT_F3_FLDMASK (0x7f0000)
#define HWIO_DDR_CTL_492_TDFI_WRCSLAT_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_492_CDNS_INTRL2_FLDMASK (0x800000)
#define HWIO_DDR_CTL_492_CDNS_INTRL2_FLDSHFT (23)
#define HWIO_DDR_CTL_492_TDFI_WRDATA_DELAY_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_492_TDFI_WRDATA_DELAY_FLDSHFT (24)

#define HWIO_DDR_CTL_493_REGOFF 0x7b4
#define HWIO_DDR_CTL_493_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_493_REGOFF)
#define HWIO_DDR_CTL_493_EN_1T_TIMING_FLDMASK (0x1)
#define HWIO_DDR_CTL_493_EN_1T_TIMING_FLDSHFT (0)
#define HWIO_DDR_CTL_493_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_493_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_493_DISABLE_MEMORY_MASKED_WRITE_FLDMASK (0x100)
#define HWIO_DDR_CTL_493_DISABLE_MEMORY_MASKED_WRITE_FLDSHFT (8)
#define HWIO_DDR_CTL_493_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_493_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_493_BL_ON_FLY_ENABLE_FLDMASK (0x10000)
#define HWIO_DDR_CTL_493_BL_ON_FLY_ENABLE_FLDSHFT (16)
#define HWIO_DDR_CTL_493_CDNS_INTRL2_FLDMASK (0xfe0000)
#define HWIO_DDR_CTL_493_CDNS_INTRL2_FLDSHFT (17)
#define HWIO_DDR_CTL_493_CDNS_INTRL3_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_493_CDNS_INTRL3_FLDSHFT (24)
#define HWIO_DDR_CTL_493_RESERVED4_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_493_RESERVED4_FLDSHFT (25)

#define HWIO_DDR_CTL_494_REGOFF 0x7b8
#define HWIO_DDR_CTL_494_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_494_REGOFF)
#define HWIO_DDR_CTL_494_CDNS_INTRL0_FLDMASK (0x7)
#define HWIO_DDR_CTL_494_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_494_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_CTL_494_RESERVED_FLDSHFT (3)
#define HWIO_DDR_CTL_494_CDNS_INTRL1_FLDMASK (0x700)
#define HWIO_DDR_CTL_494_CDNS_INTRL1_FLDSHFT (8)
#define HWIO_DDR_CTL_494_RESERVED4_FLDMASK (0xf800)
#define HWIO_DDR_CTL_494_RESERVED4_FLDSHFT (11)
#define HWIO_DDR_CTL_494_CDNS_INTRL2_FLDMASK (0x70000)
#define HWIO_DDR_CTL_494_CDNS_INTRL2_FLDSHFT (16)
#define HWIO_DDR_CTL_494_RESERVED5_FLDMASK (0xf80000)
#define HWIO_DDR_CTL_494_RESERVED5_FLDSHFT (19)
#define HWIO_DDR_CTL_494_CDNS_INTRL3_FLDMASK (0x7000000)
#define HWIO_DDR_CTL_494_CDNS_INTRL3_FLDSHFT (24)
#define HWIO_DDR_CTL_494_RESERVED6_FLDMASK (0xf8000000)
#define HWIO_DDR_CTL_494_RESERVED6_FLDSHFT (27)

#define HWIO_DDR_CTL_495_REGOFF 0x7bc
#define HWIO_DDR_CTL_495_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_495_REGOFF)
#define HWIO_DDR_CTL_495_CDNS_INTRL0_FLDMASK (0x7)
#define HWIO_DDR_CTL_495_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_495_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_CTL_495_RESERVED_FLDSHFT (3)
#define HWIO_DDR_CTL_495_CDNS_INTRL1_FLDMASK (0x700)
#define HWIO_DDR_CTL_495_CDNS_INTRL1_FLDSHFT (8)
#define HWIO_DDR_CTL_495_RESERVED4_FLDMASK (0xf800)
#define HWIO_DDR_CTL_495_RESERVED4_FLDSHFT (11)
#define HWIO_DDR_CTL_495_CDNS_INTRL2_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_495_CDNS_INTRL2_FLDSHFT (16)
#define HWIO_DDR_CTL_495_RESERVED5_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_495_RESERVED5_FLDSHFT (20)
#define HWIO_DDR_CTL_495_CDNS_INTRL3_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_495_CDNS_INTRL3_FLDSHFT (24)
#define HWIO_DDR_CTL_495_RESERVED6_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_495_RESERVED6_FLDSHFT (28)

#define HWIO_DDR_CTL_496_REGOFF 0x7c0
#define HWIO_DDR_CTL_496_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_496_REGOFF)
#define HWIO_DDR_CTL_496_CDNS_INTRL0_FLDMASK (0xf)
#define HWIO_DDR_CTL_496_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_496_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_496_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_496_CDNS_INTRL1_FLDMASK (0xf00)
#define HWIO_DDR_CTL_496_CDNS_INTRL1_FLDSHFT (8)
#define HWIO_DDR_CTL_496_RESERVED4_FLDMASK (0xf000)
#define HWIO_DDR_CTL_496_RESERVED4_FLDSHFT (12)
#define HWIO_DDR_CTL_496_CDNS_INTRL2_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_496_CDNS_INTRL2_FLDSHFT (16)
#define HWIO_DDR_CTL_496_RESERVED5_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_496_RESERVED5_FLDSHFT (20)
#define HWIO_DDR_CTL_496_CDNS_INTRL3_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_496_CDNS_INTRL3_FLDSHFT (24)
#define HWIO_DDR_CTL_496_RESERVED6_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_496_RESERVED6_FLDSHFT (28)

#define HWIO_DDR_CTL_497_REGOFF 0x7c4
#define HWIO_DDR_CTL_497_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_497_REGOFF)
#define HWIO_DDR_CTL_497_CDNS_INTRL0_FLDMASK (0xf)
#define HWIO_DDR_CTL_497_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_497_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_497_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_497_CDNS_INTRL1_FLDMASK (0xf00)
#define HWIO_DDR_CTL_497_CDNS_INTRL1_FLDSHFT (8)
#define HWIO_DDR_CTL_497_RESERVED4_FLDMASK (0xf000)
#define HWIO_DDR_CTL_497_RESERVED4_FLDSHFT (12)
#define HWIO_DDR_CTL_497_CDNS_INTRL2_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_497_CDNS_INTRL2_FLDSHFT (16)
#define HWIO_DDR_CTL_497_RESERVED5_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_497_RESERVED5_FLDSHFT (20)
#define HWIO_DDR_CTL_497_CDNS_INTRL3_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_497_CDNS_INTRL3_FLDSHFT (24)
#define HWIO_DDR_CTL_497_RESERVED6_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_497_RESERVED6_FLDSHFT (28)

#define HWIO_DDR_CTL_498_REGOFF 0x7c8
#define HWIO_DDR_CTL_498_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_498_REGOFF)
#define HWIO_DDR_CTL_498_CDNS_INTRL0_FLDMASK (0xf)
#define HWIO_DDR_CTL_498_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_498_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_498_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_498_CDNS_INTRL1_FLDMASK (0xf00)
#define HWIO_DDR_CTL_498_CDNS_INTRL1_FLDSHFT (8)
#define HWIO_DDR_CTL_498_RESERVED4_FLDMASK (0xf000)
#define HWIO_DDR_CTL_498_RESERVED4_FLDSHFT (12)
#define HWIO_DDR_CTL_498_CDNS_INTRL2_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_498_CDNS_INTRL2_FLDSHFT (16)
#define HWIO_DDR_CTL_498_RESERVED5_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_498_RESERVED5_FLDSHFT (20)
#define HWIO_DDR_CTL_498_CDNS_INTRL3_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_498_CDNS_INTRL3_FLDSHFT (24)
#define HWIO_DDR_CTL_498_RESERVED6_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_498_RESERVED6_FLDSHFT (28)

#define HWIO_DDR_CTL_499_REGOFF 0x7cc
#define HWIO_DDR_CTL_499_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_499_REGOFF)
#define HWIO_DDR_CTL_499_CDNS_INTRL0_FLDMASK (0xf)
#define HWIO_DDR_CTL_499_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_499_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_499_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_499_CDNS_INTRL1_FLDMASK (0xf00)
#define HWIO_DDR_CTL_499_CDNS_INTRL1_FLDSHFT (8)
#define HWIO_DDR_CTL_499_RESERVED4_FLDMASK (0xf000)
#define HWIO_DDR_CTL_499_RESERVED4_FLDSHFT (12)
#define HWIO_DDR_CTL_499_CDNS_INTRL2_FLDMASK (0xf0000)
#define HWIO_DDR_CTL_499_CDNS_INTRL2_FLDSHFT (16)
#define HWIO_DDR_CTL_499_RESERVED5_FLDMASK (0xf00000)
#define HWIO_DDR_CTL_499_RESERVED5_FLDSHFT (20)
#define HWIO_DDR_CTL_499_CDNS_INTRL3_FLDMASK (0xf000000)
#define HWIO_DDR_CTL_499_CDNS_INTRL3_FLDSHFT (24)
#define HWIO_DDR_CTL_499_RESERVED6_FLDMASK (0xf0000000)
#define HWIO_DDR_CTL_499_RESERVED6_FLDSHFT (28)

#define HWIO_DDR_CTL_500_REGOFF 0x7d0
#define HWIO_DDR_CTL_500_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_500_REGOFF)
#define HWIO_DDR_CTL_500_CDNS_INTRL0_FLDMASK (0xf)
#define HWIO_DDR_CTL_500_CDNS_INTRL0_FLDSHFT (0)
#define HWIO_DDR_CTL_500_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_500_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_500_CDNS_INTRL1_FLDMASK (0xf00)
#define HWIO_DDR_CTL_500_CDNS_INTRL1_FLDSHFT (8)
#define HWIO_DDR_CTL_500_CDNS_INTRL2_FLDMASK (0xf000)
#define HWIO_DDR_CTL_500_CDNS_INTRL2_FLDSHFT (12)
#define HWIO_DDR_CTL_500_SRAM_READ_LATENCY_FLDMASK (0x30000)
#define HWIO_DDR_CTL_500_SRAM_READ_LATENCY_FLDSHFT (16)
#define HWIO_DDR_CTL_500_CDNS_INTRL3_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_500_CDNS_INTRL3_FLDSHFT (18)
#define HWIO_DDR_CTL_500_AXI0_WR_ARRAY_LOG2_DEPTH_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_500_AXI0_WR_ARRAY_LOG2_DEPTH_FLDSHFT (24)

#define HWIO_DDR_CTL_501_REGOFF 0x7d4
#define HWIO_DDR_CTL_501_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_501_REGOFF)
#define HWIO_DDR_CTL_501_AXI0_TRANS_WRFIFO_LOG2_DEPTH_FLDMASK (0xff)
#define HWIO_DDR_CTL_501_AXI0_TRANS_WRFIFO_LOG2_DEPTH_FLDSHFT (0)
#define HWIO_DDR_CTL_501_AXI1_WR_ARRAY_LOG2_DEPTH_FLDMASK (0xff00)
#define HWIO_DDR_CTL_501_AXI1_WR_ARRAY_LOG2_DEPTH_FLDSHFT (8)
#define HWIO_DDR_CTL_501_AXI1_TRANS_WRFIFO_LOG2_DEPTH_FLDMASK (0xff0000)
#define HWIO_DDR_CTL_501_AXI1_TRANS_WRFIFO_LOG2_DEPTH_FLDSHFT (16)
#define HWIO_DDR_CTL_501_PBR_EN_FLDMASK (0x1000000)
#define HWIO_DDR_CTL_501_PBR_EN_FLDSHFT (24)
#define HWIO_DDR_CTL_501_RESERVED_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_501_RESERVED_FLDSHFT (25)

#define HWIO_DDR_CTL_502_REGOFF 0x7d8
#define HWIO_DDR_CTL_502_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_502_REGOFF)
#define HWIO_DDR_CTL_502_PBR_NUMERIC_ORDER_FLDMASK (0x1)
#define HWIO_DDR_CTL_502_PBR_NUMERIC_ORDER_FLDSHFT (0)
#define HWIO_DDR_CTL_502_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_502_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_502_TRFC_PB_F0_FLDMASK (0x3ff00)
#define HWIO_DDR_CTL_502_TRFC_PB_F0_FLDSHFT (8)
#define HWIO_DDR_CTL_502_CDNS_INTRL1_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_502_CDNS_INTRL1_FLDSHFT (18)
#define HWIO_DDR_CTL_502_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_502_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_503_REGOFF 0x7dc
#define HWIO_DDR_CTL_503_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_503_REGOFF)
#define HWIO_DDR_CTL_503_TREFI_PB_F0_FLDMASK (0xffff)
#define HWIO_DDR_CTL_503_TREFI_PB_F0_FLDSHFT (0)
#define HWIO_DDR_CTL_503_TRFC_PB_F1_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_503_TRFC_PB_F1_FLDSHFT (16)
#define HWIO_DDR_CTL_503_RESERVED_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_503_RESERVED_FLDSHFT (26)

#define HWIO_DDR_CTL_504_REGOFF 0x7e0
#define HWIO_DDR_CTL_504_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_504_REGOFF)
#define HWIO_DDR_CTL_504_TREFI_PB_F1_FLDMASK (0xffff)
#define HWIO_DDR_CTL_504_TREFI_PB_F1_FLDSHFT (0)
#define HWIO_DDR_CTL_504_TRFC_PB_F2_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_504_TRFC_PB_F2_FLDSHFT (16)
#define HWIO_DDR_CTL_504_RESERVED_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_504_RESERVED_FLDSHFT (26)

#define HWIO_DDR_CTL_505_REGOFF 0x7e4
#define HWIO_DDR_CTL_505_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_505_REGOFF)
#define HWIO_DDR_CTL_505_TREFI_PB_F2_FLDMASK (0xffff)
#define HWIO_DDR_CTL_505_TREFI_PB_F2_FLDSHFT (0)
#define HWIO_DDR_CTL_505_TRFC_PB_F3_FLDMASK (0x3ff0000)
#define HWIO_DDR_CTL_505_TRFC_PB_F3_FLDSHFT (16)
#define HWIO_DDR_CTL_505_RESERVED_FLDMASK (0xfc000000)
#define HWIO_DDR_CTL_505_RESERVED_FLDSHFT (26)

#define HWIO_DDR_CTL_506_REGOFF 0x7e8
#define HWIO_DDR_CTL_506_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_506_REGOFF)
#define HWIO_DDR_CTL_506_TREFI_PB_F3_FLDMASK (0xffff)
#define HWIO_DDR_CTL_506_TREFI_PB_F3_FLDSHFT (0)
#define HWIO_DDR_CTL_506_PBR_MAX_BANK_WAIT_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_506_PBR_MAX_BANK_WAIT_FLDSHFT (16)

#define HWIO_DDR_CTL_507_REGOFF 0x7ec
#define HWIO_DDR_CTL_507_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_507_REGOFF)
#define HWIO_DDR_CTL_507_PBR_BANK_SELECT_DELAY_FLDMASK (0xf)
#define HWIO_DDR_CTL_507_PBR_BANK_SELECT_DELAY_FLDSHFT (0)
#define HWIO_DDR_CTL_507_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_CTL_507_RESERVED_FLDSHFT (4)
#define HWIO_DDR_CTL_507_PBR_CONT_REQ_EN_FLDMASK (0x100)
#define HWIO_DDR_CTL_507_PBR_CONT_REQ_EN_FLDSHFT (8)
#define HWIO_DDR_CTL_507_CDNS_INTRL1_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_507_CDNS_INTRL1_FLDSHFT (9)
#define HWIO_DDR_CTL_507_AREF_PBR_CONT_EN_THRESHOLD_FLDMASK (0x1f0000)
#define HWIO_DDR_CTL_507_AREF_PBR_CONT_EN_THRESHOLD_FLDSHFT (16)
#define HWIO_DDR_CTL_507_CDNS_INTRL2_FLDMASK (0xe00000)
#define HWIO_DDR_CTL_507_CDNS_INTRL2_FLDSHFT (21)
#define HWIO_DDR_CTL_507_AREF_PBR_CONT_DIS_THRESHOLD_FLDMASK (0x1f000000)
#define HWIO_DDR_CTL_507_AREF_PBR_CONT_DIS_THRESHOLD_FLDSHFT (24)
#define HWIO_DDR_CTL_507_CDNS_INTRL3_FLDMASK (0xe0000000)
#define HWIO_DDR_CTL_507_CDNS_INTRL3_FLDSHFT (29)

#define HWIO_DDR_CTL_508_REGOFF 0x7f0
#define HWIO_DDR_CTL_508_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_508_REGOFF)
#define HWIO_DDR_CTL_508_WR_ORDER_REQ_FLDMASK (0x3)
#define HWIO_DDR_CTL_508_WR_ORDER_REQ_FLDSHFT (0)
#define HWIO_DDR_CTL_508_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_CTL_508_RESERVED_FLDSHFT (2)
#define HWIO_DDR_CTL_508_OBSOLETE1_FLDMASK (0xffffff00)
#define HWIO_DDR_CTL_508_OBSOLETE1_FLDSHFT (8)

#define HWIO_DDR_CTL_509_REGOFF 0x7f4
#define HWIO_DDR_CTL_509_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_509_REGOFF)
#define HWIO_DDR_CTL_509_TDFI_PHYUPD_TYPE0_F0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_509_TDFI_PHYUPD_TYPE0_F0_FLDSHFT (0)

#define HWIO_DDR_CTL_510_REGOFF 0x7f8
#define HWIO_DDR_CTL_510_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_510_REGOFF)
#define HWIO_DDR_CTL_510_TDFI_PHYUPD_TYPE1_F0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_510_TDFI_PHYUPD_TYPE1_F0_FLDSHFT (0)

#define HWIO_DDR_CTL_511_REGOFF 0x7fc
#define HWIO_DDR_CTL_511_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_511_REGOFF)
#define HWIO_DDR_CTL_511_TDFI_PHYUPD_TYPE2_F0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_511_TDFI_PHYUPD_TYPE2_F0_FLDSHFT (0)

#define HWIO_DDR_CTL_512_REGOFF 0x800
#define HWIO_DDR_CTL_512_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_512_REGOFF)
#define HWIO_DDR_CTL_512_TDFI_PHYUPD_TYPE3_F0_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_512_TDFI_PHYUPD_TYPE3_F0_FLDSHFT (0)

#define HWIO_DDR_CTL_513_REGOFF 0x804
#define HWIO_DDR_CTL_513_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_513_REGOFF)
#define HWIO_DDR_CTL_513_TDFI_PHYUPD_TYPE0_F1_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_513_TDFI_PHYUPD_TYPE0_F1_FLDSHFT (0)

#define HWIO_DDR_CTL_514_REGOFF 0x808
#define HWIO_DDR_CTL_514_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_514_REGOFF)
#define HWIO_DDR_CTL_514_TDFI_PHYUPD_TYPE1_F1_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_514_TDFI_PHYUPD_TYPE1_F1_FLDSHFT (0)

#define HWIO_DDR_CTL_515_REGOFF 0x80c
#define HWIO_DDR_CTL_515_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_515_REGOFF)
#define HWIO_DDR_CTL_515_TDFI_PHYUPD_TYPE2_F1_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_515_TDFI_PHYUPD_TYPE2_F1_FLDSHFT (0)

#define HWIO_DDR_CTL_516_REGOFF 0x810
#define HWIO_DDR_CTL_516_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_516_REGOFF)
#define HWIO_DDR_CTL_516_TDFI_PHYUPD_TYPE3_F1_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_516_TDFI_PHYUPD_TYPE3_F1_FLDSHFT (0)

#define HWIO_DDR_CTL_517_REGOFF 0x814
#define HWIO_DDR_CTL_517_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_517_REGOFF)
#define HWIO_DDR_CTL_517_TDFI_PHYUPD_TYPE0_F2_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_517_TDFI_PHYUPD_TYPE0_F2_FLDSHFT (0)

#define HWIO_DDR_CTL_518_REGOFF 0x818
#define HWIO_DDR_CTL_518_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_518_REGOFF)
#define HWIO_DDR_CTL_518_TDFI_PHYUPD_TYPE1_F2_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_518_TDFI_PHYUPD_TYPE1_F2_FLDSHFT (0)

#define HWIO_DDR_CTL_519_REGOFF 0x81c
#define HWIO_DDR_CTL_519_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_519_REGOFF)
#define HWIO_DDR_CTL_519_TDFI_PHYUPD_TYPE2_F2_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_519_TDFI_PHYUPD_TYPE2_F2_FLDSHFT (0)

#define HWIO_DDR_CTL_520_REGOFF 0x820
#define HWIO_DDR_CTL_520_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_520_REGOFF)
#define HWIO_DDR_CTL_520_TDFI_PHYUPD_TYPE3_F2_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_520_TDFI_PHYUPD_TYPE3_F2_FLDSHFT (0)

#define HWIO_DDR_CTL_521_REGOFF 0x824
#define HWIO_DDR_CTL_521_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_521_REGOFF)
#define HWIO_DDR_CTL_521_TDFI_PHYUPD_TYPE0_F3_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_521_TDFI_PHYUPD_TYPE0_F3_FLDSHFT (0)

#define HWIO_DDR_CTL_522_REGOFF 0x828
#define HWIO_DDR_CTL_522_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_522_REGOFF)
#define HWIO_DDR_CTL_522_TDFI_PHYUPD_TYPE1_F3_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_522_TDFI_PHYUPD_TYPE1_F3_FLDSHFT (0)

#define HWIO_DDR_CTL_523_REGOFF 0x82c
#define HWIO_DDR_CTL_523_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_523_REGOFF)
#define HWIO_DDR_CTL_523_TDFI_PHYUPD_TYPE2_F3_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_523_TDFI_PHYUPD_TYPE2_F3_FLDSHFT (0)

#define HWIO_DDR_CTL_524_REGOFF 0x830
#define HWIO_DDR_CTL_524_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_524_REGOFF)
#define HWIO_DDR_CTL_524_TDFI_PHYUPD_TYPE3_F3_FLDMASK (0xffffffff)
#define HWIO_DDR_CTL_524_TDFI_PHYUPD_TYPE3_F3_FLDSHFT (0)

#define HWIO_DDR_CTL_525_REGOFF 0x834
#define HWIO_DDR_CTL_525_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_525_REGOFF)
#define HWIO_DDR_CTL_525_CTRLUPD_AREF_HP_ENABLE_FLDMASK (0x1)
#define HWIO_DDR_CTL_525_CTRLUPD_AREF_HP_ENABLE_FLDSHFT (0)
#define HWIO_DDR_CTL_525_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_CTL_525_RESERVED_FLDSHFT (1)
#define HWIO_DDR_CTL_525_OUT_OF_RANGE_SOURCE_ID_FLDMASK (0x3ff00)
#define HWIO_DDR_CTL_525_OUT_OF_RANGE_SOURCE_ID_FLDSHFT (8)
#define HWIO_DDR_CTL_525_CDNS_INTRL1_FLDMASK (0xfc0000)
#define HWIO_DDR_CTL_525_CDNS_INTRL1_FLDSHFT (18)
#define HWIO_DDR_CTL_525_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_CTL_525_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_CTL_526_REGOFF 0x838
#define HWIO_DDR_CTL_526_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_526_REGOFF)
#define HWIO_DDR_CTL_526_PORT_CMD_ERROR_ID_FLDMASK (0x3ff)
#define HWIO_DDR_CTL_526_PORT_CMD_ERROR_ID_FLDSHFT (0)
#define HWIO_DDR_CTL_526_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_CTL_526_RESERVED_FLDSHFT (10)
#define HWIO_DDR_CTL_526_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_0_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_526_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_0_FLDSHFT (16)
#define HWIO_DDR_CTL_526_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_526_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_527_REGOFF 0x83c
#define HWIO_DDR_CTL_527_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_527_REGOFF)
#define HWIO_DDR_CTL_527_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_0_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_527_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_0_FLDSHFT (0)
#define HWIO_DDR_CTL_527_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_527_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_527_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_1_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_527_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_1_FLDSHFT (16)
#define HWIO_DDR_CTL_527_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_527_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_528_REGOFF 0x840
#define HWIO_DDR_CTL_528_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_528_REGOFF)
#define HWIO_DDR_CTL_528_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_1_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_528_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_1_FLDSHFT (0)
#define HWIO_DDR_CTL_528_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_528_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_528_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_2_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_528_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_2_FLDSHFT (16)
#define HWIO_DDR_CTL_528_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_528_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_529_REGOFF 0x844
#define HWIO_DDR_CTL_529_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_529_REGOFF)
#define HWIO_DDR_CTL_529_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_2_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_529_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_2_FLDSHFT (0)
#define HWIO_DDR_CTL_529_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_529_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_529_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_3_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_529_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_3_FLDSHFT (16)
#define HWIO_DDR_CTL_529_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_529_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_530_REGOFF 0x848
#define HWIO_DDR_CTL_530_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_530_REGOFF)
#define HWIO_DDR_CTL_530_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_3_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_530_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_3_FLDSHFT (0)
#define HWIO_DDR_CTL_530_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_530_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_530_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_4_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_530_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_4_FLDSHFT (16)
#define HWIO_DDR_CTL_530_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_530_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_531_REGOFF 0x84c
#define HWIO_DDR_CTL_531_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_531_REGOFF)
#define HWIO_DDR_CTL_531_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_4_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_531_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_4_FLDSHFT (0)
#define HWIO_DDR_CTL_531_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_531_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_531_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_5_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_531_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_5_FLDSHFT (16)
#define HWIO_DDR_CTL_531_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_531_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_532_REGOFF 0x850
#define HWIO_DDR_CTL_532_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_532_REGOFF)
#define HWIO_DDR_CTL_532_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_5_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_532_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_5_FLDSHFT (0)
#define HWIO_DDR_CTL_532_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_532_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_532_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_6_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_532_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_6_FLDSHFT (16)
#define HWIO_DDR_CTL_532_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_532_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_533_REGOFF 0x854
#define HWIO_DDR_CTL_533_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_533_REGOFF)
#define HWIO_DDR_CTL_533_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_6_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_533_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_6_FLDSHFT (0)
#define HWIO_DDR_CTL_533_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_533_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_533_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_7_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_533_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_7_FLDSHFT (16)
#define HWIO_DDR_CTL_533_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_533_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_534_REGOFF 0x858
#define HWIO_DDR_CTL_534_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_534_REGOFF)
#define HWIO_DDR_CTL_534_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_7_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_534_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_7_FLDSHFT (0)
#define HWIO_DDR_CTL_534_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_534_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_534_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_8_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_534_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_8_FLDSHFT (16)
#define HWIO_DDR_CTL_534_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_534_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_535_REGOFF 0x85c
#define HWIO_DDR_CTL_535_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_535_REGOFF)
#define HWIO_DDR_CTL_535_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_8_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_535_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_8_FLDSHFT (0)
#define HWIO_DDR_CTL_535_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_535_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_535_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_9_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_535_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_9_FLDSHFT (16)
#define HWIO_DDR_CTL_535_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_535_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_536_REGOFF 0x860
#define HWIO_DDR_CTL_536_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_536_REGOFF)
#define HWIO_DDR_CTL_536_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_9_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_536_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_9_FLDSHFT (0)
#define HWIO_DDR_CTL_536_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_536_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_536_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_10_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_536_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_10_FLDSHFT (16)
#define HWIO_DDR_CTL_536_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_536_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_537_REGOFF 0x864
#define HWIO_DDR_CTL_537_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_537_REGOFF)
#define HWIO_DDR_CTL_537_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_10_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_537_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_10_FLDSHFT (0)
#define HWIO_DDR_CTL_537_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_537_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_537_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_11_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_537_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_11_FLDSHFT (16)
#define HWIO_DDR_CTL_537_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_537_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_538_REGOFF 0x868
#define HWIO_DDR_CTL_538_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_538_REGOFF)
#define HWIO_DDR_CTL_538_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_11_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_538_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_11_FLDSHFT (0)
#define HWIO_DDR_CTL_538_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_538_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_538_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_12_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_538_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_12_FLDSHFT (16)
#define HWIO_DDR_CTL_538_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_538_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_539_REGOFF 0x86c
#define HWIO_DDR_CTL_539_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_539_REGOFF)
#define HWIO_DDR_CTL_539_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_12_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_539_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_12_FLDSHFT (0)
#define HWIO_DDR_CTL_539_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_539_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_539_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_13_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_539_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_13_FLDSHFT (16)
#define HWIO_DDR_CTL_539_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_539_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_540_REGOFF 0x870
#define HWIO_DDR_CTL_540_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_540_REGOFF)
#define HWIO_DDR_CTL_540_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_13_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_540_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_13_FLDSHFT (0)
#define HWIO_DDR_CTL_540_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_540_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_540_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_14_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_540_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_14_FLDSHFT (16)
#define HWIO_DDR_CTL_540_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_540_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_541_REGOFF 0x874
#define HWIO_DDR_CTL_541_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_541_REGOFF)
#define HWIO_DDR_CTL_541_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_14_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_541_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_14_FLDSHFT (0)
#define HWIO_DDR_CTL_541_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_541_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_541_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_15_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_541_AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_15_FLDSHFT (16)
#define HWIO_DDR_CTL_541_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_541_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_542_REGOFF 0x878
#define HWIO_DDR_CTL_542_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_542_REGOFF)
#define HWIO_DDR_CTL_542_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_15_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_542_AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_15_FLDSHFT (0)
#define HWIO_DDR_CTL_542_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_542_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_542_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_0_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_542_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_0_FLDSHFT (16)
#define HWIO_DDR_CTL_542_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_542_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_543_REGOFF 0x87c
#define HWIO_DDR_CTL_543_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_543_REGOFF)
#define HWIO_DDR_CTL_543_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_0_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_543_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_0_FLDSHFT (0)
#define HWIO_DDR_CTL_543_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_543_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_543_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_1_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_543_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_1_FLDSHFT (16)
#define HWIO_DDR_CTL_543_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_543_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_544_REGOFF 0x880
#define HWIO_DDR_CTL_544_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_544_REGOFF)
#define HWIO_DDR_CTL_544_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_1_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_544_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_1_FLDSHFT (0)
#define HWIO_DDR_CTL_544_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_544_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_544_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_2_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_544_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_2_FLDSHFT (16)
#define HWIO_DDR_CTL_544_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_544_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_545_REGOFF 0x884
#define HWIO_DDR_CTL_545_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_545_REGOFF)
#define HWIO_DDR_CTL_545_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_2_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_545_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_2_FLDSHFT (0)
#define HWIO_DDR_CTL_545_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_545_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_545_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_3_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_545_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_3_FLDSHFT (16)
#define HWIO_DDR_CTL_545_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_545_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_546_REGOFF 0x888
#define HWIO_DDR_CTL_546_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_546_REGOFF)
#define HWIO_DDR_CTL_546_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_3_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_546_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_3_FLDSHFT (0)
#define HWIO_DDR_CTL_546_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_546_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_546_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_4_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_546_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_4_FLDSHFT (16)
#define HWIO_DDR_CTL_546_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_546_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_547_REGOFF 0x88c
#define HWIO_DDR_CTL_547_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_547_REGOFF)
#define HWIO_DDR_CTL_547_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_4_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_547_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_4_FLDSHFT (0)
#define HWIO_DDR_CTL_547_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_547_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_547_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_5_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_547_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_5_FLDSHFT (16)
#define HWIO_DDR_CTL_547_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_547_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_548_REGOFF 0x890
#define HWIO_DDR_CTL_548_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_548_REGOFF)
#define HWIO_DDR_CTL_548_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_5_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_548_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_5_FLDSHFT (0)
#define HWIO_DDR_CTL_548_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_548_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_548_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_6_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_548_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_6_FLDSHFT (16)
#define HWIO_DDR_CTL_548_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_548_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_549_REGOFF 0x894
#define HWIO_DDR_CTL_549_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_549_REGOFF)
#define HWIO_DDR_CTL_549_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_6_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_549_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_6_FLDSHFT (0)
#define HWIO_DDR_CTL_549_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_549_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_549_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_7_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_549_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_7_FLDSHFT (16)
#define HWIO_DDR_CTL_549_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_549_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_550_REGOFF 0x898
#define HWIO_DDR_CTL_550_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_550_REGOFF)
#define HWIO_DDR_CTL_550_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_7_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_550_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_7_FLDSHFT (0)
#define HWIO_DDR_CTL_550_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_550_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_550_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_8_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_550_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_8_FLDSHFT (16)
#define HWIO_DDR_CTL_550_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_550_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_551_REGOFF 0x89c
#define HWIO_DDR_CTL_551_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_551_REGOFF)
#define HWIO_DDR_CTL_551_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_8_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_551_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_8_FLDSHFT (0)
#define HWIO_DDR_CTL_551_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_551_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_551_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_9_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_551_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_9_FLDSHFT (16)
#define HWIO_DDR_CTL_551_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_551_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_552_REGOFF 0x8a0
#define HWIO_DDR_CTL_552_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_552_REGOFF)
#define HWIO_DDR_CTL_552_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_9_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_552_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_9_FLDSHFT (0)
#define HWIO_DDR_CTL_552_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_552_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_552_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_10_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_552_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_10_FLDSHFT (16)
#define HWIO_DDR_CTL_552_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_552_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_553_REGOFF 0x8a4
#define HWIO_DDR_CTL_553_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_553_REGOFF)
#define HWIO_DDR_CTL_553_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_10_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_553_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_10_FLDSHFT (0)
#define HWIO_DDR_CTL_553_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_553_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_553_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_11_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_553_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_11_FLDSHFT (16)
#define HWIO_DDR_CTL_553_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_553_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_554_REGOFF 0x8a8
#define HWIO_DDR_CTL_554_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_554_REGOFF)
#define HWIO_DDR_CTL_554_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_11_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_554_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_11_FLDSHFT (0)
#define HWIO_DDR_CTL_554_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_554_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_554_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_12_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_554_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_12_FLDSHFT (16)
#define HWIO_DDR_CTL_554_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_554_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_555_REGOFF 0x8ac
#define HWIO_DDR_CTL_555_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_555_REGOFF)
#define HWIO_DDR_CTL_555_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_12_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_555_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_12_FLDSHFT (0)
#define HWIO_DDR_CTL_555_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_555_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_555_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_13_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_555_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_13_FLDSHFT (16)
#define HWIO_DDR_CTL_555_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_555_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_556_REGOFF 0x8b0
#define HWIO_DDR_CTL_556_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_556_REGOFF)
#define HWIO_DDR_CTL_556_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_13_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_556_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_13_FLDSHFT (0)
#define HWIO_DDR_CTL_556_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_556_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_556_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_14_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_556_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_14_FLDSHFT (16)
#define HWIO_DDR_CTL_556_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_556_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_557_REGOFF 0x8b4
#define HWIO_DDR_CTL_557_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_557_REGOFF)
#define HWIO_DDR_CTL_557_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_14_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_557_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_14_FLDSHFT (0)
#define HWIO_DDR_CTL_557_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_557_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_557_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_15_FLDMASK \
	(0x1ff0000)
#define HWIO_DDR_CTL_557_AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_15_FLDSHFT (16)
#define HWIO_DDR_CTL_557_CDNS_INTRL1_FLDMASK (0xfe000000)
#define HWIO_DDR_CTL_557_CDNS_INTRL1_FLDSHFT (25)

#define HWIO_DDR_CTL_558_REGOFF 0x8b8
#define HWIO_DDR_CTL_558_ADDR(bAddr, regX) (bAddr + HWIO_DDR_CTL_558_REGOFF)
#define HWIO_DDR_CTL_558_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_15_FLDMASK (0x1ff)
#define HWIO_DDR_CTL_558_AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_15_FLDSHFT (0)
#define HWIO_DDR_CTL_558_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_CTL_558_RESERVED_FLDSHFT (9)
#define HWIO_DDR_CTL_558_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_CTL_558_OBSOLETE1_FLDSHFT (16)

#endif /* __MNH_HWIO_DDR_CTL_ */