path: root/drivers/misc/mnh/mnh-hwio-ddr-pi.h

/* auto generated: Friday, August 26th, 2016 11:42:19am */
/*
 * Copyright (c) 2016, Intel Corporation. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * Redistributions of source code must retain the above copyright notice, this
 * list of conditions and the following disclaimer.
 *
 * Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * Neither the name of Intel nor the names of its contributors may be used
 * to endorse or promote products derived from this software without specific
 * prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
#ifndef __MNH_HWIO_DDR_PI_
#define __MNH_HWIO_DDR_PI_

#define HWIO_DDR_PI_00_REGOFF 0x0
#define HWIO_DDR_PI_00_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_00_REGOFF)
#define HWIO_DDR_PI_00_PI_START_FLDMASK (0x1)
#define HWIO_DDR_PI_00_PI_START_FLDSHFT (0)
#define HWIO_DDR_PI_00_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_00_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_00_PI_DRAM_CLASS_FLDMASK (0xf00)
#define HWIO_DDR_PI_00_PI_DRAM_CLASS_FLDSHFT (8)
#define HWIO_DDR_PI_00_RESERVED1_FLDMASK (0xf000)
#define HWIO_DDR_PI_00_RESERVED1_FLDSHFT (12)
#define HWIO_DDR_PI_00_PI_VERSION_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_00_PI_VERSION_FLDSHFT (16)

#define HWIO_DDR_PI_01_REGOFF 0x4
#define HWIO_DDR_PI_01_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_01_REGOFF)
#define HWIO_DDR_PI_01_PI_NORMAL_LVL_SEQ_FLDMASK (0x1)
#define HWIO_DDR_PI_01_PI_NORMAL_LVL_SEQ_FLDSHFT (0)
#define HWIO_DDR_PI_01_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_01_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_01_PI_INIT_LVL_EN_FLDMASK (0x100)
#define HWIO_DDR_PI_01_PI_INIT_LVL_EN_FLDSHFT (8)
#define HWIO_DDR_PI_01_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_01_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_01_PI_NOTCARE_PHYUPD_FLDMASK (0x10000)
#define HWIO_DDR_PI_01_PI_NOTCARE_PHYUPD_FLDSHFT (16)
#define HWIO_DDR_PI_01_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_01_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_01_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_PI_01_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_PI_02_REGOFF 0x8
#define HWIO_DDR_PI_02_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_02_REGOFF)
#define HWIO_DDR_PI_02_PI_TCMD_GAP_FLDMASK (0xffff)
#define HWIO_DDR_PI_02_PI_TCMD_GAP_FLDSHFT (0)
#define HWIO_DDR_PI_02_PI_MASTER_ACK_DURATION_MIN_FLDMASK (0xff0000)
#define HWIO_DDR_PI_02_PI_MASTER_ACK_DURATION_MIN_FLDSHFT (16)
#define HWIO_DDR_PI_02_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_PI_02_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_PI_03_REGOFF 0xc
#define HWIO_DDR_PI_03_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_03_REGOFF)
#define HWIO_DDR_PI_03_PI_TDFI_PHYMSTR_MAX_F0_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_03_PI_TDFI_PHYMSTR_MAX_F0_FLDSHFT (0)

#define HWIO_DDR_PI_04_REGOFF 0x10
#define HWIO_DDR_PI_04_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_04_REGOFF)
#define HWIO_DDR_PI_04_PI_TDFI_PHYMSTR_RESP_F0_FLDMASK (0xffff)
#define HWIO_DDR_PI_04_PI_TDFI_PHYMSTR_RESP_F0_FLDSHFT (0)
#define HWIO_DDR_PI_04_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_04_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_05_REGOFF 0x14
#define HWIO_DDR_PI_05_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_05_REGOFF)
#define HWIO_DDR_PI_05_PI_TDFI_PHYMSTR_MAX_F1_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_05_PI_TDFI_PHYMSTR_MAX_F1_FLDSHFT (0)

#define HWIO_DDR_PI_06_REGOFF 0x18
#define HWIO_DDR_PI_06_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_06_REGOFF)
#define HWIO_DDR_PI_06_PI_TDFI_PHYMSTR_RESP_F1_FLDMASK (0xffff)
#define HWIO_DDR_PI_06_PI_TDFI_PHYMSTR_RESP_F1_FLDSHFT (0)
#define HWIO_DDR_PI_06_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_06_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_07_REGOFF 0x1c
#define HWIO_DDR_PI_07_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_07_REGOFF)
#define HWIO_DDR_PI_07_PI_TDFI_PHYMSTR_MAX_F2_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_07_PI_TDFI_PHYMSTR_MAX_F2_FLDSHFT (0)

#define HWIO_DDR_PI_08_REGOFF 0x20
#define HWIO_DDR_PI_08_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_08_REGOFF)
#define HWIO_DDR_PI_08_PI_TDFI_PHYMSTR_RESP_F2_FLDMASK (0xffff)
#define HWIO_DDR_PI_08_PI_TDFI_PHYMSTR_RESP_F2_FLDSHFT (0)
#define HWIO_DDR_PI_08_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_08_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_09_REGOFF 0x24
#define HWIO_DDR_PI_09_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_09_REGOFF)
#define HWIO_DDR_PI_09_PI_TDFI_PHYMSTR_MAX_F3_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_09_PI_TDFI_PHYMSTR_MAX_F3_FLDSHFT (0)

#define HWIO_DDR_PI_10_REGOFF 0x28
#define HWIO_DDR_PI_10_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_10_REGOFF)
#define HWIO_DDR_PI_10_PI_TDFI_PHYMSTR_RESP_F3_FLDMASK (0xffff)
#define HWIO_DDR_PI_10_PI_TDFI_PHYMSTR_RESP_F3_FLDSHFT (0)
#define HWIO_DDR_PI_10_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_10_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_11_REGOFF 0x2c
#define HWIO_DDR_PI_11_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_11_REGOFF)
#define HWIO_DDR_PI_11_PI_TDFI_PHYUPD_RESP_F0_FLDMASK (0xfffff)
#define HWIO_DDR_PI_11_PI_TDFI_PHYUPD_RESP_F0_FLDSHFT (0)
#define HWIO_DDR_PI_11_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_PI_11_RESERVED_FLDSHFT (20)
#define HWIO_DDR_PI_11_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_11_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_12_REGOFF 0x30
#define HWIO_DDR_PI_12_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_12_REGOFF)
#define HWIO_DDR_PI_12_PI_TDFI_PHYUPD_TYPE0_F0_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_12_PI_TDFI_PHYUPD_TYPE0_F0_FLDSHFT (0)

#define HWIO_DDR_PI_13_REGOFF 0x34
#define HWIO_DDR_PI_13_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_13_REGOFF)
#define HWIO_DDR_PI_13_PI_TDFI_PHYUPD_TYPE1_F0_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_13_PI_TDFI_PHYUPD_TYPE1_F0_FLDSHFT (0)

#define HWIO_DDR_PI_14_REGOFF 0x38
#define HWIO_DDR_PI_14_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_14_REGOFF)
#define HWIO_DDR_PI_14_PI_TDFI_PHYUPD_TYPE2_F0_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_14_PI_TDFI_PHYUPD_TYPE2_F0_FLDSHFT (0)

#define HWIO_DDR_PI_15_REGOFF 0x3c
#define HWIO_DDR_PI_15_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_15_REGOFF)
#define HWIO_DDR_PI_15_PI_TDFI_PHYUPD_TYPE3_F0_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_15_PI_TDFI_PHYUPD_TYPE3_F0_FLDSHFT (0)

#define HWIO_DDR_PI_16_REGOFF 0x40
#define HWIO_DDR_PI_16_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_16_REGOFF)
#define HWIO_DDR_PI_16_PI_TDFI_PHYUPD_RESP_F1_FLDMASK (0xfffff)
#define HWIO_DDR_PI_16_PI_TDFI_PHYUPD_RESP_F1_FLDSHFT (0)
#define HWIO_DDR_PI_16_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_PI_16_RESERVED_FLDSHFT (20)
#define HWIO_DDR_PI_16_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_16_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_17_REGOFF 0x44
#define HWIO_DDR_PI_17_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_17_REGOFF)
#define HWIO_DDR_PI_17_PI_TDFI_PHYUPD_TYPE0_F1_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_17_PI_TDFI_PHYUPD_TYPE0_F1_FLDSHFT (0)

#define HWIO_DDR_PI_18_REGOFF 0x48
#define HWIO_DDR_PI_18_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_18_REGOFF)
#define HWIO_DDR_PI_18_PI_TDFI_PHYUPD_TYPE1_F1_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_18_PI_TDFI_PHYUPD_TYPE1_F1_FLDSHFT (0)

#define HWIO_DDR_PI_19_REGOFF 0x4c
#define HWIO_DDR_PI_19_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_19_REGOFF)
#define HWIO_DDR_PI_19_PI_TDFI_PHYUPD_TYPE2_F1_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_19_PI_TDFI_PHYUPD_TYPE2_F1_FLDSHFT (0)

#define HWIO_DDR_PI_20_REGOFF 0x50
#define HWIO_DDR_PI_20_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_20_REGOFF)
#define HWIO_DDR_PI_20_PI_TDFI_PHYUPD_TYPE3_F1_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_20_PI_TDFI_PHYUPD_TYPE3_F1_FLDSHFT (0)

#define HWIO_DDR_PI_21_REGOFF 0x54
#define HWIO_DDR_PI_21_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_21_REGOFF)
#define HWIO_DDR_PI_21_PI_TDFI_PHYUPD_RESP_F2_FLDMASK (0xfffff)
#define HWIO_DDR_PI_21_PI_TDFI_PHYUPD_RESP_F2_FLDSHFT (0)
#define HWIO_DDR_PI_21_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_PI_21_RESERVED_FLDSHFT (20)
#define HWIO_DDR_PI_21_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_21_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_22_REGOFF 0x58
#define HWIO_DDR_PI_22_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_22_REGOFF)
#define HWIO_DDR_PI_22_PI_TDFI_PHYUPD_TYPE0_F2_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_22_PI_TDFI_PHYUPD_TYPE0_F2_FLDSHFT (0)

#define HWIO_DDR_PI_23_REGOFF 0x5c
#define HWIO_DDR_PI_23_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_23_REGOFF)
#define HWIO_DDR_PI_23_PI_TDFI_PHYUPD_TYPE1_F2_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_23_PI_TDFI_PHYUPD_TYPE1_F2_FLDSHFT (0)

#define HWIO_DDR_PI_24_REGOFF 0x60
#define HWIO_DDR_PI_24_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_24_REGOFF)
#define HWIO_DDR_PI_24_PI_TDFI_PHYUPD_TYPE2_F2_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_24_PI_TDFI_PHYUPD_TYPE2_F2_FLDSHFT (0)

#define HWIO_DDR_PI_25_REGOFF 0x64
#define HWIO_DDR_PI_25_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_25_REGOFF)
#define HWIO_DDR_PI_25_PI_TDFI_PHYUPD_TYPE3_F2_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_25_PI_TDFI_PHYUPD_TYPE3_F2_FLDSHFT (0)

#define HWIO_DDR_PI_26_REGOFF 0x68
#define HWIO_DDR_PI_26_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_26_REGOFF)
#define HWIO_DDR_PI_26_PI_TDFI_PHYUPD_RESP_F3_FLDMASK (0xfffff)
#define HWIO_DDR_PI_26_PI_TDFI_PHYUPD_RESP_F3_FLDSHFT (0)
#define HWIO_DDR_PI_26_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_PI_26_RESERVED_FLDSHFT (20)
#define HWIO_DDR_PI_26_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_26_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_27_REGOFF 0x6c
#define HWIO_DDR_PI_27_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_27_REGOFF)
#define HWIO_DDR_PI_27_PI_TDFI_PHYUPD_TYPE0_F3_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_27_PI_TDFI_PHYUPD_TYPE0_F3_FLDSHFT (0)

#define HWIO_DDR_PI_28_REGOFF 0x70
#define HWIO_DDR_PI_28_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_28_REGOFF)
#define HWIO_DDR_PI_28_PI_TDFI_PHYUPD_TYPE1_F3_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_28_PI_TDFI_PHYUPD_TYPE1_F3_FLDSHFT (0)

#define HWIO_DDR_PI_29_REGOFF 0x74
#define HWIO_DDR_PI_29_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_29_REGOFF)
#define HWIO_DDR_PI_29_PI_TDFI_PHYUPD_TYPE2_F3_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_29_PI_TDFI_PHYUPD_TYPE2_F3_FLDSHFT (0)

#define HWIO_DDR_PI_30_REGOFF 0x78
#define HWIO_DDR_PI_30_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_30_REGOFF)
#define HWIO_DDR_PI_30_PI_TDFI_PHYUPD_TYPE3_F3_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_30_PI_TDFI_PHYUPD_TYPE3_F3_FLDSHFT (0)

#define HWIO_DDR_PI_31_REGOFF 0x7c
#define HWIO_DDR_PI_31_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_31_REGOFF)
#define HWIO_DDR_PI_31_PI_CONTROL_ERROR_STATUS_FLDMASK (0x1ff)
#define HWIO_DDR_PI_31_PI_CONTROL_ERROR_STATUS_FLDSHFT (0)
#define HWIO_DDR_PI_31_RESERVED_FLDMASK (0xfe00)
#define HWIO_DDR_PI_31_RESERVED_FLDSHFT (9)
#define HWIO_DDR_PI_31_PI_EXIT_AFTER_INIT_CALVL_FLDMASK (0x10000)
#define HWIO_DDR_PI_31_PI_EXIT_AFTER_INIT_CALVL_FLDSHFT (16)
#define HWIO_DDR_PI_31_RESERVED1_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_31_RESERVED1_FLDSHFT (17)
#define HWIO_DDR_PI_31_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_PI_31_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_PI_32_REGOFF 0x80
#define HWIO_DDR_PI_32_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_32_REGOFF)
#define HWIO_DDR_PI_32_PI_FREQ_MAP_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_32_PI_FREQ_MAP_FLDSHFT (0)

#define HWIO_DDR_PI_33_REGOFF 0x84
#define HWIO_DDR_PI_33_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_33_REGOFF)
#define HWIO_DDR_PI_33_PI_INIT_WORK_FREQ_FLDMASK (0x1f)
#define HWIO_DDR_PI_33_PI_INIT_WORK_FREQ_FLDSHFT (0)
#define HWIO_DDR_PI_33_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_PI_33_RESERVED_FLDSHFT (5)
#define HWIO_DDR_PI_33_PI_INIT_DFS_CALVL_ONLY_FLDMASK (0x100)
#define HWIO_DDR_PI_33_PI_INIT_DFS_CALVL_ONLY_FLDSHFT (8)
#define HWIO_DDR_PI_33_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_33_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_33_PI_POWER_ON_SEQ_BYPASS_ARRAY_FLDMASK (0xff0000)
#define HWIO_DDR_PI_33_PI_POWER_ON_SEQ_BYPASS_ARRAY_FLDSHFT (16)
#define HWIO_DDR_PI_33_PI_POWER_ON_SEQ_END_ARRAY_FLDMASK (0xff000000)
#define HWIO_DDR_PI_33_PI_POWER_ON_SEQ_END_ARRAY_FLDSHFT (24)

#define HWIO_DDR_PI_34_REGOFF 0x88
#define HWIO_DDR_PI_34_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_34_REGOFF)
#define HWIO_DDR_PI_34_PI_SEQ1_PAT_FLDMASK (0xffffff)
#define HWIO_DDR_PI_34_PI_SEQ1_PAT_FLDSHFT (0)
#define HWIO_DDR_PI_34_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_34_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_35_REGOFF 0x8c
#define HWIO_DDR_PI_35_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_35_REGOFF)
#define HWIO_DDR_PI_35_PI_SEQ1_PAT_MASK_FLDMASK (0xffffff)
#define HWIO_DDR_PI_35_PI_SEQ1_PAT_MASK_FLDSHFT (0)
#define HWIO_DDR_PI_35_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_35_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_36_REGOFF 0x90
#define HWIO_DDR_PI_36_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_36_REGOFF)
#define HWIO_DDR_PI_36_PI_SEQ2_PAT_FLDMASK (0xffffff)
#define HWIO_DDR_PI_36_PI_SEQ2_PAT_FLDSHFT (0)
#define HWIO_DDR_PI_36_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_36_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_37_REGOFF 0x94
#define HWIO_DDR_PI_37_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_37_REGOFF)
#define HWIO_DDR_PI_37_PI_SEQ2_PAT_MASK_FLDMASK (0xffffff)
#define HWIO_DDR_PI_37_PI_SEQ2_PAT_MASK_FLDSHFT (0)
#define HWIO_DDR_PI_37_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_37_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_38_REGOFF 0x98
#define HWIO_DDR_PI_38_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_38_REGOFF)
#define HWIO_DDR_PI_38_PI_SEQ3_PAT_FLDMASK (0xffffff)
#define HWIO_DDR_PI_38_PI_SEQ3_PAT_FLDSHFT (0)
#define HWIO_DDR_PI_38_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_38_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_39_REGOFF 0x9c
#define HWIO_DDR_PI_39_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_39_REGOFF)
#define HWIO_DDR_PI_39_PI_SEQ3_PAT_MASK_FLDMASK (0xffffff)
#define HWIO_DDR_PI_39_PI_SEQ3_PAT_MASK_FLDSHFT (0)
#define HWIO_DDR_PI_39_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_39_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_40_REGOFF 0xa0
#define HWIO_DDR_PI_40_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_40_REGOFF)
#define HWIO_DDR_PI_40_PI_SEQ4_PAT_FLDMASK (0xffffff)
#define HWIO_DDR_PI_40_PI_SEQ4_PAT_FLDSHFT (0)
#define HWIO_DDR_PI_40_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_40_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_41_REGOFF 0xa4
#define HWIO_DDR_PI_41_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_41_REGOFF)
#define HWIO_DDR_PI_41_PI_SEQ4_PAT_MASK_FLDMASK (0xffffff)
#define HWIO_DDR_PI_41_PI_SEQ4_PAT_MASK_FLDSHFT (0)
#define HWIO_DDR_PI_41_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_41_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_42_REGOFF 0xa8
#define HWIO_DDR_PI_42_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_42_REGOFF)
#define HWIO_DDR_PI_42_PI_SEQ5_PAT_FLDMASK (0xffffff)
#define HWIO_DDR_PI_42_PI_SEQ5_PAT_FLDSHFT (0)
#define HWIO_DDR_PI_42_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_42_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_43_REGOFF 0xac
#define HWIO_DDR_PI_43_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_43_REGOFF)
#define HWIO_DDR_PI_43_PI_SEQ5_PAT_MASK_FLDMASK (0xffffff)
#define HWIO_DDR_PI_43_PI_SEQ5_PAT_MASK_FLDSHFT (0)
#define HWIO_DDR_PI_43_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_43_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_44_REGOFF 0xb0
#define HWIO_DDR_PI_44_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_44_REGOFF)
#define HWIO_DDR_PI_44_PI_SEQ6_PAT_FLDMASK (0xffffff)
#define HWIO_DDR_PI_44_PI_SEQ6_PAT_FLDSHFT (0)
#define HWIO_DDR_PI_44_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_44_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_45_REGOFF 0xb4
#define HWIO_DDR_PI_45_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_45_REGOFF)
#define HWIO_DDR_PI_45_PI_SEQ6_PAT_MASK_FLDMASK (0xffffff)
#define HWIO_DDR_PI_45_PI_SEQ6_PAT_MASK_FLDSHFT (0)
#define HWIO_DDR_PI_45_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_45_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_46_REGOFF 0xb8
#define HWIO_DDR_PI_46_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_46_REGOFF)
#define HWIO_DDR_PI_46_PI_SEQ7_PAT_FLDMASK (0xffffff)
#define HWIO_DDR_PI_46_PI_SEQ7_PAT_FLDSHFT (0)
#define HWIO_DDR_PI_46_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_46_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_47_REGOFF 0xbc
#define HWIO_DDR_PI_47_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_47_REGOFF)
#define HWIO_DDR_PI_47_PI_SEQ7_PAT_MASK_FLDMASK (0xffffff)
#define HWIO_DDR_PI_47_PI_SEQ7_PAT_MASK_FLDSHFT (0)
#define HWIO_DDR_PI_47_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_47_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_48_REGOFF 0xc0
#define HWIO_DDR_PI_48_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_48_REGOFF)
#define HWIO_DDR_PI_48_PI_SEQ8_PAT_FLDMASK (0xffffff)
#define HWIO_DDR_PI_48_PI_SEQ8_PAT_FLDSHFT (0)
#define HWIO_DDR_PI_48_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_48_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_49_REGOFF 0xc4
#define HWIO_DDR_PI_49_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_49_REGOFF)
#define HWIO_DDR_PI_49_PI_SEQ8_PAT_MASK_FLDMASK (0xffffff)
#define HWIO_DDR_PI_49_PI_SEQ8_PAT_MASK_FLDSHFT (0)
#define HWIO_DDR_PI_49_PI_WDT_DISABLE_FLDMASK (0x1000000)
#define HWIO_DDR_PI_49_PI_WDT_DISABLE_FLDSHFT (24)
#define HWIO_DDR_PI_49_RESERVED_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_49_RESERVED_FLDSHFT (25)

#define HWIO_DDR_PI_50_REGOFF 0xc8
#define HWIO_DDR_PI_50_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_50_REGOFF)
#define HWIO_DDR_PI_50_PI_SW_RST_N_FLDMASK (0x1)
#define HWIO_DDR_PI_50_PI_SW_RST_N_FLDSHFT (0)
#define HWIO_DDR_PI_50_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_50_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_50_RESERVED1_FLDMASK (0x100)
#define HWIO_DDR_PI_50_RESERVED1_FLDSHFT (8)
#define HWIO_DDR_PI_50_RESERVED2_FLDMASK (0xfe00)
#define HWIO_DDR_PI_50_RESERVED2_FLDSHFT (9)
#define HWIO_DDR_PI_50_PI_CS_MAP_FLDMASK (0x30000)
#define HWIO_DDR_PI_50_PI_CS_MAP_FLDSHFT (16)
#define HWIO_DDR_PI_50_RESERVED3_FLDMASK (0xfc0000)
#define HWIO_DDR_PI_50_RESERVED3_FLDSHFT (18)
#define HWIO_DDR_PI_50_PI_TDELAY_RDWR_2_BUS_IDLE_F0_FLDMASK (0xff000000)
#define HWIO_DDR_PI_50_PI_TDELAY_RDWR_2_BUS_IDLE_F0_FLDSHFT (24)

#define HWIO_DDR_PI_51_REGOFF 0xcc
#define HWIO_DDR_PI_51_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_51_REGOFF)
#define HWIO_DDR_PI_51_PI_TDELAY_RDWR_2_BUS_IDLE_F1_FLDMASK (0xff)
#define HWIO_DDR_PI_51_PI_TDELAY_RDWR_2_BUS_IDLE_F1_FLDSHFT (0)
#define HWIO_DDR_PI_51_PI_TDELAY_RDWR_2_BUS_IDLE_F2_FLDMASK (0xff00)
#define HWIO_DDR_PI_51_PI_TDELAY_RDWR_2_BUS_IDLE_F2_FLDSHFT (8)
#define HWIO_DDR_PI_51_PI_TDELAY_RDWR_2_BUS_IDLE_F3_FLDMASK (0xff0000)
#define HWIO_DDR_PI_51_PI_TDELAY_RDWR_2_BUS_IDLE_F3_FLDSHFT (16)
#define HWIO_DDR_PI_51_PI_TMRR_FLDMASK (0xf000000)
#define HWIO_DDR_PI_51_PI_TMRR_FLDSHFT (24)
#define HWIO_DDR_PI_51_RESERVED_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_51_RESERVED_FLDSHFT (28)

#define HWIO_DDR_PI_52_REGOFF 0xd0
#define HWIO_DDR_PI_52_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_52_REGOFF)
#define HWIO_DDR_PI_52_PI_PREAMBLE_SUPPORT_FLDMASK (0x3)
#define HWIO_DDR_PI_52_PI_PREAMBLE_SUPPORT_FLDSHFT (0)
#define HWIO_DDR_PI_52_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_52_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_52_PI_AREFRESH_FLDMASK (0x100)
#define HWIO_DDR_PI_52_PI_AREFRESH_FLDSHFT (8)
#define HWIO_DDR_PI_52_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_52_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_52_PI_MCAREF_FORWARD_ONLY_FLDMASK (0x10000)
#define HWIO_DDR_PI_52_PI_MCAREF_FORWARD_ONLY_FLDSHFT (16)
#define HWIO_DDR_PI_52_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_52_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_52_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_PI_52_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_PI_53_REGOFF 0xd4
#define HWIO_DDR_PI_53_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_53_REGOFF)
#define HWIO_DDR_PI_53_PI_TRFC_F0_FLDMASK (0x3ff)
#define HWIO_DDR_PI_53_PI_TRFC_F0_FLDSHFT (0)
#define HWIO_DDR_PI_53_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_53_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_53_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_53_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_54_REGOFF 0xd8
#define HWIO_DDR_PI_54_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_54_REGOFF)
#define HWIO_DDR_PI_54_PI_TREF_F0_FLDMASK (0xfffff)
#define HWIO_DDR_PI_54_PI_TREF_F0_FLDSHFT (0)
#define HWIO_DDR_PI_54_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_PI_54_RESERVED_FLDSHFT (20)
#define HWIO_DDR_PI_54_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_54_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_55_REGOFF 0xdc
#define HWIO_DDR_PI_55_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_55_REGOFF)
#define HWIO_DDR_PI_55_PI_TRFC_F1_FLDMASK (0x3ff)
#define HWIO_DDR_PI_55_PI_TRFC_F1_FLDSHFT (0)
#define HWIO_DDR_PI_55_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_55_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_55_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_55_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_56_REGOFF 0xe0
#define HWIO_DDR_PI_56_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_56_REGOFF)
#define HWIO_DDR_PI_56_PI_TREF_F1_FLDMASK (0xfffff)
#define HWIO_DDR_PI_56_PI_TREF_F1_FLDSHFT (0)
#define HWIO_DDR_PI_56_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_PI_56_RESERVED_FLDSHFT (20)
#define HWIO_DDR_PI_56_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_56_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_57_REGOFF 0xe4
#define HWIO_DDR_PI_57_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_57_REGOFF)
#define HWIO_DDR_PI_57_PI_TRFC_F2_FLDMASK (0x3ff)
#define HWIO_DDR_PI_57_PI_TRFC_F2_FLDSHFT (0)
#define HWIO_DDR_PI_57_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_57_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_57_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_57_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_58_REGOFF 0xe8
#define HWIO_DDR_PI_58_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_58_REGOFF)
#define HWIO_DDR_PI_58_PI_TREF_F2_FLDMASK (0xfffff)
#define HWIO_DDR_PI_58_PI_TREF_F2_FLDSHFT (0)
#define HWIO_DDR_PI_58_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_PI_58_RESERVED_FLDSHFT (20)
#define HWIO_DDR_PI_58_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_58_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_59_REGOFF 0xec
#define HWIO_DDR_PI_59_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_59_REGOFF)
#define HWIO_DDR_PI_59_PI_TRFC_F3_FLDMASK (0x3ff)
#define HWIO_DDR_PI_59_PI_TRFC_F3_FLDSHFT (0)
#define HWIO_DDR_PI_59_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_59_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_59_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_59_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_60_REGOFF 0xf0
#define HWIO_DDR_PI_60_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_60_REGOFF)
#define HWIO_DDR_PI_60_PI_TREF_F3_FLDMASK (0xfffff)
#define HWIO_DDR_PI_60_PI_TREF_F3_FLDSHFT (0)
#define HWIO_DDR_PI_60_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_PI_60_RESERVED_FLDSHFT (20)
#define HWIO_DDR_PI_60_RESERVED1_FLDMASK (0x1000000)
#define HWIO_DDR_PI_60_RESERVED1_FLDSHFT (24)
#define HWIO_DDR_PI_60_RESERVED2_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_60_RESERVED2_FLDSHFT (25)

#define HWIO_DDR_PI_61_REGOFF 0xf4
#define HWIO_DDR_PI_61_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_61_REGOFF)
#define HWIO_DDR_PI_61_PI_FREQ_CHANGE_REG_COPY_FLDMASK (0x1f)
#define HWIO_DDR_PI_61_PI_FREQ_CHANGE_REG_COPY_FLDSHFT (0)
#define HWIO_DDR_PI_61_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_PI_61_RESERVED_FLDSHFT (5)
#define HWIO_DDR_PI_61_PI_FREQ_SEL_FROM_REGIF_FLDMASK (0x100)
#define HWIO_DDR_PI_61_PI_FREQ_SEL_FROM_REGIF_FLDSHFT (8)
#define HWIO_DDR_PI_61_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_61_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_61_PI_SWLVL_LOAD_FLDMASK (0x10000)
#define HWIO_DDR_PI_61_PI_SWLVL_LOAD_FLDSHFT (16)
#define HWIO_DDR_PI_61_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_61_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_61_PI_SWLVL_OP_DONE_FLDMASK (0x1000000)
#define HWIO_DDR_PI_61_PI_SWLVL_OP_DONE_FLDSHFT (24)
#define HWIO_DDR_PI_61_RESERVED3_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_61_RESERVED3_FLDSHFT (25)

#define HWIO_DDR_PI_62_REGOFF 0xf8
#define HWIO_DDR_PI_62_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_62_REGOFF)
#define HWIO_DDR_PI_62_PI_SW_WRLVL_RESP_0_FLDMASK (0x1)
#define HWIO_DDR_PI_62_PI_SW_WRLVL_RESP_0_FLDSHFT (0)
#define HWIO_DDR_PI_62_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_62_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_62_PI_SW_WRLVL_RESP_1_FLDMASK (0x100)
#define HWIO_DDR_PI_62_PI_SW_WRLVL_RESP_1_FLDSHFT (8)
#define HWIO_DDR_PI_62_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_62_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_62_PI_SW_WRLVL_RESP_2_FLDMASK (0x10000)
#define HWIO_DDR_PI_62_PI_SW_WRLVL_RESP_2_FLDSHFT (16)
#define HWIO_DDR_PI_62_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_62_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_62_PI_SW_WRLVL_RESP_3_FLDMASK (0x1000000)
#define HWIO_DDR_PI_62_PI_SW_WRLVL_RESP_3_FLDSHFT (24)
#define HWIO_DDR_PI_62_RESERVED3_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_62_RESERVED3_FLDSHFT (25)

#define HWIO_DDR_PI_63_REGOFF 0xfc
#define HWIO_DDR_PI_63_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_63_REGOFF)
#define HWIO_DDR_PI_63_PI_SW_RDLVL_RESP_0_FLDMASK (0x3)
#define HWIO_DDR_PI_63_PI_SW_RDLVL_RESP_0_FLDSHFT (0)
#define HWIO_DDR_PI_63_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_63_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_63_PI_SW_RDLVL_RESP_1_FLDMASK (0x300)
#define HWIO_DDR_PI_63_PI_SW_RDLVL_RESP_1_FLDSHFT (8)
#define HWIO_DDR_PI_63_RESERVED1_FLDMASK (0xfc00)
#define HWIO_DDR_PI_63_RESERVED1_FLDSHFT (10)
#define HWIO_DDR_PI_63_PI_SW_RDLVL_RESP_2_FLDMASK (0x30000)
#define HWIO_DDR_PI_63_PI_SW_RDLVL_RESP_2_FLDSHFT (16)
#define HWIO_DDR_PI_63_RESERVED2_FLDMASK (0xfc0000)
#define HWIO_DDR_PI_63_RESERVED2_FLDSHFT (18)
#define HWIO_DDR_PI_63_PI_SW_RDLVL_RESP_3_FLDMASK (0x3000000)
#define HWIO_DDR_PI_63_PI_SW_RDLVL_RESP_3_FLDSHFT (24)
#define HWIO_DDR_PI_63_RESERVED3_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_63_RESERVED3_FLDSHFT (26)

#define HWIO_DDR_PI_64_REGOFF 0x100
#define HWIO_DDR_PI_64_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_64_REGOFF)
#define HWIO_DDR_PI_64_PI_SW_CALVL_RESP_0_FLDMASK (0x3)
#define HWIO_DDR_PI_64_PI_SW_CALVL_RESP_0_FLDSHFT (0)
#define HWIO_DDR_PI_64_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_64_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_64_PI_SW_LEVELING_MODE_FLDMASK (0x700)
#define HWIO_DDR_PI_64_PI_SW_LEVELING_MODE_FLDSHFT (8)
#define HWIO_DDR_PI_64_RESERVED1_FLDMASK (0xf800)
#define HWIO_DDR_PI_64_RESERVED1_FLDSHFT (11)
#define HWIO_DDR_PI_64_PI_SWLVL_START_FLDMASK (0x10000)
#define HWIO_DDR_PI_64_PI_SWLVL_START_FLDSHFT (16)
#define HWIO_DDR_PI_64_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_64_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_64_PI_SWLVL_EXIT_FLDMASK (0x1000000)
#define HWIO_DDR_PI_64_PI_SWLVL_EXIT_FLDSHFT (24)
#define HWIO_DDR_PI_64_RESERVED3_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_64_RESERVED3_FLDSHFT (25)

#define HWIO_DDR_PI_65_REGOFF 0x104
#define HWIO_DDR_PI_65_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_65_REGOFF)
#define HWIO_DDR_PI_65_PI_SWLVL_WR_SLICE_0_FLDMASK (0x1)
#define HWIO_DDR_PI_65_PI_SWLVL_WR_SLICE_0_FLDSHFT (0)
#define HWIO_DDR_PI_65_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_65_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_65_PI_SWLVL_RD_SLICE_0_FLDMASK (0x100)
#define HWIO_DDR_PI_65_PI_SWLVL_RD_SLICE_0_FLDSHFT (8)
#define HWIO_DDR_PI_65_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_65_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_65_PI_SWLVL_VREF_UPDATE_SLICE_0_FLDMASK (0x10000)
#define HWIO_DDR_PI_65_PI_SWLVL_VREF_UPDATE_SLICE_0_FLDSHFT (16)
#define HWIO_DDR_PI_65_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_65_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_65_PI_SW_WDQLVL_RESP_0_FLDMASK (0x3000000)
#define HWIO_DDR_PI_65_PI_SW_WDQLVL_RESP_0_FLDSHFT (24)
#define HWIO_DDR_PI_65_RESERVED3_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_65_RESERVED3_FLDSHFT (26)

#define HWIO_DDR_PI_66_REGOFF 0x108
#define HWIO_DDR_PI_66_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_66_REGOFF)
#define HWIO_DDR_PI_66_PI_SWLVL_WR_SLICE_1_FLDMASK (0x1)
#define HWIO_DDR_PI_66_PI_SWLVL_WR_SLICE_1_FLDSHFT (0)
#define HWIO_DDR_PI_66_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_66_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_66_PI_SWLVL_RD_SLICE_1_FLDMASK (0x100)
#define HWIO_DDR_PI_66_PI_SWLVL_RD_SLICE_1_FLDSHFT (8)
#define HWIO_DDR_PI_66_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_66_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_66_PI_SWLVL_VREF_UPDATE_SLICE_1_FLDMASK (0x10000)
#define HWIO_DDR_PI_66_PI_SWLVL_VREF_UPDATE_SLICE_1_FLDSHFT (16)
#define HWIO_DDR_PI_66_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_66_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_66_PI_SW_WDQLVL_RESP_1_FLDMASK (0x3000000)
#define HWIO_DDR_PI_66_PI_SW_WDQLVL_RESP_1_FLDSHFT (24)
#define HWIO_DDR_PI_66_RESERVED3_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_66_RESERVED3_FLDSHFT (26)

#define HWIO_DDR_PI_67_REGOFF 0x10c
#define HWIO_DDR_PI_67_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_67_REGOFF)
#define HWIO_DDR_PI_67_PI_SWLVL_WR_SLICE_2_FLDMASK (0x1)
#define HWIO_DDR_PI_67_PI_SWLVL_WR_SLICE_2_FLDSHFT (0)
#define HWIO_DDR_PI_67_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_67_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_67_PI_SWLVL_RD_SLICE_2_FLDMASK (0x100)
#define HWIO_DDR_PI_67_PI_SWLVL_RD_SLICE_2_FLDSHFT (8)
#define HWIO_DDR_PI_67_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_67_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_67_PI_SWLVL_VREF_UPDATE_SLICE_2_FLDMASK (0x10000)
#define HWIO_DDR_PI_67_PI_SWLVL_VREF_UPDATE_SLICE_2_FLDSHFT (16)
#define HWIO_DDR_PI_67_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_67_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_67_PI_SW_WDQLVL_RESP_2_FLDMASK (0x3000000)
#define HWIO_DDR_PI_67_PI_SW_WDQLVL_RESP_2_FLDSHFT (24)
#define HWIO_DDR_PI_67_RESERVED3_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_67_RESERVED3_FLDSHFT (26)

#define HWIO_DDR_PI_68_REGOFF 0x110
#define HWIO_DDR_PI_68_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_68_REGOFF)
#define HWIO_DDR_PI_68_PI_SWLVL_WR_SLICE_3_FLDMASK (0x1)
#define HWIO_DDR_PI_68_PI_SWLVL_WR_SLICE_3_FLDSHFT (0)
#define HWIO_DDR_PI_68_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_68_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_68_PI_SWLVL_RD_SLICE_3_FLDMASK (0x100)
#define HWIO_DDR_PI_68_PI_SWLVL_RD_SLICE_3_FLDSHFT (8)
#define HWIO_DDR_PI_68_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_68_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_68_PI_SWLVL_VREF_UPDATE_SLICE_3_FLDMASK (0x10000)
#define HWIO_DDR_PI_68_PI_SWLVL_VREF_UPDATE_SLICE_3_FLDSHFT (16)
#define HWIO_DDR_PI_68_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_68_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_68_PI_SW_WDQLVL_RESP_3_FLDMASK (0x3000000)
#define HWIO_DDR_PI_68_PI_SW_WDQLVL_RESP_3_FLDSHFT (24)
#define HWIO_DDR_PI_68_RESERVED3_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_68_RESERVED3_FLDSHFT (26)

#define HWIO_DDR_PI_69_REGOFF 0x114
#define HWIO_DDR_PI_69_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_69_REGOFF)
#define HWIO_DDR_PI_69_PI_SW_WDQLVL_VREF_FLDMASK (0x7f)
#define HWIO_DDR_PI_69_PI_SW_WDQLVL_VREF_FLDSHFT (0)
#define HWIO_DDR_PI_69_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_PI_69_RESERVED_FLDSHFT (7)
#define HWIO_DDR_PI_69_PI_SWLVL_SM2_START_FLDMASK (0x100)
#define HWIO_DDR_PI_69_PI_SWLVL_SM2_START_FLDSHFT (8)
#define HWIO_DDR_PI_69_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_69_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_69_PI_SWLVL_SM2_WR_FLDMASK (0x10000)
#define HWIO_DDR_PI_69_PI_SWLVL_SM2_WR_FLDSHFT (16)
#define HWIO_DDR_PI_69_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_69_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_69_PI_SWLVL_SM2_RD_FLDMASK (0x1000000)
#define HWIO_DDR_PI_69_PI_SWLVL_SM2_RD_FLDSHFT (24)
#define HWIO_DDR_PI_69_RESERVED3_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_69_RESERVED3_FLDSHFT (25)

#define HWIO_DDR_PI_70_REGOFF 0x118
#define HWIO_DDR_PI_70_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_70_REGOFF)
#define HWIO_DDR_PI_70_PI_SEQUENTIAL_LVL_REQ_FLDMASK (0x1)
#define HWIO_DDR_PI_70_PI_SEQUENTIAL_LVL_REQ_FLDSHFT (0)
#define HWIO_DDR_PI_70_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_70_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_70_PI_DFS_PERIOD_EN_FLDMASK (0x100)
#define HWIO_DDR_PI_70_PI_DFS_PERIOD_EN_FLDSHFT (8)
#define HWIO_DDR_PI_70_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_70_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_70_PI_SRE_PERIOD_EN_FLDMASK (0x10000)
#define HWIO_DDR_PI_70_PI_SRE_PERIOD_EN_FLDSHFT (16)
#define HWIO_DDR_PI_70_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_70_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_70_PI_DFI40_POLARITY_FLDMASK (0x1000000)
#define HWIO_DDR_PI_70_PI_DFI40_POLARITY_FLDSHFT (24)
#define HWIO_DDR_PI_70_RESERVED3_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_70_RESERVED3_FLDSHFT (25)

#define HWIO_DDR_PI_71_REGOFF 0x11c
#define HWIO_DDR_PI_71_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_71_REGOFF)
#define HWIO_DDR_PI_71_PI_16BIT_DRAM_CONNECT_FLDMASK (0x1)
#define HWIO_DDR_PI_71_PI_16BIT_DRAM_CONNECT_FLDSHFT (0)
#define HWIO_DDR_PI_71_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_71_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_71_PI_TDFI_CTRL_DELAY_F0_FLDMASK (0xf00)
#define HWIO_DDR_PI_71_PI_TDFI_CTRL_DELAY_F0_FLDSHFT (8)
#define HWIO_DDR_PI_71_RESERVED1_FLDMASK (0xf000)
#define HWIO_DDR_PI_71_RESERVED1_FLDSHFT (12)
#define HWIO_DDR_PI_71_PI_TDFI_CTRL_DELAY_F1_FLDMASK (0xf0000)
#define HWIO_DDR_PI_71_PI_TDFI_CTRL_DELAY_F1_FLDSHFT (16)
#define HWIO_DDR_PI_71_RESERVED2_FLDMASK (0xf00000)
#define HWIO_DDR_PI_71_RESERVED2_FLDSHFT (20)
#define HWIO_DDR_PI_71_PI_TDFI_CTRL_DELAY_F2_FLDMASK (0xf000000)
#define HWIO_DDR_PI_71_PI_TDFI_CTRL_DELAY_F2_FLDSHFT (24)
#define HWIO_DDR_PI_71_RESERVED3_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_71_RESERVED3_FLDSHFT (28)

#define HWIO_DDR_PI_72_REGOFF 0x120
#define HWIO_DDR_PI_72_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_72_REGOFF)
#define HWIO_DDR_PI_72_PI_TDFI_CTRL_DELAY_F3_FLDMASK (0xf)
#define HWIO_DDR_PI_72_PI_TDFI_CTRL_DELAY_F3_FLDSHFT (0)
#define HWIO_DDR_PI_72_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_PI_72_RESERVED_FLDSHFT (4)
#define HWIO_DDR_PI_72_PI_WRLVL_REQ_FLDMASK (0x100)
#define HWIO_DDR_PI_72_PI_WRLVL_REQ_FLDSHFT (8)
#define HWIO_DDR_PI_72_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_72_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_72_PI_WRLVL_CS_FLDMASK (0x10000)
#define HWIO_DDR_PI_72_PI_WRLVL_CS_FLDSHFT (16)
#define HWIO_DDR_PI_72_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_72_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_72_PI_WLDQSEN_FLDMASK (0x3f000000)
#define HWIO_DDR_PI_72_PI_WLDQSEN_FLDSHFT (24)
#define HWIO_DDR_PI_72_RESERVED3_FLDMASK (0xc0000000)
#define HWIO_DDR_PI_72_RESERVED3_FLDSHFT (30)

#define HWIO_DDR_PI_73_REGOFF 0x124
#define HWIO_DDR_PI_73_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_73_REGOFF)
#define HWIO_DDR_PI_73_PI_WLMRD_FLDMASK (0x3f)
#define HWIO_DDR_PI_73_PI_WLMRD_FLDSHFT (0)
#define HWIO_DDR_PI_73_RESERVED_FLDMASK (0xc0)
#define HWIO_DDR_PI_73_RESERVED_FLDSHFT (6)
#define HWIO_DDR_PI_73_PI_WRLVL_EN_F0_FLDMASK (0x300)
#define HWIO_DDR_PI_73_PI_WRLVL_EN_F0_FLDSHFT (8)
#define HWIO_DDR_PI_73_RESERVED1_FLDMASK (0xfc00)
#define HWIO_DDR_PI_73_RESERVED1_FLDSHFT (10)
#define HWIO_DDR_PI_73_PI_WRLVL_EN_F1_FLDMASK (0x30000)
#define HWIO_DDR_PI_73_PI_WRLVL_EN_F1_FLDSHFT (16)
#define HWIO_DDR_PI_73_RESERVED2_FLDMASK (0xfc0000)
#define HWIO_DDR_PI_73_RESERVED2_FLDSHFT (18)
#define HWIO_DDR_PI_73_PI_WRLVL_EN_F2_FLDMASK (0x3000000)
#define HWIO_DDR_PI_73_PI_WRLVL_EN_F2_FLDSHFT (24)
#define HWIO_DDR_PI_73_RESERVED3_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_73_RESERVED3_FLDSHFT (26)

#define HWIO_DDR_PI_74_REGOFF 0x128
#define HWIO_DDR_PI_74_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_74_REGOFF)
#define HWIO_DDR_PI_74_PI_WRLVL_EN_F3_FLDMASK (0x3)
#define HWIO_DDR_PI_74_PI_WRLVL_EN_F3_FLDSHFT (0)
#define HWIO_DDR_PI_74_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_74_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_74_PI_WRLVL_INTERVAL_FLDMASK (0xffff00)
#define HWIO_DDR_PI_74_PI_WRLVL_INTERVAL_FLDSHFT (8)
#define HWIO_DDR_PI_74_PI_WRLVL_PERIODIC_FLDMASK (0x1000000)
#define HWIO_DDR_PI_74_PI_WRLVL_PERIODIC_FLDSHFT (24)
#define HWIO_DDR_PI_74_RESERVED1_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_74_RESERVED1_FLDSHFT (25)

#define HWIO_DDR_PI_75_REGOFF 0x12c
#define HWIO_DDR_PI_75_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_75_REGOFF)
#define HWIO_DDR_PI_75_PI_WRLVL_ON_SREF_EXIT_FLDMASK (0x1)
#define HWIO_DDR_PI_75_PI_WRLVL_ON_SREF_EXIT_FLDSHFT (0)
#define HWIO_DDR_PI_75_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_75_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_75_PI_WRLVL_DISABLE_DFS_FLDMASK (0x100)
#define HWIO_DDR_PI_75_PI_WRLVL_DISABLE_DFS_FLDSHFT (8)
#define HWIO_DDR_PI_75_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_75_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_75_PI_WRLVL_RESP_MASK_FLDMASK (0xf0000)
#define HWIO_DDR_PI_75_PI_WRLVL_RESP_MASK_FLDSHFT (16)
#define HWIO_DDR_PI_75_RESERVED2_FLDMASK (0xf00000)
#define HWIO_DDR_PI_75_RESERVED2_FLDSHFT (20)
#define HWIO_DDR_PI_75_PI_WRLVL_ROTATE_FLDMASK (0x1000000)
#define HWIO_DDR_PI_75_PI_WRLVL_ROTATE_FLDSHFT (24)
#define HWIO_DDR_PI_75_RESERVED3_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_75_RESERVED3_FLDSHFT (25)

#define HWIO_DDR_PI_76_REGOFF 0x130
#define HWIO_DDR_PI_76_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_76_REGOFF)
#define HWIO_DDR_PI_76_PI_WRLVL_CS_MAP_FLDMASK (0x3)
#define HWIO_DDR_PI_76_PI_WRLVL_CS_MAP_FLDSHFT (0)
#define HWIO_DDR_PI_76_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_76_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_76_PI_WRLVL_ERROR_STATUS_FLDMASK (0x300)
#define HWIO_DDR_PI_76_PI_WRLVL_ERROR_STATUS_FLDSHFT (8)
#define HWIO_DDR_PI_76_RESERVED1_FLDMASK (0xfc00)
#define HWIO_DDR_PI_76_RESERVED1_FLDSHFT (10)
#define HWIO_DDR_PI_76_PI_TDFI_WRLVL_EN_FLDMASK (0xff0000)
#define HWIO_DDR_PI_76_PI_TDFI_WRLVL_EN_FLDSHFT (16)
#define HWIO_DDR_PI_76_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_PI_76_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_PI_77_REGOFF 0x134
#define HWIO_DDR_PI_77_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_77_REGOFF)
#define HWIO_DDR_PI_77_PI_TDFI_WRLVL_WW_FLDMASK (0x3ff)
#define HWIO_DDR_PI_77_PI_TDFI_WRLVL_WW_FLDSHFT (0)
#define HWIO_DDR_PI_77_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_77_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_77_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_77_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_78_REGOFF 0x138
#define HWIO_DDR_PI_78_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_78_REGOFF)
#define HWIO_DDR_PI_78_PI_TDFI_WRLVL_RESP_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_78_PI_TDFI_WRLVL_RESP_FLDSHFT (0)

#define HWIO_DDR_PI_79_REGOFF 0x13c
#define HWIO_DDR_PI_79_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_79_REGOFF)
#define HWIO_DDR_PI_79_PI_TDFI_WRLVL_MAX_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_79_PI_TDFI_WRLVL_MAX_FLDSHFT (0)

#define HWIO_DDR_PI_80_REGOFF 0x140
#define HWIO_DDR_PI_80_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_80_REGOFF)
#define HWIO_DDR_PI_80_PI_WRLVL_STROBE_NUM_FLDMASK (0x1f)
#define HWIO_DDR_PI_80_PI_WRLVL_STROBE_NUM_FLDSHFT (0)
#define HWIO_DDR_PI_80_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_PI_80_RESERVED_FLDSHFT (5)
#define HWIO_DDR_PI_80_RESERVED1_FLDMASK (0x100)
#define HWIO_DDR_PI_80_RESERVED1_FLDSHFT (8)
#define HWIO_DDR_PI_80_RESERVED3_FLDMASK (0xfe00)
#define HWIO_DDR_PI_80_RESERVED3_FLDSHFT (9)
#define HWIO_DDR_PI_80_RESERVED2_FLDMASK (0x1f0000)
#define HWIO_DDR_PI_80_RESERVED2_FLDSHFT (16)
#define HWIO_DDR_PI_80_RESERVED4_FLDMASK (0xe00000)
#define HWIO_DDR_PI_80_RESERVED4_FLDSHFT (21)
#define HWIO_DDR_PI_80_PI_TODTL_2CMD_F0_FLDMASK (0xff000000)
#define HWIO_DDR_PI_80_PI_TODTL_2CMD_F0_FLDSHFT (24)

#define HWIO_DDR_PI_81_REGOFF 0x144
#define HWIO_DDR_PI_81_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_81_REGOFF)
#define HWIO_DDR_PI_81_PI_ODT_EN_F0_FLDMASK (0x1)
#define HWIO_DDR_PI_81_PI_ODT_EN_F0_FLDSHFT (0)
#define HWIO_DDR_PI_81_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_81_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_81_PI_TODTL_2CMD_F1_FLDMASK (0xff00)
#define HWIO_DDR_PI_81_PI_TODTL_2CMD_F1_FLDSHFT (8)
#define HWIO_DDR_PI_81_PI_ODT_EN_F1_FLDMASK (0x10000)
#define HWIO_DDR_PI_81_PI_ODT_EN_F1_FLDSHFT (16)
#define HWIO_DDR_PI_81_RESERVED1_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_81_RESERVED1_FLDSHFT (17)
#define HWIO_DDR_PI_81_PI_TODTL_2CMD_F2_FLDMASK (0xff000000)
#define HWIO_DDR_PI_81_PI_TODTL_2CMD_F2_FLDSHFT (24)

#define HWIO_DDR_PI_82_REGOFF 0x148
#define HWIO_DDR_PI_82_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_82_REGOFF)
#define HWIO_DDR_PI_82_PI_ODT_EN_F2_FLDMASK (0x1)
#define HWIO_DDR_PI_82_PI_ODT_EN_F2_FLDSHFT (0)
#define HWIO_DDR_PI_82_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_82_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_82_PI_TODTL_2CMD_F3_FLDMASK (0xff00)
#define HWIO_DDR_PI_82_PI_TODTL_2CMD_F3_FLDSHFT (8)
#define HWIO_DDR_PI_82_PI_ODT_EN_F3_FLDMASK (0x10000)
#define HWIO_DDR_PI_82_PI_ODT_EN_F3_FLDSHFT (16)
#define HWIO_DDR_PI_82_RESERVED1_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_82_RESERVED1_FLDSHFT (17)
#define HWIO_DDR_PI_82_PI_TODTH_WR_FLDMASK (0xf000000)
#define HWIO_DDR_PI_82_PI_TODTH_WR_FLDSHFT (24)
#define HWIO_DDR_PI_82_RESERVED2_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_82_RESERVED2_FLDSHFT (28)

#define HWIO_DDR_PI_83_REGOFF 0x14c
#define HWIO_DDR_PI_83_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_83_REGOFF)
#define HWIO_DDR_PI_83_PI_TODTH_RD_FLDMASK (0xf)
#define HWIO_DDR_PI_83_PI_TODTH_RD_FLDSHFT (0)
#define HWIO_DDR_PI_83_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_PI_83_RESERVED_FLDSHFT (4)
#define HWIO_DDR_PI_83_PI_ODT_RD_MAP_CS0_FLDMASK (0x300)
#define HWIO_DDR_PI_83_PI_ODT_RD_MAP_CS0_FLDSHFT (8)
#define HWIO_DDR_PI_83_RESERVED1_FLDMASK (0xfc00)
#define HWIO_DDR_PI_83_RESERVED1_FLDSHFT (10)
#define HWIO_DDR_PI_83_PI_ODT_WR_MAP_CS0_FLDMASK (0x30000)
#define HWIO_DDR_PI_83_PI_ODT_WR_MAP_CS0_FLDSHFT (16)
#define HWIO_DDR_PI_83_RESERVED2_FLDMASK (0xfc0000)
#define HWIO_DDR_PI_83_RESERVED2_FLDSHFT (18)
#define HWIO_DDR_PI_83_PI_ODT_RD_MAP_CS1_FLDMASK (0x3000000)
#define HWIO_DDR_PI_83_PI_ODT_RD_MAP_CS1_FLDSHFT (24)
#define HWIO_DDR_PI_83_RESERVED3_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_83_RESERVED3_FLDSHFT (26)

#define HWIO_DDR_PI_84_REGOFF 0x150
#define HWIO_DDR_PI_84_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_84_REGOFF)
#define HWIO_DDR_PI_84_PI_ODT_WR_MAP_CS1_FLDMASK (0x3)
#define HWIO_DDR_PI_84_PI_ODT_WR_MAP_CS1_FLDSHFT (0)
#define HWIO_DDR_PI_84_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_84_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_84_PI_EN_ODT_ASSERT_EXCEPT_RD_FLDMASK (0x100)
#define HWIO_DDR_PI_84_PI_EN_ODT_ASSERT_EXCEPT_RD_FLDSHFT (8)
#define HWIO_DDR_PI_84_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_84_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_84_PI_WR_TO_ODTH_F0_FLDMASK (0x3f0000)
#define HWIO_DDR_PI_84_PI_WR_TO_ODTH_F0_FLDSHFT (16)
#define HWIO_DDR_PI_84_RESERVED2_FLDMASK (0xc00000)
#define HWIO_DDR_PI_84_RESERVED2_FLDSHFT (22)
#define HWIO_DDR_PI_84_PI_WR_TO_ODTH_F1_FLDMASK (0x3f000000)
#define HWIO_DDR_PI_84_PI_WR_TO_ODTH_F1_FLDSHFT (24)
#define HWIO_DDR_PI_84_RESERVED3_FLDMASK (0xc0000000)
#define HWIO_DDR_PI_84_RESERVED3_FLDSHFT (30)

#define HWIO_DDR_PI_85_REGOFF 0x154
#define HWIO_DDR_PI_85_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_85_REGOFF)
#define HWIO_DDR_PI_85_PI_WR_TO_ODTH_F2_FLDMASK (0x3f)
#define HWIO_DDR_PI_85_PI_WR_TO_ODTH_F2_FLDSHFT (0)
#define HWIO_DDR_PI_85_RESERVED_FLDMASK (0xc0)
#define HWIO_DDR_PI_85_RESERVED_FLDSHFT (6)
#define HWIO_DDR_PI_85_PI_WR_TO_ODTH_F3_FLDMASK (0x3f00)
#define HWIO_DDR_PI_85_PI_WR_TO_ODTH_F3_FLDSHFT (8)
#define HWIO_DDR_PI_85_RESERVED1_FLDMASK (0xc000)
#define HWIO_DDR_PI_85_RESERVED1_FLDSHFT (14)
#define HWIO_DDR_PI_85_PI_RD_TO_ODTH_F0_FLDMASK (0x3f0000)
#define HWIO_DDR_PI_85_PI_RD_TO_ODTH_F0_FLDSHFT (16)
#define HWIO_DDR_PI_85_RESERVED2_FLDMASK (0xc00000)
#define HWIO_DDR_PI_85_RESERVED2_FLDSHFT (22)
#define HWIO_DDR_PI_85_PI_RD_TO_ODTH_F1_FLDMASK (0x3f000000)
#define HWIO_DDR_PI_85_PI_RD_TO_ODTH_F1_FLDSHFT (24)
#define HWIO_DDR_PI_85_RESERVED3_FLDMASK (0xc0000000)
#define HWIO_DDR_PI_85_RESERVED3_FLDSHFT (30)

#define HWIO_DDR_PI_86_REGOFF 0x158
#define HWIO_DDR_PI_86_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_86_REGOFF)
#define HWIO_DDR_PI_86_PI_RD_TO_ODTH_F2_FLDMASK (0x3f)
#define HWIO_DDR_PI_86_PI_RD_TO_ODTH_F2_FLDSHFT (0)
#define HWIO_DDR_PI_86_RESERVED_FLDMASK (0xc0)
#define HWIO_DDR_PI_86_RESERVED_FLDSHFT (6)
#define HWIO_DDR_PI_86_PI_RD_TO_ODTH_F3_FLDMASK (0x3f00)
#define HWIO_DDR_PI_86_PI_RD_TO_ODTH_F3_FLDSHFT (8)
#define HWIO_DDR_PI_86_RESERVED1_FLDMASK (0xc000)
#define HWIO_DDR_PI_86_RESERVED1_FLDSHFT (14)
#define HWIO_DDR_PI_86_PI_RDLVL_REQ_FLDMASK (0x10000)
#define HWIO_DDR_PI_86_PI_RDLVL_REQ_FLDSHFT (16)
#define HWIO_DDR_PI_86_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_86_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_86_PI_RDLVL_GATE_REQ_FLDMASK (0x1000000)
#define HWIO_DDR_PI_86_PI_RDLVL_GATE_REQ_FLDSHFT (24)
#define HWIO_DDR_PI_86_RESERVED3_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_86_RESERVED3_FLDSHFT (25)

#define HWIO_DDR_PI_87_REGOFF 0x15c
#define HWIO_DDR_PI_87_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_87_REGOFF)
#define HWIO_DDR_PI_87_PI_RDLVL_CS_FLDMASK (0x1)
#define HWIO_DDR_PI_87_PI_RDLVL_CS_FLDSHFT (0)
#define HWIO_DDR_PI_87_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_87_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_87_PI_RDLVL_SEQ_EN_FLDMASK (0xf00)
#define HWIO_DDR_PI_87_PI_RDLVL_SEQ_EN_FLDSHFT (8)
#define HWIO_DDR_PI_87_RESERVED1_FLDMASK (0xf000)
#define HWIO_DDR_PI_87_RESERVED1_FLDSHFT (12)
#define HWIO_DDR_PI_87_PI_RDLVL_GATE_SEQ_EN_FLDMASK (0xf0000)
#define HWIO_DDR_PI_87_PI_RDLVL_GATE_SEQ_EN_FLDSHFT (16)
#define HWIO_DDR_PI_87_RESERVED2_FLDMASK (0xf00000)
#define HWIO_DDR_PI_87_RESERVED2_FLDSHFT (20)
#define HWIO_DDR_PI_87_PI_RDLVL_PERIODIC_FLDMASK (0x1000000)
#define HWIO_DDR_PI_87_PI_RDLVL_PERIODIC_FLDSHFT (24)
#define HWIO_DDR_PI_87_RESERVED3_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_87_RESERVED3_FLDSHFT (25)

#define HWIO_DDR_PI_88_REGOFF 0x160
#define HWIO_DDR_PI_88_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_88_REGOFF)
#define HWIO_DDR_PI_88_PI_RDLVL_ON_SREF_EXIT_FLDMASK (0x1)
#define HWIO_DDR_PI_88_PI_RDLVL_ON_SREF_EXIT_FLDSHFT (0)
#define HWIO_DDR_PI_88_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_88_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_88_PI_RDLVL_DISABLE_DFS_FLDMASK (0x100)
#define HWIO_DDR_PI_88_PI_RDLVL_DISABLE_DFS_FLDSHFT (8)
#define HWIO_DDR_PI_88_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_88_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_88_PI_RDLVL_GATE_PERIODIC_FLDMASK (0x10000)
#define HWIO_DDR_PI_88_PI_RDLVL_GATE_PERIODIC_FLDSHFT (16)
#define HWIO_DDR_PI_88_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_88_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_88_PI_RDLVL_GATE_ON_SREF_EXIT_FLDMASK (0x1000000)
#define HWIO_DDR_PI_88_PI_RDLVL_GATE_ON_SREF_EXIT_FLDSHFT (24)
#define HWIO_DDR_PI_88_RESERVED3_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_88_RESERVED3_FLDSHFT (25)

#define HWIO_DDR_PI_89_REGOFF 0x164
#define HWIO_DDR_PI_89_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_89_REGOFF)
#define HWIO_DDR_PI_89_PI_RDLVL_GATE_DISABLE_DFS_FLDMASK (0x1)
#define HWIO_DDR_PI_89_PI_RDLVL_GATE_DISABLE_DFS_FLDSHFT (0)
#define HWIO_DDR_PI_89_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_89_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_89_RESERVED1_FLDMASK (0x100)
#define HWIO_DDR_PI_89_RESERVED1_FLDSHFT (8)
#define HWIO_DDR_PI_89_RESERVED2_FLDMASK (0xfe00)
#define HWIO_DDR_PI_89_RESERVED2_FLDSHFT (9)
#define HWIO_DDR_PI_89_PI_RDLVL_ROTATE_FLDMASK (0x10000)
#define HWIO_DDR_PI_89_PI_RDLVL_ROTATE_FLDSHFT (16)
#define HWIO_DDR_PI_89_RESERVED3_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_89_RESERVED3_FLDSHFT (17)
#define HWIO_DDR_PI_89_PI_RDLVL_GATE_ROTATE_FLDMASK (0x1000000)
#define HWIO_DDR_PI_89_PI_RDLVL_GATE_ROTATE_FLDSHFT (24)
#define HWIO_DDR_PI_89_RESERVED4_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_89_RESERVED4_FLDSHFT (25)

#define HWIO_DDR_PI_90_REGOFF 0x168
#define HWIO_DDR_PI_90_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_90_REGOFF)
#define HWIO_DDR_PI_90_PI_RDLVL_CS_MAP_FLDMASK (0x3)
#define HWIO_DDR_PI_90_PI_RDLVL_CS_MAP_FLDSHFT (0)
#define HWIO_DDR_PI_90_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_90_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_90_PI_RDLVL_GATE_CS_MAP_FLDMASK (0x300)
#define HWIO_DDR_PI_90_PI_RDLVL_GATE_CS_MAP_FLDSHFT (8)
#define HWIO_DDR_PI_90_RESERVED1_FLDMASK (0xfc00)
#define HWIO_DDR_PI_90_RESERVED1_FLDSHFT (10)
#define HWIO_DDR_PI_90_PI_TDFI_RDLVL_RR_FLDMASK (0x3ff0000)
#define HWIO_DDR_PI_90_PI_TDFI_RDLVL_RR_FLDSHFT (16)
#define HWIO_DDR_PI_90_RESERVED2_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_90_RESERVED2_FLDSHFT (26)

#define HWIO_DDR_PI_91_REGOFF 0x16c
#define HWIO_DDR_PI_91_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_91_REGOFF)
#define HWIO_DDR_PI_91_PI_TDFI_RDLVL_RESP_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_91_PI_TDFI_RDLVL_RESP_FLDSHFT (0)

#define HWIO_DDR_PI_92_REGOFF 0x170
#define HWIO_DDR_PI_92_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_92_REGOFF)
#define HWIO_DDR_PI_92_PI_RDLVL_RESP_MASK_FLDMASK (0xf)
#define HWIO_DDR_PI_92_PI_RDLVL_RESP_MASK_FLDSHFT (0)
#define HWIO_DDR_PI_92_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_PI_92_RESERVED_FLDSHFT (4)
#define HWIO_DDR_PI_92_PI_TDFI_RDLVL_EN_FLDMASK (0xff00)
#define HWIO_DDR_PI_92_PI_TDFI_RDLVL_EN_FLDSHFT (8)
#define HWIO_DDR_PI_92_PI_RDLVL_EN_F0_FLDMASK (0x30000)
#define HWIO_DDR_PI_92_PI_RDLVL_EN_F0_FLDSHFT (16)
#define HWIO_DDR_PI_92_RESERVED1_FLDMASK (0xfc0000)
#define HWIO_DDR_PI_92_RESERVED1_FLDSHFT (18)
#define HWIO_DDR_PI_92_PI_RDLVL_GATE_EN_F0_FLDMASK (0x3000000)
#define HWIO_DDR_PI_92_PI_RDLVL_GATE_EN_F0_FLDSHFT (24)
#define HWIO_DDR_PI_92_RESERVED2_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_92_RESERVED2_FLDSHFT (26)

#define HWIO_DDR_PI_93_REGOFF 0x174
#define HWIO_DDR_PI_93_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_93_REGOFF)
#define HWIO_DDR_PI_93_PI_RDLVL_EN_F1_FLDMASK (0x3)
#define HWIO_DDR_PI_93_PI_RDLVL_EN_F1_FLDSHFT (0)
#define HWIO_DDR_PI_93_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_93_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_93_PI_RDLVL_GATE_EN_F1_FLDMASK (0x300)
#define HWIO_DDR_PI_93_PI_RDLVL_GATE_EN_F1_FLDSHFT (8)
#define HWIO_DDR_PI_93_RESERVED1_FLDMASK (0xfc00)
#define HWIO_DDR_PI_93_RESERVED1_FLDSHFT (10)
#define HWIO_DDR_PI_93_PI_RDLVL_EN_F2_FLDMASK (0x30000)
#define HWIO_DDR_PI_93_PI_RDLVL_EN_F2_FLDSHFT (16)
#define HWIO_DDR_PI_93_RESERVED2_FLDMASK (0xfc0000)
#define HWIO_DDR_PI_93_RESERVED2_FLDSHFT (18)
#define HWIO_DDR_PI_93_PI_RDLVL_GATE_EN_F2_FLDMASK (0x3000000)
#define HWIO_DDR_PI_93_PI_RDLVL_GATE_EN_F2_FLDSHFT (24)
#define HWIO_DDR_PI_93_RESERVED3_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_93_RESERVED3_FLDSHFT (26)

#define HWIO_DDR_PI_94_REGOFF 0x178
#define HWIO_DDR_PI_94_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_94_REGOFF)
#define HWIO_DDR_PI_94_PI_RDLVL_EN_F3_FLDMASK (0x3)
#define HWIO_DDR_PI_94_PI_RDLVL_EN_F3_FLDSHFT (0)
#define HWIO_DDR_PI_94_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_94_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_94_PI_RDLVL_GATE_EN_F3_FLDMASK (0x300)
#define HWIO_DDR_PI_94_PI_RDLVL_GATE_EN_F3_FLDSHFT (8)
#define HWIO_DDR_PI_94_RESERVED1_FLDMASK (0xfc00)
#define HWIO_DDR_PI_94_RESERVED1_FLDSHFT (10)
#define HWIO_DDR_PI_94_OBSOLETE2_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_94_OBSOLETE2_FLDSHFT (16)

#define HWIO_DDR_PI_95_REGOFF 0x17c
#define HWIO_DDR_PI_95_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_95_REGOFF)
#define HWIO_DDR_PI_95_PI_TDFI_RDLVL_MAX_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_95_PI_TDFI_RDLVL_MAX_FLDSHFT (0)

#define HWIO_DDR_PI_96_REGOFF 0x180
#define HWIO_DDR_PI_96_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_96_REGOFF)
#define HWIO_DDR_PI_96_PI_RDLVL_ERROR_STATUS_FLDMASK (0x3)
#define HWIO_DDR_PI_96_PI_RDLVL_ERROR_STATUS_FLDSHFT (0)
#define HWIO_DDR_PI_96_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_96_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_96_PI_RDLVL_INTERVAL_FLDMASK (0xffff00)
#define HWIO_DDR_PI_96_PI_RDLVL_INTERVAL_FLDSHFT (8)
#define HWIO_DDR_PI_96_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_PI_96_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_PI_97_REGOFF 0x184
#define HWIO_DDR_PI_97_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_97_REGOFF)
#define HWIO_DDR_PI_97_PI_RDLVL_GATE_INTERVAL_FLDMASK (0xffff)
#define HWIO_DDR_PI_97_PI_RDLVL_GATE_INTERVAL_FLDSHFT (0)
#define HWIO_DDR_PI_97_PI_RDLVL_PATTERN_START_FLDMASK (0xf0000)
#define HWIO_DDR_PI_97_PI_RDLVL_PATTERN_START_FLDSHFT (16)
#define HWIO_DDR_PI_97_RESERVED_FLDMASK (0xf00000)
#define HWIO_DDR_PI_97_RESERVED_FLDSHFT (20)
#define HWIO_DDR_PI_97_PI_RDLVL_PATTERN_NUM_FLDMASK (0xf000000)
#define HWIO_DDR_PI_97_PI_RDLVL_PATTERN_NUM_FLDSHFT (24)
#define HWIO_DDR_PI_97_RESERVED1_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_97_RESERVED1_FLDSHFT (28)

#define HWIO_DDR_PI_98_REGOFF 0x188
#define HWIO_DDR_PI_98_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_98_REGOFF)
#define HWIO_DDR_PI_98_PI_RDLVL_STROBE_NUM_FLDMASK (0x1f)
#define HWIO_DDR_PI_98_PI_RDLVL_STROBE_NUM_FLDSHFT (0)
#define HWIO_DDR_PI_98_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_PI_98_RESERVED_FLDSHFT (5)
#define HWIO_DDR_PI_98_PI_RDLVL_GATE_STROBE_NUM_FLDMASK (0x1f00)
#define HWIO_DDR_PI_98_PI_RDLVL_GATE_STROBE_NUM_FLDSHFT (8)
#define HWIO_DDR_PI_98_RESERVED1_FLDMASK (0xe000)
#define HWIO_DDR_PI_98_RESERVED1_FLDSHFT (13)
#define HWIO_DDR_PI_98_OBSOLETE2_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_98_OBSOLETE2_FLDSHFT (16)

#define HWIO_DDR_PI_99_REGOFF 0x18c
#define HWIO_DDR_PI_99_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_99_REGOFF)
#define HWIO_DDR_PI_99_PI_LPDDR4_RDLVL_PATTERN_8_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_99_PI_LPDDR4_RDLVL_PATTERN_8_FLDSHFT (0)

#define HWIO_DDR_PI_100_REGOFF 0x190
#define HWIO_DDR_PI_100_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_100_REGOFF)
#define HWIO_DDR_PI_100_PI_LPDDR4_RDLVL_PATTERN_9_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_100_PI_LPDDR4_RDLVL_PATTERN_9_FLDSHFT (0)

#define HWIO_DDR_PI_101_REGOFF 0x194
#define HWIO_DDR_PI_101_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_101_REGOFF)
#define HWIO_DDR_PI_101_PI_LPDDR4_RDLVL_PATTERN_10_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_101_PI_LPDDR4_RDLVL_PATTERN_10_FLDSHFT (0)

#define HWIO_DDR_PI_102_REGOFF 0x198
#define HWIO_DDR_PI_102_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_102_REGOFF)
#define HWIO_DDR_PI_102_PI_LPDDR4_RDLVL_PATTERN_11_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_102_PI_LPDDR4_RDLVL_PATTERN_11_FLDSHFT (0)

#define HWIO_DDR_PI_103_REGOFF 0x19c
#define HWIO_DDR_PI_103_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_103_REGOFF)
#define HWIO_DDR_PI_103_PI_RD_PREAMBLE_TRAINING_EN_FLDMASK (0x1)
#define HWIO_DDR_PI_103_PI_RD_PREAMBLE_TRAINING_EN_FLDSHFT (0)
#define HWIO_DDR_PI_103_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_103_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_103_PI_REG_DIMM_ENABLE_FLDMASK (0x100)
#define HWIO_DDR_PI_103_PI_REG_DIMM_ENABLE_FLDSHFT (8)
#define HWIO_DDR_PI_103_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_103_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_103_PI_RDLAT_ADJ_F0_FLDMASK (0x7f0000)
#define HWIO_DDR_PI_103_PI_RDLAT_ADJ_F0_FLDSHFT (16)
#define HWIO_DDR_PI_103_RESERVED2_FLDMASK (0x800000)
#define HWIO_DDR_PI_103_RESERVED2_FLDSHFT (23)
#define HWIO_DDR_PI_103_PI_RDLAT_ADJ_F1_FLDMASK (0x7f000000)
#define HWIO_DDR_PI_103_PI_RDLAT_ADJ_F1_FLDSHFT (24)
#define HWIO_DDR_PI_103_RESERVED3_FLDMASK (0x80000000)
#define HWIO_DDR_PI_103_RESERVED3_FLDSHFT (31)

#define HWIO_DDR_PI_104_REGOFF 0x1a0
#define HWIO_DDR_PI_104_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_104_REGOFF)
#define HWIO_DDR_PI_104_PI_RDLAT_ADJ_F2_FLDMASK (0x7f)
#define HWIO_DDR_PI_104_PI_RDLAT_ADJ_F2_FLDSHFT (0)
#define HWIO_DDR_PI_104_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_PI_104_RESERVED_FLDSHFT (7)
#define HWIO_DDR_PI_104_PI_RDLAT_ADJ_F3_FLDMASK (0x7f00)
#define HWIO_DDR_PI_104_PI_RDLAT_ADJ_F3_FLDSHFT (8)
#define HWIO_DDR_PI_104_RESERVED1_FLDMASK (0x8000)
#define HWIO_DDR_PI_104_RESERVED1_FLDSHFT (15)
#define HWIO_DDR_PI_104_PI_TDFI_RDDATA_EN_FLDMASK (0x7f0000)
#define HWIO_DDR_PI_104_PI_TDFI_RDDATA_EN_FLDSHFT (16)
#define HWIO_DDR_PI_104_RESERVED2_FLDMASK (0x800000)
#define HWIO_DDR_PI_104_RESERVED2_FLDSHFT (23)
#define HWIO_DDR_PI_104_PI_WRLAT_ADJ_F0_FLDMASK (0x7f000000)
#define HWIO_DDR_PI_104_PI_WRLAT_ADJ_F0_FLDSHFT (24)
#define HWIO_DDR_PI_104_RESERVED3_FLDMASK (0x80000000)
#define HWIO_DDR_PI_104_RESERVED3_FLDSHFT (31)

#define HWIO_DDR_PI_105_REGOFF 0x1a4
#define HWIO_DDR_PI_105_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_105_REGOFF)
#define HWIO_DDR_PI_105_PI_WRLAT_ADJ_F1_FLDMASK (0x7f)
#define HWIO_DDR_PI_105_PI_WRLAT_ADJ_F1_FLDSHFT (0)
#define HWIO_DDR_PI_105_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_PI_105_RESERVED_FLDSHFT (7)
#define HWIO_DDR_PI_105_PI_WRLAT_ADJ_F2_FLDMASK (0x7f00)
#define HWIO_DDR_PI_105_PI_WRLAT_ADJ_F2_FLDSHFT (8)
#define HWIO_DDR_PI_105_RESERVED1_FLDMASK (0x8000)
#define HWIO_DDR_PI_105_RESERVED1_FLDSHFT (15)
#define HWIO_DDR_PI_105_PI_WRLAT_ADJ_F3_FLDMASK (0x7f0000)
#define HWIO_DDR_PI_105_PI_WRLAT_ADJ_F3_FLDSHFT (16)
#define HWIO_DDR_PI_105_RESERVED2_FLDMASK (0x800000)
#define HWIO_DDR_PI_105_RESERVED2_FLDSHFT (23)
#define HWIO_DDR_PI_105_PI_TDFI_PHY_WRLAT_FLDMASK (0x7f000000)
#define HWIO_DDR_PI_105_PI_TDFI_PHY_WRLAT_FLDSHFT (24)
#define HWIO_DDR_PI_105_RESERVED3_FLDMASK (0x80000000)
#define HWIO_DDR_PI_105_RESERVED3_FLDSHFT (31)

#define HWIO_DDR_PI_106_REGOFF 0x1a8
#define HWIO_DDR_PI_106_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_106_REGOFF)
#define HWIO_DDR_PI_106_PI_TDFI_RDCSLAT_F0_FLDMASK (0x7f)
#define HWIO_DDR_PI_106_PI_TDFI_RDCSLAT_F0_FLDSHFT (0)
#define HWIO_DDR_PI_106_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_PI_106_RESERVED_FLDSHFT (7)
#define HWIO_DDR_PI_106_PI_TDFI_RDCSLAT_F1_FLDMASK (0x7f00)
#define HWIO_DDR_PI_106_PI_TDFI_RDCSLAT_F1_FLDSHFT (8)
#define HWIO_DDR_PI_106_RESERVED1_FLDMASK (0x8000)
#define HWIO_DDR_PI_106_RESERVED1_FLDSHFT (15)
#define HWIO_DDR_PI_106_PI_TDFI_RDCSLAT_F2_FLDMASK (0x7f0000)
#define HWIO_DDR_PI_106_PI_TDFI_RDCSLAT_F2_FLDSHFT (16)
#define HWIO_DDR_PI_106_RESERVED2_FLDMASK (0x800000)
#define HWIO_DDR_PI_106_RESERVED2_FLDSHFT (23)
#define HWIO_DDR_PI_106_PI_TDFI_RDCSLAT_F3_FLDMASK (0x7f000000)
#define HWIO_DDR_PI_106_PI_TDFI_RDCSLAT_F3_FLDSHFT (24)
#define HWIO_DDR_PI_106_RESERVED3_FLDMASK (0x80000000)
#define HWIO_DDR_PI_106_RESERVED3_FLDSHFT (31)

#define HWIO_DDR_PI_107_REGOFF 0x1ac
#define HWIO_DDR_PI_107_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_107_REGOFF)
#define HWIO_DDR_PI_107_PI_TDFI_PHY_WRDATA_F0_FLDMASK (0x7)
#define HWIO_DDR_PI_107_PI_TDFI_PHY_WRDATA_F0_FLDSHFT (0)
#define HWIO_DDR_PI_107_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_PI_107_RESERVED_FLDSHFT (3)
#define HWIO_DDR_PI_107_PI_TDFI_PHY_WRDATA_F1_FLDMASK (0x700)
#define HWIO_DDR_PI_107_PI_TDFI_PHY_WRDATA_F1_FLDSHFT (8)
#define HWIO_DDR_PI_107_RESERVED1_FLDMASK (0xf800)
#define HWIO_DDR_PI_107_RESERVED1_FLDSHFT (11)
#define HWIO_DDR_PI_107_PI_TDFI_PHY_WRDATA_F2_FLDMASK (0x70000)
#define HWIO_DDR_PI_107_PI_TDFI_PHY_WRDATA_F2_FLDSHFT (16)
#define HWIO_DDR_PI_107_RESERVED2_FLDMASK (0xf80000)
#define HWIO_DDR_PI_107_RESERVED2_FLDSHFT (19)
#define HWIO_DDR_PI_107_PI_TDFI_PHY_WRDATA_F3_FLDMASK (0x7000000)
#define HWIO_DDR_PI_107_PI_TDFI_PHY_WRDATA_F3_FLDSHFT (24)
#define HWIO_DDR_PI_107_RESERVED3_FLDMASK (0xf8000000)
#define HWIO_DDR_PI_107_RESERVED3_FLDSHFT (27)

#define HWIO_DDR_PI_108_REGOFF 0x1b0
#define HWIO_DDR_PI_108_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_108_REGOFF)
#define HWIO_DDR_PI_108_PI_CALVL_REQ_FLDMASK (0x1)
#define HWIO_DDR_PI_108_PI_CALVL_REQ_FLDSHFT (0)
#define HWIO_DDR_PI_108_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_108_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_108_PI_CALVL_CS_FLDMASK (0x100)
#define HWIO_DDR_PI_108_PI_CALVL_CS_FLDSHFT (8)
#define HWIO_DDR_PI_108_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_108_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_108_RESERVED2_FLDMASK (0x10000)
#define HWIO_DDR_PI_108_RESERVED2_FLDSHFT (16)
#define HWIO_DDR_PI_108_RESERVED4_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_108_RESERVED4_FLDSHFT (17)
#define HWIO_DDR_PI_108_RESERVED3_FLDMASK (0xf000000)
#define HWIO_DDR_PI_108_RESERVED3_FLDSHFT (24)
#define HWIO_DDR_PI_108_RESERVED5_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_108_RESERVED5_FLDSHFT (28)

#define HWIO_DDR_PI_109_REGOFF 0x1b4
#define HWIO_DDR_PI_109_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_109_REGOFF)
#define HWIO_DDR_PI_109_PI_CALVL_SEQ_EN_FLDMASK (0x3)
#define HWIO_DDR_PI_109_PI_CALVL_SEQ_EN_FLDSHFT (0)
#define HWIO_DDR_PI_109_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_109_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_109_PI_CALVL_PERIODIC_FLDMASK (0x100)
#define HWIO_DDR_PI_109_PI_CALVL_PERIODIC_FLDSHFT (8)
#define HWIO_DDR_PI_109_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_109_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_109_PI_CALVL_ON_SREF_EXIT_FLDMASK (0x10000)
#define HWIO_DDR_PI_109_PI_CALVL_ON_SREF_EXIT_FLDSHFT (16)
#define HWIO_DDR_PI_109_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_109_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_109_PI_CALVL_DISABLE_DFS_FLDMASK (0x1000000)
#define HWIO_DDR_PI_109_PI_CALVL_DISABLE_DFS_FLDSHFT (24)
#define HWIO_DDR_PI_109_RESERVED3_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_109_RESERVED3_FLDSHFT (25)

#define HWIO_DDR_PI_110_REGOFF 0x1b8
#define HWIO_DDR_PI_110_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_110_REGOFF)
#define HWIO_DDR_PI_110_PI_CALVL_ROTATE_FLDMASK (0x1)
#define HWIO_DDR_PI_110_PI_CALVL_ROTATE_FLDSHFT (0)
#define HWIO_DDR_PI_110_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_110_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_110_PI_CALVL_CS_MAP_FLDMASK (0x300)
#define HWIO_DDR_PI_110_PI_CALVL_CS_MAP_FLDSHFT (8)
#define HWIO_DDR_PI_110_RESERVED1_FLDMASK (0xfc00)
#define HWIO_DDR_PI_110_RESERVED1_FLDSHFT (10)
#define HWIO_DDR_PI_110_PI_TDFI_CALVL_EN_FLDMASK (0xff0000)
#define HWIO_DDR_PI_110_PI_TDFI_CALVL_EN_FLDSHFT (16)
#define HWIO_DDR_PI_110_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_PI_110_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_PI_111_REGOFF 0x1bc
#define HWIO_DDR_PI_111_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_111_REGOFF)
#define HWIO_DDR_PI_111_PI_TDFI_CALVL_CC_F0_FLDMASK (0x3ff)
#define HWIO_DDR_PI_111_PI_TDFI_CALVL_CC_F0_FLDSHFT (0)
#define HWIO_DDR_PI_111_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_111_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_111_PI_TDFI_CALVL_CAPTURE_F0_FLDMASK (0x3ff0000)
#define HWIO_DDR_PI_111_PI_TDFI_CALVL_CAPTURE_F0_FLDSHFT (16)
#define HWIO_DDR_PI_111_RESERVED1_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_111_RESERVED1_FLDSHFT (26)

#define HWIO_DDR_PI_112_REGOFF 0x1c0
#define HWIO_DDR_PI_112_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_112_REGOFF)
#define HWIO_DDR_PI_112_PI_TDFI_CALVL_CC_F1_FLDMASK (0x3ff)
#define HWIO_DDR_PI_112_PI_TDFI_CALVL_CC_F1_FLDSHFT (0)
#define HWIO_DDR_PI_112_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_112_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_112_PI_TDFI_CALVL_CAPTURE_F1_FLDMASK (0x3ff0000)
#define HWIO_DDR_PI_112_PI_TDFI_CALVL_CAPTURE_F1_FLDSHFT (16)
#define HWIO_DDR_PI_112_RESERVED1_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_112_RESERVED1_FLDSHFT (26)

#define HWIO_DDR_PI_113_REGOFF 0x1c4
#define HWIO_DDR_PI_113_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_113_REGOFF)
#define HWIO_DDR_PI_113_PI_TDFI_CALVL_CC_F2_FLDMASK (0x3ff)
#define HWIO_DDR_PI_113_PI_TDFI_CALVL_CC_F2_FLDSHFT (0)
#define HWIO_DDR_PI_113_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_113_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_113_PI_TDFI_CALVL_CAPTURE_F2_FLDMASK (0x3ff0000)
#define HWIO_DDR_PI_113_PI_TDFI_CALVL_CAPTURE_F2_FLDSHFT (16)
#define HWIO_DDR_PI_113_RESERVED1_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_113_RESERVED1_FLDSHFT (26)

#define HWIO_DDR_PI_114_REGOFF 0x1c8
#define HWIO_DDR_PI_114_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_114_REGOFF)
#define HWIO_DDR_PI_114_PI_TDFI_CALVL_CC_F3_FLDMASK (0x3ff)
#define HWIO_DDR_PI_114_PI_TDFI_CALVL_CC_F3_FLDSHFT (0)
#define HWIO_DDR_PI_114_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_114_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_114_PI_TDFI_CALVL_CAPTURE_F3_FLDMASK (0x3ff0000)
#define HWIO_DDR_PI_114_PI_TDFI_CALVL_CAPTURE_F3_FLDSHFT (16)
#define HWIO_DDR_PI_114_RESERVED1_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_114_RESERVED1_FLDSHFT (26)

#define HWIO_DDR_PI_115_REGOFF 0x1cc
#define HWIO_DDR_PI_115_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_115_REGOFF)
#define HWIO_DDR_PI_115_PI_TDFI_CALVL_RESP_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_115_PI_TDFI_CALVL_RESP_FLDSHFT (0)

#define HWIO_DDR_PI_116_REGOFF 0x1d0
#define HWIO_DDR_PI_116_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_116_REGOFF)
#define HWIO_DDR_PI_116_PI_TDFI_CALVL_MAX_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_116_PI_TDFI_CALVL_MAX_FLDSHFT (0)

#define HWIO_DDR_PI_117_REGOFF 0x1d4
#define HWIO_DDR_PI_117_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_117_REGOFF)
#define HWIO_DDR_PI_117_PI_CALVL_RESP_MASK_FLDMASK (0x1)
#define HWIO_DDR_PI_117_PI_CALVL_RESP_MASK_FLDSHFT (0)
#define HWIO_DDR_PI_117_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_117_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_117_PI_CALVL_EN_F0_FLDMASK (0x300)
#define HWIO_DDR_PI_117_PI_CALVL_EN_F0_FLDSHFT (8)
#define HWIO_DDR_PI_117_RESERVED1_FLDMASK (0xfc00)
#define HWIO_DDR_PI_117_RESERVED1_FLDSHFT (10)
#define HWIO_DDR_PI_117_PI_CALVL_EN_F1_FLDMASK (0x30000)
#define HWIO_DDR_PI_117_PI_CALVL_EN_F1_FLDSHFT (16)
#define HWIO_DDR_PI_117_RESERVED2_FLDMASK (0xfc0000)
#define HWIO_DDR_PI_117_RESERVED2_FLDSHFT (18)
#define HWIO_DDR_PI_117_PI_CALVL_EN_F2_FLDMASK (0x3000000)
#define HWIO_DDR_PI_117_PI_CALVL_EN_F2_FLDSHFT (24)
#define HWIO_DDR_PI_117_RESERVED3_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_117_RESERVED3_FLDSHFT (26)

#define HWIO_DDR_PI_118_REGOFF 0x1d8
#define HWIO_DDR_PI_118_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_118_REGOFF)
#define HWIO_DDR_PI_118_PI_CALVL_EN_F3_FLDMASK (0x3)
#define HWIO_DDR_PI_118_PI_CALVL_EN_F3_FLDSHFT (0)
#define HWIO_DDR_PI_118_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_118_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_118_PI_CALVL_ERROR_STATUS_FLDMASK (0x300)
#define HWIO_DDR_PI_118_PI_CALVL_ERROR_STATUS_FLDSHFT (8)
#define HWIO_DDR_PI_118_RESERVED1_FLDMASK (0xfc00)
#define HWIO_DDR_PI_118_RESERVED1_FLDSHFT (10)
#define HWIO_DDR_PI_118_PI_CALVL_INTERVAL_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_118_PI_CALVL_INTERVAL_FLDSHFT (16)

#define HWIO_DDR_PI_119_REGOFF 0x1dc
#define HWIO_DDR_PI_119_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_119_REGOFF)
#define HWIO_DDR_PI_119_PI_TCACKEL_FLDMASK (0x1f)
#define HWIO_DDR_PI_119_PI_TCACKEL_FLDSHFT (0)
#define HWIO_DDR_PI_119_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_PI_119_RESERVED_FLDSHFT (5)
#define HWIO_DDR_PI_119_PI_TCAMRD_FLDMASK (0x3f00)
#define HWIO_DDR_PI_119_PI_TCAMRD_FLDSHFT (8)
#define HWIO_DDR_PI_119_RESERVED1_FLDMASK (0xc000)
#define HWIO_DDR_PI_119_RESERVED1_FLDSHFT (14)
#define HWIO_DDR_PI_119_PI_TCACKEH_FLDMASK (0x1f0000)
#define HWIO_DDR_PI_119_PI_TCACKEH_FLDSHFT (16)
#define HWIO_DDR_PI_119_RESERVED2_FLDMASK (0xe00000)
#define HWIO_DDR_PI_119_RESERVED2_FLDSHFT (21)
#define HWIO_DDR_PI_119_PI_TMRZ_F0_FLDMASK (0x1f000000)
#define HWIO_DDR_PI_119_PI_TMRZ_F0_FLDSHFT (24)
#define HWIO_DDR_PI_119_RESERVED3_FLDMASK (0xe0000000)
#define HWIO_DDR_PI_119_RESERVED3_FLDSHFT (29)

#define HWIO_DDR_PI_120_REGOFF 0x1e0
#define HWIO_DDR_PI_120_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_120_REGOFF)
#define HWIO_DDR_PI_120_PI_TCAENT_F0_FLDMASK (0x3fff)
#define HWIO_DDR_PI_120_PI_TCAENT_F0_FLDSHFT (0)
#define HWIO_DDR_PI_120_RESERVED_FLDMASK (0xc000)
#define HWIO_DDR_PI_120_RESERVED_FLDSHFT (14)
#define HWIO_DDR_PI_120_PI_TMRZ_F1_FLDMASK (0x1f0000)
#define HWIO_DDR_PI_120_PI_TMRZ_F1_FLDSHFT (16)
#define HWIO_DDR_PI_120_RESERVED1_FLDMASK (0xe00000)
#define HWIO_DDR_PI_120_RESERVED1_FLDSHFT (21)
#define HWIO_DDR_PI_120_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_PI_120_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_PI_121_REGOFF 0x1e4
#define HWIO_DDR_PI_121_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_121_REGOFF)
#define HWIO_DDR_PI_121_PI_TCAENT_F1_FLDMASK (0x3fff)
#define HWIO_DDR_PI_121_PI_TCAENT_F1_FLDSHFT (0)
#define HWIO_DDR_PI_121_RESERVED_FLDMASK (0xc000)
#define HWIO_DDR_PI_121_RESERVED_FLDSHFT (14)
#define HWIO_DDR_PI_121_PI_TMRZ_F2_FLDMASK (0x1f0000)
#define HWIO_DDR_PI_121_PI_TMRZ_F2_FLDSHFT (16)
#define HWIO_DDR_PI_121_RESERVED1_FLDMASK (0xe00000)
#define HWIO_DDR_PI_121_RESERVED1_FLDSHFT (21)
#define HWIO_DDR_PI_121_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_PI_121_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_PI_122_REGOFF 0x1e8
#define HWIO_DDR_PI_122_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_122_REGOFF)
#define HWIO_DDR_PI_122_PI_TCAENT_F2_FLDMASK (0x3fff)
#define HWIO_DDR_PI_122_PI_TCAENT_F2_FLDSHFT (0)
#define HWIO_DDR_PI_122_RESERVED_FLDMASK (0xc000)
#define HWIO_DDR_PI_122_RESERVED_FLDSHFT (14)
#define HWIO_DDR_PI_122_PI_TMRZ_F3_FLDMASK (0x1f0000)
#define HWIO_DDR_PI_122_PI_TMRZ_F3_FLDSHFT (16)
#define HWIO_DDR_PI_122_RESERVED1_FLDMASK (0xe00000)
#define HWIO_DDR_PI_122_RESERVED1_FLDSHFT (21)
#define HWIO_DDR_PI_122_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_PI_122_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_PI_123_REGOFF 0x1ec
#define HWIO_DDR_PI_123_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_123_REGOFF)
#define HWIO_DDR_PI_123_PI_TCAENT_F3_FLDMASK (0x3fff)
#define HWIO_DDR_PI_123_PI_TCAENT_F3_FLDSHFT (0)
#define HWIO_DDR_PI_123_RESERVED_FLDMASK (0xc000)
#define HWIO_DDR_PI_123_RESERVED_FLDSHFT (14)
#define HWIO_DDR_PI_123_PI_TCAEXT_FLDMASK (0x1f0000)
#define HWIO_DDR_PI_123_PI_TCAEXT_FLDSHFT (16)
#define HWIO_DDR_PI_123_RESERVED1_FLDMASK (0xe00000)
#define HWIO_DDR_PI_123_RESERVED1_FLDSHFT (21)
#define HWIO_DDR_PI_123_PI_CA_TRAIN_VREF_EN_FLDMASK (0x1000000)
#define HWIO_DDR_PI_123_PI_CA_TRAIN_VREF_EN_FLDSHFT (24)
#define HWIO_DDR_PI_123_RESERVED2_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_123_RESERVED2_FLDSHFT (25)

#define HWIO_DDR_PI_124_REGOFF 0x1f0
#define HWIO_DDR_PI_124_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_124_REGOFF)
#define HWIO_DDR_PI_124_PI_TDFI_CACSCA_F0_FLDMASK (0x1f)
#define HWIO_DDR_PI_124_PI_TDFI_CACSCA_F0_FLDSHFT (0)
#define HWIO_DDR_PI_124_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_PI_124_RESERVED_FLDSHFT (5)
#define HWIO_DDR_PI_124_PI_TDFI_CASEL_F0_FLDMASK (0x1f00)
#define HWIO_DDR_PI_124_PI_TDFI_CASEL_F0_FLDSHFT (8)
#define HWIO_DDR_PI_124_RESERVED1_FLDMASK (0xe000)
#define HWIO_DDR_PI_124_RESERVED1_FLDSHFT (13)
#define HWIO_DDR_PI_124_PI_TVREF_SHORT_F0_FLDMASK (0x3ff0000)
#define HWIO_DDR_PI_124_PI_TVREF_SHORT_F0_FLDSHFT (16)
#define HWIO_DDR_PI_124_RESERVED2_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_124_RESERVED2_FLDSHFT (26)

#define HWIO_DDR_PI_125_REGOFF 0x1f4
#define HWIO_DDR_PI_125_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_125_REGOFF)
#define HWIO_DDR_PI_125_PI_TVREF_LONG_F0_FLDMASK (0x3ff)
#define HWIO_DDR_PI_125_PI_TVREF_LONG_F0_FLDSHFT (0)
#define HWIO_DDR_PI_125_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_125_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_125_PI_TDFI_CACSCA_F1_FLDMASK (0x1f0000)
#define HWIO_DDR_PI_125_PI_TDFI_CACSCA_F1_FLDSHFT (16)
#define HWIO_DDR_PI_125_RESERVED1_FLDMASK (0xe00000)
#define HWIO_DDR_PI_125_RESERVED1_FLDSHFT (21)
#define HWIO_DDR_PI_125_PI_TDFI_CASEL_F1_FLDMASK (0x1f000000)
#define HWIO_DDR_PI_125_PI_TDFI_CASEL_F1_FLDSHFT (24)
#define HWIO_DDR_PI_125_RESERVED2_FLDMASK (0xe0000000)
#define HWIO_DDR_PI_125_RESERVED2_FLDSHFT (29)

#define HWIO_DDR_PI_126_REGOFF 0x1f8
#define HWIO_DDR_PI_126_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_126_REGOFF)
#define HWIO_DDR_PI_126_PI_TVREF_SHORT_F1_FLDMASK (0x3ff)
#define HWIO_DDR_PI_126_PI_TVREF_SHORT_F1_FLDSHFT (0)
#define HWIO_DDR_PI_126_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_126_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_126_PI_TVREF_LONG_F1_FLDMASK (0x3ff0000)
#define HWIO_DDR_PI_126_PI_TVREF_LONG_F1_FLDSHFT (16)
#define HWIO_DDR_PI_126_RESERVED1_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_126_RESERVED1_FLDSHFT (26)

#define HWIO_DDR_PI_127_REGOFF 0x1fc
#define HWIO_DDR_PI_127_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_127_REGOFF)
#define HWIO_DDR_PI_127_PI_TDFI_CACSCA_F2_FLDMASK (0x1f)
#define HWIO_DDR_PI_127_PI_TDFI_CACSCA_F2_FLDSHFT (0)
#define HWIO_DDR_PI_127_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_PI_127_RESERVED_FLDSHFT (5)
#define HWIO_DDR_PI_127_PI_TDFI_CASEL_F2_FLDMASK (0x1f00)
#define HWIO_DDR_PI_127_PI_TDFI_CASEL_F2_FLDSHFT (8)
#define HWIO_DDR_PI_127_RESERVED1_FLDMASK (0xe000)
#define HWIO_DDR_PI_127_RESERVED1_FLDSHFT (13)
#define HWIO_DDR_PI_127_PI_TVREF_SHORT_F2_FLDMASK (0x3ff0000)
#define HWIO_DDR_PI_127_PI_TVREF_SHORT_F2_FLDSHFT (16)
#define HWIO_DDR_PI_127_RESERVED2_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_127_RESERVED2_FLDSHFT (26)

#define HWIO_DDR_PI_128_REGOFF 0x200
#define HWIO_DDR_PI_128_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_128_REGOFF)
#define HWIO_DDR_PI_128_PI_TVREF_LONG_F2_FLDMASK (0x3ff)
#define HWIO_DDR_PI_128_PI_TVREF_LONG_F2_FLDSHFT (0)
#define HWIO_DDR_PI_128_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_128_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_128_PI_TDFI_CACSCA_F3_FLDMASK (0x1f0000)
#define HWIO_DDR_PI_128_PI_TDFI_CACSCA_F3_FLDSHFT (16)
#define HWIO_DDR_PI_128_RESERVED1_FLDMASK (0xe00000)
#define HWIO_DDR_PI_128_RESERVED1_FLDSHFT (21)
#define HWIO_DDR_PI_128_PI_TDFI_CASEL_F3_FLDMASK (0x1f000000)
#define HWIO_DDR_PI_128_PI_TDFI_CASEL_F3_FLDSHFT (24)
#define HWIO_DDR_PI_128_RESERVED2_FLDMASK (0xe0000000)
#define HWIO_DDR_PI_128_RESERVED2_FLDSHFT (29)

#define HWIO_DDR_PI_129_REGOFF 0x204
#define HWIO_DDR_PI_129_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_129_REGOFF)
#define HWIO_DDR_PI_129_PI_TVREF_SHORT_F3_FLDMASK (0x3ff)
#define HWIO_DDR_PI_129_PI_TVREF_SHORT_F3_FLDSHFT (0)
#define HWIO_DDR_PI_129_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_129_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_129_PI_TVREF_LONG_F3_FLDMASK (0x3ff0000)
#define HWIO_DDR_PI_129_PI_TVREF_LONG_F3_FLDSHFT (16)
#define HWIO_DDR_PI_129_RESERVED1_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_129_RESERVED1_FLDSHFT (26)

#define HWIO_DDR_PI_130_REGOFF 0x208
#define HWIO_DDR_PI_130_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_130_REGOFF)
#define HWIO_DDR_PI_130_PI_CALVL_VREF_INITIAL_START_POINT_FLDMASK (0x7f)
#define HWIO_DDR_PI_130_PI_CALVL_VREF_INITIAL_START_POINT_FLDSHFT (0)
#define HWIO_DDR_PI_130_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_PI_130_RESERVED_FLDSHFT (7)
#define HWIO_DDR_PI_130_PI_CALVL_VREF_INITIAL_STOP_POINT_FLDMASK (0x7f00)
#define HWIO_DDR_PI_130_PI_CALVL_VREF_INITIAL_STOP_POINT_FLDSHFT (8)
#define HWIO_DDR_PI_130_RESERVED1_FLDMASK (0x8000)
#define HWIO_DDR_PI_130_RESERVED1_FLDSHFT (15)
#define HWIO_DDR_PI_130_PI_CALVL_VREF_INITIAL_STEPSIZE_FLDMASK (0xf0000)
#define HWIO_DDR_PI_130_PI_CALVL_VREF_INITIAL_STEPSIZE_FLDSHFT (16)
#define HWIO_DDR_PI_130_RESERVED2_FLDMASK (0xf00000)
#define HWIO_DDR_PI_130_RESERVED2_FLDSHFT (20)
#define HWIO_DDR_PI_130_PI_CALVL_VREF_NORMAL_STEPSIZE_FLDMASK (0xf000000)
#define HWIO_DDR_PI_130_PI_CALVL_VREF_NORMAL_STEPSIZE_FLDSHFT (24)
#define HWIO_DDR_PI_130_RESERVED3_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_130_RESERVED3_FLDSHFT (28)

#define HWIO_DDR_PI_131_REGOFF 0x20c
#define HWIO_DDR_PI_131_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_131_REGOFF)
#define HWIO_DDR_PI_131_PI_CALVL_VREF_DELTA_FLDMASK (0xf)
#define HWIO_DDR_PI_131_PI_CALVL_VREF_DELTA_FLDSHFT (0)
#define HWIO_DDR_PI_131_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_PI_131_RESERVED_FLDSHFT (4)
#define HWIO_DDR_PI_131_PI_TDFI_INIT_START_MIN_FLDMASK (0xff00)
#define HWIO_DDR_PI_131_PI_TDFI_INIT_START_MIN_FLDSHFT (8)
#define HWIO_DDR_PI_131_PI_TDFI_INIT_COMPLETE_MIN_FLDMASK (0xff0000)
#define HWIO_DDR_PI_131_PI_TDFI_INIT_COMPLETE_MIN_FLDSHFT (16)
#define HWIO_DDR_PI_131_PI_TDFI_CALVL_STROBE_F0_FLDMASK (0xf000000)
#define HWIO_DDR_PI_131_PI_TDFI_CALVL_STROBE_F0_FLDSHFT (24)
#define HWIO_DDR_PI_131_RESERVED1_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_131_RESERVED1_FLDSHFT (28)

#define HWIO_DDR_PI_132_REGOFF 0x210
#define HWIO_DDR_PI_132_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_132_REGOFF)
#define HWIO_DDR_PI_132_PI_TDFI_CALVL_STROBE_F1_FLDMASK (0xf)
#define HWIO_DDR_PI_132_PI_TDFI_CALVL_STROBE_F1_FLDSHFT (0)
#define HWIO_DDR_PI_132_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_PI_132_RESERVED_FLDSHFT (4)
#define HWIO_DDR_PI_132_PI_TDFI_CALVL_STROBE_F2_FLDMASK (0xf00)
#define HWIO_DDR_PI_132_PI_TDFI_CALVL_STROBE_F2_FLDSHFT (8)
#define HWIO_DDR_PI_132_RESERVED1_FLDMASK (0xf000)
#define HWIO_DDR_PI_132_RESERVED1_FLDSHFT (12)
#define HWIO_DDR_PI_132_PI_TDFI_CALVL_STROBE_F3_FLDMASK (0xf0000)
#define HWIO_DDR_PI_132_PI_TDFI_CALVL_STROBE_F3_FLDSHFT (16)
#define HWIO_DDR_PI_132_RESERVED2_FLDMASK (0xf00000)
#define HWIO_DDR_PI_132_RESERVED2_FLDSHFT (20)
#define HWIO_DDR_PI_132_PI_TCKCKEH_FLDMASK (0xf000000)
#define HWIO_DDR_PI_132_PI_TCKCKEH_FLDSHFT (24)
#define HWIO_DDR_PI_132_RESERVED3_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_132_RESERVED3_FLDSHFT (28)

#define HWIO_DDR_PI_133_REGOFF 0x214
#define HWIO_DDR_PI_133_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_133_REGOFF)
#define HWIO_DDR_PI_133_PI_CALVL_STROBE_NUM_FLDMASK (0x1f)
#define HWIO_DDR_PI_133_PI_CALVL_STROBE_NUM_FLDSHFT (0)
#define HWIO_DDR_PI_133_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_PI_133_RESERVED_FLDSHFT (5)
#define HWIO_DDR_PI_133_PI_SW_CA_TRAIN_VREF_FLDMASK (0x7f00)
#define HWIO_DDR_PI_133_PI_SW_CA_TRAIN_VREF_FLDSHFT (8)
#define HWIO_DDR_PI_133_RESERVED1_FLDMASK (0x8000)
#define HWIO_DDR_PI_133_RESERVED1_FLDSHFT (15)
#define HWIO_DDR_PI_133_PI_TDFI_INIT_START_F0_FLDMASK (0xff0000)
#define HWIO_DDR_PI_133_PI_TDFI_INIT_START_F0_FLDSHFT (16)
#define HWIO_DDR_PI_133_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_PI_133_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_PI_134_REGOFF 0x218
#define HWIO_DDR_PI_134_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_134_REGOFF)
#define HWIO_DDR_PI_134_PI_TDFI_INIT_COMPLETE_F0_FLDMASK (0xffff)
#define HWIO_DDR_PI_134_PI_TDFI_INIT_COMPLETE_F0_FLDSHFT (0)
#define HWIO_DDR_PI_134_PI_TDFI_INIT_START_F1_FLDMASK (0xff0000)
#define HWIO_DDR_PI_134_PI_TDFI_INIT_START_F1_FLDSHFT (16)
#define HWIO_DDR_PI_134_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_PI_134_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_PI_135_REGOFF 0x21c
#define HWIO_DDR_PI_135_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_135_REGOFF)
#define HWIO_DDR_PI_135_PI_TDFI_INIT_COMPLETE_F1_FLDMASK (0xffff)
#define HWIO_DDR_PI_135_PI_TDFI_INIT_COMPLETE_F1_FLDSHFT (0)
#define HWIO_DDR_PI_135_PI_TDFI_INIT_START_F2_FLDMASK (0xff0000)
#define HWIO_DDR_PI_135_PI_TDFI_INIT_START_F2_FLDSHFT (16)
#define HWIO_DDR_PI_135_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_PI_135_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_PI_136_REGOFF 0x220
#define HWIO_DDR_PI_136_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_136_REGOFF)
#define HWIO_DDR_PI_136_PI_TDFI_INIT_COMPLETE_F2_FLDMASK (0xffff)
#define HWIO_DDR_PI_136_PI_TDFI_INIT_COMPLETE_F2_FLDSHFT (0)
#define HWIO_DDR_PI_136_PI_TDFI_INIT_START_F3_FLDMASK (0xff0000)
#define HWIO_DDR_PI_136_PI_TDFI_INIT_START_F3_FLDSHFT (16)
#define HWIO_DDR_PI_136_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_PI_136_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_PI_137_REGOFF 0x224
#define HWIO_DDR_PI_137_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_137_REGOFF)
#define HWIO_DDR_PI_137_PI_TDFI_INIT_COMPLETE_F3_FLDMASK (0xffff)
#define HWIO_DDR_PI_137_PI_TDFI_INIT_COMPLETE_F3_FLDSHFT (0)
#define HWIO_DDR_PI_137_PI_CLKDISABLE_2_INIT_START_FLDMASK (0xff0000)
#define HWIO_DDR_PI_137_PI_CLKDISABLE_2_INIT_START_FLDSHFT (16)
#define HWIO_DDR_PI_137_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_FLDMASK \
	(0xff000000)
#define HWIO_DDR_PI_137_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_FLDSHFT (24)

#define HWIO_DDR_PI_138_REGOFF 0x228
#define HWIO_DDR_PI_138_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_138_REGOFF)
#define HWIO_DDR_PI_138_PI_DRAM_CLK_DISABLE_DEASSERT_SEL_FLDMASK (0x1)
#define HWIO_DDR_PI_138_PI_DRAM_CLK_DISABLE_DEASSERT_SEL_FLDSHFT (0)
#define HWIO_DDR_PI_138_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_138_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_138_PI_REFRESH_BETWEEN_SEGMENT_DISABLE_FLDMASK (0x100)
#define HWIO_DDR_PI_138_PI_REFRESH_BETWEEN_SEGMENT_DISABLE_FLDSHFT (8)
#define HWIO_DDR_PI_138_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_138_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_138_PI_TCKEHDQS_F0_FLDMASK (0x3f0000)
#define HWIO_DDR_PI_138_PI_TCKEHDQS_F0_FLDSHFT (16)
#define HWIO_DDR_PI_138_RESERVED2_FLDMASK (0xc00000)
#define HWIO_DDR_PI_138_RESERVED2_FLDSHFT (22)
#define HWIO_DDR_PI_138_PI_TCKEHDQS_F1_FLDMASK (0x3f000000)
#define HWIO_DDR_PI_138_PI_TCKEHDQS_F1_FLDSHFT (24)
#define HWIO_DDR_PI_138_RESERVED3_FLDMASK (0xc0000000)
#define HWIO_DDR_PI_138_RESERVED3_FLDSHFT (30)

#define HWIO_DDR_PI_139_REGOFF 0x22c
#define HWIO_DDR_PI_139_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_139_REGOFF)
#define HWIO_DDR_PI_139_PI_TCKEHDQS_F2_FLDMASK (0x3f)
#define HWIO_DDR_PI_139_PI_TCKEHDQS_F2_FLDSHFT (0)
#define HWIO_DDR_PI_139_RESERVED_FLDMASK (0xc0)
#define HWIO_DDR_PI_139_RESERVED_FLDSHFT (6)
#define HWIO_DDR_PI_139_PI_TCKEHDQS_F3_FLDMASK (0x3f00)
#define HWIO_DDR_PI_139_PI_TCKEHDQS_F3_FLDSHFT (8)
#define HWIO_DDR_PI_139_RESERVED1_FLDMASK (0xc000)
#define HWIO_DDR_PI_139_RESERVED1_FLDSHFT (14)
#define HWIO_DDR_PI_139_PI_MC_DFS_PI_SET_VREF_ENABLE_FLDMASK (0x10000)
#define HWIO_DDR_PI_139_PI_MC_DFS_PI_SET_VREF_ENABLE_FLDSHFT (16)
#define HWIO_DDR_PI_139_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_139_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_139_PI_WDQLVL_VREF_EN_FLDMASK (0x1000000)
#define HWIO_DDR_PI_139_PI_WDQLVL_VREF_EN_FLDSHFT (24)
#define HWIO_DDR_PI_139_RESERVED3_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_139_RESERVED3_FLDSHFT (25)

#define HWIO_DDR_PI_140_REGOFF 0x230
#define HWIO_DDR_PI_140_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_140_REGOFF)
#define HWIO_DDR_PI_140_PI_WDQLVL_BST_NUM_FLDMASK (0x7)
#define HWIO_DDR_PI_140_PI_WDQLVL_BST_NUM_FLDSHFT (0)
#define HWIO_DDR_PI_140_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_PI_140_RESERVED_FLDSHFT (3)
#define HWIO_DDR_PI_140_PI_TDFI_WDQLVL_WR_F0_FLDMASK (0x3ff00)
#define HWIO_DDR_PI_140_PI_TDFI_WDQLVL_WR_F0_FLDSHFT (8)
#define HWIO_DDR_PI_140_RESERVED1_FLDMASK (0xfc0000)
#define HWIO_DDR_PI_140_RESERVED1_FLDSHFT (18)
#define HWIO_DDR_PI_140_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_PI_140_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_PI_141_REGOFF 0x234
#define HWIO_DDR_PI_141_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_141_REGOFF)
#define HWIO_DDR_PI_141_PI_TDFI_WDQLVL_WR_F1_FLDMASK (0x3ff)
#define HWIO_DDR_PI_141_PI_TDFI_WDQLVL_WR_F1_FLDSHFT (0)
#define HWIO_DDR_PI_141_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_141_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_141_PI_TDFI_WDQLVL_WR_F2_FLDMASK (0x3ff0000)
#define HWIO_DDR_PI_141_PI_TDFI_WDQLVL_WR_F2_FLDSHFT (16)
#define HWIO_DDR_PI_141_RESERVED1_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_141_RESERVED1_FLDSHFT (26)

#define HWIO_DDR_PI_142_REGOFF 0x238
#define HWIO_DDR_PI_142_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_142_REGOFF)
#define HWIO_DDR_PI_142_PI_TDFI_WDQLVL_WR_F3_FLDMASK (0x3ff)
#define HWIO_DDR_PI_142_PI_TDFI_WDQLVL_WR_F3_FLDSHFT (0)
#define HWIO_DDR_PI_142_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_142_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_142_PI_TDFI_WDQLVL_RW_FLDMASK (0x3ff0000)
#define HWIO_DDR_PI_142_PI_TDFI_WDQLVL_RW_FLDSHFT (16)
#define HWIO_DDR_PI_142_RESERVED1_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_142_RESERVED1_FLDSHFT (26)

#define HWIO_DDR_PI_143_REGOFF 0x23c
#define HWIO_DDR_PI_143_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_143_REGOFF)
#define HWIO_DDR_PI_143_PI_WDQLVL_RESP_MASK_FLDMASK (0xf)
#define HWIO_DDR_PI_143_PI_WDQLVL_RESP_MASK_FLDSHFT (0)
#define HWIO_DDR_PI_143_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_PI_143_RESERVED_FLDSHFT (4)
#define HWIO_DDR_PI_143_PI_WDQLVL_ROTATE_FLDMASK (0x100)
#define HWIO_DDR_PI_143_PI_WDQLVL_ROTATE_FLDSHFT (8)
#define HWIO_DDR_PI_143_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_143_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_143_PI_WDQLVL_CS_MAP_FLDMASK (0x30000)
#define HWIO_DDR_PI_143_PI_WDQLVL_CS_MAP_FLDSHFT (16)
#define HWIO_DDR_PI_143_RESERVED2_FLDMASK (0xfc0000)
#define HWIO_DDR_PI_143_RESERVED2_FLDSHFT (18)
#define HWIO_DDR_PI_143_PI_WDQLVL_VREF_INITIAL_START_POINT_FLDMASK (0x7f000000)
#define HWIO_DDR_PI_143_PI_WDQLVL_VREF_INITIAL_START_POINT_FLDSHFT (24)
#define HWIO_DDR_PI_143_RESERVED3_FLDMASK (0x80000000)
#define HWIO_DDR_PI_143_RESERVED3_FLDSHFT (31)

#define HWIO_DDR_PI_144_REGOFF 0x240
#define HWIO_DDR_PI_144_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_144_REGOFF)
#define HWIO_DDR_PI_144_PI_WDQLVL_VREF_INITIAL_STOP_POINT_FLDMASK (0x7f)
#define HWIO_DDR_PI_144_PI_WDQLVL_VREF_INITIAL_STOP_POINT_FLDSHFT (0)
#define HWIO_DDR_PI_144_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_PI_144_RESERVED_FLDSHFT (7)
#define HWIO_DDR_PI_144_PI_WDQLVL_VREF_INITIAL_STEPSIZE_FLDMASK (0x1f00)
#define HWIO_DDR_PI_144_PI_WDQLVL_VREF_INITIAL_STEPSIZE_FLDSHFT (8)
#define HWIO_DDR_PI_144_RESERVED1_FLDMASK (0xe000)
#define HWIO_DDR_PI_144_RESERVED1_FLDSHFT (13)
#define HWIO_DDR_PI_144_PI_WDQLVL_VREF_NORMAL_STEPSIZE_FLDMASK (0x1f0000)
#define HWIO_DDR_PI_144_PI_WDQLVL_VREF_NORMAL_STEPSIZE_FLDSHFT (16)
#define HWIO_DDR_PI_144_RESERVED2_FLDMASK (0xe00000)
#define HWIO_DDR_PI_144_RESERVED2_FLDSHFT (21)
#define HWIO_DDR_PI_144_PI_WDQLVL_VREF_DELTA_FLDMASK (0xf000000)
#define HWIO_DDR_PI_144_PI_WDQLVL_VREF_DELTA_FLDSHFT (24)
#define HWIO_DDR_PI_144_RESERVED3_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_144_RESERVED3_FLDSHFT (28)

#define HWIO_DDR_PI_145_REGOFF 0x244
#define HWIO_DDR_PI_145_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_145_REGOFF)
#define HWIO_DDR_PI_145_PI_WDQLVL_PERIODIC_FLDMASK (0x1)
#define HWIO_DDR_PI_145_PI_WDQLVL_PERIODIC_FLDSHFT (0)
#define HWIO_DDR_PI_145_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_145_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_145_PI_WDQLVL_REQ_FLDMASK (0x100)
#define HWIO_DDR_PI_145_PI_WDQLVL_REQ_FLDSHFT (8)
#define HWIO_DDR_PI_145_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_145_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_145_PI_WDQLVL_CS_FLDMASK (0x10000)
#define HWIO_DDR_PI_145_PI_WDQLVL_CS_FLDSHFT (16)
#define HWIO_DDR_PI_145_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_145_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_145_PI_TDFI_WDQLVL_EN_FLDMASK (0xff000000)
#define HWIO_DDR_PI_145_PI_TDFI_WDQLVL_EN_FLDSHFT (24)

#define HWIO_DDR_PI_146_REGOFF 0x248
#define HWIO_DDR_PI_146_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_146_REGOFF)
#define HWIO_DDR_PI_146_PI_TDFI_WDQLVL_RESP_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_146_PI_TDFI_WDQLVL_RESP_FLDSHFT (0)

#define HWIO_DDR_PI_147_REGOFF 0x24c
#define HWIO_DDR_PI_147_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_147_REGOFF)
#define HWIO_DDR_PI_147_PI_TDFI_WDQLVL_MAX_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_147_PI_TDFI_WDQLVL_MAX_FLDSHFT (0)

#define HWIO_DDR_PI_148_REGOFF 0x250
#define HWIO_DDR_PI_148_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_148_REGOFF)
#define HWIO_DDR_PI_148_PI_WDQLVL_INTERVAL_FLDMASK (0xffff)
#define HWIO_DDR_PI_148_PI_WDQLVL_INTERVAL_FLDSHFT (0)
#define HWIO_DDR_PI_148_PI_WDQLVL_EN_F0_FLDMASK (0x30000)
#define HWIO_DDR_PI_148_PI_WDQLVL_EN_F0_FLDSHFT (16)
#define HWIO_DDR_PI_148_RESERVED_FLDMASK (0xfc0000)
#define HWIO_DDR_PI_148_RESERVED_FLDSHFT (18)
#define HWIO_DDR_PI_148_PI_WDQLVL_EN_F1_FLDMASK (0x3000000)
#define HWIO_DDR_PI_148_PI_WDQLVL_EN_F1_FLDSHFT (24)
#define HWIO_DDR_PI_148_RESERVED1_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_148_RESERVED1_FLDSHFT (26)

#define HWIO_DDR_PI_149_REGOFF 0x254
#define HWIO_DDR_PI_149_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_149_REGOFF)
#define HWIO_DDR_PI_149_PI_WDQLVL_EN_F2_FLDMASK (0x3)
#define HWIO_DDR_PI_149_PI_WDQLVL_EN_F2_FLDSHFT (0)
#define HWIO_DDR_PI_149_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_149_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_149_PI_WDQLVL_EN_F3_FLDMASK (0x300)
#define HWIO_DDR_PI_149_PI_WDQLVL_EN_F3_FLDSHFT (8)
#define HWIO_DDR_PI_149_RESERVED1_FLDMASK (0xfc00)
#define HWIO_DDR_PI_149_RESERVED1_FLDSHFT (10)
#define HWIO_DDR_PI_149_PI_WDQLVL_ON_SREF_EXIT_FLDMASK (0x10000)
#define HWIO_DDR_PI_149_PI_WDQLVL_ON_SREF_EXIT_FLDSHFT (16)
#define HWIO_DDR_PI_149_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_149_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_149_PI_WDQLVL_DISABLE_DFS_FLDMASK (0x1000000)
#define HWIO_DDR_PI_149_PI_WDQLVL_DISABLE_DFS_FLDSHFT (24)
#define HWIO_DDR_PI_149_RESERVED3_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_149_RESERVED3_FLDSHFT (25)

#define HWIO_DDR_PI_150_REGOFF 0x258
#define HWIO_DDR_PI_150_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_150_REGOFF)
#define HWIO_DDR_PI_150_PI_WDQLVL_ERROR_STATUS_FLDMASK (0x3)
#define HWIO_DDR_PI_150_PI_WDQLVL_ERROR_STATUS_FLDSHFT (0)
#define HWIO_DDR_PI_150_RESERVED_FLDMASK (0xfc)
#define HWIO_DDR_PI_150_RESERVED_FLDSHFT (2)
#define HWIO_DDR_PI_150_PI_MR1_DATA_F0_0_FLDMASK (0xff00)
#define HWIO_DDR_PI_150_PI_MR1_DATA_F0_0_FLDSHFT (8)
#define HWIO_DDR_PI_150_PI_MR2_DATA_F0_0_FLDMASK (0xff0000)
#define HWIO_DDR_PI_150_PI_MR2_DATA_F0_0_FLDSHFT (16)
#define HWIO_DDR_PI_150_PI_MR3_DATA_F0_0_FLDMASK (0xff000000)
#define HWIO_DDR_PI_150_PI_MR3_DATA_F0_0_FLDSHFT (24)

#define HWIO_DDR_PI_151_REGOFF 0x25c
#define HWIO_DDR_PI_151_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_151_REGOFF)
#define HWIO_DDR_PI_151_PI_MR11_DATA_F0_0_FLDMASK (0xff)
#define HWIO_DDR_PI_151_PI_MR11_DATA_F0_0_FLDSHFT (0)
#define HWIO_DDR_PI_151_PI_MR12_DATA_F0_0_FLDMASK (0xff00)
#define HWIO_DDR_PI_151_PI_MR12_DATA_F0_0_FLDSHFT (8)
#define HWIO_DDR_PI_151_PI_MR14_DATA_F0_0_FLDMASK (0xff0000)
#define HWIO_DDR_PI_151_PI_MR14_DATA_F0_0_FLDSHFT (16)
#define HWIO_DDR_PI_151_PI_MR22_DATA_F0_0_FLDMASK (0xff000000)
#define HWIO_DDR_PI_151_PI_MR22_DATA_F0_0_FLDSHFT (24)

#define HWIO_DDR_PI_152_REGOFF 0x260
#define HWIO_DDR_PI_152_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_152_REGOFF)
#define HWIO_DDR_PI_152_PI_MR1_DATA_F1_0_FLDMASK (0xff)
#define HWIO_DDR_PI_152_PI_MR1_DATA_F1_0_FLDSHFT (0)
#define HWIO_DDR_PI_152_PI_MR2_DATA_F1_0_FLDMASK (0xff00)
#define HWIO_DDR_PI_152_PI_MR2_DATA_F1_0_FLDSHFT (8)
#define HWIO_DDR_PI_152_PI_MR3_DATA_F1_0_FLDMASK (0xff0000)
#define HWIO_DDR_PI_152_PI_MR3_DATA_F1_0_FLDSHFT (16)
#define HWIO_DDR_PI_152_PI_MR11_DATA_F1_0_FLDMASK (0xff000000)
#define HWIO_DDR_PI_152_PI_MR11_DATA_F1_0_FLDSHFT (24)

#define HWIO_DDR_PI_153_REGOFF 0x264
#define HWIO_DDR_PI_153_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_153_REGOFF)
#define HWIO_DDR_PI_153_PI_MR12_DATA_F1_0_FLDMASK (0xff)
#define HWIO_DDR_PI_153_PI_MR12_DATA_F1_0_FLDSHFT (0)
#define HWIO_DDR_PI_153_PI_MR14_DATA_F1_0_FLDMASK (0xff00)
#define HWIO_DDR_PI_153_PI_MR14_DATA_F1_0_FLDSHFT (8)
#define HWIO_DDR_PI_153_PI_MR22_DATA_F1_0_FLDMASK (0xff0000)
#define HWIO_DDR_PI_153_PI_MR22_DATA_F1_0_FLDSHFT (16)
#define HWIO_DDR_PI_153_PI_MR1_DATA_F2_0_FLDMASK (0xff000000)
#define HWIO_DDR_PI_153_PI_MR1_DATA_F2_0_FLDSHFT (24)

#define HWIO_DDR_PI_154_REGOFF 0x268
#define HWIO_DDR_PI_154_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_154_REGOFF)
#define HWIO_DDR_PI_154_PI_MR2_DATA_F2_0_FLDMASK (0xff)
#define HWIO_DDR_PI_154_PI_MR2_DATA_F2_0_FLDSHFT (0)
#define HWIO_DDR_PI_154_PI_MR3_DATA_F2_0_FLDMASK (0xff00)
#define HWIO_DDR_PI_154_PI_MR3_DATA_F2_0_FLDSHFT (8)
#define HWIO_DDR_PI_154_PI_MR11_DATA_F2_0_FLDMASK (0xff0000)
#define HWIO_DDR_PI_154_PI_MR11_DATA_F2_0_FLDSHFT (16)
#define HWIO_DDR_PI_154_PI_MR12_DATA_F2_0_FLDMASK (0xff000000)
#define HWIO_DDR_PI_154_PI_MR12_DATA_F2_0_FLDSHFT (24)

#define HWIO_DDR_PI_155_REGOFF 0x26c
#define HWIO_DDR_PI_155_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_155_REGOFF)
#define HWIO_DDR_PI_155_PI_MR14_DATA_F2_0_FLDMASK (0xff)
#define HWIO_DDR_PI_155_PI_MR14_DATA_F2_0_FLDSHFT (0)
#define HWIO_DDR_PI_155_PI_MR22_DATA_F2_0_FLDMASK (0xff00)
#define HWIO_DDR_PI_155_PI_MR22_DATA_F2_0_FLDSHFT (8)
#define HWIO_DDR_PI_155_PI_MR1_DATA_F3_0_FLDMASK (0xff0000)
#define HWIO_DDR_PI_155_PI_MR1_DATA_F3_0_FLDSHFT (16)
#define HWIO_DDR_PI_155_PI_MR2_DATA_F3_0_FLDMASK (0xff000000)
#define HWIO_DDR_PI_155_PI_MR2_DATA_F3_0_FLDSHFT (24)

#define HWIO_DDR_PI_156_REGOFF 0x270
#define HWIO_DDR_PI_156_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_156_REGOFF)
#define HWIO_DDR_PI_156_PI_MR3_DATA_F3_0_FLDMASK (0xff)
#define HWIO_DDR_PI_156_PI_MR3_DATA_F3_0_FLDSHFT (0)
#define HWIO_DDR_PI_156_PI_MR11_DATA_F3_0_FLDMASK (0xff00)
#define HWIO_DDR_PI_156_PI_MR11_DATA_F3_0_FLDSHFT (8)
#define HWIO_DDR_PI_156_PI_MR12_DATA_F3_0_FLDMASK (0xff0000)
#define HWIO_DDR_PI_156_PI_MR12_DATA_F3_0_FLDSHFT (16)
#define HWIO_DDR_PI_156_PI_MR14_DATA_F3_0_FLDMASK (0xff000000)
#define HWIO_DDR_PI_156_PI_MR14_DATA_F3_0_FLDSHFT (24)

#define HWIO_DDR_PI_157_REGOFF 0x274
#define HWIO_DDR_PI_157_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_157_REGOFF)
#define HWIO_DDR_PI_157_PI_MR22_DATA_F3_0_FLDMASK (0xff)
#define HWIO_DDR_PI_157_PI_MR22_DATA_F3_0_FLDSHFT (0)
#define HWIO_DDR_PI_157_PI_MR13_DATA_0_FLDMASK (0xff00)
#define HWIO_DDR_PI_157_PI_MR13_DATA_0_FLDSHFT (8)
#define HWIO_DDR_PI_157_PI_MR1_DATA_F0_1_FLDMASK (0xff0000)
#define HWIO_DDR_PI_157_PI_MR1_DATA_F0_1_FLDSHFT (16)
#define HWIO_DDR_PI_157_PI_MR2_DATA_F0_1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_157_PI_MR2_DATA_F0_1_FLDSHFT (24)

#define HWIO_DDR_PI_158_REGOFF 0x278
#define HWIO_DDR_PI_158_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_158_REGOFF)
#define HWIO_DDR_PI_158_PI_MR3_DATA_F0_1_FLDMASK (0xff)
#define HWIO_DDR_PI_158_PI_MR3_DATA_F0_1_FLDSHFT (0)
#define HWIO_DDR_PI_158_PI_MR11_DATA_F0_1_FLDMASK (0xff00)
#define HWIO_DDR_PI_158_PI_MR11_DATA_F0_1_FLDSHFT (8)
#define HWIO_DDR_PI_158_PI_MR12_DATA_F0_1_FLDMASK (0xff0000)
#define HWIO_DDR_PI_158_PI_MR12_DATA_F0_1_FLDSHFT (16)
#define HWIO_DDR_PI_158_PI_MR14_DATA_F0_1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_158_PI_MR14_DATA_F0_1_FLDSHFT (24)

#define HWIO_DDR_PI_159_REGOFF 0x27c
#define HWIO_DDR_PI_159_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_159_REGOFF)
#define HWIO_DDR_PI_159_PI_MR22_DATA_F0_1_FLDMASK (0xff)
#define HWIO_DDR_PI_159_PI_MR22_DATA_F0_1_FLDSHFT (0)
#define HWIO_DDR_PI_159_PI_MR1_DATA_F1_1_FLDMASK (0xff00)
#define HWIO_DDR_PI_159_PI_MR1_DATA_F1_1_FLDSHFT (8)
#define HWIO_DDR_PI_159_PI_MR2_DATA_F1_1_FLDMASK (0xff0000)
#define HWIO_DDR_PI_159_PI_MR2_DATA_F1_1_FLDSHFT (16)
#define HWIO_DDR_PI_159_PI_MR3_DATA_F1_1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_159_PI_MR3_DATA_F1_1_FLDSHFT (24)

#define HWIO_DDR_PI_160_REGOFF 0x280
#define HWIO_DDR_PI_160_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_160_REGOFF)
#define HWIO_DDR_PI_160_PI_MR11_DATA_F1_1_FLDMASK (0xff)
#define HWIO_DDR_PI_160_PI_MR11_DATA_F1_1_FLDSHFT (0)
#define HWIO_DDR_PI_160_PI_MR12_DATA_F1_1_FLDMASK (0xff00)
#define HWIO_DDR_PI_160_PI_MR12_DATA_F1_1_FLDSHFT (8)
#define HWIO_DDR_PI_160_PI_MR14_DATA_F1_1_FLDMASK (0xff0000)
#define HWIO_DDR_PI_160_PI_MR14_DATA_F1_1_FLDSHFT (16)
#define HWIO_DDR_PI_160_PI_MR22_DATA_F1_1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_160_PI_MR22_DATA_F1_1_FLDSHFT (24)

#define HWIO_DDR_PI_161_REGOFF 0x284
#define HWIO_DDR_PI_161_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_161_REGOFF)
#define HWIO_DDR_PI_161_PI_MR1_DATA_F2_1_FLDMASK (0xff)
#define HWIO_DDR_PI_161_PI_MR1_DATA_F2_1_FLDSHFT (0)
#define HWIO_DDR_PI_161_PI_MR2_DATA_F2_1_FLDMASK (0xff00)
#define HWIO_DDR_PI_161_PI_MR2_DATA_F2_1_FLDSHFT (8)
#define HWIO_DDR_PI_161_PI_MR3_DATA_F2_1_FLDMASK (0xff0000)
#define HWIO_DDR_PI_161_PI_MR3_DATA_F2_1_FLDSHFT (16)
#define HWIO_DDR_PI_161_PI_MR11_DATA_F2_1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_161_PI_MR11_DATA_F2_1_FLDSHFT (24)

#define HWIO_DDR_PI_162_REGOFF 0x288
#define HWIO_DDR_PI_162_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_162_REGOFF)
#define HWIO_DDR_PI_162_PI_MR12_DATA_F2_1_FLDMASK (0xff)
#define HWIO_DDR_PI_162_PI_MR12_DATA_F2_1_FLDSHFT (0)
#define HWIO_DDR_PI_162_PI_MR14_DATA_F2_1_FLDMASK (0xff00)
#define HWIO_DDR_PI_162_PI_MR14_DATA_F2_1_FLDSHFT (8)
#define HWIO_DDR_PI_162_PI_MR22_DATA_F2_1_FLDMASK (0xff0000)
#define HWIO_DDR_PI_162_PI_MR22_DATA_F2_1_FLDSHFT (16)
#define HWIO_DDR_PI_162_PI_MR1_DATA_F3_1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_162_PI_MR1_DATA_F3_1_FLDSHFT (24)

#define HWIO_DDR_PI_163_REGOFF 0x28c
#define HWIO_DDR_PI_163_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_163_REGOFF)
#define HWIO_DDR_PI_163_PI_MR2_DATA_F3_1_FLDMASK (0xff)
#define HWIO_DDR_PI_163_PI_MR2_DATA_F3_1_FLDSHFT (0)
#define HWIO_DDR_PI_163_PI_MR3_DATA_F3_1_FLDMASK (0xff00)
#define HWIO_DDR_PI_163_PI_MR3_DATA_F3_1_FLDSHFT (8)
#define HWIO_DDR_PI_163_PI_MR11_DATA_F3_1_FLDMASK (0xff0000)
#define HWIO_DDR_PI_163_PI_MR11_DATA_F3_1_FLDSHFT (16)
#define HWIO_DDR_PI_163_PI_MR12_DATA_F3_1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_163_PI_MR12_DATA_F3_1_FLDSHFT (24)

#define HWIO_DDR_PI_164_REGOFF 0x290
#define HWIO_DDR_PI_164_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_164_REGOFF)
#define HWIO_DDR_PI_164_PI_MR14_DATA_F3_1_FLDMASK (0xff)
#define HWIO_DDR_PI_164_PI_MR14_DATA_F3_1_FLDSHFT (0)
#define HWIO_DDR_PI_164_PI_MR22_DATA_F3_1_FLDMASK (0xff00)
#define HWIO_DDR_PI_164_PI_MR22_DATA_F3_1_FLDSHFT (8)
#define HWIO_DDR_PI_164_PI_MR13_DATA_1_FLDMASK (0xff0000)
#define HWIO_DDR_PI_164_PI_MR13_DATA_1_FLDSHFT (16)
#define HWIO_DDR_PI_164_PI_BANK_DIFF_FLDMASK (0x3000000)
#define HWIO_DDR_PI_164_PI_BANK_DIFF_FLDSHFT (24)
#define HWIO_DDR_PI_164_RESERVED_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_164_RESERVED_FLDSHFT (26)

#define HWIO_DDR_PI_165_REGOFF 0x294
#define HWIO_DDR_PI_165_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_165_REGOFF)
#define HWIO_DDR_PI_165_PI_ROW_DIFF_FLDMASK (0x7)
#define HWIO_DDR_PI_165_PI_ROW_DIFF_FLDSHFT (0)
#define HWIO_DDR_PI_165_RESERVED_FLDMASK (0xf8)
#define HWIO_DDR_PI_165_RESERVED_FLDSHFT (3)
#define HWIO_DDR_PI_165_PI_TFC_F0_FLDMASK (0x3ff00)
#define HWIO_DDR_PI_165_PI_TFC_F0_FLDSHFT (8)
#define HWIO_DDR_PI_165_RESERVED1_FLDMASK (0xfc0000)
#define HWIO_DDR_PI_165_RESERVED1_FLDSHFT (18)
#define HWIO_DDR_PI_165_OBSOLETE2_FLDMASK (0xff000000)
#define HWIO_DDR_PI_165_OBSOLETE2_FLDSHFT (24)

#define HWIO_DDR_PI_166_REGOFF 0x298
#define HWIO_DDR_PI_166_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_166_REGOFF)
#define HWIO_DDR_PI_166_PI_TFC_F1_FLDMASK (0x3ff)
#define HWIO_DDR_PI_166_PI_TFC_F1_FLDSHFT (0)
#define HWIO_DDR_PI_166_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_166_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_166_PI_TFC_F2_FLDMASK (0x3ff0000)
#define HWIO_DDR_PI_166_PI_TFC_F2_FLDSHFT (16)
#define HWIO_DDR_PI_166_RESERVED1_FLDMASK (0xfc000000)
#define HWIO_DDR_PI_166_RESERVED1_FLDSHFT (26)

#define HWIO_DDR_PI_167_REGOFF 0x29c
#define HWIO_DDR_PI_167_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_167_REGOFF)
#define HWIO_DDR_PI_167_PI_TFC_F3_FLDMASK (0x3ff)
#define HWIO_DDR_PI_167_PI_TFC_F3_FLDSHFT (0)
#define HWIO_DDR_PI_167_RESERVED_FLDMASK (0xfc00)
#define HWIO_DDR_PI_167_RESERVED_FLDSHFT (10)
#define HWIO_DDR_PI_167_PI_TMRD_F0_FLDMASK (0x3f0000)
#define HWIO_DDR_PI_167_PI_TMRD_F0_FLDSHFT (16)
#define HWIO_DDR_PI_167_RESERVED1_FLDMASK (0xc00000)
#define HWIO_DDR_PI_167_RESERVED1_FLDSHFT (22)
#define HWIO_DDR_PI_167_PI_TMRW_F0_FLDMASK (0xff000000)
#define HWIO_DDR_PI_167_PI_TMRW_F0_FLDSHFT (24)

#define HWIO_DDR_PI_168_REGOFF 0x2a0
#define HWIO_DDR_PI_168_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_168_REGOFF)
#define HWIO_DDR_PI_168_PI_TMRD_F1_FLDMASK (0x3f)
#define HWIO_DDR_PI_168_PI_TMRD_F1_FLDSHFT (0)
#define HWIO_DDR_PI_168_RESERVED_FLDMASK (0xc0)
#define HWIO_DDR_PI_168_RESERVED_FLDSHFT (6)
#define HWIO_DDR_PI_168_PI_TMRW_F1_FLDMASK (0xff00)
#define HWIO_DDR_PI_168_PI_TMRW_F1_FLDSHFT (8)
#define HWIO_DDR_PI_168_PI_TMRD_F2_FLDMASK (0x3f0000)
#define HWIO_DDR_PI_168_PI_TMRD_F2_FLDSHFT (16)
#define HWIO_DDR_PI_168_RESERVED1_FLDMASK (0xc00000)
#define HWIO_DDR_PI_168_RESERVED1_FLDSHFT (22)
#define HWIO_DDR_PI_168_PI_TMRW_F2_FLDMASK (0xff000000)
#define HWIO_DDR_PI_168_PI_TMRW_F2_FLDSHFT (24)

#define HWIO_DDR_PI_169_REGOFF 0x2a4
#define HWIO_DDR_PI_169_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_169_REGOFF)
#define HWIO_DDR_PI_169_PI_TMRD_F3_FLDMASK (0x3f)
#define HWIO_DDR_PI_169_PI_TMRD_F3_FLDSHFT (0)
#define HWIO_DDR_PI_169_RESERVED_FLDMASK (0xc0)
#define HWIO_DDR_PI_169_RESERVED_FLDSHFT (6)
#define HWIO_DDR_PI_169_PI_TMRW_F3_FLDMASK (0xff00)
#define HWIO_DDR_PI_169_PI_TMRW_F3_FLDSHFT (8)
#define HWIO_DDR_PI_169_RESERVED2_FLDMASK (0xf0000)
#define HWIO_DDR_PI_169_RESERVED2_FLDSHFT (16)
#define HWIO_DDR_PI_169_RESERVED1_FLDMASK (0xf00000)
#define HWIO_DDR_PI_169_RESERVED1_FLDSHFT (20)
#define HWIO_DDR_PI_169_RESERVED3_FLDMASK (0xf000000)
#define HWIO_DDR_PI_169_RESERVED3_FLDSHFT (24)
#define HWIO_DDR_PI_169_RESERVED4_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_169_RESERVED4_FLDSHFT (28)

#define HWIO_DDR_PI_170_REGOFF 0x2a8
#define HWIO_DDR_PI_170_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_170_REGOFF)
#define HWIO_DDR_PI_170_RESERVED0_FLDMASK (0xf)
#define HWIO_DDR_PI_170_RESERVED0_FLDSHFT (0)
#define HWIO_DDR_PI_170_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_PI_170_RESERVED_FLDSHFT (4)
#define HWIO_DDR_PI_170_RESERVED1_FLDMASK (0xf00)
#define HWIO_DDR_PI_170_RESERVED1_FLDSHFT (8)
#define HWIO_DDR_PI_170_RESERVED4_FLDMASK (0xf000)
#define HWIO_DDR_PI_170_RESERVED4_FLDSHFT (12)
#define HWIO_DDR_PI_170_RESERVED2_FLDMASK (0xf0000)
#define HWIO_DDR_PI_170_RESERVED2_FLDSHFT (16)
#define HWIO_DDR_PI_170_RESERVED5_FLDMASK (0xf00000)
#define HWIO_DDR_PI_170_RESERVED5_FLDSHFT (20)
#define HWIO_DDR_PI_170_RESERVED3_FLDMASK (0xf000000)
#define HWIO_DDR_PI_170_RESERVED3_FLDSHFT (24)
#define HWIO_DDR_PI_170_RESERVED6_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_170_RESERVED6_FLDSHFT (28)

#define HWIO_DDR_PI_171_REGOFF 0x2ac
#define HWIO_DDR_PI_171_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_171_REGOFF)
#define HWIO_DDR_PI_171_RESERVED0_FLDMASK (0xf)
#define HWIO_DDR_PI_171_RESERVED0_FLDSHFT (0)
#define HWIO_DDR_PI_171_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_PI_171_RESERVED_FLDSHFT (4)
#define HWIO_DDR_PI_171_RESERVED1_FLDMASK (0xf00)
#define HWIO_DDR_PI_171_RESERVED1_FLDSHFT (8)
#define HWIO_DDR_PI_171_RESERVED4_FLDMASK (0xf000)
#define HWIO_DDR_PI_171_RESERVED4_FLDSHFT (12)
#define HWIO_DDR_PI_171_RESERVED2_FLDMASK (0xf0000)
#define HWIO_DDR_PI_171_RESERVED2_FLDSHFT (16)
#define HWIO_DDR_PI_171_RESERVED5_FLDMASK (0xf00000)
#define HWIO_DDR_PI_171_RESERVED5_FLDSHFT (20)
#define HWIO_DDR_PI_171_RESERVED3_FLDMASK (0xf000000)
#define HWIO_DDR_PI_171_RESERVED3_FLDSHFT (24)
#define HWIO_DDR_PI_171_RESERVED6_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_171_RESERVED6_FLDSHFT (28)

#define HWIO_DDR_PI_172_REGOFF 0x2b0
#define HWIO_DDR_PI_172_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_172_REGOFF)
#define HWIO_DDR_PI_172_PI_INT_STATUS_FLDMASK (0x1ffff)
#define HWIO_DDR_PI_172_PI_INT_STATUS_FLDSHFT (0)
#define HWIO_DDR_PI_172_RESERVED_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_172_RESERVED_FLDSHFT (17)
#define HWIO_DDR_PI_172_OBSOLETE1_FLDMASK (0xff000000)
#define HWIO_DDR_PI_172_OBSOLETE1_FLDSHFT (24)

#define HWIO_DDR_PI_173_REGOFF 0x2b4
#define HWIO_DDR_PI_173_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_173_REGOFF)
#define HWIO_DDR_PI_173_PI_INT_ACK_FLDMASK (0xffff)
#define HWIO_DDR_PI_173_PI_INT_ACK_FLDSHFT (0)
#define HWIO_DDR_PI_173_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_173_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_174_REGOFF 0x2b8
#define HWIO_DDR_PI_174_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_174_REGOFF)
#define HWIO_DDR_PI_174_PI_INT_MASK_FLDMASK (0x1ffff)
#define HWIO_DDR_PI_174_PI_INT_MASK_FLDSHFT (0)
#define HWIO_DDR_PI_174_RESERVED_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_174_RESERVED_FLDSHFT (17)
#define HWIO_DDR_PI_174_PI_BSTLEN_FLDMASK (0x1f000000)
#define HWIO_DDR_PI_174_PI_BSTLEN_FLDSHFT (24)
#define HWIO_DDR_PI_174_RESERVED1_FLDMASK (0xe0000000)
#define HWIO_DDR_PI_174_RESERVED1_FLDSHFT (29)

#define HWIO_DDR_PI_175_REGOFF 0x2bc
#define HWIO_DDR_PI_175_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_175_REGOFF)
#define HWIO_DDR_PI_175_PI_LONG_COUNT_MASK_FLDMASK (0x1f)
#define HWIO_DDR_PI_175_PI_LONG_COUNT_MASK_FLDSHFT (0)
#define HWIO_DDR_PI_175_RESERVED_FLDMASK (0xe0)
#define HWIO_DDR_PI_175_RESERVED_FLDSHFT (5)
#define HWIO_DDR_PI_175_PI_CTRLUPD_REQ_PER_AREF_EN_FLDMASK (0x100)
#define HWIO_DDR_PI_175_PI_CTRLUPD_REQ_PER_AREF_EN_FLDSHFT (8)
#define HWIO_DDR_PI_175_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_175_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_175_PI_TDFI_CTRLUPD_MIN_FLDMASK (0xf0000)
#define HWIO_DDR_PI_175_PI_TDFI_CTRLUPD_MIN_FLDSHFT (16)
#define HWIO_DDR_PI_175_RESERVED2_FLDMASK (0xf00000)
#define HWIO_DDR_PI_175_RESERVED2_FLDSHFT (20)
#define HWIO_DDR_PI_175_OBSOLETE3_FLDMASK (0xff000000)
#define HWIO_DDR_PI_175_OBSOLETE3_FLDSHFT (24)

#define HWIO_DDR_PI_176_REGOFF 0x2c0
#define HWIO_DDR_PI_176_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_176_REGOFF)
#define HWIO_DDR_PI_176_PI_TDFI_CTRLUPD_MAX_F0_FLDMASK (0xffff)
#define HWIO_DDR_PI_176_PI_TDFI_CTRLUPD_MAX_F0_FLDSHFT (0)
#define HWIO_DDR_PI_176_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_176_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_177_REGOFF 0x2c4
#define HWIO_DDR_PI_177_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_177_REGOFF)
#define HWIO_DDR_PI_177_PI_TDFI_CTRLUPD_INTERVAL_F0_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_177_PI_TDFI_CTRLUPD_INTERVAL_F0_FLDSHFT (0)

#define HWIO_DDR_PI_178_REGOFF 0x2c8
#define HWIO_DDR_PI_178_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_178_REGOFF)
#define HWIO_DDR_PI_178_PI_TDFI_CTRLUPD_MAX_F1_FLDMASK (0xffff)
#define HWIO_DDR_PI_178_PI_TDFI_CTRLUPD_MAX_F1_FLDSHFT (0)
#define HWIO_DDR_PI_178_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_178_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_179_REGOFF 0x2cc
#define HWIO_DDR_PI_179_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_179_REGOFF)
#define HWIO_DDR_PI_179_PI_TDFI_CTRLUPD_INTERVAL_F1_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_179_PI_TDFI_CTRLUPD_INTERVAL_F1_FLDSHFT (0)

#define HWIO_DDR_PI_180_REGOFF 0x2d0
#define HWIO_DDR_PI_180_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_180_REGOFF)
#define HWIO_DDR_PI_180_PI_TDFI_CTRLUPD_MAX_F2_FLDMASK (0xffff)
#define HWIO_DDR_PI_180_PI_TDFI_CTRLUPD_MAX_F2_FLDSHFT (0)
#define HWIO_DDR_PI_180_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_180_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_181_REGOFF 0x2d4
#define HWIO_DDR_PI_181_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_181_REGOFF)
#define HWIO_DDR_PI_181_PI_TDFI_CTRLUPD_INTERVAL_F2_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_181_PI_TDFI_CTRLUPD_INTERVAL_F2_FLDSHFT (0)

#define HWIO_DDR_PI_182_REGOFF 0x2d8
#define HWIO_DDR_PI_182_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_182_REGOFF)
#define HWIO_DDR_PI_182_PI_TDFI_CTRLUPD_MAX_F3_FLDMASK (0xffff)
#define HWIO_DDR_PI_182_PI_TDFI_CTRLUPD_MAX_F3_FLDSHFT (0)
#define HWIO_DDR_PI_182_OBSOLETE1_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_182_OBSOLETE1_FLDSHFT (16)

#define HWIO_DDR_PI_183_REGOFF 0x2dc
#define HWIO_DDR_PI_183_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_183_REGOFF)
#define HWIO_DDR_PI_183_PI_TDFI_CTRLUPD_INTERVAL_F3_FLDMASK (0xffffffff)
#define HWIO_DDR_PI_183_PI_TDFI_CTRLUPD_INTERVAL_F3_FLDSHFT (0)

#define HWIO_DDR_PI_184_REGOFF 0x2e0
#define HWIO_DDR_PI_184_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_184_REGOFF)
#define HWIO_DDR_PI_184_PI_UPDATE_ERROR_STATUS_FLDMASK (0x7f)
#define HWIO_DDR_PI_184_PI_UPDATE_ERROR_STATUS_FLDSHFT (0)
#define HWIO_DDR_PI_184_RESERVED_FLDMASK (0x80)
#define HWIO_DDR_PI_184_RESERVED_FLDSHFT (7)
#define HWIO_DDR_PI_184_PI_MONITOR_SRC_SEL_0_FLDMASK (0xf00)
#define HWIO_DDR_PI_184_PI_MONITOR_SRC_SEL_0_FLDSHFT (8)
#define HWIO_DDR_PI_184_RESERVED1_FLDMASK (0xf000)
#define HWIO_DDR_PI_184_RESERVED1_FLDSHFT (12)
#define HWIO_DDR_PI_184_PI_MONITOR_CAP_SEL_0_FLDMASK (0x10000)
#define HWIO_DDR_PI_184_PI_MONITOR_CAP_SEL_0_FLDSHFT (16)
#define HWIO_DDR_PI_184_RESERVED2_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_184_RESERVED2_FLDSHFT (17)
#define HWIO_DDR_PI_184_PI_MONITOR_0_FLDMASK (0xff000000)
#define HWIO_DDR_PI_184_PI_MONITOR_0_FLDSHFT (24)

#define HWIO_DDR_PI_185_REGOFF 0x2e4
#define HWIO_DDR_PI_185_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_185_REGOFF)
#define HWIO_DDR_PI_185_PI_MONITOR_SRC_SEL_1_FLDMASK (0xf)
#define HWIO_DDR_PI_185_PI_MONITOR_SRC_SEL_1_FLDSHFT (0)
#define HWIO_DDR_PI_185_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_PI_185_RESERVED_FLDSHFT (4)
#define HWIO_DDR_PI_185_PI_MONITOR_CAP_SEL_1_FLDMASK (0x100)
#define HWIO_DDR_PI_185_PI_MONITOR_CAP_SEL_1_FLDSHFT (8)
#define HWIO_DDR_PI_185_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_185_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_185_PI_MONITOR_1_FLDMASK (0xff0000)
#define HWIO_DDR_PI_185_PI_MONITOR_1_FLDSHFT (16)
#define HWIO_DDR_PI_185_PI_MONITOR_SRC_SEL_2_FLDMASK (0xf000000)
#define HWIO_DDR_PI_185_PI_MONITOR_SRC_SEL_2_FLDSHFT (24)
#define HWIO_DDR_PI_185_RESERVED2_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_185_RESERVED2_FLDSHFT (28)

#define HWIO_DDR_PI_186_REGOFF 0x2e8
#define HWIO_DDR_PI_186_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_186_REGOFF)
#define HWIO_DDR_PI_186_PI_MONITOR_CAP_SEL_2_FLDMASK (0x1)
#define HWIO_DDR_PI_186_PI_MONITOR_CAP_SEL_2_FLDSHFT (0)
#define HWIO_DDR_PI_186_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_186_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_186_PI_MONITOR_2_FLDMASK (0xff00)
#define HWIO_DDR_PI_186_PI_MONITOR_2_FLDSHFT (8)
#define HWIO_DDR_PI_186_PI_MONITOR_SRC_SEL_3_FLDMASK (0xf0000)
#define HWIO_DDR_PI_186_PI_MONITOR_SRC_SEL_3_FLDSHFT (16)
#define HWIO_DDR_PI_186_RESERVED1_FLDMASK (0xf00000)
#define HWIO_DDR_PI_186_RESERVED1_FLDSHFT (20)
#define HWIO_DDR_PI_186_PI_MONITOR_CAP_SEL_3_FLDMASK (0x1000000)
#define HWIO_DDR_PI_186_PI_MONITOR_CAP_SEL_3_FLDSHFT (24)
#define HWIO_DDR_PI_186_RESERVED2_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_186_RESERVED2_FLDSHFT (25)

#define HWIO_DDR_PI_187_REGOFF 0x2ec
#define HWIO_DDR_PI_187_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_187_REGOFF)
#define HWIO_DDR_PI_187_PI_MONITOR_3_FLDMASK (0xff)
#define HWIO_DDR_PI_187_PI_MONITOR_3_FLDSHFT (0)
#define HWIO_DDR_PI_187_PI_MONITOR_SRC_SEL_4_FLDMASK (0xf00)
#define HWIO_DDR_PI_187_PI_MONITOR_SRC_SEL_4_FLDSHFT (8)
#define HWIO_DDR_PI_187_RESERVED_FLDMASK (0xf000)
#define HWIO_DDR_PI_187_RESERVED_FLDSHFT (12)
#define HWIO_DDR_PI_187_PI_MONITOR_CAP_SEL_4_FLDMASK (0x10000)
#define HWIO_DDR_PI_187_PI_MONITOR_CAP_SEL_4_FLDSHFT (16)
#define HWIO_DDR_PI_187_RESERVED1_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_187_RESERVED1_FLDSHFT (17)
#define HWIO_DDR_PI_187_PI_MONITOR_4_FLDMASK (0xff000000)
#define HWIO_DDR_PI_187_PI_MONITOR_4_FLDSHFT (24)

#define HWIO_DDR_PI_188_REGOFF 0x2f0
#define HWIO_DDR_PI_188_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_188_REGOFF)
#define HWIO_DDR_PI_188_PI_MONITOR_SRC_SEL_5_FLDMASK (0xf)
#define HWIO_DDR_PI_188_PI_MONITOR_SRC_SEL_5_FLDSHFT (0)
#define HWIO_DDR_PI_188_RESERVED_FLDMASK (0xf0)
#define HWIO_DDR_PI_188_RESERVED_FLDSHFT (4)
#define HWIO_DDR_PI_188_PI_MONITOR_CAP_SEL_5_FLDMASK (0x100)
#define HWIO_DDR_PI_188_PI_MONITOR_CAP_SEL_5_FLDSHFT (8)
#define HWIO_DDR_PI_188_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_188_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_188_PI_MONITOR_5_FLDMASK (0xff0000)
#define HWIO_DDR_PI_188_PI_MONITOR_5_FLDSHFT (16)
#define HWIO_DDR_PI_188_PI_MONITOR_SRC_SEL_6_FLDMASK (0xf000000)
#define HWIO_DDR_PI_188_PI_MONITOR_SRC_SEL_6_FLDSHFT (24)
#define HWIO_DDR_PI_188_RESERVED2_FLDMASK (0xf0000000)
#define HWIO_DDR_PI_188_RESERVED2_FLDSHFT (28)

#define HWIO_DDR_PI_189_REGOFF 0x2f4
#define HWIO_DDR_PI_189_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_189_REGOFF)
#define HWIO_DDR_PI_189_PI_MONITOR_CAP_SEL_6_FLDMASK (0x1)
#define HWIO_DDR_PI_189_PI_MONITOR_CAP_SEL_6_FLDSHFT (0)
#define HWIO_DDR_PI_189_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_189_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_189_PI_MONITOR_6_FLDMASK (0xff00)
#define HWIO_DDR_PI_189_PI_MONITOR_6_FLDSHFT (8)
#define HWIO_DDR_PI_189_PI_MONITOR_SRC_SEL_7_FLDMASK (0xf0000)
#define HWIO_DDR_PI_189_PI_MONITOR_SRC_SEL_7_FLDSHFT (16)
#define HWIO_DDR_PI_189_RESERVED1_FLDMASK (0xf00000)
#define HWIO_DDR_PI_189_RESERVED1_FLDSHFT (20)
#define HWIO_DDR_PI_189_PI_MONITOR_CAP_SEL_7_FLDMASK (0x1000000)
#define HWIO_DDR_PI_189_PI_MONITOR_CAP_SEL_7_FLDSHFT (24)
#define HWIO_DDR_PI_189_RESERVED2_FLDMASK (0xfe000000)
#define HWIO_DDR_PI_189_RESERVED2_FLDSHFT (25)

#define HWIO_DDR_PI_190_REGOFF 0x2f8
#define HWIO_DDR_PI_190_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_190_REGOFF)
#define HWIO_DDR_PI_190_PI_MONITOR_7_FLDMASK (0xff)
#define HWIO_DDR_PI_190_PI_MONITOR_7_FLDSHFT (0)
#define HWIO_DDR_PI_190_PI_MONITOR_STROBE_FLDMASK (0xff00)
#define HWIO_DDR_PI_190_PI_MONITOR_STROBE_FLDSHFT (8)
#define HWIO_DDR_PI_190_PI_DLL_LOCK_FLDMASK (0x10000)
#define HWIO_DDR_PI_190_PI_DLL_LOCK_FLDSHFT (16)
#define HWIO_DDR_PI_190_RESERVED_FLDMASK (0xfe0000)
#define HWIO_DDR_PI_190_RESERVED_FLDSHFT (17)
#define HWIO_DDR_PI_190_PI_FREQ_NUMBER_STATUS_FLDMASK (0x1f000000)
#define HWIO_DDR_PI_190_PI_FREQ_NUMBER_STATUS_FLDSHFT (24)
#define HWIO_DDR_PI_190_RESERVED1_FLDMASK (0xe0000000)
#define HWIO_DDR_PI_190_RESERVED1_FLDSHFT (29)

#define HWIO_DDR_PI_191_REGOFF 0x2fc
#define HWIO_DDR_PI_191_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PI_191_REGOFF)
#define HWIO_DDR_PI_191_RESERVED0_FLDMASK (0x1)
#define HWIO_DDR_PI_191_RESERVED0_FLDSHFT (0)
#define HWIO_DDR_PI_191_RESERVED_FLDMASK (0xfe)
#define HWIO_DDR_PI_191_RESERVED_FLDSHFT (1)
#define HWIO_DDR_PI_191_PI_PHYMSTR_TYPE_FLDMASK (0x100)
#define HWIO_DDR_PI_191_PI_PHYMSTR_TYPE_FLDSHFT (8)
#define HWIO_DDR_PI_191_RESERVED1_FLDMASK (0xfe00)
#define HWIO_DDR_PI_191_RESERVED1_FLDSHFT (9)
#define HWIO_DDR_PI_191_OBSOLETE2_FLDMASK (0xffff0000)
#define HWIO_DDR_PI_191_OBSOLETE2_FLDSHFT (16)

#endif /* __MNH_HWIO_DDR_PI_ */