diff options
| author | Ian Chang <ianc@nvidia.com> | 2015-01-28 13:14:07 +0800 |
|---|---|---|
| committer | Aaron Kling <webgeek1234@gmail.com> | 2015-03-30 12:46:08 -0500 |
| commit | bf642fad4b823811ae2882cc77449f5978fc62f0 (patch) | |
| tree | 2850f623d9b2f517df09ee2d0fc8188ae4af00b1 /arch | |
| parent | 2728ffa985b6443cd282587a21f389c653001585 (diff) | |
Modified PLLDP/D2 enable sequence, so that in case when SSC is set by
default PLL configuration, PLL is locked before SSC is turned ON.
Bug 200015629
Cherry-pick from http://git-master/r/#/c/677174/
(The code base is different so can't cherry-pick directly)
Change-Id: I0d95a2204043cdd00b43246fb1eebf6342f4bbda
Signed-off-by: Ian Chang <ianc@nvidia.com>
Reviewed-on: http://git-master/r/678169
(cherry picked from commit 2089a049849c79289c09eddccb99415ebab9ad0e)
Reviewed-on: http://git-master/r/707246
Reviewed-by: Dhiren Parmar <dparmar@nvidia.com>
Tested-by: Dhiren Parmar <dparmar@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/tegra12_clocks.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra12_clocks.c b/arch/arm/mach-tegra/tegra12_clocks.c index c6a2b2d3830..19263841534 100644 --- a/arch/arm/mach-tegra/tegra12_clocks.c +++ b/arch/arm/mach-tegra/tegra12_clocks.c @@ -415,6 +415,8 @@ #define PLLSS_CTRL2_DEFAULT_VALUE \ ((PLLSS_SDM_SSC_STEP << 16) | (PLLSS_SDM_DIN << 0)) +#define PLLSS_CFG_EN_SSC (0x1 << 30) + /* PLLSS configuration */ #define PLLSS_MISC_KCP 0 #define PLLSS_MISC_KVCO 0 @@ -3764,15 +3766,31 @@ static void tegra12_pllss_clk_init(struct clk *c) static int tegra12_pllss_clk_enable(struct clk *c) { u32 val; + + bool ssc_enabled = false; pr_debug("%s on clock %s\n", __func__, c->name); pll_do_iddq(c, PLL_BASE, PLLSS_BASE_IDDQ, false); + val = clk_readl(c->reg + PLLSS_CFG(c)); + if (val & PLLSS_CFG_EN_SSC) { + val &= ~PLLSS_CFG_EN_SSC; + clk_writel(val, c->reg + PLLSS_CFG(c)); + ssc_enabled = true; + } + val = clk_readl(c->reg + PLL_BASE); val |= PLL_BASE_ENABLE; clk_writel(val, c->reg + PLL_BASE); tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLLSS_BASE_LOCK); + + if (ssc_enabled) { + val = clk_readl(c->reg + PLLSS_CFG(c)); + val |= PLLSS_CFG_EN_SSC; + pll_writel_delay(val, c->reg + PLLSS_CFG(c)); + } + return 0; } |