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| author | Matt Wagantall <mattw@codeaurora.org> | 2012-02-03 20:18:23 -0800 |
|---|---|---|
| committer | Matt Wagantall <mattw@codeaurora.org> | 2012-02-06 22:25:28 -0800 |
| commit | 19ac4fdd506e855890ccd508a1776475760f17e9 (patch) | |
| tree | 57dc0b3402f8ff655c2beb85e8b35f134c608f7a /scripts/gcc-wrapper.py | |
| parent | 8c6d485cf3db9b8b01c33aaf77f98c1f17d95a8e (diff) | |
msm: pil-gss: Apply workaround for QGIC bus access issue
On 8064 v1.0, QGIC registers are inaccessible from the GSS A5
processor unless a special sequence of register writes and reads
is first performed from the Krait0 CPU. This sequence affects the
initial state of an internal GSS bus, resolving the access issue.
CRs-Fixed: 334608
Change-Id: If0bf1f3f16e5e73399de4593b02ba92daf10e5b6
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Diffstat (limited to 'scripts/gcc-wrapper.py')
0 files changed, 0 insertions, 0 deletions