diff options
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c | 94 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/msm_atomic.c | 40 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/sde/sde_core_irq.c | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/sde/sde_crtc.c | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c | 22 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/sde/sde_hw_interrupts.c | 70 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/sde/sde_hw_interrupts.h | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/sde/sde_hw_intf.c | 14 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/sde/sde_hw_intf.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/sde/sde_hw_pingpong.c | 14 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/sde/sde_hw_pingpong.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/msm/Makefile | 8 | ||||
| -rw-r--r-- | drivers/gpu/msm/adreno-gpulist.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/msm/adreno.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/msm/adreno_cp_parser.h | 23 | ||||
| -rw-r--r-- | drivers/gpu/msm/kgsl.c | 2 |
16 files changed, 131 insertions, 198 deletions
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c index 243c213e89e6..b1d1432b1acd 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c @@ -980,36 +980,25 @@ error: return rc; } -static int dsi_ctrl_copy_and_pad_cmd(struct dsi_ctrl *dsi_ctrl, - const struct mipi_dsi_packet *packet, - u8 **buffer, - u32 *size) +static int dsi_ctrl_copy_and_pad_cmd(const struct mipi_dsi_packet *packet, + u8 *buf, size_t len) { int rc = 0; - u8 *buf = NULL; - u32 len, i; u8 cmd_type = 0; - len = packet->size; - len += 0x3; len &= ~0x03; /* Align to 32 bits */ - - buf = devm_kzalloc(&dsi_ctrl->pdev->dev, len * sizeof(u8), GFP_KERNEL); - if (!buf) - return -ENOMEM; + if (unlikely(len < packet->size)) + return -EINVAL; - for (i = 0; i < len; i++) { - if (i >= packet->size) - buf[i] = 0xFF; - else if (i < sizeof(packet->header)) - buf[i] = packet->header[i]; - else - buf[i] = packet->payload[i - sizeof(packet->header)]; - } + memcpy(buf, packet->header, sizeof(packet->header)); + if (packet->payload_length) + memcpy(buf + sizeof(packet->header), packet->payload, + packet->payload_length); + if (packet->size < len) + memset(buf + packet->size, 0xFF, len - packet->size); if (packet->payload_length > 0) buf[3] |= BIT(6); - /* send embedded BTA for read commands */ cmd_type = buf[2] & 0x3f; if ((cmd_type == MIPI_DSI_DCS_READ) || @@ -1018,9 +1007,6 @@ static int dsi_ctrl_copy_and_pad_cmd(struct dsi_ctrl *dsi_ctrl, (cmd_type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM)) buf[3] |= BIT(5); - *buffer = buf; - *size = len; - return rc; } @@ -1141,11 +1127,13 @@ int dsi_message_validate_tx_mode(struct dsi_ctrl *dsi_ctrl, pr_err("Cannot transfer,size is greater than 4096\n"); return -ENOTSUPP; } - } + } else if (*flags & DSI_CTRL_CMD_FETCH_MEMORY) { + const size_t transfer_size = dsi_ctrl->cmd_len + cmd_len + 4; - if (*flags & DSI_CTRL_CMD_FETCH_MEMORY) { - if ((dsi_ctrl->cmd_len + cmd_len + 4) > SZ_4K) { - pr_err("Cannot transfer,size is greater than 4096\n"); + if (transfer_size > DSI_EMBEDDED_MODE_DMA_MAX_SIZE_BYTES) { + pr_err("Cannot transfer, size: %zu is greater than %d\n", + transfer_size, + DSI_EMBEDDED_MODE_DMA_MAX_SIZE_BYTES); return -ENOTSUPP; } } @@ -1162,9 +1150,9 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, struct dsi_ctrl_cmd_dma_fifo_info cmd; struct dsi_ctrl_cmd_dma_info cmd_mem; u32 hw_flags = 0; - u32 length = 0; + u32 length; u8 *buffer = NULL; - u32 cnt = 0, line_no = 0x1; + u32 line_no = 0x1; u8 *cmdbuf; struct dsi_mode_info *timing; struct dsi_ctrl_hw_ops dsi_hw_ops = dsi_ctrl->hw.ops; @@ -1180,6 +1168,10 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, goto error; } + pr_debug("cmd tx type=%02x cmd=%02x len=%d last=%d\n", msg->type, + msg->tx_len ? *((u8 *)msg->tx_buf) : 0, msg->tx_len, + (msg->flags & MIPI_DSI_MSG_LASTCOMMAND) != 0); + if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) { cmd_mem.offset = dsi_ctrl->cmd_buffer_iova; cmd_mem.en_broadcast = (flags & DSI_CTRL_CMD_BROADCAST) ? @@ -1205,20 +1197,22 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, goto error; } - rc = dsi_ctrl_copy_and_pad_cmd(dsi_ctrl, - &packet, - &buffer, - &length); - if (rc) { - pr_err("[%s] failed to copy message, rc=%d\n", - dsi_ctrl->name, rc); - goto error; - } + length = ALIGN(packet.size, 4); if ((msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) - buffer[3] |= BIT(7);//set the last cmd bit in header. + packet.header[3] |= BIT(7);//set the last cmd bit in header. if (flags & DSI_CTRL_CMD_FETCH_MEMORY) { + msm_gem_sync(dsi_ctrl->tx_cmd_buf); + cmdbuf = dsi_ctrl->vaddr + dsi_ctrl->cmd_len; + + rc = dsi_ctrl_copy_and_pad_cmd(&packet, cmdbuf, length); + if (rc) { + pr_err("[%s] failed to copy message, rc=%d\n", + dsi_ctrl->name, rc); + goto error; + } + /* Embedded mode config is selected */ cmd_mem.offset = dsi_ctrl->cmd_buffer_iova; cmd_mem.en_broadcast = (flags & DSI_CTRL_CMD_BROADCAST) ? @@ -1228,12 +1222,6 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, cmd_mem.use_lpm = (msg->flags & MIPI_DSI_MSG_USE_LPM) ? true : false; - cmdbuf = (u8 *)(dsi_ctrl->vaddr); - - msm_gem_sync(dsi_ctrl->tx_cmd_buf); - for (cnt = 0; cnt < length; cnt++) - cmdbuf[dsi_ctrl->cmd_len + cnt] = buffer[cnt]; - dsi_ctrl->cmd_len += length; if (!(msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) { @@ -1244,6 +1232,20 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, } } else if (flags & DSI_CTRL_CMD_FIFO_STORE) { + buffer = devm_kzalloc(&dsi_ctrl->pdev->dev, length, + GFP_KERNEL); + if (!buffer) { + rc = -ENOMEM; + goto error; + } + + rc = dsi_ctrl_copy_and_pad_cmd(&packet, buffer, length); + if (rc) { + pr_err("[%s] failed to copy message, rc=%d\n", + dsi_ctrl->name, rc); + goto error; + } + cmd.command = (u32 *)buffer; cmd.size = length; cmd.en_broadcast = (flags & DSI_CTRL_CMD_BROADCAST) ? diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index c1e6cb5b4718..c19f9e22e75d 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -33,7 +33,10 @@ struct msm_commit { uint32_t crtc_mask; uint32_t plane_mask; bool nonblock; - struct kthread_work commit_work; + union { + struct kthread_work commit_work; + struct work_struct clean_work; + }; }; static BLOCKING_NOTIFIER_HEAD(msm_drm_notifier_list); @@ -117,7 +120,6 @@ static void end_atomic(struct msm_drm_private *priv, uint32_t crtc_mask, static void commit_destroy(struct msm_commit *c) { - end_atomic(c->dev->dev_private, c->crtc_mask, c->plane_mask); if (c->nonblock) kfree(c); } @@ -528,6 +530,16 @@ static void msm_atomic_helper_commit_modeset_enables(struct drm_device *dev, SDE_ATRACE_END("msm_enable"); } +static void complete_commit_cleanup(struct work_struct *work) +{ + struct msm_commit *c = container_of(work, typeof(*c), clean_work); + struct drm_atomic_state *state = c->state; + + drm_atomic_state_put(state); + + commit_destroy(c); +} + /* The (potentially) asynchronous part of the commit. At this point * nothing can fail short of armageddon. */ @@ -567,25 +579,24 @@ static void complete_commit(struct msm_commit *c) kms->funcs->complete_commit(kms, state); - drm_atomic_state_put(state); - - commit_destroy(c); + end_atomic(priv, c->crtc_mask, c->plane_mask); } static void _msm_drm_commit_work_cb(struct kthread_work *work) { - struct msm_commit *commit = NULL; - - if (!work) { - DRM_ERROR("%s: Invalid commit work data!\n", __func__); - return; - } - - commit = container_of(work, struct msm_commit, commit_work); + struct msm_commit *c = container_of(work, typeof(*c), commit_work); SDE_ATRACE_BEGIN("complete_commit"); - complete_commit(commit); + complete_commit(c); SDE_ATRACE_END("complete_commit"); + + if (c->nonblock) { + /* Offload the cleanup onto little CPUs (an unbound wq) */ + INIT_WORK(&c->clean_work, complete_commit_cleanup); + queue_work(system_unbound_wq, &c->clean_work); + } else { + complete_commit_cleanup(&c->clean_work); + } } static struct msm_commit *commit_init(struct drm_atomic_state *state, @@ -656,6 +667,7 @@ static void msm_atomic_commit_dispatch(struct drm_device *dev, */ DRM_ERROR("failed to dispatch commit to any CRTC\n"); complete_commit(commit); + complete_commit_cleanup(&commit->clean_work); } else if (!nonblock) { kthread_flush_work(&commit->commit_work); } diff --git a/drivers/gpu/drm/msm/sde/sde_core_irq.c b/drivers/gpu/drm/msm/sde/sde_core_irq.c index b082778a4590..c250fbb6d402 100644 --- a/drivers/gpu/drm/msm/sde/sde_core_irq.c +++ b/drivers/gpu/drm/msm/sde/sde_core_irq.c @@ -662,15 +662,6 @@ int sde_core_irq_domain_fini(struct sde_kms *sde_kms) irqreturn_t sde_core_irq(struct sde_kms *sde_kms) { /* - * Read interrupt status from all sources. Interrupt status are - * stored within hw_intr. - * Function will also clear the interrupt status after reading. - * Individual interrupt status bit will only get stored if it - * is enabled. - */ - sde_kms->hw_intr->ops.get_interrupt_statuses(sde_kms->hw_intr); - - /* * Dispatch to HW driver to handle interrupt lookup that is being * fired. When matching interrupt is located, HW driver will call to * sde_core_irq_callback_handler with the irq_idx from the lookup table. diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c index 77dd68db9b4b..b5e41c826351 100644 --- a/drivers/gpu/drm/msm/sde/sde_crtc.c +++ b/drivers/gpu/drm/msm/sde/sde_crtc.c @@ -2251,9 +2251,11 @@ static void _sde_crtc_blend_setup(struct drm_crtc *crtc, mixer[i].hw_ctl); /* clear dim_layer settings */ - lm = mixer[i].hw_lm; - if (lm->ops.clear_dim_layer) - lm->ops.clear_dim_layer(lm); + if (sde_crtc_state->num_dim_layers > 0) { + lm = mixer[i].hw_lm; + if (lm->ops.clear_dim_layer) + lm->ops.clear_dim_layer(lm); + } } _sde_crtc_swap_mixers_for_right_partial_update(crtc); @@ -4395,8 +4397,6 @@ void sde_crtc_commit_kickoff(struct drm_crtc *crtc, if (_sde_crtc_commit_kickoff_rot(crtc, cstate)) is_error = true; - sde_vbif_clear_errors(sde_kms); - if (is_error) { _sde_crtc_remove_pipe_flush(crtc); _sde_crtc_blend_setup(crtc, old_state, false); diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c index 1e50e8ff76ee..655a48a225eb 100644 --- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c @@ -663,9 +663,9 @@ static int _sde_encoder_phys_cmd_poll_write_pointer_started( } if (phys_enc->has_intf_te) - ret = hw_intf->ops.get_vsync_info(hw_intf, &info); + ret = hw_intf->ops.get_vsync_info(hw_intf, &info, false); else - ret = hw_pp->ops.get_vsync_info(hw_pp, &info); + ret = hw_pp->ops.get_vsync_info(hw_pp, &info, false); if (ret) return ret; @@ -714,13 +714,13 @@ static bool _sde_encoder_phys_cmd_is_ongoing_pptx( if (!hw_intf || !hw_intf->ops.get_vsync_info) return false; - hw_intf->ops.get_vsync_info(hw_intf, &info); + hw_intf->ops.get_vsync_info(hw_intf, &info, true); } else { hw_pp = phys_enc->hw_pp; if (!hw_pp || !hw_pp->ops.get_vsync_info) return false; - hw_pp->ops.get_vsync_info(hw_pp, &info); + hw_pp->ops.get_vsync_info(hw_pp, &info, true); } SDE_EVT32(DRMID(phys_enc->parent), @@ -1173,12 +1173,20 @@ static void sde_encoder_phys_cmd_enable(struct sde_encoder_phys *phys_enc) static bool sde_encoder_phys_cmd_is_autorefresh_enabled( struct sde_encoder_phys *phys_enc) { + struct sde_encoder_phys_cmd *cmd_enc; struct sde_hw_pingpong *hw_pp; struct sde_hw_intf *hw_intf; struct sde_hw_autorefresh cfg; int ret; - if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_intf) + if (!phys_enc) + return 0; + + cmd_enc = to_sde_encoder_phys_cmd(phys_enc); + if (!cmd_enc->autorefresh.cfg.enable) + return 0; + + if (!phys_enc->hw_pp || !phys_enc->hw_intf) return 0; if (!sde_encoder_phys_cmd_is_master(phys_enc)) @@ -1271,14 +1279,14 @@ static int sde_encoder_phys_cmd_get_write_line_count( if (!hw_intf->ops.get_vsync_info) return -EINVAL; - if (hw_intf->ops.get_vsync_info(hw_intf, &info)) + if (hw_intf->ops.get_vsync_info(hw_intf, &info, true)) return -EINVAL; } else { hw_pp = phys_enc->hw_pp; if (!hw_pp->ops.get_vsync_info) return -EINVAL; - if (hw_pp->ops.get_vsync_info(hw_pp, &info)) + if (hw_pp->ops.get_vsync_info(hw_pp, &info, true)) return -EINVAL; } diff --git a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c index 0fc778e35f88..038b1fc53907 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c +++ b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c @@ -886,8 +886,6 @@ static void sde_hw_intr_dispatch_irq(struct sde_hw_intr *intr, */ spin_lock_irqsave(&intr->irq_lock, irq_flags); for (reg_idx = 0; reg_idx < intr->sde_irq_size; reg_idx++) { - irq_status = intr->save_irq_status[reg_idx]; - /* get the global offset in 'sde_irq_map' */ sde_irq_idx = intr->sde_irq_tbl[reg_idx].sde_irq_idx; if (sde_irq_idx < 0) @@ -904,6 +902,9 @@ static void sde_hw_intr_dispatch_irq(struct sde_hw_intr *intr, end_idx > ARRAY_SIZE(sde_irq_map)) continue; + irq_status = SDE_REG_READ(&intr->hw, + intr->sde_irq_tbl[reg_idx].status_off); + /* * Search through matching intr status from irq map. * start_idx and end_idx defined the search range in @@ -924,8 +925,9 @@ static void sde_hw_intr_dispatch_irq(struct sde_hw_intr *intr, if (cbfunc) cbfunc(arg, irq_idx); else - intr->ops.clear_intr_status_nolock( - intr, irq_idx); + SDE_REG_WRITE(&intr->hw, + intr->sde_irq_tbl[reg_idx].clr_off, + sde_irq_map[irq_idx].irq_mask); /* * When callback finish, clear the irq_status @@ -977,9 +979,6 @@ static int sde_hw_intr_enable_irq(struct sde_hw_intr *intr, int irq_idx) /* Enabling interrupts with the new mask */ SDE_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); - /* ensure register write goes through */ - wmb(); - intr->cache_irq_mask[reg_idx] = cache_irq_mask; } spin_unlock_irqrestore(&intr->irq_lock, irq_flags); @@ -1115,40 +1114,6 @@ static int sde_hw_intr_get_interrupt_sources(struct sde_hw_intr *intr, return 0; } -static void sde_hw_intr_get_interrupt_statuses(struct sde_hw_intr *intr) -{ - int i; - u32 enable_mask; - unsigned long irq_flags; - - if (!intr) - return; - - spin_lock_irqsave(&intr->irq_lock, irq_flags); - for (i = 0; i < intr->sde_irq_size; i++) { - /* Read interrupt status */ - intr->save_irq_status[i] = SDE_REG_READ(&intr->hw, - intr->sde_irq_tbl[i].status_off); - - /* Read enable mask */ - enable_mask = SDE_REG_READ(&intr->hw, - intr->sde_irq_tbl[i].en_off); - - /* and clear the interrupt */ - if (intr->save_irq_status[i]) - SDE_REG_WRITE(&intr->hw, intr->sde_irq_tbl[i].clr_off, - intr->save_irq_status[i]); - - /* Finally update IRQ status based on enable mask */ - intr->save_irq_status[i] &= enable_mask; - } - - /* ensure register writes go through */ - wmb(); - - spin_unlock_irqrestore(&intr->irq_lock, irq_flags); -} - static void sde_hw_intr_clear_intr_status_force_mask(struct sde_hw_intr *intr, int irq_idx, u32 irq_mask) { @@ -1200,12 +1165,20 @@ static void sde_hw_intr_clear_interrupt_status(struct sde_hw_intr *intr, int irq_idx) { unsigned long irq_flags; + int reg_idx; if (!intr) return; + reg_idx = sde_irq_map[irq_idx].reg_idx; + if (reg_idx < 0 || reg_idx > intr->sde_irq_size) { + pr_err("invalid irq reg:%d irq:%d\n", reg_idx, irq_idx); + return; + } + spin_lock_irqsave(&intr->irq_lock, irq_flags); - sde_hw_intr_clear_intr_status_nolock(intr, irq_idx); + SDE_REG_WRITE(&intr->hw, intr->sde_irq_tbl[reg_idx].clr_off, + sde_irq_map[irq_idx].irq_mask); spin_unlock_irqrestore(&intr->irq_lock, irq_flags); } @@ -1272,9 +1245,6 @@ static u32 sde_hw_intr_get_interrupt_status(struct sde_hw_intr *intr, SDE_REG_WRITE(&intr->hw, intr->sde_irq_tbl[reg_idx].clr_off, intr_status); - /* ensure register writes go through */ - wmb(); - spin_unlock_irqrestore(&intr->irq_lock, irq_flags); return intr_status; @@ -1321,7 +1291,6 @@ static void __setup_intr_ops(struct sde_hw_intr_ops *ops) ops->disable_all_irqs = sde_hw_intr_disable_irqs; ops->get_valid_interrupts = sde_hw_intr_get_valid_interrupts; ops->get_interrupt_sources = sde_hw_intr_get_interrupt_sources; - ops->get_interrupt_statuses = sde_hw_intr_get_interrupt_statuses; ops->clear_interrupt_status = sde_hw_intr_clear_interrupt_status; ops->clear_intr_status_nolock = sde_hw_intr_clear_intr_status_nolock; ops->clear_intr_status_force_mask = @@ -1469,7 +1438,6 @@ void sde_hw_intr_destroy(struct sde_hw_intr *intr) if (intr) { kfree(intr->sde_irq_tbl); kfree(intr->cache_irq_mask); - kfree(intr->save_irq_status); kfree(intr); } } @@ -1578,13 +1546,6 @@ struct sde_hw_intr *sde_hw_intr_init(void __iomem *addr, goto exit; } - intr->save_irq_status = kcalloc(intr->sde_irq_size, sizeof(u32), - GFP_KERNEL); - if (intr->save_irq_status == NULL) { - ret = -ENOMEM; - goto exit; - } - spin_lock_init(&intr->irq_lock); return intr; @@ -1592,7 +1553,6 @@ struct sde_hw_intr *sde_hw_intr_init(void __iomem *addr, exit: kfree(intr->sde_irq_tbl); kfree(intr->cache_irq_mask); - kfree(intr->save_irq_status); kfree(intr); return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h index 1d5a8427d0aa..e2de0e33bd59 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h +++ b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h @@ -189,14 +189,6 @@ struct sde_hw_intr_ops { void *arg); /** - * get_interrupt_statuses - Gets and store value from all interrupt - * status registers that are currently fired. - * @intr: HW interrupt handle - */ - void (*get_interrupt_statuses)( - struct sde_hw_intr *intr); - - /** * clear_interrupt_status - Clears HW interrupt status based on given * lookup IRQ index. * @intr: HW interrupt handle @@ -292,7 +284,6 @@ struct sde_hw_intr_ops { * @hw: virtual address mapping * @ops: function pointer mapping for IRQ handling * @cache_irq_mask: array of IRQ enable masks reg storage created during init - * @save_irq_status: array of IRQ status reg storage created during init * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts * @irq_lock: spinlock for accessing IRQ resources * @sde_irq_size: total number of elements of the sde_irq_tbl @@ -303,7 +294,6 @@ struct sde_hw_intr { struct sde_hw_blk_reg_map hw; struct sde_hw_intr_ops ops; u32 *cache_irq_mask; - u32 *save_irq_status; u32 irq_idx_tbl_size; u32 sde_irq_size; struct sde_intr_reg *sde_irq_tbl; diff --git a/drivers/gpu/drm/msm/sde/sde_hw_intf.c b/drivers/gpu/drm/msm/sde/sde_hw_intf.c index 21b671164786..ba7510ab310d 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_intf.c +++ b/drivers/gpu/drm/msm/sde/sde_hw_intf.c @@ -613,7 +613,7 @@ static int sde_hw_intf_connect_external_te(struct sde_hw_intf *intf, } static int sde_hw_intf_get_vsync_info(struct sde_hw_intf *intf, - struct sde_hw_pp_vsync_info *info) + struct sde_hw_pp_vsync_info *info, bool wr_ptr_only) { struct sde_hw_blk_reg_map *c = &intf->hw; u32 val; @@ -623,12 +623,14 @@ static int sde_hw_intf_get_vsync_info(struct sde_hw_intf *intf, c = &intf->hw; - val = SDE_REG_READ(c, INTF_TEAR_VSYNC_INIT_VAL); - info->rd_ptr_init_val = val & 0xffff; + if (!wr_ptr_only) { + val = SDE_REG_READ(c, INTF_TEAR_VSYNC_INIT_VAL); + info->rd_ptr_init_val = val & 0xffff; - val = SDE_REG_READ(c, INTF_TEAR_INT_COUNT_VAL); - info->rd_ptr_frame_count = (val & 0xffff0000) >> 16; - info->rd_ptr_line_count = val & 0xffff; + val = SDE_REG_READ(c, INTF_TEAR_INT_COUNT_VAL); + info->rd_ptr_frame_count = (val & 0xffff0000) >> 16; + info->rd_ptr_line_count = val & 0xffff; + } val = SDE_REG_READ(c, INTF_TEAR_LINE_COUNT); info->wr_ptr_line_count = val & 0xffff; diff --git a/drivers/gpu/drm/msm/sde/sde_hw_intf.h b/drivers/gpu/drm/msm/sde/sde_hw_intf.h index 413aac279619..ec38000c1970 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_intf.h +++ b/drivers/gpu/drm/msm/sde/sde_hw_intf.h @@ -141,7 +141,7 @@ struct sde_hw_intf_ops { * line_count */ int (*get_vsync_info)(struct sde_hw_intf *intf, - struct sde_hw_pp_vsync_info *info); + struct sde_hw_pp_vsync_info *info, bool wr_ptr_only); /** * configure and enable the autorefresh config diff --git a/drivers/gpu/drm/msm/sde/sde_hw_pingpong.c b/drivers/gpu/drm/msm/sde/sde_hw_pingpong.c index 64c1a90f5952..e03eb3d8391f 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_pingpong.c +++ b/drivers/gpu/drm/msm/sde/sde_hw_pingpong.c @@ -404,7 +404,7 @@ static int sde_hw_pp_connect_external_te(struct sde_hw_pingpong *pp, } static int sde_hw_pp_get_vsync_info(struct sde_hw_pingpong *pp, - struct sde_hw_pp_vsync_info *info) + struct sde_hw_pp_vsync_info *info, bool wr_ptr_only) { struct sde_hw_blk_reg_map *c; u32 val; @@ -413,12 +413,14 @@ static int sde_hw_pp_get_vsync_info(struct sde_hw_pingpong *pp, return -EINVAL; c = &pp->hw; - val = SDE_REG_READ(c, PP_VSYNC_INIT_VAL); - info->rd_ptr_init_val = val & 0xffff; + if (!wr_ptr_only) { + val = SDE_REG_READ(c, PP_VSYNC_INIT_VAL); + info->rd_ptr_init_val = val & 0xffff; - val = SDE_REG_READ(c, PP_INT_COUNT_VAL); - info->rd_ptr_frame_count = (val & 0xffff0000) >> 16; - info->rd_ptr_line_count = val & 0xffff; + val = SDE_REG_READ(c, PP_INT_COUNT_VAL); + info->rd_ptr_frame_count = (val & 0xffff0000) >> 16; + info->rd_ptr_line_count = val & 0xffff; + } val = SDE_REG_READ(c, PP_LINE_COUNT); info->wr_ptr_line_count = val & 0xffff; diff --git a/drivers/gpu/drm/msm/sde/sde_hw_pingpong.h b/drivers/gpu/drm/msm/sde/sde_hw_pingpong.h index 9cc755237c68..e83c26bf0eb0 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_pingpong.h +++ b/drivers/gpu/drm/msm/sde/sde_hw_pingpong.h @@ -72,7 +72,7 @@ struct sde_hw_pingpong_ops { * line_count */ int (*get_vsync_info)(struct sde_hw_pingpong *pp, - struct sde_hw_pp_vsync_info *info); + struct sde_hw_pp_vsync_info *info, bool wr_ptr_only); /** * configure and enable the autorefresh config diff --git a/drivers/gpu/msm/Makefile b/drivers/gpu/msm/Makefile index b1f075ce037d..623feb5a6cdf 100644 --- a/drivers/gpu/msm/Makefile +++ b/drivers/gpu/msm/Makefile @@ -30,16 +30,8 @@ msm_adreno-y += \ adreno_snapshot.o \ adreno_coresight.o \ adreno_trace.o \ - adreno_a3xx.o \ - adreno_a4xx.o \ - adreno_a5xx.o \ adreno_a6xx.o \ - adreno_a3xx_snapshot.o \ - adreno_a4xx_snapshot.o \ - adreno_a5xx_snapshot.o \ adreno_a6xx_snapshot.o \ - adreno_a4xx_preempt.o \ - adreno_a5xx_preempt.o \ adreno_a6xx_preempt.o \ adreno_a6xx_gmu.o \ adreno_a6xx_rgmu.o \ diff --git a/drivers/gpu/msm/adreno-gpulist.h b/drivers/gpu/msm/adreno-gpulist.h index 1a7df11bda16..f2adcb7fd1d5 100644 --- a/drivers/gpu/msm/adreno-gpulist.h +++ b/drivers/gpu/msm/adreno-gpulist.h @@ -14,6 +14,7 @@ #define ANY_ID (~0) static const struct adreno_gpu_core adreno_gpulist[] = { +#if 0 { .gpurev = ADRENO_REV_A306, .core = 3, @@ -335,6 +336,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .num_protected_regs = 0x20, .busy_mask = 0xFFFFFFFE, }, +#endif { .gpurev = ADRENO_REV_A630, .core = 6, diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index e4021fd73e4a..3b1ed485e80f 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -1686,13 +1686,6 @@ int adreno_set_unsecured_mode(struct adreno_device *adreno_dev, if (!adreno_is_a5xx(adreno_dev) && !adreno_is_a6xx(adreno_dev)) return -EINVAL; - if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_CRITICAL_PACKETS) && - adreno_is_a5xx(adreno_dev)) { - ret = a5xx_critical_packet_submit(adreno_dev, rb); - if (ret) - return ret; - } - /* GPU comes up in secured mode, make it unsecured by default */ if (adreno_dev->zap_handle_ptr) ret = adreno_switch_to_unsecure_mode(adreno_dev, rb); diff --git a/drivers/gpu/msm/adreno_cp_parser.h b/drivers/gpu/msm/adreno_cp_parser.h index 1fa46c147c3c..fa6a43ad33d6 100644 --- a/drivers/gpu/msm/adreno_cp_parser.h +++ b/drivers/gpu/msm/adreno_cp_parser.h @@ -134,15 +134,7 @@ static inline void adreno_ib_init_ib_obj(uint64_t gpuaddr, static inline int adreno_cp_parser_getreg(struct adreno_device *adreno_dev, enum adreno_cp_addr_regs reg_enum) { - if (reg_enum == ADRENO_CP_ADDR_MAX) - return -EEXIST; - - if (adreno_is_a3xx(adreno_dev)) - return a3xx_cp_addr_regs[reg_enum]; - else if (adreno_is_a4xx(adreno_dev)) - return a4xx_cp_addr_regs[reg_enum]; - else - return -EEXIST; + return -EEXIST; } /* @@ -160,19 +152,6 @@ static inline int adreno_cp_parser_regindex(struct adreno_device *adreno_dev, enum adreno_cp_addr_regs start, enum adreno_cp_addr_regs end) { - int i; - const unsigned int *regs; - - if (adreno_is_a4xx(adreno_dev)) - regs = a4xx_cp_addr_regs; - else if (adreno_is_a3xx(adreno_dev)) - regs = a3xx_cp_addr_regs; - else - return -EEXIST; - - for (i = start; i <= end && i < ADRENO_CP_ADDR_MAX; i++) - if (regs[i] == offset) - return i; return -EEXIST; } diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index 0ced8a2450e5..b296299a6afd 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -5154,7 +5154,7 @@ static void kgsl_core_exit(void) static int __init kgsl_core_init(void) { int result = 0; - struct sched_param param = { .sched_priority = 2 }; + struct sched_param param = { .sched_priority = 16 }; place_marker("M - DRIVER KGSL Init"); |