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* ARM64: Support interm. address for object arrays.Artem Serov2018-10-251-0/+69
| | | | | | | | | | | | | | | | Support IntermediateAddress on arm64 for object array reads in Baker read barrier configuration. The patch brings minor boot.oat size reduction and performance improvement on Puzzle benchmark. Test: test-art-target, test-art-host, gc_stress. Test: 527-checker-array-access-split. Bug: 26601270 Bug: 32578862 Change-Id: I781a911905038b36428964a990771fdf74e99bbd
* ART: Remove unneeded SideEffects for fatal instructions.Artem Serov2018-08-311-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | Remove "CanTriggerGC" side effect for NullCheck, BoundsCheck and DivZeroCheck - instructions which have fatal slow paths. Even though GC might happen after going through those instructions' slow path execution doesn't return to the next instruction after the exceptional one so side effects can be relaxed. Performance improvement (angler, arm64, little core): - Geomean: 2.8% - Particular benchmarks - algorithm/Sort.SystemSort: 13.0% - stanford/IntMM: 12.7% - stanford/Puzzle: 9.5% - benchmarksgame/revcomp: 8.9% - reversigame/Reversi: 3.5% Test: 510-checker-try-catch. Test: 706-checker-scheduler. Test: 527-checker-array-access-split. Test: test-art-host, test-art-target. Change-Id: I55ac011822e5dbac82c828a700213dbea87329c8
* ART: Implement loop full unrolling.Artem Serov2018-07-041-4/+4
| | | | | | | | | | | | Performs whole loop unrolling for small loops with small trip count to eliminate the loop check overhead, to have more opportunities for inter-iteration optimizations. caffeinemark/FloatAtom: 1.2x performance on arm64 Cortex-A57. Test: 530-checker-peel-unroll. Test: test-art-host, test-art-target. Change-Id: Idf3fe3cb611376935d176c60db8c49907222e28a
* Replace + by / to avoid vectorization of loop.Aart Bik2017-03-221-36/+36
| | | | | | | | | | Rationale: Break-out CL of ART Vectorizer. Ensure loop is not vectorized to avoid messing up checker test. Bug: 34083438 Test: test-art-host-527-checker-array-access-split Change-Id: Idab70a03a0f710e1e9b775891d726e1f044df916
* Remove the `CanTriggerGC` side-effects on a few instructions.Alexandre Rames2016-09-191-32/+32
| | | | | | | | | | The side-effect was specified for these instructions as they call runtime. We now have a list of entrypoints that we know cannot trigger GC. We can avoid requiring the side-effect for those. Test: Run ART test suite on Nexus 5X and host. Change-Id: I0e0e6a4d701ce6c75aff486cb0d1bc7fe2e8dda4
* Implement running user defined list of passesWojciech Staszkiewicz2016-08-081-10/+10
| | | | | | | | | | | | | | | | | | This change introduces new dex2oat switch --run-passes=. This switch accepts path to a text file with names of passes to run. Compiler will run optimization passes specified in the file rather then the default ones. There is no verification implemented on the compiler side. It is user's responsibility to provide a list of passes that leads to successful generation of correct code. Care should be taken to prepare a list that satisfies all dependencies between optimizations. We only take control of the optional optimizations. Codegen (builder), and all passes required for register allocation will run unaffected by this mechanism. Change-Id: Ic3694e53515fefcc5ce6f28d9371776b5afcbb4f
* ARM: Port instr simplification of array accesses.Artem Serov2016-07-211-30/+268
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After changing the addressing mode for array accesses (in https://android-review.googlesource.com/248406) the 'add' instruction that calculates the base address for the array can be shared across accesses to the same array. Before https://android-review.googlesource.com/248406: add IP, r[Array], r[Index0], LSL #2 ldr r0, [IP, #12] add IP, r[Array], r[Index1], LSL #2 ldr r0, [IP, #12] Before this CL: add IP. r[Array], #12 ldr r0, [IP, r[Index0], LSL #2] add IP. r[Array], #12 ldr r0, [IP, r[Index1], LSL #2] After this CL: add IP. r[Array], #12 ldr r0, [IP, r[Index0], LSL #2] ldr r0, [IP, r[Index1], LSL #2] Link to the original optimization: https://android-review.googlesource.com/#/c/127310/ Test: Run ART test suite on Nexus 6. Change-Id: Iee26f9a0a7ca46abb90e3f60d19d22dc8dee4d8f
* ARM64: Instruction simplification for array accesses.Alexandre Rames2015-10-191-0/+341
HArrayGet and HArraySet with variable indexes generate two instructions on arm64, like add temp, obj, #data_offset ldr out, [temp, index LSL #shift_amount] When we have multiple accesses to the same array, the initial `add` instruction is redundant. This patch introduces the first instruction simplification in the arm64-specific instruction simplification pass. It splits HArrayGet and HArraySet using the new arm64-specific IR HIntermediateAddress. After that we run GVN again to squash the multiple occurrences of HIntermediateAddress. Change-Id: I2e3d12fbb07fed07b2cb2f3f47f99f5a032f8312
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