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* JIT tuning; set cache size on command linebuzbee2013-05-231-1/+5
| | | | | | | | | | | | | | | | | The tuning knobs for triggering trace compilation for the JIT had not been revisited for several years. In that time, the working set of some applications have significantly increased, leading to frequent cache overlows & flushes. This CL adds the ability to set the maximum size of the JIT's cache on the command line, and we expect to use different settings depending on device configuration (rule of thumb: 1K for each 1M for system RAM, with 2M limit). Additionally, the trace compilation trigger has been tightened to limit the compilation of cold traces. Change-Id: Ice22c5d9d46a93e465c57dd83f50ca3912f1672e
* Fix -Xjitthreshold (for real this time).Elliott Hughes2013-03-011-1/+1
| | | | | | | | | | | | | My previous "fix" (c89d83e1c05979b68037ad15413fa4460a88e36f) had the conditions reversed, so you _had_ to use -Xjitthreshold to get a non-zero threshold, but when you did, you'd get the default instead of what you asked for! This was spotted by the jank tests. Bug: 8285558 Bug: https://code.google.com/p/android/issues/detail?id=52017 Change-Id: I28270f2573d46929eb10d30789fecf7d5a8cea75
* Fix -Xjitthreshold.Elliott Hughes2013-02-251-1/+3
| | | | | | | | Previously, we'd always overwrite the user-supplied value because the architecture-specific default gets set so late. Bug: https://code.google.com/p/android/issues/detail?id=52017 Change-Id: I469bf9ce599820f5ce3dea346aa8f680deffb0c5
* [MIPS] Fixing FP registers fs0 and fs1 corruption bug.Douglas Leung2012-11-261-0/+8
| | | | | | | | For performance reasons, we don't want to use "callee saved" FP registers. The fix is to just use temporary FP registers instead. Change-Id: Ifae20c707ff7022905a080892348bfbc151e4935 Signed-off-by: Douglas Leung <douglas@mips.com>
* MIPS: Missing zero-checks in JIT compiler.Douglas Leung2012-10-051-1/+9
| | | | | | | | | Zero-checks were not generated by the JIT compiler for some instructions. This caused crashes instead of the expected ArithmeticException. Change-Id: Ic7f20c78ef9ac22bb529b6ed9a38f0ffb2fab33c Signed-off-by: Douglas Leung <douglas@mips.com>
* Optimize those StrictMath routines that are identical to Math routines.Elliott Hughes2012-09-141-6/+16
| | | | | | | We can just use the existing Math intinsics. Bug: 7146208 Change-Id: I9e78d33cf65a5dcc5a7c0133e67bd9c3c1e43f23
* Fix an array out-of-bound read in the JIT compiler.Douglas Leung2012-08-011-4/+10
| | | | | | | | | | Without the fix the compiler is still safe since the offending memory access is a read, though the hoisted distance is non-deterministic. The easiest and safest fix is to unconditionally hoist a load when it can reach the scheduling barrier. Change-Id: I021161cb2a6e011301ab65ba62bc2a74af1cb552 Signed-off-by: Douglas Leung <douglas@mips.com>
* Fix the MIPS build:Raghu Gandham2012-07-319-230/+142
| | | | | | | 1. LOG->ALOG conversion 2. Remove Jumbo opcodes support Change-Id: Ifbd1eae2f5e7a1cab5828ebfbdba380ad499abfd
* [X86] X86 trace JIT compiler supportDong-Yuan Chen2012-07-202-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides a fully functional x86 trace JIT compiler for Dalvik VM. It is built on top of the existing x86 fast interpreter with bug fixes and needed extension to support trace JIT interface. The x86 trace JIT code generator was developed independent of the existing template-based code generator and thus does not share exactly the same infrastructure. Included in this patch are: * Deprecated and removed the x86-atom fast interpreter that is no longer functional since ICS. * Augmented x86 fast interpreter to provide interfaces for x86 trace JIT compiler. * Added x86 trace JIT code generator with full JDWP debugging support. * Method JIT and self-verification mode are not supported. The x86 code generator uses the x86 instruction encoder/decoder library from the Apache Harmony project. Additional wrapper extension and bug fixes were added to support the x86 trace JIT code generator. The x86 instruction encoder/decoder is embedded inside the x86 code generator under the libenc subdirectory. Change-Id: I241113681963a16c13a3562390813cbaaa6eedf0 Signed-off-by: Dong-Yuan Chen <dong-yuan.chen@intel.com> Signed-off-by: Yixin Shou <yixin.shou@intel.com> Signed-off-by: Johnnie Birch <johnnie.l.birch.jr@intel.com> Signed-off-by: Udayan <udayan.banerji@intel.com> Signed-off-by: Sushma Kyasaralli Thimmappa <sushma.kyasaralli.thimmappa@intel.com> Signed-off-by: Bijoy Jose <bijoy.a.jose@intel.com> Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com> Signed-off-by: Tim Hartley <timothy.d.hartley@intel.com>
* Avoid sign extension in packed-switch.Elliott Hughes2012-07-172-16/+9
| | | | | | | | | | | | | | This code (at least in the ARM version) is trying to assign to r0 and r1 from C by returning a 64-bit result. The mistaken use of signed integers for pointers can lead to sign extension if the JIT code cache is at a sufficiently high address. Bug: 6799823 Bug: 6703991 (cherry-pick from 2d0c1c2dbe44458ebb199c47ce1047f266db5349.) Change-Id: I79e72228b60e195272d11899ac69bb4a76b7402f
* Remove some dead code in the MIPS stuff, and run rebuild.sh.Elliott Hughes2012-07-171-1/+0
| | | | Change-Id: I7c3226efe97e6e5678b757eb2350d0eeb2efd8b5
* [MIPS] Dalvik fast interpreter support and JIT implementationRaghu Gandham2012-05-0221-0/+13411
Change-Id: I9bb4f6875b7061d3ffaee73f204026cb8ba3ed39 Signed-off-by: Raghu Gandham <raghu@mips.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Douglas Leung <douglas@mips.com> Signed-off-by: Don Padgett <don@mips.com>
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