diff options
| author | Yuanyuan Zhong <zyy@motorola.com> | 2016-09-23 11:21:03 -0500 |
|---|---|---|
| committer | Nathan Chancellor <natechancellor@gmail.com> | 2018-05-13 10:42:21 -0700 |
| commit | d86ab74daa066cd15deb5ff62b70ce380b611ab7 (patch) | |
| tree | 8f1f05abc0ab19a65803daea9404fdfd0d154e4e /net/lapb/lapb_timer.c | |
| parent | 3d11ab38e01c7c4c0c84cc5122b1142c58dd6bba (diff) | |
arm64: strcmp: align to 64B cache line
Align strcmp to 64B. This will ensure the preformance critical
loop is within one 64B cache line.
Change-Id: I9240fbb4407637b2290a44e02ad59098a377b356
Signed-off-by: Yuanyuan Zhong <zyy@motorola.com>
Reviewed-on: https://gerrit.mot.com/902536
SME-Granted: SME Approvals Granted
SLTApproved: Slta Waiver <sltawvr@motorola.com>
Tested-by: Jira Key <jirakey@motorola.com>
Reviewed-by: Yi-Wei Zhao <gbjc64@motorola.com>
Reviewed-by: Igor Kovalenko <igork@motorola.com>
Submit-Approved: Jira Key <jirakey@motorola.com>
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Diffstat (limited to 'net/lapb/lapb_timer.c')
0 files changed, 0 insertions, 0 deletions