aboutsummaryrefslogtreecommitdiff
path: root/vm/compiler/codegen/arm/LocalOptimizations.c
Commit message (Collapse)AuthorAgeFilesLines
* Move the compiler into C++.Carl Shapiro2011-04-191-450/+0
| | | | Change-Id: Idffbdb02c29e2be03a75f5a0a664603f2299504a
* Add support to do suspend polling on backward branches in JIT'ed code.Ben Cheng2011-02-161-383/+321
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The polling is expensive for now as it is done through three instructions: ld/ld/branch. As a result, a bunch of bonus stuff has been worked on to mitigate the extra overhead: - Cleaned up resource flags for memory disambiguation. - Rewrote load/store elimination and scheduler routines to hide the ld/ld latency for GC flag. Seperate the dependency checking into memory disambiguation part and resource conflict part. - Allowed code motion for Dalvik/constant/non-aliasing loads to be hoisted above branches for null/range checks. - Created extended basic blocks following goto instructions so that longer instruction streams can be optimized as a whole. Without the bonus stuff, the performance dropped about ~5-10% on some benchmarks because of the lack of headroom to hide the polling latency in tight loops. With the bonus stuff, the performance delta is between +/-5% with polling code generated. With the bonus stuff but disabling polling, the new bonus stuff provides consistent performance improvements: CaffeineMark 3.6% Linpack 11.1% Scimark 9.7% Sieve 33.0% Checkers 6.0% As a result, GC polling is disabled by default but can be turned on through the -Xjitsuspendpoll flag for experimental purposes. Change-Id: Ia81fc85de3e2b70e6cc93bc37c2b845892003cdb
* Misc goodies in the JIT in preparation for more aggressive code motion.Ben Cheng2011-02-081-20/+20
| | | | | | | | | - Set up resource masks correctly for Thumb push/pop when LR/PC are involved. - Preserve LR around simulated heap references under self-verification mode. - Compact a few simple flags in ArmLIR into bit fields. - Minor performance tuning in TEMPLATE_MEM_OP_DECODE Change-Id: Id73edac837c5bb37dfd21f372d6fa21c238cf42a
* Fix implicit conversions, rename reserved works, enable -Wc++-compat.Carl Shapiro2010-12-071-3/+3
| | | | Change-Id: I06292964a6882ea2d0c17c5c962db95e46b01543
* It's "opcode" not "opCode".Dan Bornstein2010-12-011-4/+4
| | | | | | | | | | Similarly "Opcode" not "OpCode". This appears to be the general worldwide consensus on the matter. Other residents of my office didn't seem to mind one way or the other how it's spelled in our code, but for whatever reason, it really bugged me. Change-Id: Ia0b73d19c54aefc0f543a9c9451dda22ee876a59
* Clean up warnings detected by gcc.Ben Cheng2010-05-281-0/+3
| | | | | | Also re-enabled the JIT for the ARMv5te target. Change-Id: I89fd229205e30e6ee92a4933290a7d8dca001232
* Remove unused labels, variables, and functions. Enable warnings.Carl Shapiro2010-05-211-3/+0
| | | | Change-Id: Icbe24eaf1ad499f28b68b6a5f05368271a0a7e86
* Use correct resource flags for Dalvik ld/st instructions to enable code motion.Ben Cheng2010-03-251-13/+39
| | | | Change-Id: I9b371af4150b6245c0ff59eea63d83406edbbcee
* Bug fix for JIT peephole optimization.Ben Cheng2010-03-171-4/+6
| | | | | Bug: 2520500 Change-Id: I36dbd8b3a6d13c40f9735df4918ab02b5f053b07
* Jit: Sapphire tuning - mostly scheduling.Bill Buzbee2010-03-031-6/+142
| | | | | | | | | | | | Re-enabled load/store motion that had inadvertently been turned off for non-armv7 targets. Tagged memory references with the kind of memory they touch (Dalvik frame, literal pool, heap) to enable more aggressive load hoisting. Eliminated some largely duplicate code in the target specific files. Reworked temp register allocation code to allocate next temp round-robin (to improve scheduling opportunities). Overall, nice gain for Sapphire. Shows 5% to 15% on some benchmarks, and measurable improvements for Passion.
* Restructure the codegen to make architectural depedency explicit.Ben Cheng2009-11-221-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original Codegen.c is broken into three components: - CodegenCommon.c (arch-independend) - CodegenFactory.c (Thumb1/2 dependent) - CodegenDriver.c (Dalvik dependent) For the Thumb/Thumb2 directories, each contain the followin three files: - Factory.c (low-level routines for instruction selections) - Gen.c (invoke the ISA-specific instruction selection routines) - Ralloc.c (arch-dependent register pools) The FP directory contains FP-specific codegen routines depending on Thumb/Thumb2/VFP/PortableFP: - Thumb2VFP.c - ThumbVFP.c - ThumbPortableFP.c Then the hierarchy is formed by stacking these files in the following top-down order: 1 CodegenCommon.c 2 Thumb[2]/Factory.c 3 CodegenFactory.c 4 Thumb[2]/Gen.c 5 FP stuff 6 Thumb[2]/Ralloc.c 7 CodegenDriver.c
* Fix a memory disambiguation and a SFP/DFP assembling bug in the JIT.Ben Cheng2009-09-301-8/+5
|
* Implemented a new scheduler and FP register allocator.Ben Cheng2009-09-251-90/+138
| | | | Improved performance by 50% over existing JIT for some FP benchmarks.
* Model resource usage for each Thumb/Thumb2 instrution.Ben Cheng2009-09-111-18/+127
| | | | | This is an mid-point checkin to avoid future merge nightmare for the register allocator work.
* Improved codegen for inline, continuing codegen restructuringBill Buzbee2009-08-281-0/+3
| | | | | | | Added support for Thumb2 IT. Moved compare-long and floating point comparisons inline. Temporarily disabled use of Thumb2 CBZ & CBNZ because they were causing too many out-of-range assembly restarts. Bug fix for LIR3 assert.
* Thumb/Thumb2 instruction selection rework.Bill Buzbee2009-08-251-2/+28
| | | | Change-id: I7428278f07f49e675d0271c58b3cbf1f6a4e9da1
* Continuing evolution of Thumb2 support.Bill Buzbee2009-08-131-24/+45
| | | | | Bug fix for local optimization Enable partial floating point store sinking (with significant perf gain!)
* Stage 3 of Thumb2 support. armv7-a now generates vfp code inline.Bill Buzbee2009-07-311-0/+6
|
* Stage 2 of structural changes for support of THUMB2. No logic changes.Bill Buzbee2009-07-281-0/+139
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-21 12:22:39 +0000