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path: root/vm/compiler/codegen/arm/ArchUtility.c
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* Move the compiler into C++.Carl Shapiro2011-04-191-427/+0
| | | | Change-Id: Idffbdb02c29e2be03a75f5a0a664603f2299504a
* Generate code for loops formed with the new builderBen Cheng2011-03-311-0/+5
| | | | | | | | | | | | | | | | Adapt the existing counted loop analysis and range/null check elimination code to work with the new loop building heuristics. Cleaned up the old ad-hoc loop builder. Suspend polling is enabled by default for loops. The backward chaining cell will be used in self-verification and profiling mode. If the loop includes accesses to resolved fields/classes, abort code generation for now and revert to the basic acyclic trace. Added tests/090-loop-formation to make sure the JIT won't choke on such instructions. Change-Id: Idbc57df0a745be3b692f68c1acb6d4861c537f75
* Dump the current code stream when the assembler fails on size issues.Ben Cheng2011-03-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Since the assembler is very robust and will recover from such problems, adding the verbose/noisy mode will make it easier to detect overly aggressive optimizations that don't actually work. Example: D/dalvikvm( 2348): Assembler abort #1 on 1 D/dalvikvm( 2348): kThumbBCond@16: delta=260 : Instruction at 0x16 is a conditional branch: D/dalvikvm( 2348): 0x16 (0016): beq 0x0000001a (L0xb6c0c) : Label at L0xb6c0c is a PC reconstruction cell: D/dalvikvm( 2348): L0xb6c0c: D/dalvikvm( 2348): -------- reconstruct dalvik PC : 0x401854d6 @ +0x002b D/dalvikvm( 2348): 0x11e (011e): ldr r0, [r15pc, #0] D/dalvikvm( 2348): 0x122 (0122): b 0x00000126 (L0xb685c) where 0x11e - 0x16 - 4 = 260 Change-Id: Icbc3dae581949f5976722e24e38f04ec882c7d79
* Print class/method info for virtual callsites in JIT verbose mode.Ben Cheng2011-03-141-2/+5
| | | | | | | For example: chaining cell (predicted): Ljava/lang/Object;getClass Change-Id: Ia53340baab87d6b744fc7189b141737a4a54cc42
* Handle relocatable class objects in JIT'ed code.Ben Cheng2011-03-101-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1) Split the original literal pool into class object literals and constants. Elements in the class object pool have to match the specicial values perfectly (ie no +delta space optimizations) since they might be relocated. 2) Implement dvmJitScanAllClassPointers(void (*callback)(void *)) which is the entry routine to report all memory locations in the code cache that contain class objects (ie class object pool and predicted chaining cells for virtual calls). 3) Major codegen changes on how/when the class object pool are populated and how predicted chains are patched. Before this change the compiler thread is always in the VM_WAIT state, which won't prevent GC from running. Since the class object pointers captured by a worker thread are no longer guaranteed to be stable at JIT time, change various internal data structures to capture the class descriptor/loader tuple instead. The conversion from descriptor/loader tuple to actual class object pointers are only performed when the thread state is RUNNING or at GC safe point. 4) Separate the class object installation phase out of the main dvmCompilerAssembleLIR routine so that the impact to blocking GC requests is minimal. Add new stats to report the potential block time. For example: Potential GC blocked by compiler: max 46 us / avg 25 us 5) Various cleanup in the trace structure walkup code. Modified the verbose print routine to show the class descriptor in the class literal pool. For example: D/dalvikvm( 1450): -------- end of chaining cells (0x007c) D/dalvikvm( 1450): 0x44020628 (00b4): .class (Lcom/android/unit_tests/PerformanceTests$EmptyClass;) D/dalvikvm( 1450): 0x4402062c (00b8): .word (0xaca8d1a5) D/dalvikvm( 1450): 0x44020630 (00bc): .word (0x401abc02) D/dalvikvm( 1450): End Bug: 3482956 Change-Id: I2e736b00d63adc255c33067544606b8b96b72ffc
* Handle OP_THROW in the method JIT.Ben Cheng2011-03-021-2/+2
| | | | | | | | | | | | | | | | | | | The current implementation is to reconstruct the leaf Dalvik frame and punt to the interpreter, since the amount of work involed to match each catch block and walk through the stack frames is just not worth JIT'ing. Additional changes: - Fixed a control-flow bug where a block that ends with a throw shouldn't have a fall-through block. - Fixed a code cache lookup bug so that method-based compilation is guaranteed a slot in the profiling table. - Created separate handler routines based on opcode format for the method-based JIT. - Renamed a few core registers that also have special meanings to the VM or ARM architecture. Change-Id: I429b3633f281a0e04d352ae17a1c4f4a41bab156
* Add support to do suspend polling on backward branches in JIT'ed code.Ben Cheng2011-02-161-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The polling is expensive for now as it is done through three instructions: ld/ld/branch. As a result, a bunch of bonus stuff has been worked on to mitigate the extra overhead: - Cleaned up resource flags for memory disambiguation. - Rewrote load/store elimination and scheduler routines to hide the ld/ld latency for GC flag. Seperate the dependency checking into memory disambiguation part and resource conflict part. - Allowed code motion for Dalvik/constant/non-aliasing loads to be hoisted above branches for null/range checks. - Created extended basic blocks following goto instructions so that longer instruction streams can be optimized as a whole. Without the bonus stuff, the performance dropped about ~5-10% on some benchmarks because of the lack of headroom to hide the polling latency in tight loops. With the bonus stuff, the performance delta is between +/-5% with polling code generated. With the bonus stuff but disabling polling, the new bonus stuff provides consistent performance improvements: CaffeineMark 3.6% Linpack 11.1% Scimark 9.7% Sieve 33.0% Checkers 6.0% As a result, GC polling is disabled by default but can be turned on through the -Xjitsuspendpoll flag for experimental purposes. Change-Id: Ia81fc85de3e2b70e6cc93bc37c2b845892003cdb
* Misc goodies in the JIT in preparation for more aggressive code motion.Ben Cheng2011-02-081-4/+4
| | | | | | | | | - Set up resource masks correctly for Thumb push/pop when LR/PC are involved. - Preserve LR around simulated heap references under self-verification mode. - Compact a few simple flags in ArmLIR into bit fields. - Minor performance tuning in TEMPLATE_MEM_OP_DECODE Change-Id: Id73edac837c5bb37dfd21f372d6fa21c238cf42a
* Add runtime support for method based compilation.Ben Cheng2011-01-261-5/+5
| | | | | | | | | | Enhanced code cache management to accommodate both trace and method compilations. Also implemented a hacky dispatch routine for virtual leaf methods. Microbenchmark showed 3x speedup in leaf method invocation. Change-Id: I79d95b7300ba993667b3aa221c1df9c7b0583521
* Fix push/pop instruction selection and encoding.Ben Cheng2011-01-241-5/+11
| | | | | | | | | | 1) Thumb 'push' can handle lr and 'pop' can handle pc, so make use of them. 2) Thumb2 push was incorrectly encoded as stmia, which should be stmdb instead. None of the above affect the code that we currently ship. Change-Id: I89ab46b032a3d562355c2cc3bc05fe308ba40957
* Stamp out some x86/host mode warningsbuzbee2010-12-141-0/+6
| | | | | | | Nuked a void* cast warnings and moved cacheflush into a target-specific utility wrapper. Change-Id: I36c841288b9ec7e03c0cb29b2e89db344f36fad1
* Fix implicit conversions, rename reserved works, enable -Wc++-compat.Carl Shapiro2010-12-071-1/+1
| | | | Change-Id: I06292964a6882ea2d0c17c5c962db95e46b01543
* It's "opcode" not "opCode".Dan Bornstein2010-12-011-3/+3
| | | | | | | | | | Similarly "Opcode" not "OpCode". This appears to be the general worldwide consensus on the matter. Other residents of my office didn't seem to mind one way or the other how it's spelled in our code, but for whatever reason, it really bugged me. Change-Id: Ia0b73d19c54aefc0f543a9c9451dda22ee876a59
* Rename OpCode.h -> DexOpcodes.h.Dan Bornstein2010-12-011-1/+1
| | | | | | | | Also incorporate the former contents of OpCodeNames.h. This is a small attempt to increase naming consistency in libdex. There will be a bit more to come, in a follow-up. Change-Id: Ia7ab06042dde2e19eda02ef1fee72fb4260e899d
* JIT: Support for shift field in disassembler [issue 2465170]buzbee2010-08-051-0/+14
| | | | | | | | Many Thumb2 instructions allow for an optional shift to be applied to operand 2. This cl enhances the disassembler to show a non-zero shift in the dump output. Change-Id: I6cbfec46cd45e3f2acc9553f880e80764a1eb65d
* Implement method inlining for getters/settersBen Cheng2010-08-021-1/+2
| | | | | | | | | | | | | | | | | | Changes include: 1) Force the trace that ends with an invoke instruction to include the next instruction if it is a move-result (because both need to be turned into no-ops if callee is inlined). 2) Interpreter entry point/trace builder changes so that return target won't automatically be considered as trace starting points (to avoid duplicate traces that include the move result instructions). 3) Codegen changes to handle getters/setters invoked from both monomorphic and polymorphic callsites. 4) Extend/fix self-verification to form identical trace regions and handle traces with inlined callees. 5) Apply touchups to the method based parsing - still not in use. Change-Id: I116b934df01bf9ada6d5a25187510e352bccd13c
* JIT: Support for Dalvik volatiles (issue 2781881)buzbee2010-07-211-0/+27
| | | | | | Also, on SMP systems generate memory barriers. Change-Id: If64f7c98a8de426930b8f36ac77913e53b7b2d7a
* Relocate OpCodeNames.[ch].Andy McFadden2010-06-221-1/+1
| | | | | | | The JIT was pulling it out of the dexdump directory, which is Just Plain Wrong[tm]. Now it's part of libdex, for all to enjoy. Change-Id: Ic1e4c981eb2d70ccc3c841ceb5a54f4f77af2008
* Remove unused labels, variables, and functions. Enable warnings.Carl Shapiro2010-05-211-1/+0
| | | | Change-Id: Icbe24eaf1ad499f28b68b6a5f05368271a0a7e86
* Fix a race condition in JIT state refresh under debugging / misc code cleanup.Ben Cheng2010-03-311-10/+10
| | | | | Bug: 2561283 Change-Id: I9fd94928f3e661de97098808340ea92b28cafa07
* Fix chaining offset mis-calculation for translations w/ large switch statements.Ben Cheng2010-01-151-0/+3
| | | | | | | | | Bug: 2369821 There are 12 bytes of additional code after the 65th chaining cell. So if a switch statement with more than that many cases is translated by the JIT, it will run fine until the next unchaining event, which will patch the wrong code and lead to all kinds of unexpected crashes.
* Major registor allocation rework - stage 1.Bill Buzbee2009-10-301-25/+25
| | | | | | | | | | | | | | | Direct usage of registers abstracted out. Live values tracked locally. Redundant loads and stores suppressed. Address of registers and register pairs unified w/ single "location" mechanism Register types inferred using existing dataflow analysis pass. Interim (i.e. Hack) mechanism for storing register liveness info. Rewrite TBD. Stubbed-out code for linear scan allocation (for loop and long traces) Moved optimistic lock check for monitor-enter/exit inline for Thumb2 Minor restructuring, renaming and general cleanup of codegen Renaming of enums to follow coding convention Formatting fixes introduced by the enum renaming Rewrite of RallocUtil.c and addition of linear scan to come in stage 2.
* Make the traige process for self-verification found divergence easier.Ben Cheng2009-10-151-1/+1
| | | | | | | | | 1. Automatically replay the code compilation with verbose mode turned on for the offending compilation. 3. Mark the registers with divergence explicitly. 2. Print accurate operand names using the dataflow attributes. Constant values are still printed for reference only. 3. Fixed a few correctness/style issues in self-verification code.
* Implemented a new scheduler and FP register allocator.Ben Cheng2009-09-251-11/+61
| | | | Improved performance by 50% over existing JIT for some FP benchmarks.
* Model resource usage for each Thumb/Thumb2 instrution.Ben Cheng2009-09-111-1/+5
| | | | | This is an mid-point checkin to avoid future merge nightmare for the register allocator work.
* Implement SSA-based loop optimizations.Ben Cheng2009-09-011-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For traces of simple natural loops (ie no invokes/side exits) null and range checks will be hoisted in to entry block. For acyclic traces SSA representation will be formed but no optimizations are applied (for now). SSA representation will be printed with the normal verbose output. For example: D/dalvikvm( 1248): Dumping LIR insns D/dalvikvm( 1248): installed code is at 0x428559d4 D/dalvikvm( 1248): total size is 324 bytes D/dalvikvm( 1248): 0x428559d4 (0000): data 0x012c(300) D/dalvikvm( 1248): -------- entry offset: 0x002b D/dalvikvm( 1248): -------- MIR_OP_NULL_N_RANGE_UP_CHECK D/dalvikvm( 1248): 0x428559d6 (0002): ldr r0, [r5, #36] D/dalvikvm( 1248): 0x428559d8 (0004): ldr r1, [r5, #12] D/dalvikvm( 1248): 0x428559da (0006): cbz r0,0x42855a06 D/dalvikvm( 1248): 0x428559dc (0008): ldr r0, [r0, #8] D/dalvikvm( 1248): 0x428559de (000a): subs r1, #1 D/dalvikvm( 1248): 0x428559e0 (000c): cmp r1, r0 D/dalvikvm( 1248): 0x428559e2 (000e): bge 0x42855a06 D/dalvikvm( 1248): -------- MIR_OP_NULL_N_RANGE_UP_CHECK D/dalvikvm( 1248): 0x428559e4 (0010): ldr r0, [r5, #40] D/dalvikvm( 1248): 0x428559e6 (0012): ldr r1, [r5, #12] D/dalvikvm( 1248): 0x428559e8 (0014): cbz r0,0x42855a06 D/dalvikvm( 1248): 0x428559ea (0016): ldr r0, [r0, #8] D/dalvikvm( 1248): 0x428559ec (0018): subs r1, #1 D/dalvikvm( 1248): 0x428559ee (001a): cmp r1, r0 D/dalvikvm( 1248): 0x428559f0 (001c): bge 0x42855a06 D/dalvikvm( 1248): -------- MIR_OP_NULL_N_RANGE_UP_CHECK D/dalvikvm( 1248): 0x428559f2 (001e): ldr r0, [r5, #32] D/dalvikvm( 1248): 0x428559f4 (0020): ldr r1, [r5, #12] D/dalvikvm( 1248): 0x428559f6 (0022): cbz r0,0x42855a06 D/dalvikvm( 1248): 0x428559f8 (0024): ldr r0, [r0, #8] D/dalvikvm( 1248): 0x428559fa (0026): cmp r1, r0 D/dalvikvm( 1248): 0x428559fc (0028): bge 0x42855a06 D/dalvikvm( 1248): -------- MIR_OP_LOWER_BOUND_CHECK D/dalvikvm( 1248): 0x428559fe (002a): ldr r0, [r5, #44] D/dalvikvm( 1248): 0x42855a00 (002c): cmp r0, #1 D/dalvikvm( 1248): 0x42855a02 (002e): blt 0x42855a06 D/dalvikvm( 1248): 0x42855a04 (0030): b 0x42855a08 D/dalvikvm( 1248): 0x42855a06 (0032): b 0x42855af0 D/dalvikvm( 1248): L0x002b: D/dalvikvm( 1248): -------- MIR_OP_PHI D/dalvikvm( 1248): -------- s20(v11_1) <- s11(v11_0) s46(v11_2) D/dalvikvm( 1248): -------- dalvik offset: 0x002b @ aget-wide D/dalvikvm( 1248): -------- s21(v12_1) s22(v13_1) <- s9(v9_0) s20(v11_1) D/dalvikvm( 1248): 0x42855a08 (0034): ldr r2, [r5, #36] D/dalvikvm( 1248): 0x42855a0a (0036): ldr r3, [r5, #44] D/dalvikvm( 1248): 0x42855a0c (0038): adds r2, r2, #16 D/dalvikvm( 1248): 0x42855a0e (003a): lsls r3, r3, #3 D/dalvikvm( 1248): 0x42855a10 (003c): ldr r0, [r2, r3] D/dalvikvm( 1248): 0x42855a12 (003e): adds r2, r2, #4 D/dalvikvm( 1248): 0x42855a14 (0040): ldr r1, [r2, r3] D/dalvikvm( 1248): -------- dalvik offset: 0x002d @ aget-wide D/dalvikvm( 1248): -------- s23(v14_1) s24(v15_1) <- s10(v10_0) s20(v11_1) D/dalvikvm( 1248): 0x42855a16 (0042): ldr r3, [r5, #40] D/dalvikvm( 1248): 0x42855a18 (0044): str r0, [r5, #48] D/dalvikvm( 1248): 0x42855a1a (0046): ldr r0, [r5, #44] D/dalvikvm( 1248): 0x42855a1c (0048): adds r3, r3, #16 D/dalvikvm( 1248): 0x42855a1e (004a): lsls r0, r0, #3 D/dalvikvm( 1248): 0x42855a20 (004c): str r1, [r5, #52] D/dalvikvm( 1248): 0x42855a22 (004e): ldr r1, [r3, r0] D/dalvikvm( 1248): 0x42855a24 (0050): adds r3, r3, #4 D/dalvikvm( 1248): 0x42855a26 (0052): ldr r2, [r3, r0] D/dalvikvm( 1248): -------- dalvik offset: 0x002f @ add-double/2addr D/dalvikvm( 1248): -------- s25(v12_2) s26(v13_2) <- s21(v12_1) s22(v13_1) s23(v14_1) s24(v15_1) D/dalvikvm( 1248): 0x42855a28 (0054): str r1, [r5, #56] D/dalvikvm( 1248): 0x42855a2a (0056): str r2, [r5, #60] D/dalvikvm( 1248): 0x42855a2c (0058): vldr d1, [r5, #48] D/dalvikvm( 1248): 0x42855a30 (005c): vldr d2, [r5, #56] D/dalvikvm( 1248): 0x42855a34 (0060): vadd d0, d1, d2 D/dalvikvm( 1248): -------- dalvik offset: 0x0030 @ const/4 D/dalvikvm( 1248): -------- s27(v14_2) <- D/dalvikvm( 1248): 0x42855a38 (0064): movs r2, #1 D/dalvikvm( 1248): -------- dalvik offset: 0x0031 @ sub-int D/dalvikvm( 1248): -------- s28(v14_3) <- s20(v11_1) s27(v14_2) D/dalvikvm( 1248): 0x42855a3a (0066): ldr r3, [r5, #44] D/dalvikvm( 1248): 0x42855a3c (0068): subs r0, r3, r2 D/dalvikvm( 1248): -------- dalvik offset: 0x0033 @ aget-wide D/dalvikvm( 1248): -------- s29(v14_4) s30(v15_2) <- s8(v8_0) s28(v14_3) D/dalvikvm( 1248): 0x42855a3e (006a): ldr r3, [r5, #32] D/dalvikvm( 1248): 0x42855a40 (006c): adds r3, r3, #16 D/dalvikvm( 1248): 0x42855a42 (006e): str r0, [r5, #56] D/dalvikvm( 1248): 0x42855a44 (0070): lsls r0, r0, #3 D/dalvikvm( 1248): 0x42855a46 (0072): vstr d0, [r5, #48] D/dalvikvm( 1248): 0x42855a4a (0076): ldr r1, [r3, r0] D/dalvikvm( 1248): 0x42855a4c (0078): adds r3, r3, #4 D/dalvikvm( 1248): 0x42855a4e (007a): ldr r2, [r3, r0] D/dalvikvm( 1248): -------- dalvik offset: 0x0035 @ add-double/2addr D/dalvikvm( 1248): -------- s31(v12_3) s32(v13_3) <- s25(v12_2) s26(v13_2) s29(v14_4) s30(v15_2) D/dalvikvm( 1248): 0x42855a50 (007c): str r1, [r5, #56] D/dalvikvm( 1248): 0x42855a52 (007e): str r2, [r5, #60] D/dalvikvm( 1248): 0x42855a54 (0080): vldr d1, [r5, #48] D/dalvikvm( 1248): 0x42855a58 (0084): vldr d2, [r5, #56] D/dalvikvm( 1248): 0x42855a5c (0088): vadd d0, d1, d2 D/dalvikvm( 1248): -------- dalvik offset: 0x0036 @ add-int/lit8 D/dalvikvm( 1248): -------- s33(v14_5) <- s20(v11_1) D/dalvikvm( 1248): 0x42855a60 (008c): ldr r2, [r5, #44] D/dalvikvm( 1248): 0x42855a62 (008e): adds r2, r2, #1 D/dalvikvm( 1248): -------- dalvik offset: 0x0038 @ aget-wide D/dalvikvm( 1248): -------- s34(v14_6) s35(v15_3) <- s8(v8_0) s33(v14_5) D/dalvikvm( 1248): 0x42855a64 (0090): ldr r1, [r5, #32] D/dalvikvm( 1248): 0x42855a66 (0092): adds r1, r1, #16 D/dalvikvm( 1248): 0x42855a68 (0094): str r2, [r5, #56] D/dalvikvm( 1248): 0x42855a6a (0096): lsls r2, r2, #3 D/dalvikvm( 1248): 0x42855a6c (0098): vstr d0, [r5, #48] D/dalvikvm( 1248): 0x42855a70 (009c): ldr r3, [r1, r2] D/dalvikvm( 1248): 0x42855a72 (009e): adds r1, r1, #4 D/dalvikvm( 1248): 0x42855a74 (00a0): ldr r0, [r1, r2] D/dalvikvm( 1248): -------- dalvik offset: 0x003a @ add-double/2addr D/dalvikvm( 1248): -------- s36(v12_4) s37(v13_4) <- s31(v12_3) s32(v13_3) s34(v14_6) s35(v15_3) D/dalvikvm( 1248): 0x42855a76 (00a2): str r3, [r5, #56] D/dalvikvm( 1248): 0x42855a78 (00a4): str r0, [r5, #60] D/dalvikvm( 1248): 0x42855a7a (00a6): vldr d1, [r5, #48] D/dalvikvm( 1248): 0x42855a7e (00aa): vldr d2, [r5, #56] D/dalvikvm( 1248): 0x42855a82 (00ae): vadd d0, d1, d2 D/dalvikvm( 1248): 0x42855a86 (00b2): vstr d0, [r5, #48] D/dalvikvm( 1248): -------- dalvik offset: 0x003b @ mul-double/2addr D/dalvikvm( 1248): -------- s38(v12_5) s39(v13_5) <- s36(v12_4) s37(v13_4) s4(v4_0) s5(v5_0) D/dalvikvm( 1248): 0x42855a8a (00b6): vmov.f64 s2, s0 D/dalvikvm( 1248): 0x42855a8e (00ba): vldr d2, [r5, #16] D/dalvikvm( 1248): 0x42855a92 (00be): vmuld d0, d1, d2 D/dalvikvm( 1248): -------- dalvik offset: 0x003c @ aget-wide D/dalvikvm( 1248): -------- s40(v14_7) s41(v15_4) <- s8(v8_0) s20(v11_1) D/dalvikvm( 1248): 0x42855a96 (00c2): ldr r2, [r5, #32] D/dalvikvm( 1248): 0x42855a98 (00c4): ldr r3, [r5, #44] D/dalvikvm( 1248): 0x42855a9a (00c6): adds r2, r2, #16 D/dalvikvm( 1248): 0x42855a9c (00c8): lsls r3, r3, #3 D/dalvikvm( 1248): 0x42855a9e (00ca): vstr d0, [r5, #48] D/dalvikvm( 1248): 0x42855aa2 (00ce): ldr r0, [r2, r3] D/dalvikvm( 1248): 0x42855aa4 (00d0): adds r2, r2, #4 D/dalvikvm( 1248): 0x42855aa6 (00d2): ldr r1, [r2, r3] D/dalvikvm( 1248): 0x42855aa8 (00d4): str r0, [r5, #56] D/dalvikvm( 1248): 0x42855aaa (00d6): str r1, [r5, #60] D/dalvikvm( 1248): -------- dalvik offset: 0x003e @ mul-double D/dalvikvm( 1248): -------- s42(v14_8) s43(v15_5) <- s40(v14_7) s41(v15_4) s16(v16_0) s17(v17_0) D/dalvikvm( 1248): 0x42855aac (00d8): vldr d1, [r5, #56] D/dalvikvm( 1248): 0x42855ab0 (00dc): vldr d2, [r5, #64] D/dalvikvm( 1248): 0x42855ab4 (00e0): vmuld d0, d1, d2 D/dalvikvm( 1248): 0x42855ab8 (00e4): vstr d0, [r5, #56] D/dalvikvm( 1248): -------- dalvik offset: 0x0040 @ add-double/2addr D/dalvikvm( 1248): -------- s44(v12_6) s45(v13_6) <- s38(v12_5) s39(v13_5) s42(v14_8) s43(v15_5) D/dalvikvm( 1248): 0x42855abc (00e8): vldr d1, [r5, #48] D/dalvikvm( 1248): 0x42855ac0 (00ec): vldr d2, [r5, #56] D/dalvikvm( 1248): 0x42855ac4 (00f0): vadd d0, d1, d2 D/dalvikvm( 1248): 0x42855ac8 (00f4): vstr d0, [r5, #48] D/dalvikvm( 1248): -------- dalvik offset: 0x0041 @ aput-wide D/dalvikvm( 1248): -------- s44(v12_6) s45(v13_6) s8(v8_0) s20(v11_1) D/dalvikvm( 1248): 0x42855acc (00f8): ldr r3, [r5, #32] D/dalvikvm( 1248): 0x42855ace (00fa): ldr r0, [r5, #44] D/dalvikvm( 1248): 0x42855ad0 (00fc): adds r3, r3, #16 D/dalvikvm( 1248): 0x42855ad2 (00fe): ldr r1, [r5, #48] D/dalvikvm( 1248): 0x42855ad4 (0100): ldr r2, [r5, #52] D/dalvikvm( 1248): 0x42855ad6 (0102): lsls r0, r0, #3 D/dalvikvm( 1248): 0x42855ad8 (0104): str r1, [r3, r0] D/dalvikvm( 1248): 0x42855ada (0106): adds r3, r3, #4 D/dalvikvm( 1248): 0x42855adc (0108): str r2, [r3, r0] D/dalvikvm( 1248): -------- dalvik offset: 0x0043 @ add-int/lit8 D/dalvikvm( 1248): -------- s46(v11_2) <- s20(v11_1) D/dalvikvm( 1248): 0x42855ade (010a): ldr r2, [r5, #44] D/dalvikvm( 1248): 0x42855ae0 (010c): adds r2, r2, #1 D/dalvikvm( 1248): 0x42855ae2 (010e): str r2, [r5, #44] D/dalvikvm( 1248): -------- dalvik offset: 0x0045 @ goto D/dalvikvm( 1248): -------- D/dalvikvm( 1248): L0x0029: D/dalvikvm( 1248): -------- dalvik offset: 0x0029 @ if-ge D/dalvikvm( 1248): -------- s46(v11_2) s3(v3_0) D/dalvikvm( 1248): 0x42855ae4 (0110): ldr r0, [r5, #44] D/dalvikvm( 1248): 0x42855ae6 (0112): ldr r1, [r5, #12] D/dalvikvm( 1248): 0x42855ae8 (0114): cmp r0, r1 D/dalvikvm( 1248): 0x42855aea (0116): bge 0x42855aee D/dalvikvm( 1248): 0x42855aec (0118): b 0x42855a08 D/dalvikvm( 1248): -------- exit offset: 0x0046 D/dalvikvm( 1248): 0x42855aee (011a): b 0x42855af8 D/dalvikvm( 1248): -------- reconstruct dalvik PC : 0x42a644d6 @ +0x002b D/dalvikvm( 1248): 0x42855af0 (011c): ldr r0, [pc, #32] D/dalvikvm( 1248): Exception_Handling: D/dalvikvm( 1248): 0x42855af2 (011e): ldr r1, [r6, #84] D/dalvikvm( 1248): 0x42855af4 (0120): blx r1 D/dalvikvm( 1248): 0x42855af6 (0122): .align4 D/dalvikvm( 1248): -------- chaining cell (normal): 0x0046 D/dalvikvm( 1248): 0x42855af8 (0124): ldr r0, [r6, #76] D/dalvikvm( 1248): 0x42855afa (0126): blx r0 D/dalvikvm( 1248): 0x42855afc (0128): data 0x450c(17676) D/dalvikvm( 1248): 0x42855afe (012a): data 0x42a6(17062) D/dalvikvm( 1248): 0x42855b14 (0140): .word (0x42a644d6) D/dalvikvm( 1248): End Ljnt/scimark2/SOR;execute, 18 Dalvik instructions
* Improved codegen for inline, continuing codegen restructuringBill Buzbee2009-08-281-8/+15
| | | | | | | Added support for Thumb2 IT. Moved compare-long and floating point comparisons inline. Temporarily disabled use of Thumb2 CBZ & CBNZ because they were causing too many out-of-range assembly restarts. Bug fix for LIR3 assert.
* Thumb/Thumb2 instruction selection rework.Bill Buzbee2009-08-251-1/+5
| | | | Change-id: I7428278f07f49e675d0271c58b3cbf1f6a4e9da1
* New changes to enable self verification mode.Jeff Hao2009-08-211-0/+3
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* Continuing evolution of Thumb2 support.Bill Buzbee2009-08-131-0/+28
| | | | | Bug fix for local optimization Enable partial floating point store sinking (with significant perf gain!)
* Fixed 2 floating point bugs; improved debug output; armv7-a thumb2 inline sqrtBill Buzbee2009-08-011-0/+6
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* Stage 2 of structural changes for support of THUMB2. No logic changes.Bill Buzbee2009-07-281-0/+230
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-21 12:22:34 +0000